* [PATCH v4 0/2] riscv: Rename memmap enum constants
@ 2020-09-11 17:34 ` Eduardo Habkost
0 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, qemu-riscv, Sagar Karandikar,
Bastian Koppelmann, Alistair Francis, Palmer Dabbelt
Resending the enum constant rename patches from a previous QOM
cleanup series[1] separately, because of conflicts with other
sifive patches.
Series based on tags/pull-riscv-to-apply-20200910 [2]
[1] [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate
https://lore.kernel.org/qemu-devel/20200825192110.3528606-1-ehabkost@redhat.com/
[2] [PULL 00/30] riscv-to-apply queue
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
https://lore.kernel.org/qemu-devel/20200910180938.584205-1-alistair.francis@wdc.com
Based-on: 20200910180938.584205-1-alistair.francis@wdc.com
Eduardo Habkost (2):
sifive_e: Rename memmap enum constants
sifive_u: Rename memmap enum constants
include/hw/riscv/sifive_e.h | 38 ++++-----
include/hw/riscv/sifive_u.h | 34 ++++----
hw/riscv/sifive_e.c | 82 +++++++++----------
hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
4 files changed, 155 insertions(+), 155 deletions(-)
base-commit: 9435a8b3dd35f1f926f1b9127e8a906217a5518a
prerequisite-patch-id: 8e8c13fd7650f4455348e2e12064ec3ad71833c9
prerequisite-patch-id: 2df90a089a8f5af984270b7feb259d18eb64b69e
prerequisite-patch-id: c7cbdd9cd6cc5b9f8aa9df0a7ac0c8c8693bc780
prerequisite-patch-id: 22a9a9f874d70099c7bf11e627daf5f73c8f3df9
prerequisite-patch-id: 30e7cd7cea97875ad2fbaf24e3d522243293839d
prerequisite-patch-id: a8d6dbaaaf8d35270de9c7ba6f2e8ff9d9db7a40
prerequisite-patch-id: 626a1da60314d6b18d83f64c6162890d9b287c38
prerequisite-patch-id: e478dab67068db8a25317cef162ae9531e93f8c0
prerequisite-patch-id: 0d79d052dcbcbf1b8fc115ff8ae7f9200bd16618
prerequisite-patch-id: 06d93dde5aa72136224e8812db276512184ad048
prerequisite-patch-id: d59378c76baa7765bb17aca826d14a8c69452bdf
prerequisite-patch-id: 187121ba7231bc823e4acc5941a5c9fd897f26fd
prerequisite-patch-id: df311e9276e03d8bb96144a87349ec23a6ba5b6c
prerequisite-patch-id: e706cd915562ec18efba170c769047ebe2dde54e
prerequisite-patch-id: 32a079f8fda7af4ee016e54c0a95d790cb7b9916
prerequisite-patch-id: 7b413a0fc07d717c4e5fe441e2c7b60192b4b31e
prerequisite-patch-id: 6f233317f711cbb5acae045996d12260e27ab10c
prerequisite-patch-id: 35c979882cd2400363fce562d1e028c4f2e7f934
prerequisite-patch-id: d137705ec1707ef7066908e502fcef537c59383e
prerequisite-patch-id: 13c3906d42c185c7d11e2533b8f9273e10798afa
prerequisite-patch-id: d30d7757543c9f52c54ef12d9e1a1d76edd070d2
prerequisite-patch-id: 3b22c421eaad038b2d17cfb4cc7907590080ebe1
prerequisite-patch-id: 1e6b61970a34225d00ee3e5f57630f6d3cfdbee4
prerequisite-patch-id: 1c36c766b6154fe30e076845608e6be230228c1e
prerequisite-patch-id: ccaa15790633f16dfd69aaf4885f0b3f2398658c
prerequisite-patch-id: 594fe48326a7dea997a4f4e85eb72b3549d1c8e5
prerequisite-patch-id: 2db557a303b7b99a8f8d979bf5281887f3a8162c
prerequisite-patch-id: e58aa7d72a085408bccf3ba08774eda34804548c
prerequisite-patch-id: ed0319b770df843515910350348269d6eeb4c89c
prerequisite-patch-id: 89dfbe30d51576960af2b726523d75fe9130f6c6
--
2.26.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 0/2] riscv: Rename memmap enum constants
@ 2020-09-11 17:34 ` Eduardo Habkost
0 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, Bastian Koppelmann, Alistair Francis,
qemu-riscv, Sagar Karandikar, Palmer Dabbelt
Resending the enum constant rename patches from a previous QOM
cleanup series[1] separately, because of conflicts with other
sifive patches.
Series based on tags/pull-riscv-to-apply-20200910 [2]
[1] [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate
https://lore.kernel.org/qemu-devel/20200825192110.3528606-1-ehabkost@redhat.com/
[2] [PULL 00/30] riscv-to-apply queue
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
https://lore.kernel.org/qemu-devel/20200910180938.584205-1-alistair.francis@wdc.com
Based-on: 20200910180938.584205-1-alistair.francis@wdc.com
Eduardo Habkost (2):
sifive_e: Rename memmap enum constants
sifive_u: Rename memmap enum constants
include/hw/riscv/sifive_e.h | 38 ++++-----
include/hw/riscv/sifive_u.h | 34 ++++----
hw/riscv/sifive_e.c | 82 +++++++++----------
hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
4 files changed, 155 insertions(+), 155 deletions(-)
base-commit: 9435a8b3dd35f1f926f1b9127e8a906217a5518a
prerequisite-patch-id: 8e8c13fd7650f4455348e2e12064ec3ad71833c9
prerequisite-patch-id: 2df90a089a8f5af984270b7feb259d18eb64b69e
prerequisite-patch-id: c7cbdd9cd6cc5b9f8aa9df0a7ac0c8c8693bc780
prerequisite-patch-id: 22a9a9f874d70099c7bf11e627daf5f73c8f3df9
prerequisite-patch-id: 30e7cd7cea97875ad2fbaf24e3d522243293839d
prerequisite-patch-id: a8d6dbaaaf8d35270de9c7ba6f2e8ff9d9db7a40
prerequisite-patch-id: 626a1da60314d6b18d83f64c6162890d9b287c38
prerequisite-patch-id: e478dab67068db8a25317cef162ae9531e93f8c0
prerequisite-patch-id: 0d79d052dcbcbf1b8fc115ff8ae7f9200bd16618
prerequisite-patch-id: 06d93dde5aa72136224e8812db276512184ad048
prerequisite-patch-id: d59378c76baa7765bb17aca826d14a8c69452bdf
prerequisite-patch-id: 187121ba7231bc823e4acc5941a5c9fd897f26fd
prerequisite-patch-id: df311e9276e03d8bb96144a87349ec23a6ba5b6c
prerequisite-patch-id: e706cd915562ec18efba170c769047ebe2dde54e
prerequisite-patch-id: 32a079f8fda7af4ee016e54c0a95d790cb7b9916
prerequisite-patch-id: 7b413a0fc07d717c4e5fe441e2c7b60192b4b31e
prerequisite-patch-id: 6f233317f711cbb5acae045996d12260e27ab10c
prerequisite-patch-id: 35c979882cd2400363fce562d1e028c4f2e7f934
prerequisite-patch-id: d137705ec1707ef7066908e502fcef537c59383e
prerequisite-patch-id: 13c3906d42c185c7d11e2533b8f9273e10798afa
prerequisite-patch-id: d30d7757543c9f52c54ef12d9e1a1d76edd070d2
prerequisite-patch-id: 3b22c421eaad038b2d17cfb4cc7907590080ebe1
prerequisite-patch-id: 1e6b61970a34225d00ee3e5f57630f6d3cfdbee4
prerequisite-patch-id: 1c36c766b6154fe30e076845608e6be230228c1e
prerequisite-patch-id: ccaa15790633f16dfd69aaf4885f0b3f2398658c
prerequisite-patch-id: 594fe48326a7dea997a4f4e85eb72b3549d1c8e5
prerequisite-patch-id: 2db557a303b7b99a8f8d979bf5281887f3a8162c
prerequisite-patch-id: e58aa7d72a085408bccf3ba08774eda34804548c
prerequisite-patch-id: ed0319b770df843515910350348269d6eeb4c89c
prerequisite-patch-id: 89dfbe30d51576960af2b726523d75fe9130f6c6
--
2.26.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 1/2] sifive_e: Rename memmap enum constants
2020-09-11 17:34 ` Eduardo Habkost
@ 2020-09-11 17:34 ` Eduardo Habkost
-1 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, qemu-riscv, Sagar Karandikar,
Bastian Koppelmann, Alistair Francis, Palmer Dabbelt
Some of the enum constant names conflict with a QOM type check
macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
transform the QOM type check macros into functions generated by
OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v3 -> v4:
* Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
Link to v3:
https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat.com/
Changes v2 -> v3: none
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/riscv/sifive_e.h | 38 ++++++++---------
hw/riscv/sifive_e.c | 82 ++++++++++++++++++-------------------
2 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index b1400843c2..83604da805 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -53,25 +53,25 @@ typedef struct SiFiveEState {
OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
enum {
- SIFIVE_E_DEBUG,
- SIFIVE_E_MROM,
- SIFIVE_E_OTP,
- SIFIVE_E_CLINT,
- SIFIVE_E_PLIC,
- SIFIVE_E_AON,
- SIFIVE_E_PRCI,
- SIFIVE_E_OTP_CTRL,
- SIFIVE_E_GPIO0,
- SIFIVE_E_UART0,
- SIFIVE_E_QSPI0,
- SIFIVE_E_PWM0,
- SIFIVE_E_UART1,
- SIFIVE_E_QSPI1,
- SIFIVE_E_PWM1,
- SIFIVE_E_QSPI2,
- SIFIVE_E_PWM2,
- SIFIVE_E_XIP,
- SIFIVE_E_DTIM
+ SIFIVE_E_DEV_DEBUG,
+ SIFIVE_E_DEV_MROM,
+ SIFIVE_E_DEV_OTP,
+ SIFIVE_E_DEV_CLINT,
+ SIFIVE_E_DEV_PLIC,
+ SIFIVE_E_DEV_AON,
+ SIFIVE_E_DEV_PRCI,
+ SIFIVE_E_DEV_OTP_CTRL,
+ SIFIVE_E_DEV_GPIO0,
+ SIFIVE_E_DEV_UART0,
+ SIFIVE_E_DEV_QSPI0,
+ SIFIVE_E_DEV_PWM0,
+ SIFIVE_E_DEV_UART1,
+ SIFIVE_E_DEV_QSPI1,
+ SIFIVE_E_DEV_PWM1,
+ SIFIVE_E_DEV_QSPI2,
+ SIFIVE_E_DEV_PWM2,
+ SIFIVE_E_DEV_XIP,
+ SIFIVE_E_DEV_DTIM
};
enum {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 40bbf530d4..759059cd7b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -54,25 +54,25 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_e_memmap[] = {
- [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
- [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
- [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
- [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
- [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
- [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
- [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
- [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
- [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
- [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
- [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
- [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
- [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
- [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
- [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
- [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
+ [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
+ [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
+ [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
+ [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
+ [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
+ [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
+ [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
+ [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
+ [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
+ [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
+ [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
+ [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
+ [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
+ [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
};
static void sifive_e_machine_init(MachineState *machine)
@@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
/* Data Tightly Integrated Memory */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
- memmap[SIFIVE_E_DTIM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_DTIM].base, main_mem);
+ memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
/* Mask ROM reset vector */
uint32_t reset_vec[4];
@@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_E_MROM].base, &address_space_memory);
+ memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename, NULL);
@@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
- memmap[SIFIVE_E_MROM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_MROM].base, &s->mask_rom);
+ memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
(char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
SIFIVE_E_PLIC_NUM_SOURCES,
SIFIVE_E_PLIC_NUM_PRIORITIES,
@@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_ENABLE_STRIDE,
SIFIVE_E_PLIC_CONTEXT_BASE,
SIFIVE_E_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_E_PLIC].size);
- sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
+ memmap[SIFIVE_E_DEV_PLIC].size);
+ sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
+ memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
create_unimplemented_device("riscv.sifive.e.aon",
- memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
- sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
+ memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
+ sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
/* GPIO */
@@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
}
/* Map GPIO registers */
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_GPIO0_IRQ0 + i));
}
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi0",
- memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
+ memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
create_unimplemented_device("riscv.sifive.e.pwm0",
- memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
+ memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi1",
- memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
+ memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
create_unimplemented_device("riscv.sifive.e.pwm1",
- memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
+ memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
create_unimplemented_device("riscv.sifive.e.qspi2",
- memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
+ memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
create_unimplemented_device("riscv.sifive.e.pwm2",
- memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
+ memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
/* Flash memory */
memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
- memmap[SIFIVE_E_XIP].size, &error_fatal);
- memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
+ memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
+ memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
&s->xip_mem);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 1/2] sifive_e: Rename memmap enum constants
@ 2020-09-11 17:34 ` Eduardo Habkost
0 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, Bastian Koppelmann, Alistair Francis,
qemu-riscv, Sagar Karandikar, Palmer Dabbelt
Some of the enum constant names conflict with a QOM type check
macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
transform the QOM type check macros into functions generated by
OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v3 -> v4:
* Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
Link to v3:
https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat.com/
Changes v2 -> v3: none
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/riscv/sifive_e.h | 38 ++++++++---------
hw/riscv/sifive_e.c | 82 ++++++++++++++++++-------------------
2 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index b1400843c2..83604da805 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -53,25 +53,25 @@ typedef struct SiFiveEState {
OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
enum {
- SIFIVE_E_DEBUG,
- SIFIVE_E_MROM,
- SIFIVE_E_OTP,
- SIFIVE_E_CLINT,
- SIFIVE_E_PLIC,
- SIFIVE_E_AON,
- SIFIVE_E_PRCI,
- SIFIVE_E_OTP_CTRL,
- SIFIVE_E_GPIO0,
- SIFIVE_E_UART0,
- SIFIVE_E_QSPI0,
- SIFIVE_E_PWM0,
- SIFIVE_E_UART1,
- SIFIVE_E_QSPI1,
- SIFIVE_E_PWM1,
- SIFIVE_E_QSPI2,
- SIFIVE_E_PWM2,
- SIFIVE_E_XIP,
- SIFIVE_E_DTIM
+ SIFIVE_E_DEV_DEBUG,
+ SIFIVE_E_DEV_MROM,
+ SIFIVE_E_DEV_OTP,
+ SIFIVE_E_DEV_CLINT,
+ SIFIVE_E_DEV_PLIC,
+ SIFIVE_E_DEV_AON,
+ SIFIVE_E_DEV_PRCI,
+ SIFIVE_E_DEV_OTP_CTRL,
+ SIFIVE_E_DEV_GPIO0,
+ SIFIVE_E_DEV_UART0,
+ SIFIVE_E_DEV_QSPI0,
+ SIFIVE_E_DEV_PWM0,
+ SIFIVE_E_DEV_UART1,
+ SIFIVE_E_DEV_QSPI1,
+ SIFIVE_E_DEV_PWM1,
+ SIFIVE_E_DEV_QSPI2,
+ SIFIVE_E_DEV_PWM2,
+ SIFIVE_E_DEV_XIP,
+ SIFIVE_E_DEV_DTIM
};
enum {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 40bbf530d4..759059cd7b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -54,25 +54,25 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_e_memmap[] = {
- [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
- [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
- [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
- [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
- [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
- [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
- [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
- [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
- [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
- [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
- [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
- [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
- [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
- [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
- [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
- [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
+ [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
+ [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
+ [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
+ [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
+ [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
+ [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
+ [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
+ [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
+ [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
+ [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
+ [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
+ [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
+ [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
+ [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
+ [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
};
static void sifive_e_machine_init(MachineState *machine)
@@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
/* Data Tightly Integrated Memory */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
- memmap[SIFIVE_E_DTIM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_DTIM].base, main_mem);
+ memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
/* Mask ROM reset vector */
uint32_t reset_vec[4];
@@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_E_MROM].base, &address_space_memory);
+ memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename, NULL);
@@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
- memmap[SIFIVE_E_MROM].size, &error_fatal);
+ memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
- memmap[SIFIVE_E_MROM].base, &s->mask_rom);
+ memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
(char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
SIFIVE_E_PLIC_NUM_SOURCES,
SIFIVE_E_PLIC_NUM_PRIORITIES,
@@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_ENABLE_STRIDE,
SIFIVE_E_PLIC_CONTEXT_BASE,
SIFIVE_E_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_E_PLIC].size);
- sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
+ memmap[SIFIVE_E_DEV_PLIC].size);
+ sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
+ memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
create_unimplemented_device("riscv.sifive.e.aon",
- memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
- sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
+ memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
+ sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
/* GPIO */
@@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
}
/* Map GPIO registers */
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_GPIO0_IRQ0 + i));
}
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi0",
- memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
+ memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
create_unimplemented_device("riscv.sifive.e.pwm0",
- memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
- sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
+ memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
+ sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
create_unimplemented_device("riscv.sifive.e.qspi1",
- memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
+ memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
create_unimplemented_device("riscv.sifive.e.pwm1",
- memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
+ memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
create_unimplemented_device("riscv.sifive.e.qspi2",
- memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
+ memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
create_unimplemented_device("riscv.sifive.e.pwm2",
- memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
+ memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
/* Flash memory */
memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
- memmap[SIFIVE_E_XIP].size, &error_fatal);
- memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
+ memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
+ memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
&s->xip_mem);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/2] sifive_u: Rename memmap enum constants
2020-09-11 17:34 ` Eduardo Habkost
@ 2020-09-11 17:34 ` Eduardo Habkost
-1 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, qemu-riscv, Sagar Karandikar,
Bastian Koppelmann, Alistair Francis, Palmer Dabbelt
Some of the enum constant names conflict with the QOM type check
macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
to allow us to transform the QOM type check macros into functions
generated by OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v3 -> v4:
* Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
Link to v3:
https://lore.kernel.org/qemu-devel/20200825192110.3528606-10-ehabkost@redhat.com/
Changes v2 -> v3:
* Solved conflicts on rebase to latest qemu.git
* As this is a new patch, Reviewed-by lines from Alistair Francis
and Daniel P. Berrangé were dropped
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/riscv/sifive_u.h | 34 ++++----
hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
2 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index fe5c580845..22e7e6efa1 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -70,23 +70,23 @@ typedef struct SiFiveUState {
} SiFiveUState;
enum {
- SIFIVE_U_DEBUG,
- SIFIVE_U_MROM,
- SIFIVE_U_CLINT,
- SIFIVE_U_L2CC,
- SIFIVE_U_PDMA,
- SIFIVE_U_L2LIM,
- SIFIVE_U_PLIC,
- SIFIVE_U_PRCI,
- SIFIVE_U_UART0,
- SIFIVE_U_UART1,
- SIFIVE_U_GPIO,
- SIFIVE_U_OTP,
- SIFIVE_U_DMC,
- SIFIVE_U_FLASH0,
- SIFIVE_U_DRAM,
- SIFIVE_U_GEM,
- SIFIVE_U_GEM_MGMT
+ SIFIVE_U_DEV_DEBUG,
+ SIFIVE_U_DEV_MROM,
+ SIFIVE_U_DEV_CLINT,
+ SIFIVE_U_DEV_L2CC,
+ SIFIVE_U_DEV_PDMA,
+ SIFIVE_U_DEV_L2LIM,
+ SIFIVE_U_DEV_PLIC,
+ SIFIVE_U_DEV_PRCI,
+ SIFIVE_U_DEV_UART0,
+ SIFIVE_U_DEV_UART1,
+ SIFIVE_U_DEV_GPIO,
+ SIFIVE_U_DEV_OTP,
+ SIFIVE_U_DEV_DMC,
+ SIFIVE_U_DEV_FLASH0,
+ SIFIVE_U_DEV_DRAM,
+ SIFIVE_U_DEV_GEM,
+ SIFIVE_U_DEV_GEM_MGMT
};
enum {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4f12a93188..a97637fb33 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -70,23 +70,23 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
- [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
- [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
- [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
- [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
- [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
- [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
- [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
- [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
- [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
+ [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
+ [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
+ [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
+ [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
+ [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
+ [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
+ [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
@@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx",
- (long)memmap[SIFIVE_U_DRAM].base);
+ (long)memmap[SIFIVE_U_DEV_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
mem_size >> 32, mem_size);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
g_free(nodename);
@@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/clint@%lx",
- (long)memmap[SIFIVE_U_CLINT].base);
+ (long)memmap[SIFIVE_U_DEV_CLINT].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_CLINT].base,
- 0x0, memmap[SIFIVE_U_CLINT].size);
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
nodename = g_strdup_printf("/soc/otp@%lx",
- (long)memmap[SIFIVE_U_OTP].base);
+ (long)memmap[SIFIVE_U_DEV_OTP].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_OTP].base,
- 0x0, memmap[SIFIVE_U_OTP].size);
+ 0x0, memmap[SIFIVE_U_DEV_OTP].base,
+ 0x0, memmap[SIFIVE_U_DEV_OTP].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-otp");
g_free(nodename);
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
- (long)memmap[SIFIVE_U_PRCI].base);
+ (long)memmap[SIFIVE_U_DEV_PRCI].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
hfclk_phandle, rtcclk_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PRCI].base,
- 0x0, memmap[SIFIVE_U_PRCI].size);
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-prci");
g_free(nodename);
@@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
- (long)memmap[SIFIVE_U_PLIC].base);
+ (long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PLIC].base,
- 0x0, memmap[SIFIVE_U_PLIC].size);
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
- (long)memmap[SIFIVE_U_GPIO].base);
+ (long)memmap[SIFIVE_U_DEV_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
@@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GPIO].base,
- 0x0, memmap[SIFIVE_U_GPIO].size);
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
@@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/dma@%lx",
- (long)memmap[SIFIVE_U_PDMA].base);
+ (long)memmap[SIFIVE_U_DEV_PDMA].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
@@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PDMA].base,
- 0x0, memmap[SIFIVE_U_PDMA].size);
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-pdma");
g_free(nodename);
nodename = g_strdup_printf("/soc/cache-controller@%lx",
- (long)memmap[SIFIVE_U_L2CC].base);
+ (long)memmap[SIFIVE_U_DEV_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_L2CC].base,
- 0x0, memmap[SIFIVE_U_L2CC].size);
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-gem");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GEM].base,
- 0x0, memmap[SIFIVE_U_GEM].size,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+ 0x0, memmap[SIFIVE_U_DEV_GEM].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM].size,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
@@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
- (long)memmap[SIFIVE_U_UART0].base);
+ (long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_UART0].base,
- 0x0, memmap[SIFIVE_U_UART0].size);
+ 0x0, memmap[SIFIVE_U_DEV_UART0].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART0].size);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machine)
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
main_mem);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
- memmap[SIFIVE_U_FLASH0].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
flash0);
/* register gpio-restart */
@@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machine)
switch (s->msel) {
case MSEL_MEMMAP_QSPI0_FLASH:
- start_addr = memmap[SIFIVE_U_FLASH0].base;
+ start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
break;
case MSEL_L2LIM_QSPI0_FLASH:
case MSEL_L2LIM_QSPI2_SD:
- start_addr = memmap[SIFIVE_U_L2LIM].base;
+ start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
break;
default:
- start_addr = memmap[SIFIVE_U_DRAM].base;
+ start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
break;
}
@@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
@@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_U_MROM].base, &address_space_memory);
+ memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
- memmap[SIFIVE_U_MROM].size,
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
}
@@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
mask_rom);
/*
@@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
- memmap[SIFIVE_U_L2LIM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
@@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config, 0,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
@@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_U_PLIC].size);
+ memmap[SIFIVE_U_DEV_PLIC].size);
g_free(plic_hart_config);
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
+ sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+ memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* PDMA */
sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
/* Connect PDMA interrupts to the PLIC */
for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
@@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd->used) {
@@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
- memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+ memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
create_unimplemented_device("riscv.sifive.u.dmc",
- memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+ memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
create_unimplemented_device("riscv.sifive.u.l2cc",
- memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
+ memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
}
static Property sifive_u_soc_props[] = {
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/2] sifive_u: Rename memmap enum constants
@ 2020-09-11 17:34 ` Eduardo Habkost
0 siblings, 0 replies; 10+ messages in thread
From: Eduardo Habkost @ 2020-09-11 17:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel P. Berrange, Bastian Koppelmann, Alistair Francis,
qemu-riscv, Sagar Karandikar, Palmer Dabbelt
Some of the enum constant names conflict with the QOM type check
macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
to allow us to transform the QOM type check macros into functions
generated by OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v3 -> v4:
* Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
Link to v3:
https://lore.kernel.org/qemu-devel/20200825192110.3528606-10-ehabkost@redhat.com/
Changes v2 -> v3:
* Solved conflicts on rebase to latest qemu.git
* As this is a new patch, Reviewed-by lines from Alistair Francis
and Daniel P. Berrangé were dropped
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/riscv/sifive_u.h | 34 ++++----
hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
2 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index fe5c580845..22e7e6efa1 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -70,23 +70,23 @@ typedef struct SiFiveUState {
} SiFiveUState;
enum {
- SIFIVE_U_DEBUG,
- SIFIVE_U_MROM,
- SIFIVE_U_CLINT,
- SIFIVE_U_L2CC,
- SIFIVE_U_PDMA,
- SIFIVE_U_L2LIM,
- SIFIVE_U_PLIC,
- SIFIVE_U_PRCI,
- SIFIVE_U_UART0,
- SIFIVE_U_UART1,
- SIFIVE_U_GPIO,
- SIFIVE_U_OTP,
- SIFIVE_U_DMC,
- SIFIVE_U_FLASH0,
- SIFIVE_U_DRAM,
- SIFIVE_U_GEM,
- SIFIVE_U_GEM_MGMT
+ SIFIVE_U_DEV_DEBUG,
+ SIFIVE_U_DEV_MROM,
+ SIFIVE_U_DEV_CLINT,
+ SIFIVE_U_DEV_L2CC,
+ SIFIVE_U_DEV_PDMA,
+ SIFIVE_U_DEV_L2LIM,
+ SIFIVE_U_DEV_PLIC,
+ SIFIVE_U_DEV_PRCI,
+ SIFIVE_U_DEV_UART0,
+ SIFIVE_U_DEV_UART1,
+ SIFIVE_U_DEV_GPIO,
+ SIFIVE_U_DEV_OTP,
+ SIFIVE_U_DEV_DMC,
+ SIFIVE_U_DEV_FLASH0,
+ SIFIVE_U_DEV_DRAM,
+ SIFIVE_U_DEV_GEM,
+ SIFIVE_U_DEV_GEM_MGMT
};
enum {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4f12a93188..a97637fb33 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -70,23 +70,23 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
- [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
- [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
- [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
- [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
- [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
- [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
- [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
- [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
- [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
+ [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
+ [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
+ [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
+ [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
+ [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
+ [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
+ [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
@@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx",
- (long)memmap[SIFIVE_U_DRAM].base);
+ (long)memmap[SIFIVE_U_DEV_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
mem_size >> 32, mem_size);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
g_free(nodename);
@@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/clint@%lx",
- (long)memmap[SIFIVE_U_CLINT].base);
+ (long)memmap[SIFIVE_U_DEV_CLINT].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_CLINT].base,
- 0x0, memmap[SIFIVE_U_CLINT].size);
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
nodename = g_strdup_printf("/soc/otp@%lx",
- (long)memmap[SIFIVE_U_OTP].base);
+ (long)memmap[SIFIVE_U_DEV_OTP].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_OTP].base,
- 0x0, memmap[SIFIVE_U_OTP].size);
+ 0x0, memmap[SIFIVE_U_DEV_OTP].base,
+ 0x0, memmap[SIFIVE_U_DEV_OTP].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-otp");
g_free(nodename);
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
- (long)memmap[SIFIVE_U_PRCI].base);
+ (long)memmap[SIFIVE_U_DEV_PRCI].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
hfclk_phandle, rtcclk_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PRCI].base,
- 0x0, memmap[SIFIVE_U_PRCI].size);
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-prci");
g_free(nodename);
@@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
- (long)memmap[SIFIVE_U_PLIC].base);
+ (long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PLIC].base,
- 0x0, memmap[SIFIVE_U_PLIC].size);
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
- (long)memmap[SIFIVE_U_GPIO].base);
+ (long)memmap[SIFIVE_U_DEV_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
@@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GPIO].base,
- 0x0, memmap[SIFIVE_U_GPIO].size);
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
@@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/dma@%lx",
- (long)memmap[SIFIVE_U_PDMA].base);
+ (long)memmap[SIFIVE_U_DEV_PDMA].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
@@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PDMA].base,
- 0x0, memmap[SIFIVE_U_PDMA].size);
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
+ 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-pdma");
g_free(nodename);
nodename = g_strdup_printf("/soc/cache-controller@%lx",
- (long)memmap[SIFIVE_U_L2CC].base);
+ (long)memmap[SIFIVE_U_DEV_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_L2CC].base,
- 0x0, memmap[SIFIVE_U_L2CC].size);
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-gem");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GEM].base,
- 0x0, memmap[SIFIVE_U_GEM].size,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+ 0x0, memmap[SIFIVE_U_DEV_GEM].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM].size,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
@@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
- (long)memmap[SIFIVE_U_UART0].base);
+ (long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_UART0].base,
- 0x0, memmap[SIFIVE_U_UART0].size);
+ 0x0, memmap[SIFIVE_U_DEV_UART0].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART0].size);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machine)
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
main_mem);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
- memmap[SIFIVE_U_FLASH0].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
flash0);
/* register gpio-restart */
@@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machine)
switch (s->msel) {
case MSEL_MEMMAP_QSPI0_FLASH:
- start_addr = memmap[SIFIVE_U_FLASH0].base;
+ start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
break;
case MSEL_L2LIM_QSPI0_FLASH:
case MSEL_L2LIM_QSPI2_SD:
- start_addr = memmap[SIFIVE_U_L2LIM].base;
+ start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
break;
default:
- start_addr = memmap[SIFIVE_U_DRAM].base;
+ start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
break;
}
@@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
@@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_U_MROM].base, &address_space_memory);
+ memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
- memmap[SIFIVE_U_MROM].size,
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
}
@@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
mask_rom);
/*
@@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
- memmap[SIFIVE_U_L2LIM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
@@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config, 0,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
@@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_U_PLIC].size);
+ memmap[SIFIVE_U_DEV_PLIC].size);
g_free(plic_hart_config);
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
+ sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+ memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* PDMA */
sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
/* Connect PDMA interrupts to the PLIC */
for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
@@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd->used) {
@@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
- memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+ memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
create_unimplemented_device("riscv.sifive.u.dmc",
- memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+ memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
create_unimplemented_device("riscv.sifive.u.l2cc",
- memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
+ memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
}
static Property sifive_u_soc_props[] = {
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] sifive_u: Rename memmap enum constants
2020-09-11 17:34 ` Eduardo Habkost
@ 2020-09-11 20:33 ` Alistair Francis
-1 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2020-09-11 20:33 UTC (permalink / raw)
To: Eduardo Habkost
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Daniel P. Berrange, Palmer Dabbelt
On Fri, Sep 11, 2020 at 10:35 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
> to allow us to transform the QOM type check macros into functions
> generated by OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Changes v3 -> v4:
> * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
>
> Link to v3:
> https://lore.kernel.org/qemu-devel/20200825192110.3528606-10-ehabkost@redhat.com/
>
> Changes v2 -> v3:
> * Solved conflicts on rebase to latest qemu.git
> * As this is a new patch, Reviewed-by lines from Alistair Francis
> and Daniel P. Berrangé were dropped
>
> Changes v1 -> v2:
> * Added more details to commit message
> ---
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: qemu-riscv@nongnu.org
> Cc: qemu-devel@nongnu.org
> ---
> include/hw/riscv/sifive_u.h | 34 ++++----
> hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
> 2 files changed, 95 insertions(+), 95 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index fe5c580845..22e7e6efa1 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -70,23 +70,23 @@ typedef struct SiFiveUState {
> } SiFiveUState;
>
> enum {
> - SIFIVE_U_DEBUG,
> - SIFIVE_U_MROM,
> - SIFIVE_U_CLINT,
> - SIFIVE_U_L2CC,
> - SIFIVE_U_PDMA,
> - SIFIVE_U_L2LIM,
> - SIFIVE_U_PLIC,
> - SIFIVE_U_PRCI,
> - SIFIVE_U_UART0,
> - SIFIVE_U_UART1,
> - SIFIVE_U_GPIO,
> - SIFIVE_U_OTP,
> - SIFIVE_U_DMC,
> - SIFIVE_U_FLASH0,
> - SIFIVE_U_DRAM,
> - SIFIVE_U_GEM,
> - SIFIVE_U_GEM_MGMT
> + SIFIVE_U_DEV_DEBUG,
> + SIFIVE_U_DEV_MROM,
> + SIFIVE_U_DEV_CLINT,
> + SIFIVE_U_DEV_L2CC,
> + SIFIVE_U_DEV_PDMA,
> + SIFIVE_U_DEV_L2LIM,
> + SIFIVE_U_DEV_PLIC,
> + SIFIVE_U_DEV_PRCI,
> + SIFIVE_U_DEV_UART0,
> + SIFIVE_U_DEV_UART1,
> + SIFIVE_U_DEV_GPIO,
> + SIFIVE_U_DEV_OTP,
> + SIFIVE_U_DEV_DMC,
> + SIFIVE_U_DEV_FLASH0,
> + SIFIVE_U_DEV_DRAM,
> + SIFIVE_U_DEV_GEM,
> + SIFIVE_U_DEV_GEM_MGMT
> };
>
> enum {
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 4f12a93188..a97637fb33 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -70,23 +70,23 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_u_memmap[] = {
> - [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
> - [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
> - [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
> - [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
> - [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
> - [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
> - [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
> - [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> - [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> - [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> - [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> - [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> - [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> + [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
> + [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
> + [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
> + [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
> + [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
> + [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
> + [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
> + [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
> + [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
> + [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
> + [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
> + [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
> + [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
> + [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
> + [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> @@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/memory@%lx",
> - (long)memmap[SIFIVE_U_DRAM].base);
> + (long)memmap[SIFIVE_U_DEV_DRAM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
> + memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
> mem_size >> 32, mem_size);
> qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
> g_free(nodename);
> @@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
> nodename = g_strdup_printf("/soc/clint@%lx",
> - (long)memmap[SIFIVE_U_CLINT].base);
> + (long)memmap[SIFIVE_U_DEV_CLINT].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_CLINT].base,
> - 0x0, memmap[SIFIVE_U_CLINT].size);
> + 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
> + 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> cells, ms->smp.cpus * sizeof(uint32_t) * 4);
> g_free(cells);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/otp@%lx",
> - (long)memmap[SIFIVE_U_OTP].base);
> + (long)memmap[SIFIVE_U_DEV_OTP].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_OTP].base,
> - 0x0, memmap[SIFIVE_U_OTP].size);
> + 0x0, memmap[SIFIVE_U_DEV_OTP].base,
> + 0x0, memmap[SIFIVE_U_DEV_OTP].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-otp");
> g_free(nodename);
>
> prci_phandle = phandle++;
> nodename = g_strdup_printf("/soc/clock-controller@%lx",
> - (long)memmap[SIFIVE_U_PRCI].base);
> + (long)memmap[SIFIVE_U_DEV_PRCI].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> hfclk_phandle, rtcclk_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PRCI].base,
> - 0x0, memmap[SIFIVE_U_PRCI].size);
> + 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
> + 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-prci");
> g_free(nodename);
> @@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
> nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
> - (long)memmap[SIFIVE_U_PLIC].base);
> + (long)memmap[SIFIVE_U_DEV_PLIC].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
> @@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PLIC].base,
> - 0x0, memmap[SIFIVE_U_PLIC].size);
> + 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
> + 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> @@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> gpio_phandle = phandle++;
> nodename = g_strdup_printf("/soc/gpio@%lx",
> - (long)memmap[SIFIVE_U_GPIO].base);
> + (long)memmap[SIFIVE_U_DEV_GPIO].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> @@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
> qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_GPIO].base,
> - 0x0, memmap[SIFIVE_U_GPIO].size);
> + 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
> + 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
> SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
> SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
> @@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/dma@%lx",
> - (long)memmap[SIFIVE_U_PDMA].base);
> + (long)memmap[SIFIVE_U_DEV_PDMA].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> @@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PDMA].base,
> - 0x0, memmap[SIFIVE_U_PDMA].size);
> + 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
> + 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-pdma");
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/cache-controller@%lx",
> - (long)memmap[SIFIVE_U_L2CC].base);
> + (long)memmap[SIFIVE_U_DEV_L2CC].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_L2CC].base,
> - 0x0, memmap[SIFIVE_U_L2CC].size);
> + 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
> + 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> @@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> - (long)memmap[SIFIVE_U_GEM].base);
> + (long)memmap[SIFIVE_U_DEV_GEM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-gem");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_GEM].base,
> - 0x0, memmap[SIFIVE_U_GEM].size,
> - 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
> - 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
> + 0x0, memmap[SIFIVE_U_DEV_GEM].base,
> + 0x0, memmap[SIFIVE_U_DEV_GEM].size,
> + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
> + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
> qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
> @@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
> - (long)memmap[SIFIVE_U_GEM].base);
> + (long)memmap[SIFIVE_U_DEV_GEM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/serial@%lx",
> - (long)memmap[SIFIVE_U_UART0].base);
> + (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_UART0].base,
> - 0x0, memmap[SIFIVE_U_UART0].size);
> + 0x0, memmap[SIFIVE_U_DEV_UART0].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART0].size);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> prci_phandle, PRCI_CLK_TLCLK);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> @@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *flash0 = g_new(MemoryRegion, 1);
> - target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
> + target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> uint32_t start_addr_hi32 = 0x00000000;
> int i;
> uint32_t fdt_load_addr;
> @@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machine)
> /* register RAM */
> memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
> machine->ram_size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
> main_mem);
>
> /* register QSPI0 Flash */
> memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
> - memmap[SIFIVE_U_FLASH0].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
> + memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
> flash0);
>
> /* register gpio-restart */
> @@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machine)
>
> switch (s->msel) {
> case MSEL_MEMMAP_QSPI0_FLASH:
> - start_addr = memmap[SIFIVE_U_FLASH0].base;
> + start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
> break;
> case MSEL_L2LIM_QSPI0_FLASH:
> case MSEL_L2LIM_QSPI2_SD:
> - start_addr = memmap[SIFIVE_U_L2LIM].base;
> + start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
> break;
> default:
> - start_addr = memmap[SIFIVE_U_DRAM].base;
> + start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> break;
> }
>
> @@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine)
> }
>
> /* Compute the fdt load address in dram */
> - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
> + fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
> machine->ram_size, s->fdt);
> #if defined(TARGET_RISCV64)
> start_addr_hi32 = start_addr >> 32;
> @@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machine)
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> }
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> - memmap[SIFIVE_U_MROM].base, &address_space_memory);
> + memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
>
> - riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
> - memmap[SIFIVE_U_MROM].size,
> + riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
> + memmap[SIFIVE_U_DEV_MROM].size,
> sizeof(reset_vec), kernel_entry);
> }
>
> @@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> /* boot rom */
> memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
> - memmap[SIFIVE_U_MROM].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
> + memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
> mask_rom);
>
> /*
> @@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> * too generous to misbehaving guests.
> */
> memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
> - memmap[SIFIVE_U_L2LIM].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
> + memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> @@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* MMIO */
> - s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
> + s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
> plic_hart_config, 0,
> SIFIVE_U_PLIC_NUM_SOURCES,
> SIFIVE_U_PLIC_NUM_PRIORITIES,
> @@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_U_PLIC_ENABLE_STRIDE,
> SIFIVE_U_PLIC_CONTEXT_BASE,
> SIFIVE_U_PLIC_CONTEXT_STRIDE,
> - memmap[SIFIVE_U_PLIC].size);
> + memmap[SIFIVE_U_DEV_PLIC].size);
> g_free(plic_hart_config);
> - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
> + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
> - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
> - sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
> - memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
> + sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
> + memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> SIFIVE_CLINT_TIMEBASE_FREQ, false);
>
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
>
> qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
>
> /* Pass all GPIOs to the SOC layer so they are available to the board */
> qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> @@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> /* PDMA */
> sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
>
> /* Connect PDMA interrupts to the PLIC */
> for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
> @@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
>
> /* FIXME use qdev NIC properties instead of nd_table[] */
> if (nd->used) {
> @@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
> qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> - memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> + memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
>
> create_unimplemented_device("riscv.sifive.u.dmc",
> - memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
> + memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
>
> create_unimplemented_device("riscv.sifive.u.l2cc",
> - memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
> + memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
> }
>
> static Property sifive_u_soc_props[] = {
> --
> 2.26.2
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/2] sifive_u: Rename memmap enum constants
@ 2020-09-11 20:33 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2020-09-11 20:33 UTC (permalink / raw)
To: Eduardo Habkost
Cc: qemu-devel@nongnu.org Developers, Daniel P. Berrange,
open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt
On Fri, Sep 11, 2020 at 10:35 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> Some of the enum constant names conflict with the QOM type check
> macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
> to allow us to transform the QOM type check macros into functions
> generated by OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Changes v3 -> v4:
> * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
>
> Link to v3:
> https://lore.kernel.org/qemu-devel/20200825192110.3528606-10-ehabkost@redhat.com/
>
> Changes v2 -> v3:
> * Solved conflicts on rebase to latest qemu.git
> * As this is a new patch, Reviewed-by lines from Alistair Francis
> and Daniel P. Berrangé were dropped
>
> Changes v1 -> v2:
> * Added more details to commit message
> ---
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: qemu-riscv@nongnu.org
> Cc: qemu-devel@nongnu.org
> ---
> include/hw/riscv/sifive_u.h | 34 ++++----
> hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------
> 2 files changed, 95 insertions(+), 95 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index fe5c580845..22e7e6efa1 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -70,23 +70,23 @@ typedef struct SiFiveUState {
> } SiFiveUState;
>
> enum {
> - SIFIVE_U_DEBUG,
> - SIFIVE_U_MROM,
> - SIFIVE_U_CLINT,
> - SIFIVE_U_L2CC,
> - SIFIVE_U_PDMA,
> - SIFIVE_U_L2LIM,
> - SIFIVE_U_PLIC,
> - SIFIVE_U_PRCI,
> - SIFIVE_U_UART0,
> - SIFIVE_U_UART1,
> - SIFIVE_U_GPIO,
> - SIFIVE_U_OTP,
> - SIFIVE_U_DMC,
> - SIFIVE_U_FLASH0,
> - SIFIVE_U_DRAM,
> - SIFIVE_U_GEM,
> - SIFIVE_U_GEM_MGMT
> + SIFIVE_U_DEV_DEBUG,
> + SIFIVE_U_DEV_MROM,
> + SIFIVE_U_DEV_CLINT,
> + SIFIVE_U_DEV_L2CC,
> + SIFIVE_U_DEV_PDMA,
> + SIFIVE_U_DEV_L2LIM,
> + SIFIVE_U_DEV_PLIC,
> + SIFIVE_U_DEV_PRCI,
> + SIFIVE_U_DEV_UART0,
> + SIFIVE_U_DEV_UART1,
> + SIFIVE_U_DEV_GPIO,
> + SIFIVE_U_DEV_OTP,
> + SIFIVE_U_DEV_DMC,
> + SIFIVE_U_DEV_FLASH0,
> + SIFIVE_U_DEV_DRAM,
> + SIFIVE_U_DEV_GEM,
> + SIFIVE_U_DEV_GEM_MGMT
> };
>
> enum {
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 4f12a93188..a97637fb33 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -70,23 +70,23 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_u_memmap[] = {
> - [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
> - [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
> - [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
> - [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
> - [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
> - [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
> - [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
> - [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> - [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> - [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> - [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> - [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> - [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> + [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
> + [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
> + [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
> + [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
> + [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
> + [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
> + [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
> + [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
> + [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
> + [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
> + [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
> + [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
> + [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
> + [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
> + [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> @@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/memory@%lx",
> - (long)memmap[SIFIVE_U_DRAM].base);
> + (long)memmap[SIFIVE_U_DEV_DRAM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
> + memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
> mem_size >> 32, mem_size);
> qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
> g_free(nodename);
> @@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
> nodename = g_strdup_printf("/soc/clint@%lx",
> - (long)memmap[SIFIVE_U_CLINT].base);
> + (long)memmap[SIFIVE_U_DEV_CLINT].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_CLINT].base,
> - 0x0, memmap[SIFIVE_U_CLINT].size);
> + 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
> + 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> cells, ms->smp.cpus * sizeof(uint32_t) * 4);
> g_free(cells);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/otp@%lx",
> - (long)memmap[SIFIVE_U_OTP].base);
> + (long)memmap[SIFIVE_U_DEV_OTP].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_OTP].base,
> - 0x0, memmap[SIFIVE_U_OTP].size);
> + 0x0, memmap[SIFIVE_U_DEV_OTP].base,
> + 0x0, memmap[SIFIVE_U_DEV_OTP].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-otp");
> g_free(nodename);
>
> prci_phandle = phandle++;
> nodename = g_strdup_printf("/soc/clock-controller@%lx",
> - (long)memmap[SIFIVE_U_PRCI].base);
> + (long)memmap[SIFIVE_U_DEV_PRCI].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> hfclk_phandle, rtcclk_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PRCI].base,
> - 0x0, memmap[SIFIVE_U_PRCI].size);
> + 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
> + 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-prci");
> g_free(nodename);
> @@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
> nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
> - (long)memmap[SIFIVE_U_PLIC].base);
> + (long)memmap[SIFIVE_U_DEV_PLIC].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
> @@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PLIC].base,
> - 0x0, memmap[SIFIVE_U_PLIC].size);
> + 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
> + 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
> qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
> plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
> @@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> gpio_phandle = phandle++;
> nodename = g_strdup_printf("/soc/gpio@%lx",
> - (long)memmap[SIFIVE_U_GPIO].base);
> + (long)memmap[SIFIVE_U_DEV_GPIO].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> @@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
> qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_GPIO].base,
> - 0x0, memmap[SIFIVE_U_GPIO].size);
> + 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
> + 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
> SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
> SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
> @@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/dma@%lx",
> - (long)memmap[SIFIVE_U_PDMA].base);
> + (long)memmap[SIFIVE_U_DEV_PDMA].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> @@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_PDMA].base,
> - 0x0, memmap[SIFIVE_U_PDMA].size);
> + 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
> + 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-pdma");
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/cache-controller@%lx",
> - (long)memmap[SIFIVE_U_L2CC].base);
> + (long)memmap[SIFIVE_U_DEV_L2CC].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_L2CC].base,
> - 0x0, memmap[SIFIVE_U_L2CC].size);
> + 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
> + 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
> qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> @@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> - (long)memmap[SIFIVE_U_GEM].base);
> + (long)memmap[SIFIVE_U_DEV_GEM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible",
> "sifive,fu540-c000-gem");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_GEM].base,
> - 0x0, memmap[SIFIVE_U_GEM].size,
> - 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
> - 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
> + 0x0, memmap[SIFIVE_U_DEV_GEM].base,
> + 0x0, memmap[SIFIVE_U_DEV_GEM].size,
> + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
> + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
> qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
> qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
> qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
> @@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
> - (long)memmap[SIFIVE_U_GEM].base);
> + (long)memmap[SIFIVE_U_DEV_GEM].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> nodename = g_strdup_printf("/soc/serial@%lx",
> - (long)memmap[SIFIVE_U_UART0].base);
> + (long)memmap[SIFIVE_U_DEV_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> - 0x0, memmap[SIFIVE_U_UART0].base,
> - 0x0, memmap[SIFIVE_U_UART0].size);
> + 0x0, memmap[SIFIVE_U_DEV_UART0].base,
> + 0x0, memmap[SIFIVE_U_DEV_UART0].size);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> prci_phandle, PRCI_CLK_TLCLK);
> qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> @@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> MemoryRegion *flash0 = g_new(MemoryRegion, 1);
> - target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
> + target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> uint32_t start_addr_hi32 = 0x00000000;
> int i;
> uint32_t fdt_load_addr;
> @@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machine)
> /* register RAM */
> memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
> machine->ram_size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
> main_mem);
>
> /* register QSPI0 Flash */
> memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
> - memmap[SIFIVE_U_FLASH0].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
> + memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
> flash0);
>
> /* register gpio-restart */
> @@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machine)
>
> switch (s->msel) {
> case MSEL_MEMMAP_QSPI0_FLASH:
> - start_addr = memmap[SIFIVE_U_FLASH0].base;
> + start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
> break;
> case MSEL_L2LIM_QSPI0_FLASH:
> case MSEL_L2LIM_QSPI2_SD:
> - start_addr = memmap[SIFIVE_U_L2LIM].base;
> + start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
> break;
> default:
> - start_addr = memmap[SIFIVE_U_DRAM].base;
> + start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
> break;
> }
>
> @@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine)
> }
>
> /* Compute the fdt load address in dram */
> - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
> + fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
> machine->ram_size, s->fdt);
> #if defined(TARGET_RISCV64)
> start_addr_hi32 = start_addr >> 32;
> @@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machine)
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> }
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> - memmap[SIFIVE_U_MROM].base, &address_space_memory);
> + memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
>
> - riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
> - memmap[SIFIVE_U_MROM].size,
> + riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
> + memmap[SIFIVE_U_DEV_MROM].size,
> sizeof(reset_vec), kernel_entry);
> }
>
> @@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> /* boot rom */
> memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
> - memmap[SIFIVE_U_MROM].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
> + memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
> mask_rom);
>
> /*
> @@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> * too generous to misbehaving guests.
> */
> memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
> - memmap[SIFIVE_U_L2LIM].size, &error_fatal);
> - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
> + memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
> + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> @@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* MMIO */
> - s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
> + s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
> plic_hart_config, 0,
> SIFIVE_U_PLIC_NUM_SOURCES,
> SIFIVE_U_PLIC_NUM_PRIORITIES,
> @@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_U_PLIC_ENABLE_STRIDE,
> SIFIVE_U_PLIC_CONTEXT_BASE,
> SIFIVE_U_PLIC_CONTEXT_STRIDE,
> - memmap[SIFIVE_U_PLIC].size);
> + memmap[SIFIVE_U_DEV_PLIC].size);
> g_free(plic_hart_config);
> - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
> + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
> - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
> + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
> - sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
> - memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
> + sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
> + memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> SIFIVE_CLINT_TIMEBASE_FREQ, false);
>
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
>
> qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
>
> /* Pass all GPIOs to the SOC layer so they are available to the board */
> qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> @@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> /* PDMA */
> sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
>
> /* Connect PDMA interrupts to the PLIC */
> for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
> @@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
>
> /* FIXME use qdev NIC properties instead of nd_table[] */
> if (nd->used) {
> @@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
> return;
> }
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
> qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> - memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> + memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
>
> create_unimplemented_device("riscv.sifive.u.dmc",
> - memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
> + memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
>
> create_unimplemented_device("riscv.sifive.u.l2cc",
> - memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
> + memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
> }
>
> static Property sifive_u_soc_props[] = {
> --
> 2.26.2
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/2] sifive_e: Rename memmap enum constants
2020-09-11 17:34 ` Eduardo Habkost
@ 2020-09-11 20:33 ` Alistair Francis
-1 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2020-09-11 20:33 UTC (permalink / raw)
To: Eduardo Habkost
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Daniel P. Berrange, Palmer Dabbelt
On Fri, Sep 11, 2020 at 10:35 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> Some of the enum constant names conflict with a QOM type check
> macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
> transform the QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Changes v3 -> v4:
> * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
>
> Link to v3:
> https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat.com/
>
> Changes v2 -> v3: none
>
> Changes v1 -> v2:
> * Added more details to commit message
> ---
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: qemu-riscv@nongnu.org
> Cc: qemu-devel@nongnu.org
> ---
> include/hw/riscv/sifive_e.h | 38 ++++++++---------
> hw/riscv/sifive_e.c | 82 ++++++++++++++++++-------------------
> 2 files changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index b1400843c2..83604da805 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -53,25 +53,25 @@ typedef struct SiFiveEState {
> OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
>
> enum {
> - SIFIVE_E_DEBUG,
> - SIFIVE_E_MROM,
> - SIFIVE_E_OTP,
> - SIFIVE_E_CLINT,
> - SIFIVE_E_PLIC,
> - SIFIVE_E_AON,
> - SIFIVE_E_PRCI,
> - SIFIVE_E_OTP_CTRL,
> - SIFIVE_E_GPIO0,
> - SIFIVE_E_UART0,
> - SIFIVE_E_QSPI0,
> - SIFIVE_E_PWM0,
> - SIFIVE_E_UART1,
> - SIFIVE_E_QSPI1,
> - SIFIVE_E_PWM1,
> - SIFIVE_E_QSPI2,
> - SIFIVE_E_PWM2,
> - SIFIVE_E_XIP,
> - SIFIVE_E_DTIM
> + SIFIVE_E_DEV_DEBUG,
> + SIFIVE_E_DEV_MROM,
> + SIFIVE_E_DEV_OTP,
> + SIFIVE_E_DEV_CLINT,
> + SIFIVE_E_DEV_PLIC,
> + SIFIVE_E_DEV_AON,
> + SIFIVE_E_DEV_PRCI,
> + SIFIVE_E_DEV_OTP_CTRL,
> + SIFIVE_E_DEV_GPIO0,
> + SIFIVE_E_DEV_UART0,
> + SIFIVE_E_DEV_QSPI0,
> + SIFIVE_E_DEV_PWM0,
> + SIFIVE_E_DEV_UART1,
> + SIFIVE_E_DEV_QSPI1,
> + SIFIVE_E_DEV_PWM1,
> + SIFIVE_E_DEV_QSPI2,
> + SIFIVE_E_DEV_PWM2,
> + SIFIVE_E_DEV_XIP,
> + SIFIVE_E_DEV_DTIM
> };
>
> enum {
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 40bbf530d4..759059cd7b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -54,25 +54,25 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_e_memmap[] = {
> - [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> - [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> - [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> - [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> - [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
> - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> - [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
> - [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
> - [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
> - [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
> - [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
> - [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
> - [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
> - [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
> - [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
> - [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
> - [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
> - [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> + [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
> + [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
> + [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
> + [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
> + [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
> + [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
> + [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
> + [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
> + [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
> + [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
> + [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
> + [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
> + [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
> + [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
> + [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
> + [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
> };
>
> static void sifive_e_machine_init(MachineState *machine)
> @@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
>
> /* Data Tightly Integrated Memory */
> memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DTIM].size, &error_fatal);
> + memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine)
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> }
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> - memmap[SIFIVE_E_MROM].base, &address_space_memory);
> + memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
>
> if (machine->kernel_filename) {
> riscv_load_kernel(machine->kernel_filename, NULL);
> @@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
>
> /* Mask ROM */
> memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
> - memmap[SIFIVE_E_MROM].size, &error_fatal);
> + memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_MROM].base, &s->mask_rom);
> + memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
>
> /* MMIO */
> - s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
> + s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
> (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
> SIFIVE_E_PLIC_NUM_SOURCES,
> SIFIVE_E_PLIC_NUM_PRIORITIES,
> @@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_E_PLIC_ENABLE_STRIDE,
> SIFIVE_E_PLIC_CONTEXT_BASE,
> SIFIVE_E_PLIC_CONTEXT_STRIDE,
> - memmap[SIFIVE_E_PLIC].size);
> - sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> - memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
> + memmap[SIFIVE_E_DEV_PLIC].size);
> + sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
> + memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> SIFIVE_CLINT_TIMEBASE_FREQ, false);
> create_unimplemented_device("riscv.sifive.e.aon",
> - memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> - sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
> + memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
> + sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
>
> /* GPIO */
>
> @@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* Map GPIO registers */
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
>
> /* Pass all GPIOs to the SOC layer so they are available to the board */
> qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> @@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_E_GPIO0_IRQ0 + i));
> }
>
> - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
> + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
> create_unimplemented_device("riscv.sifive.e.qspi0",
> - memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
> + memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
> create_unimplemented_device("riscv.sifive.e.pwm0",
> - memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
> - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
> + memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
> + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
> create_unimplemented_device("riscv.sifive.e.qspi1",
> - memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
> + memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
> create_unimplemented_device("riscv.sifive.e.pwm1",
> - memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
> + memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
> create_unimplemented_device("riscv.sifive.e.qspi2",
> - memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
> + memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
> create_unimplemented_device("riscv.sifive.e.pwm2",
> - memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
> + memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
>
> /* Flash memory */
> memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
> - memmap[SIFIVE_E_XIP].size, &error_fatal);
> - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
> + memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
> + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
> &s->xip_mem);
> }
>
> --
> 2.26.2
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/2] sifive_e: Rename memmap enum constants
@ 2020-09-11 20:33 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2020-09-11 20:33 UTC (permalink / raw)
To: Eduardo Habkost
Cc: qemu-devel@nongnu.org Developers, Daniel P. Berrange,
open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt
On Fri, Sep 11, 2020 at 10:35 AM Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> Some of the enum constant names conflict with a QOM type check
> macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
> transform the QOM type check macros into functions generated by
> OBJECT_DECLARE_TYPE().
>
> Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> Changes v3 -> v4:
> * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910
>
> Link to v3:
> https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat.com/
>
> Changes v2 -> v3: none
>
> Changes v1 -> v2:
> * Added more details to commit message
> ---
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: qemu-riscv@nongnu.org
> Cc: qemu-devel@nongnu.org
> ---
> include/hw/riscv/sifive_e.h | 38 ++++++++---------
> hw/riscv/sifive_e.c | 82 ++++++++++++++++++-------------------
> 2 files changed, 60 insertions(+), 60 deletions(-)
>
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index b1400843c2..83604da805 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -53,25 +53,25 @@ typedef struct SiFiveEState {
> OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
>
> enum {
> - SIFIVE_E_DEBUG,
> - SIFIVE_E_MROM,
> - SIFIVE_E_OTP,
> - SIFIVE_E_CLINT,
> - SIFIVE_E_PLIC,
> - SIFIVE_E_AON,
> - SIFIVE_E_PRCI,
> - SIFIVE_E_OTP_CTRL,
> - SIFIVE_E_GPIO0,
> - SIFIVE_E_UART0,
> - SIFIVE_E_QSPI0,
> - SIFIVE_E_PWM0,
> - SIFIVE_E_UART1,
> - SIFIVE_E_QSPI1,
> - SIFIVE_E_PWM1,
> - SIFIVE_E_QSPI2,
> - SIFIVE_E_PWM2,
> - SIFIVE_E_XIP,
> - SIFIVE_E_DTIM
> + SIFIVE_E_DEV_DEBUG,
> + SIFIVE_E_DEV_MROM,
> + SIFIVE_E_DEV_OTP,
> + SIFIVE_E_DEV_CLINT,
> + SIFIVE_E_DEV_PLIC,
> + SIFIVE_E_DEV_AON,
> + SIFIVE_E_DEV_PRCI,
> + SIFIVE_E_DEV_OTP_CTRL,
> + SIFIVE_E_DEV_GPIO0,
> + SIFIVE_E_DEV_UART0,
> + SIFIVE_E_DEV_QSPI0,
> + SIFIVE_E_DEV_PWM0,
> + SIFIVE_E_DEV_UART1,
> + SIFIVE_E_DEV_QSPI1,
> + SIFIVE_E_DEV_PWM1,
> + SIFIVE_E_DEV_QSPI2,
> + SIFIVE_E_DEV_PWM2,
> + SIFIVE_E_DEV_XIP,
> + SIFIVE_E_DEV_DTIM
> };
>
> enum {
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 40bbf530d4..759059cd7b 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -54,25 +54,25 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } sifive_e_memmap[] = {
> - [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
> - [SIFIVE_E_MROM] = { 0x1000, 0x2000 },
> - [SIFIVE_E_OTP] = { 0x20000, 0x2000 },
> - [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
> - [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_E_AON] = { 0x10000000, 0x8000 },
> - [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
> - [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
> - [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
> - [SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
> - [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
> - [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
> - [SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
> - [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
> - [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
> - [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
> - [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
> - [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
> - [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> + [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
> + [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
> + [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
> + [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
> + [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
> + [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
> + [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
> + [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
> + [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
> + [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
> + [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
> + [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
> + [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
> + [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
> + [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
> + [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
> + [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
> };
>
> static void sifive_e_machine_init(MachineState *machine)
> @@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
>
> /* Data Tightly Integrated Memory */
> memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
> - memmap[SIFIVE_E_DTIM].size, &error_fatal);
> + memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_DTIM].base, main_mem);
> + memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> uint32_t reset_vec[4];
> @@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine)
> reset_vec[i] = cpu_to_le32(reset_vec[i]);
> }
> rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
> - memmap[SIFIVE_E_MROM].base, &address_space_memory);
> + memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
>
> if (machine->kernel_filename) {
> riscv_load_kernel(machine->kernel_filename, NULL);
> @@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
>
> /* Mask ROM */
> memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
> - memmap[SIFIVE_E_MROM].size, &error_fatal);
> + memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
> memory_region_add_subregion(sys_mem,
> - memmap[SIFIVE_E_MROM].base, &s->mask_rom);
> + memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
>
> /* MMIO */
> - s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
> + s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
> (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
> SIFIVE_E_PLIC_NUM_SOURCES,
> SIFIVE_E_PLIC_NUM_PRIORITIES,
> @@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_E_PLIC_ENABLE_STRIDE,
> SIFIVE_E_PLIC_CONTEXT_BASE,
> SIFIVE_E_PLIC_CONTEXT_STRIDE,
> - memmap[SIFIVE_E_PLIC].size);
> - sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> - memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
> + memmap[SIFIVE_E_DEV_PLIC].size);
> + sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
> + memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> SIFIVE_CLINT_TIMEBASE_FREQ, false);
> create_unimplemented_device("riscv.sifive.e.aon",
> - memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> - sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
> + memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
> + sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
>
> /* GPIO */
>
> @@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* Map GPIO registers */
> - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
>
> /* Pass all GPIOs to the SOC layer so they are available to the board */
> qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> @@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> SIFIVE_E_GPIO0_IRQ0 + i));
> }
>
> - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
> + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
> create_unimplemented_device("riscv.sifive.e.qspi0",
> - memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
> + memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
> create_unimplemented_device("riscv.sifive.e.pwm0",
> - memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
> - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
> + memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
> + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
> create_unimplemented_device("riscv.sifive.e.qspi1",
> - memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
> + memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
> create_unimplemented_device("riscv.sifive.e.pwm1",
> - memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
> + memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
> create_unimplemented_device("riscv.sifive.e.qspi2",
> - memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
> + memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
> create_unimplemented_device("riscv.sifive.e.pwm2",
> - memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
> + memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
>
> /* Flash memory */
> memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
> - memmap[SIFIVE_E_XIP].size, &error_fatal);
> - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
> + memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
> + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
> &s->xip_mem);
> }
>
> --
> 2.26.2
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-09-11 20:46 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-11 17:34 [PATCH v4 0/2] riscv: Rename memmap enum constants Eduardo Habkost
2020-09-11 17:34 ` Eduardo Habkost
2020-09-11 17:34 ` [PATCH v4 1/2] sifive_e: " Eduardo Habkost
2020-09-11 17:34 ` Eduardo Habkost
2020-09-11 20:33 ` Alistair Francis
2020-09-11 20:33 ` Alistair Francis
2020-09-11 17:34 ` [PATCH v4 2/2] sifive_u: " Eduardo Habkost
2020-09-11 17:34 ` Eduardo Habkost
2020-09-11 20:33 ` Alistair Francis
2020-09-11 20:33 ` Alistair Francis
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