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From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
Date: Mon, 6 Sep 2021 15:33:05 +1000	[thread overview]
Message-ID: <CAKmqyKNjenjONzvzEP51DsOr0gRVQUJNnEWFGecZvjHyvSXYgQ@mail.gmail.com> (raw)
In-Reply-To: <20210902112520.475901-6-anup.patel@wdc.com>

On Thu, Sep 2, 2021 at 9:42 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The machine or device emulation should be able to force set certain
> CPU features because:
> 1) We can have certain CPU features which are in-general optional
>    but implemented by RISC-V CPUs on machine.
> 2) We can have devices which require certain CPU feature. For example,
>    AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 11 +++--------
>  target/riscv/cpu.h |  5 +++++
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0ade6ad144..9dc9d04923 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,11 +137,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
>      env->vext_ver = vext_ver;
>  }
>
> -static void set_feature(CPURISCVState *env, int feature)
> -{
> -    env->features |= (1ULL << feature);
> -}
> -
>  static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
>  {
>  #ifndef CONFIG_USER_ONLY
> @@ -423,18 +418,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      }
>
>      if (cpu->cfg.mmu) {
> -        set_feature(env, RISCV_FEATURE_MMU);
> +        riscv_set_feature(env, RISCV_FEATURE_MMU);
>      }
>
>      if (cpu->cfg.pmp) {
> -        set_feature(env, RISCV_FEATURE_PMP);
> +        riscv_set_feature(env, RISCV_FEATURE_PMP);
>
>          /*
>           * Enhanced PMP should only be available
>           * on harts with PMP support
>           */
>          if (cpu->cfg.epmp) {
> -            set_feature(env, RISCV_FEATURE_EPMP);
> +            riscv_set_feature(env, RISCV_FEATURE_EPMP);
>          }
>      }
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 59b36f758f..6fe1cc67e5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -323,6 +323,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
>      return env->features & (1ULL << feature);
>  }
>
> +static inline void riscv_set_feature(CPURISCVState *env, int feature)
> +{
> +    env->features |= (1ULL << feature);
> +}
> +
>  #include "cpu_user.h"
>  #include "cpu_bits.h"
>
> --
> 2.25.1
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	 Atish Patra <atish.patra@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation
Date: Mon, 6 Sep 2021 15:33:05 +1000	[thread overview]
Message-ID: <CAKmqyKNjenjONzvzEP51DsOr0gRVQUJNnEWFGecZvjHyvSXYgQ@mail.gmail.com> (raw)
In-Reply-To: <20210902112520.475901-6-anup.patel@wdc.com>

On Thu, Sep 2, 2021 at 9:42 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The machine or device emulation should be able to force set certain
> CPU features because:
> 1) We can have certain CPU features which are in-general optional
>    but implemented by RISC-V CPUs on machine.
> 2) We can have devices which require certain CPU feature. For example,
>    AIA IMSIC devices expects AIA CSRs implemented by RISC-V CPUs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 11 +++--------
>  target/riscv/cpu.h |  5 +++++
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0ade6ad144..9dc9d04923 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -137,11 +137,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
>      env->vext_ver = vext_ver;
>  }
>
> -static void set_feature(CPURISCVState *env, int feature)
> -{
> -    env->features |= (1ULL << feature);
> -}
> -
>  static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
>  {
>  #ifndef CONFIG_USER_ONLY
> @@ -423,18 +418,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      }
>
>      if (cpu->cfg.mmu) {
> -        set_feature(env, RISCV_FEATURE_MMU);
> +        riscv_set_feature(env, RISCV_FEATURE_MMU);
>      }
>
>      if (cpu->cfg.pmp) {
> -        set_feature(env, RISCV_FEATURE_PMP);
> +        riscv_set_feature(env, RISCV_FEATURE_PMP);
>
>          /*
>           * Enhanced PMP should only be available
>           * on harts with PMP support
>           */
>          if (cpu->cfg.epmp) {
> -            set_feature(env, RISCV_FEATURE_EPMP);
> +            riscv_set_feature(env, RISCV_FEATURE_EPMP);
>          }
>      }
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 59b36f758f..6fe1cc67e5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -323,6 +323,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
>      return env->features & (1ULL << feature);
>  }
>
> +static inline void riscv_set_feature(CPURISCVState *env, int feature)
> +{
> +    env->features |= (1ULL << feature);
> +}
> +
>  #include "cpu_user.h"
>  #include "cpu_bits.h"
>
> --
> 2.25.1
>
>


  parent reply	other threads:[~2021-09-06  5:34 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 11:24 [PATCH v2 00/22] QEMU RISC-V AIA support Anup Patel
2021-09-02 11:24 ` Anup Patel
2021-09-02 11:24 ` [PATCH v2 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-09-02 11:24   ` Anup Patel
2021-09-03  3:32   ` Alistair Francis
2021-09-03  3:32     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-15  1:03   ` Alistair Francis
2021-09-15  1:03     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 03/22] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-15  2:41   ` Alistair Francis
2021-09-15  2:41     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-09  6:44   ` Alistair Francis
2021-09-09  6:44     ` Alistair Francis
2021-09-09 16:35     ` Bin Meng
2021-09-09 16:35       ` Bin Meng
2021-09-13 16:33     ` Anup Patel
2021-09-13 16:33       ` Anup Patel
2021-09-15  0:49       ` Alistair Francis
2021-09-15  0:49         ` Alistair Francis
2021-09-16 13:42         ` Anup Patel
2021-09-16 13:42           ` Anup Patel
2021-10-15  6:24           ` Alistair Francis
2021-10-15  6:24             ` Alistair Francis
2021-10-18 12:55             ` Anup Patel
2021-10-18 12:55               ` Anup Patel
2021-10-18 22:55               ` Alistair Francis
2021-10-18 22:55                 ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-04 15:12   ` Bin Meng
2021-09-04 15:12     ` Bin Meng
2021-10-21 17:06     ` Anup Patel
2021-10-21 17:06       ` Anup Patel
2021-09-06  5:33   ` Alistair Francis [this message]
2021-09-06  5:33     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 06/22] target/riscv: Add AIA cpu feature Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-04 15:13   ` Bin Meng
2021-09-04 15:13     ` Bin Meng
2021-09-06  5:33   ` Alistair Francis
2021-09-06  5:33     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 07/22] target/riscv: Add defines for AIA CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-15  1:17   ` Alistair Francis
2021-09-15  1:17     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-15  1:16   ` Alistair Francis
2021-09-15  1:16     ` Alistair Francis
2021-09-02 11:25 ` [PATCH v2 18/22] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 19/22] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 20/22] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 21/22] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-02 11:25 ` [PATCH v2 22/22] docs/system: riscv: Document AIA options for " Anup Patel
2021-09-02 11:25   ` Anup Patel
2021-09-09  6:51   ` Alistair Francis
2021-09-09  6:51     ` Alistair Francis
2021-09-04 13:51 ` [PATCH v2 00/22] QEMU RISC-V AIA support Bin Meng
2021-09-04 13:51   ` Bin Meng
2021-09-04 15:33   ` Anup Patel
2021-09-04 15:33     ` Anup Patel

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