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From: Alistair Francis <alistair23@gmail.com>
To: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: xen-devel@lists.xenproject.org, Jan Beulich <jbeulich@suse.com>,
	 Julien Grall <julien@xen.org>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	 Stefano Stabellini <sstabellini@kernel.org>,
	Gianluca Guida <gianluca@rivosinc.com>,
	 Bob Eshleman <bobbyeshleman@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Connor Davis <connojdavis@gmail.com>
Subject: Re: [PATCH v2 04/14] xen/riscv: add <asm/csr.h> header
Date: Mon, 30 Jan 2023 23:26:47 +1000	[thread overview]
Message-ID: <CAKmqyKNjsxZPZDeZwbOaOAdS2F8H5U+imEdd1p9ro_J15gBw7g@mail.gmail.com> (raw)
In-Reply-To: <b26d981f189adad8af4560fcc10360da02df97a9.1674818705.git.oleksii.kurochko@gmail.com>

On Sat, Jan 28, 2023 at 12:00 AM Oleksii Kurochko
<oleksii.kurochko@gmail.com> wrote:
>
> The following changes were made in comparison with <asm/csr.h> from
> Linux:
>   * remove all defines as they are defined in riscv_encoding.h
>   * leave only csr_* macros
>
> Origin: https://github.com/torvalds/linux.git 2475bf0250de
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
> Changes in V2:
>   - Minor refactoring mentioned in the commit message, switch tabs to
>     spaces and refactor things around __asm__ __volatile__.
>   - Update the commit message and add "Origin:" tag.
> ---
>  xen/arch/riscv/include/asm/csr.h | 84 ++++++++++++++++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 xen/arch/riscv/include/asm/csr.h
>
> diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h
> new file mode 100644
> index 0000000000..4275cf6515
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/csr.h
> @@ -0,0 +1,84 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-only
> + *
> + * Copyright (C) 2015 Regents of the University of California
> + */
> +
> +#ifndef _ASM_RISCV_CSR_H
> +#define _ASM_RISCV_CSR_H
> +
> +#include <asm/asm.h>
> +#include <xen/const.h>
> +#include <asm/riscv_encoding.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#define csr_read(csr)                                           \
> +({                                                              \
> +    register unsigned long __v;                                 \
> +    __asm__ __volatile__ (  "csrr %0, " __ASM_STR(csr)          \
> +                            : "=r" (__v)                        \
> +                            : : "memory" );                     \
> +    __v;                                                        \
> +})
> +
> +#define csr_write(csr, val)                                     \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrw " __ASM_STR(csr) ", %0"       \
> +                            : /* no outputs */                  \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +})
> +
> +#define csr_swap(csr, val)                                      \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrrw %0, " __ASM_STR(csr) ", %1"  \
> +                            : "=r" (__v)                        \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +    __v;                                                        \
> +})
> +
> +#define csr_read_set(csr, val)                                  \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrrs %0, " __ASM_STR(csr) ", %1"  \
> +                            : "=r" (__v)                        \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +    __v;                                                        \
> +})
> +
> +#define csr_set(csr, val)                                       \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrs " __ASM_STR(csr) ", %0"       \
> +                            : /* no outputs */                  \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +})
> +
> +#define csr_read_clear(csr, val)                                \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrrc %0, " __ASM_STR(csr) ", %1"  \
> +                            : "=r" (__v)                        \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +    __v;                                                        \
> +})
> +
> +#define csr_clear(csr, val)                                     \
> +({                                                              \
> +    unsigned long __v = (unsigned long)(val);                   \
> +    __asm__ __volatile__ (  "csrc " __ASM_STR(csr) ", %0"       \
> +                            : /*no outputs */                   \
> +                            : "rK" (__v)                        \
> +                            : "memory" );                       \
> +})
> +
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _ASM_RISCV_CSR_H */
> --
> 2.39.0
>
>


  parent reply	other threads:[~2023-01-30 13:28 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-27 13:59 [PATCH v2 00/14] RISCV basic exception handling implementation Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 01/14] xen/riscv: add _zicsr to CFLAGS Oleksii Kurochko
2023-01-31  0:21   ` Alistair Francis
2023-01-31  9:14     ` Jan Beulich
2023-02-06 16:09       ` Oleksii
2023-01-27 13:59 ` [PATCH v2 02/14] xen/riscv: add <asm/asm.h> header Oleksii Kurochko
2023-01-31  0:49   ` Alistair Francis
2023-02-06 16:22   ` Oleksii
2023-01-27 13:59 ` [PATCH v2 03/14] xen/riscv: add <asm/riscv_encoding.h header Oleksii Kurochko
2023-01-30 13:29   ` Alistair Francis
2023-01-27 13:59 ` [PATCH v2 04/14] xen/riscv: add <asm/csr.h> header Oleksii Kurochko
2023-01-27 14:10   ` Jan Beulich
2023-01-30 11:37     ` Oleksii
2023-01-30 13:26   ` Alistair Francis [this message]
2023-01-27 13:59 ` [PATCH v2 05/14] xen/riscv: introduce empty <asm/string.h> Oleksii Kurochko
2023-01-31  0:49   ` Alistair Francis
2023-01-27 13:59 ` [PATCH v2 06/14] xen/riscv: introduce empty <asm/cache.h> Oleksii Kurochko
2023-01-31  0:50   ` Alistair Francis
2023-01-27 13:59 ` [PATCH v2 07/14] xen/riscv: introduce exception context Oleksii Kurochko
2023-01-27 14:24   ` Jan Beulich
2023-01-30 11:54     ` Oleksii
2023-01-30 13:50       ` Jan Beulich
2023-01-30 22:44         ` Julien Grall
2023-02-01  2:27           ` Andrew Cooper
2023-02-01  1:30         ` Stefano Stabellini
2023-02-06 17:13           ` Oleksii
2023-01-27 14:54   ` Julien Grall
2023-01-30 11:40     ` Oleksii
2023-01-30 22:11       ` Julien Grall
2023-01-31 12:24         ` Oleksii
2023-01-31 12:39           ` Julien Grall
2023-01-27 13:59 ` [PATCH v2 08/14] xen/riscv: introduce exception handlers implementation Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 09/14] xen/riscv: introduce decode_cause() stuff Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 10/14] xen/riscv: mask all interrupts Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 11/14] xen/riscv: introduce trap_init() Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 12/14] xen/riscv: introduce an implementation of macros from <asm/bug.h> Oleksii Kurochko
2023-01-27 14:34   ` Jan Beulich
2023-01-30 11:23     ` Oleksii
2023-01-27 14:38   ` Jan Beulich
2023-01-27 16:02   ` Julien Grall
2023-01-30 11:35     ` Oleksii
2023-01-30 11:49       ` Juergen Gross
2023-01-30 22:28       ` Julien Grall
2023-01-31 12:34         ` Oleksii
2023-02-01 17:40         ` Oleksii
2023-02-01 22:11           ` Julien Grall
2023-02-02 11:50             ` Jan Beulich
2023-02-03 13:15             ` Oleksii
2023-02-03 13:23               ` Julien Grall
2023-02-03 16:25                 ` Oleksii
2023-01-27 13:59 ` [PATCH v2 13/14] xen/riscv: test basic handling stuff Oleksii Kurochko
2023-01-27 13:59 ` [PATCH v2 14/14] automation: add smoke test to verify macros from bug.h Oleksii Kurochko
2023-01-27 14:43   ` Michal Orzel
2023-01-30 11:15     ` Oleksii

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