From: Alistair Francis <alistair23@gmail.com>
To: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v2] gdb: riscv: Add target description
Date: Tue, 5 Jan 2021 13:03:15 -0800 [thread overview]
Message-ID: <CAKmqyKO-7x9Ea9xKuAAm5Z0b8zLr0Xqhrwya43iqByhxjeDCGw@mail.gmail.com> (raw)
In-Reply-To: <CAOkUe-BGMmUTtY8bdTgi2Vrmq-pL2O36bY_kmE5rfbv0SQTJmA@mail.gmail.com>
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Hello,
This patch fails to apply. How did you send the email?
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v2] gdb: riscv: Add target description
Date: Tue, 5 Jan 2021 13:03:15 -0800 [thread overview]
Message-ID: <CAKmqyKO-7x9Ea9xKuAAm5Z0b8zLr0Xqhrwya43iqByhxjeDCGw@mail.gmail.com> (raw)
In-Reply-To: <CAOkUe-BGMmUTtY8bdTgi2Vrmq-pL2O36bY_kmE5rfbv0SQTJmA@mail.gmail.com>
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Hello,
This patch fails to apply. How did you send the email?
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
next prev parent reply other threads:[~2021-01-05 21:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-30 8:25 [PATCH v2] gdb: riscv: Add target description Sylvain Pelissier
2020-12-30 8:32 ` Bin Meng
2020-12-30 8:32 ` Bin Meng
2021-01-05 20:33 ` Alistair Francis
2021-01-05 20:33 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis [this message]
2021-01-05 21:03 ` Alistair Francis
2021-01-06 10:48 ` Sylvain Pelissier
2021-01-06 10:48 ` Sylvain Pelissier
2021-01-06 11:35 ` Alex Bennée
2021-01-06 11:35 ` Alex Bennée
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