Re: [PATCH v2] gdb: riscv: Add target description

[Sylvain Pelissier <sylvain.pelissier@gmail.com>]

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Hello,

I may have made an error by copy pasting the comment into the file. I sent
a new v3 with git send-email. I hope it is fine now.
Regards

Sylvain

On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote:

> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
> <sylvain.pelissier@gmail.com> wrote:
> >
> > Target description is not currently implemented in RISC-V architecture.
> Thus GDB won't set it properly when attached. The patch implements the
> target description response.
> >
> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
>
> Hello,
>
> This patch fails to apply. How did you send the email?
>
> Alistair
>
> > ---
> >  target/riscv/cpu.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 254cd83f8b..ed4971978b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> >      DEFINE_PROP_END_OF_LIST(),
> >  };
> >
> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
> > +{
> > +    RISCVCPU *cpu = RISCV_CPU(cs);
> > +    CPURISCVState *env = &cpu->env;
> > +
> > +    if (riscv_cpu_is_32bit(env)) {
> > +        return g_strdup("riscv:rv32");
> > +    } else {
> > +        return g_strdup("riscv:rv64");
> > +    }
> > +}
> > +
> >  static void riscv_cpu_class_init(ObjectClass *c, void *data)
> >  {
> >      RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
> void *data)
> >      /* For now, mark unmigratable: */
> >      cc->vmsd = &vmstate_riscv_cpu;
> >  #endif
> > +    cc->gdb_arch_name = riscv_gdb_arch_name;
> >  #ifdef CONFIG_TCG
> >      cc->tcg_initialize = riscv_translate_init;
> >      cc->tlb_fill = riscv_cpu_tlb_fill;
> > --
> > 2.25.1
>

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