* [PATCH] riscv: Set xPIE to 1 after xRET
@ 2020-01-03 3:53 Yiting Wang
2020-01-03 14:22 ` Bin Meng
2020-01-03 19:24 ` Alistair Francis
0 siblings, 2 replies; 5+ messages in thread
From: Yiting Wang @ 2020-01-03 3:53 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
---
target/riscv/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36..e87c911 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_SIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
@@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
env->priv_ver >= PRIV_VERSION_1_10_0 ?
MSTATUS_MIE : MSTATUS_UIE << prev_priv,
get_field(mstatus, MSTATUS_MPIE));
- mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
+ mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Set xPIE to 1 after xRET
2020-01-03 3:53 [PATCH] riscv: Set xPIE to 1 after xRET Yiting Wang
@ 2020-01-03 14:22 ` Bin Meng
2020-01-03 19:24 ` Alistair Francis
1 sibling, 0 replies; 5+ messages in thread
From: Bin Meng @ 2020-01-03 14:22 UTC (permalink / raw)
To: Yiting Wang
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jan 3, 2020 at 4:03 PM Yiting Wang <yiting.wang@windriver.com> wrote:
>
> When executing an xRET instruction, supposing xPP holds the
> value y, xIE is set to xPIE; the privilege mode is changed to y;
> xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
>
> Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
> ---
> target/riscv/op_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Set xPIE to 1 after xRET
@ 2020-01-03 14:22 ` Bin Meng
0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2020-01-03 14:22 UTC (permalink / raw)
To: Yiting Wang
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V
On Fri, Jan 3, 2020 at 4:03 PM Yiting Wang <yiting.wang@windriver.com> wrote:
>
> When executing an xRET instruction, supposing xPP holds the
> value y, xIE is set to xPIE; the privilege mode is changed to y;
> xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
>
> Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
> ---
> target/riscv/op_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Set xPIE to 1 after xRET
2020-01-03 3:53 [PATCH] riscv: Set xPIE to 1 after xRET Yiting Wang
@ 2020-01-03 19:24 ` Alistair Francis
2020-01-03 19:24 ` Alistair Francis
1 sibling, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2020-01-03 19:24 UTC (permalink / raw)
To: Yiting Wang
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Jan 3, 2020 at 12:01 AM Yiting Wang <yiting.wang@windriver.com> wrote:
>
> When executing an xRET instruction, supposing xPP holds the
> value y, xIE is set to xPIE; the privilege mode is changed to y;
> xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
>
> Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/op_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 331cc36..e87c911 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> env->priv_ver >= PRIV_VERSION_1_10_0 ?
> MSTATUS_SIE : MSTATUS_UIE << prev_priv,
> get_field(mstatus, MSTATUS_SPIE));
> - mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> + mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
> @@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> env->priv_ver >= PRIV_VERSION_1_10_0 ?
> MSTATUS_MIE : MSTATUS_UIE << prev_priv,
> get_field(mstatus, MSTATUS_MPIE));
> - mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> + mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: Set xPIE to 1 after xRET
@ 2020-01-03 19:24 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2020-01-03 19:24 UTC (permalink / raw)
To: Yiting Wang
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V
On Fri, Jan 3, 2020 at 12:01 AM Yiting Wang <yiting.wang@windriver.com> wrote:
>
> When executing an xRET instruction, supposing xPP holds the
> value y, xIE is set to xPIE; the privilege mode is changed to y;
> xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.
>
> Signed-off-by: Yiting Wang <yiting.wang@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/op_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 331cc36..e87c911 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -93,7 +93,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> env->priv_ver >= PRIV_VERSION_1_10_0 ?
> MSTATUS_SIE : MSTATUS_UIE << prev_priv,
> get_field(mstatus, MSTATUS_SPIE));
> - mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> + mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
> @@ -118,7 +118,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> env->priv_ver >= PRIV_VERSION_1_10_0 ?
> MSTATUS_MIE : MSTATUS_UIE << prev_priv,
> get_field(mstatus, MSTATUS_MPIE));
> - mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> + mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-03 19:26 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-01-03 3:53 [PATCH] riscv: Set xPIE to 1 after xRET Yiting Wang
2020-01-03 14:22 ` Bin Meng
2020-01-03 14:22 ` Bin Meng
2020-01-03 19:24 ` Alistair Francis
2020-01-03 19:24 ` Alistair Francis
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