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From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions
Date: Tue, 16 Mar 2021 10:38:06 -0400	[thread overview]
Message-ID: <CAKmqyKP69ixzifGhxHmB03twB_1=hFD9QT1hs4fj1JUELCznXQ@mail.gmail.com> (raw)
In-Reply-To: <20210212150256.885-14-zhiwei_liu@c-sky.com>

On Fri, Feb 12, 2021 at 10:30 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   |  12 +++
>  target/riscv/insn32.decode              |  12 +++
>  target/riscv/insn_trans/trans_rvp.c.inc |  13 +++
>  target/riscv/packed_helper.c            | 115 ++++++++++++++++++++++++
>  4 files changed, 152 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 866484e37d..83778b532a 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1240,3 +1240,15 @@ DEF_HELPER_2(clrs16, tl, env, tl)
>  DEF_HELPER_2(clz16, tl, env, tl)
>  DEF_HELPER_2(clo16, tl, env, tl)
>  DEF_HELPER_2(swap16, tl, env, tl)
> +
> +DEF_HELPER_3(smin8, tl, env, tl, tl)
> +DEF_HELPER_3(umin8, tl, env, tl, tl)
> +DEF_HELPER_3(smax8, tl, env, tl, tl)
> +DEF_HELPER_3(umax8, tl, env, tl, tl)
> +DEF_HELPER_3(sclip8, tl, env, tl, tl)
> +DEF_HELPER_3(uclip8, tl, env, tl, tl)
> +DEF_HELPER_2(kabs8, tl, env, tl)
> +DEF_HELPER_2(clrs8, tl, env, tl)
> +DEF_HELPER_2(clz8, tl, env, tl)
> +DEF_HELPER_2(clo8, tl, env, tl)
> +DEF_HELPER_2(swap8, tl, env, tl)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index bc9d5fc967..e158066353 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -708,3 +708,15 @@ clrs16     1010111  01000 ..... 000 ..... 1111111 @r2
>  clz16      1010111  01001 ..... 000 ..... 1111111 @r2
>  clo16      1010111  01011 ..... 000 ..... 1111111 @r2
>  swap16     1010110  11001 ..... 000 ..... 1111111 @r2
> +
> +smin8      1000100  ..... ..... 000 ..... 1111111 @r
> +umin8      1001100  ..... ..... 000 ..... 1111111 @r
> +smax8      1000101  ..... ..... 000 ..... 1111111 @r
> +umax8      1001101  ..... ..... 000 ..... 1111111 @r
> +sclip8     1000110  00... ..... 000 ..... 1111111 @sh3
> +uclip8     1000110  10... ..... 000 ..... 1111111 @sh3
> +kabs8      1010110  10000 ..... 000 ..... 1111111 @r2
> +clrs8      1010111  00000 ..... 000 ..... 1111111 @r2
> +clz8       1010111  00001 ..... 000 ..... 1111111 @r2
> +clo8       1010111  00011 ..... 000 ..... 1111111 @r2
> +swap8      1010110  11000 ..... 000 ..... 1111111 @r2
> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
> index 56fb8b2523..5ad057d7ac 100644
> --- a/target/riscv/insn_trans/trans_rvp.c.inc
> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
> @@ -486,3 +486,16 @@ GEN_RVP_R2_OOL(clrs16);
>  GEN_RVP_R2_OOL(clz16);
>  GEN_RVP_R2_OOL(clo16);
>  GEN_RVP_R2_OOL(swap16);
> +
> +/* SIMD 8-bit Miscellaneous Instructions */
> +GEN_RVP_R_OOL(smin8);
> +GEN_RVP_R_OOL(umin8);
> +GEN_RVP_R_OOL(smax8);
> +GEN_RVP_R_OOL(umax8);
> +GEN_RVP_SHIFTI(sclip8, sclip8, NULL);
> +GEN_RVP_SHIFTI(uclip8, uclip8, NULL);
> +GEN_RVP_R2_OOL(kabs8);
> +GEN_RVP_R2_OOL(clrs8);
> +GEN_RVP_R2_OOL(clz8);
> +GEN_RVP_R2_OOL(clo8);
> +GEN_RVP_R2_OOL(swap8);
> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
> index a6ab011ace..be91d308e5 100644
> --- a/target/riscv/packed_helper.c
> +++ b/target/riscv/packed_helper.c
> @@ -1087,3 +1087,118 @@ static inline void do_swap16(CPURISCVState *env, void *vd, void *va, uint8_t i)
>  }
>
>  RVPR2(swap16, 2, 2);
> +
> +/* SIMD 8-bit Miscellaneous Instructions */
> +static inline void do_smin8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] < b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(smin8, 1, 1);
> +
> +static inline void do_umin8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    uint8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] < b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(umin8, 1, 1);
> +
> +static inline void do_smax8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] > b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(smax8, 1, 1);
> +
> +static inline void do_umax8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    uint8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] > b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(umax8, 1, 1);
> +
> +static inline void do_sclip8(CPURISCVState *env, void *vd, void *va,
> +                             void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    uint8_t shift = *(uint8_t *)vb & 0x7;
> +
> +    d[i] = sat64(env, a[i], shift);
> +}
> +
> +RVPR(sclip8, 1, 1);
> +
> +static inline void do_uclip8(CPURISCVState *env, void *vd, void *va,
> +                              void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    uint8_t shift = *(uint8_t *)vb & 0x7;
> +
> +    if (a[i] < 0) {
> +        d[i] = 0;
> +        env->vxsat = 0x1;
> +    } else {
> +        d[i] = satu64(env, a[i], shift);
> +    }
> +}
> +
> +RVPR(uclip8, 1, 1);
> +
> +static inline void do_kabs8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +
> +    if (a[i] == INT8_MIN) {
> +        d[i] = INT8_MAX;
> +        env->vxsat = 0x1;
> +    } else {
> +        d[i] = abs(a[i]);
> +    }
> +}
> +
> +RVPR2(kabs8, 1, 1);
> +
> +static inline void do_clrs8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = clrsb32(a[i]) - 24;
> +}
> +
> +RVPR2(clrs8, 1, 1);
> +
> +static inline void do_clz8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = (a[i] < 0) ? 0 : (clz32(a[i]) - 24);
> +}
> +
> +RVPR2(clz8, 1, 1);
> +
> +static inline void do_clo8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = (a[i] >= 0) ? 0 : (clo32(a[i]) - 24);
> +}
> +
> +RVPR2(clo8, 1, 1);
> +
> +static inline void do_swap8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[H1(i)] = a[H1(i + 1)];
> +    d[H1(i + 1)] = a[H1(i)];
> +}
> +
> +RVPR2(swap8, 2, 1);
> --
> 2.17.1
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Richard Henderson <richard.henderson@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions
Date: Tue, 16 Mar 2021 10:38:06 -0400	[thread overview]
Message-ID: <CAKmqyKP69ixzifGhxHmB03twB_1=hFD9QT1hs4fj1JUELCznXQ@mail.gmail.com> (raw)
In-Reply-To: <20210212150256.885-14-zhiwei_liu@c-sky.com>

On Fri, Feb 12, 2021 at 10:30 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   |  12 +++
>  target/riscv/insn32.decode              |  12 +++
>  target/riscv/insn_trans/trans_rvp.c.inc |  13 +++
>  target/riscv/packed_helper.c            | 115 ++++++++++++++++++++++++
>  4 files changed, 152 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 866484e37d..83778b532a 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1240,3 +1240,15 @@ DEF_HELPER_2(clrs16, tl, env, tl)
>  DEF_HELPER_2(clz16, tl, env, tl)
>  DEF_HELPER_2(clo16, tl, env, tl)
>  DEF_HELPER_2(swap16, tl, env, tl)
> +
> +DEF_HELPER_3(smin8, tl, env, tl, tl)
> +DEF_HELPER_3(umin8, tl, env, tl, tl)
> +DEF_HELPER_3(smax8, tl, env, tl, tl)
> +DEF_HELPER_3(umax8, tl, env, tl, tl)
> +DEF_HELPER_3(sclip8, tl, env, tl, tl)
> +DEF_HELPER_3(uclip8, tl, env, tl, tl)
> +DEF_HELPER_2(kabs8, tl, env, tl)
> +DEF_HELPER_2(clrs8, tl, env, tl)
> +DEF_HELPER_2(clz8, tl, env, tl)
> +DEF_HELPER_2(clo8, tl, env, tl)
> +DEF_HELPER_2(swap8, tl, env, tl)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index bc9d5fc967..e158066353 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -708,3 +708,15 @@ clrs16     1010111  01000 ..... 000 ..... 1111111 @r2
>  clz16      1010111  01001 ..... 000 ..... 1111111 @r2
>  clo16      1010111  01011 ..... 000 ..... 1111111 @r2
>  swap16     1010110  11001 ..... 000 ..... 1111111 @r2
> +
> +smin8      1000100  ..... ..... 000 ..... 1111111 @r
> +umin8      1001100  ..... ..... 000 ..... 1111111 @r
> +smax8      1000101  ..... ..... 000 ..... 1111111 @r
> +umax8      1001101  ..... ..... 000 ..... 1111111 @r
> +sclip8     1000110  00... ..... 000 ..... 1111111 @sh3
> +uclip8     1000110  10... ..... 000 ..... 1111111 @sh3
> +kabs8      1010110  10000 ..... 000 ..... 1111111 @r2
> +clrs8      1010111  00000 ..... 000 ..... 1111111 @r2
> +clz8       1010111  00001 ..... 000 ..... 1111111 @r2
> +clo8       1010111  00011 ..... 000 ..... 1111111 @r2
> +swap8      1010110  11000 ..... 000 ..... 1111111 @r2
> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
> index 56fb8b2523..5ad057d7ac 100644
> --- a/target/riscv/insn_trans/trans_rvp.c.inc
> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
> @@ -486,3 +486,16 @@ GEN_RVP_R2_OOL(clrs16);
>  GEN_RVP_R2_OOL(clz16);
>  GEN_RVP_R2_OOL(clo16);
>  GEN_RVP_R2_OOL(swap16);
> +
> +/* SIMD 8-bit Miscellaneous Instructions */
> +GEN_RVP_R_OOL(smin8);
> +GEN_RVP_R_OOL(umin8);
> +GEN_RVP_R_OOL(smax8);
> +GEN_RVP_R_OOL(umax8);
> +GEN_RVP_SHIFTI(sclip8, sclip8, NULL);
> +GEN_RVP_SHIFTI(uclip8, uclip8, NULL);
> +GEN_RVP_R2_OOL(kabs8);
> +GEN_RVP_R2_OOL(clrs8);
> +GEN_RVP_R2_OOL(clz8);
> +GEN_RVP_R2_OOL(clo8);
> +GEN_RVP_R2_OOL(swap8);
> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
> index a6ab011ace..be91d308e5 100644
> --- a/target/riscv/packed_helper.c
> +++ b/target/riscv/packed_helper.c
> @@ -1087,3 +1087,118 @@ static inline void do_swap16(CPURISCVState *env, void *vd, void *va, uint8_t i)
>  }
>
>  RVPR2(swap16, 2, 2);
> +
> +/* SIMD 8-bit Miscellaneous Instructions */
> +static inline void do_smin8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] < b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(smin8, 1, 1);
> +
> +static inline void do_umin8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    uint8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] < b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(umin8, 1, 1);
> +
> +static inline void do_smax8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] > b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(smax8, 1, 1);
> +
> +static inline void do_umax8(CPURISCVState *env, void *vd, void *va,
> +                            void *vb, uint8_t i)
> +{
> +    uint8_t *d = vd, *a = va, *b = vb;
> +
> +    d[i] = (a[i] > b[i]) ? a[i] : b[i];
> +}
> +
> +RVPR(umax8, 1, 1);
> +
> +static inline void do_sclip8(CPURISCVState *env, void *vd, void *va,
> +                             void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    uint8_t shift = *(uint8_t *)vb & 0x7;
> +
> +    d[i] = sat64(env, a[i], shift);
> +}
> +
> +RVPR(sclip8, 1, 1);
> +
> +static inline void do_uclip8(CPURISCVState *env, void *vd, void *va,
> +                              void *vb, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    uint8_t shift = *(uint8_t *)vb & 0x7;
> +
> +    if (a[i] < 0) {
> +        d[i] = 0;
> +        env->vxsat = 0x1;
> +    } else {
> +        d[i] = satu64(env, a[i], shift);
> +    }
> +}
> +
> +RVPR(uclip8, 1, 1);
> +
> +static inline void do_kabs8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +
> +    if (a[i] == INT8_MIN) {
> +        d[i] = INT8_MAX;
> +        env->vxsat = 0x1;
> +    } else {
> +        d[i] = abs(a[i]);
> +    }
> +}
> +
> +RVPR2(kabs8, 1, 1);
> +
> +static inline void do_clrs8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = clrsb32(a[i]) - 24;
> +}
> +
> +RVPR2(clrs8, 1, 1);
> +
> +static inline void do_clz8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = (a[i] < 0) ? 0 : (clz32(a[i]) - 24);
> +}
> +
> +RVPR2(clz8, 1, 1);
> +
> +static inline void do_clo8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[i] = (a[i] >= 0) ? 0 : (clo32(a[i]) - 24);
> +}
> +
> +RVPR2(clo8, 1, 1);
> +
> +static inline void do_swap8(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> +    int8_t *d = vd, *a = va;
> +    d[H1(i)] = a[H1(i + 1)];
> +    d[H1(i + 1)] = a[H1(i)];
> +}
> +
> +RVPR2(swap8, 2, 1);
> --
> 2.17.1
>


  reply	other threads:[~2021-03-16 14:45 UTC|newest]

Thread overview: 150+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-09 14:08   ` Alistair Francis
2021-03-09 14:08     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-09 14:10   ` Alistair Francis
2021-03-09 14:10     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 18:52   ` Richard Henderson
2021-02-12 18:52     ` Richard Henderson
2021-03-09 14:11   ` Alistair Francis
2021-03-09 14:11     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 18:03   ` Richard Henderson
2021-02-12 18:03     ` Richard Henderson
2021-02-18  8:39     ` LIU Zhiwei
2021-02-18  8:39       ` LIU Zhiwei
2021-02-18 16:20       ` Richard Henderson
2021-02-18 16:20         ` Richard Henderson
2021-02-12 19:02   ` Richard Henderson
2021-02-12 19:02     ` Richard Henderson
2021-02-18  8:47     ` LIU Zhiwei
2021-02-18  8:47       ` LIU Zhiwei
2021-02-18 16:21       ` Richard Henderson
2021-02-18 16:21         ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:22   ` Alistair Francis
2021-03-15 21:22     ` Alistair Francis
2021-05-24  1:00     ` Palmer Dabbelt
2021-05-24  1:00       ` Palmer Dabbelt
2021-05-26  5:43       ` LIU Zhiwei
2021-05-26  5:43         ` LIU Zhiwei
2021-05-26  6:15         ` Palmer Dabbelt
2021-05-26  6:15           ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:25   ` Alistair Francis
2021-03-15 21:25     ` Alistair Francis
2021-03-16  2:40     ` LIU Zhiwei
2021-03-16  2:40       ` LIU Zhiwei
2021-03-16 19:54       ` Alistair Francis
2021-03-16 19:54         ` Alistair Francis
2021-03-17  2:30         ` LIU Zhiwei
2021-03-17  2:30           ` LIU Zhiwei
2021-03-17 20:39           ` Alistair Francis
2021-03-17 20:39             ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:27   ` Alistair Francis
2021-03-15 21:27     ` Alistair Francis
2021-05-24  4:46   ` Palmer Dabbelt
2021-05-24  4:46     ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:28   ` Alistair Francis
2021-03-15 21:28     ` Alistair Francis
2021-05-26  5:30   ` Palmer Dabbelt
2021-05-26  5:30     ` Palmer Dabbelt
2021-05-26  5:31     ` Palmer Dabbelt
2021-05-26  5:31       ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:31   ` Alistair Francis
2021-03-15 21:31     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:33   ` Alistair Francis
2021-03-15 21:33     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:35   ` Alistair Francis
2021-03-15 21:35     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:38   ` Alistair Francis [this message]
2021-03-16 14:38     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:40   ` Alistair Francis
2021-03-16 14:40     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:42   ` Alistair Francis
2021-03-16 14:42     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 16:01   ` Alistair Francis
2021-03-16 16:01     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 19:44   ` Alistair Francis
2021-03-16 19:44     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-05  6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-03-05  6:14   ` LIU Zhiwei
2021-04-13  3:27 ` LIU Zhiwei
2021-04-13  3:27   ` LIU Zhiwei
2021-04-15  4:46   ` Alistair Francis
2021-04-15  4:46     ` Alistair Francis
2021-04-15  5:50     ` LIU Zhiwei
2021-04-15  5:50       ` LIU Zhiwei

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