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From: Palmer Dabbelt <palmer@dabbelt.com>
To: zhiwei_liu@c-sky.com
Cc: richard.henderson@linaro.org, zhiwei_liu@c-sky.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	alistair23@gmail.com
Subject: Re: [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
Date: Tue, 25 May 2021 22:31:47 -0700 (PDT)	[thread overview]
Message-ID: <mhng-3ecb3cda-6b88-4cf1-95d9-ab9c28d8c71a@palmerdabbelt-glaptop> (raw)
In-Reply-To: <mhng-21817afa-4f8d-4096-b64f-6f0b766c6174@palmerdabbelt-glaptop>

On Tue, 25 May 2021 22:30:14 PDT (-0700), Palmer Dabbelt wrote:
> On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_liu@c-sky.com wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>  target/riscv/helper.h                   |  6 ++++
>>  target/riscv/insn32.decode              |  6 ++++
>>  target/riscv/insn_trans/trans_rvp.c.inc |  7 ++++
>>  target/riscv/packed_helper.c            | 46 +++++++++++++++++++++++++
>>  4 files changed, 65 insertions(+)
>>
>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
>> index 0ecd4d53f9..f41f9acccc 100644
>> --- a/target/riscv/helper.h
>> +++ b/target/riscv/helper.h
>> @@ -1202,3 +1202,9 @@ DEF_HELPER_3(sll8, tl, env, tl, tl)
>>  DEF_HELPER_3(ksll8, tl, env, tl, tl)
>>  DEF_HELPER_3(kslra8, tl, env, tl, tl)
>>  DEF_HELPER_3(kslra8_u, tl, env, tl, tl)
>> +
>> +DEF_HELPER_3(cmpeq16, tl, env, tl, tl)
>> +DEF_HELPER_3(scmplt16, tl, env, tl, tl)
>> +DEF_HELPER_3(scmple16, tl, env, tl, tl)
>> +DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
>> +DEF_HELPER_3(ucmple16, tl, env, tl, tl)
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index cc782fcde5..f3cd508396 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -669,3 +669,9 @@ ksll8      0110110  ..... ..... 000 ..... 1111111 @r
>>  kslli8     0111110  01... ..... 000 ..... 1111111 @sh3
>>  kslra8     0101111  ..... ..... 000 ..... 1111111 @r
>>  kslra8_u   0110111  ..... ..... 000 ..... 1111111 @r
>> +
>> +cmpeq16    0100110  ..... ..... 000 ..... 1111111 @r
>> +scmplt16   0000110  ..... ..... 000 ..... 1111111 @r
>> +scmple16   0001110  ..... ..... 000 ..... 1111111 @r
>> +ucmplt16   0010110  ..... ..... 000 ..... 1111111 @r
>> +ucmple16   0011110  ..... ..... 000 ..... 1111111 @r
>> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
>> index 12a64849eb..6438dfb776 100644
>> --- a/target/riscv/insn_trans/trans_rvp.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
>> @@ -369,3 +369,10 @@ GEN_RVP_SHIFTI(slli8, sll8, tcg_gen_vec_shl8i_i64);
>>  GEN_RVP_SHIFTI(srai8_u, sra8_u, NULL);
>>  GEN_RVP_SHIFTI(srli8_u, srl8_u, NULL);
>>  GEN_RVP_SHIFTI(kslli8, ksll8, NULL);
>> +
>> +/* SIMD 16-bit Compare Instructions */
>> +GEN_RVP_R_OOL(cmpeq16);
>> +GEN_RVP_R_OOL(scmplt16);
>> +GEN_RVP_R_OOL(scmple16);
>> +GEN_RVP_R_OOL(ucmplt16);
>> +GEN_RVP_R_OOL(ucmple16);
>> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
>> index ab9ebc472b..30b916b5ad 100644
>> --- a/target/riscv/packed_helper.c
>> +++ b/target/riscv/packed_helper.c
>> @@ -631,3 +631,49 @@ static inline void do_kslra8_u(CPURISCVState *env, void *vd, void *va,
>>  }
>>
>>  RVPR(kslra8_u, 1, 1);
>> +
>> +/* SIMD 16-bit Compare Instructions */
>> +static inline void do_cmpeq16(CPURISCVState *env, void *vd, void *va,
>> +                              void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] == b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(cmpeq16, 1, 2);
>> +
>> +static inline void do_scmplt16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    int16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(scmplt16, 1, 2);
>> +
>> +static inline void do_scmple16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    int16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(scmple16, 1, 2);
>> +
>> +static inline void do_ucmplt16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(ucmplt16, 1, 2);
>> +
>> +static inline void do_ucmple16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(ucmple16, 1, 2);
>
> Thanks, this is on for-next.

Oops, got my threads crossed.


WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@dabbelt.com>
To: zhiwei_liu@c-sky.com
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	richard.henderson@linaro.org, alistair23@gmail.com,
	zhiwei_liu@c-sky.com
Subject: Re: [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions
Date: Tue, 25 May 2021 22:31:47 -0700 (PDT)	[thread overview]
Message-ID: <mhng-3ecb3cda-6b88-4cf1-95d9-ab9c28d8c71a@palmerdabbelt-glaptop> (raw)
In-Reply-To: <mhng-21817afa-4f8d-4096-b64f-6f0b766c6174@palmerdabbelt-glaptop>

On Tue, 25 May 2021 22:30:14 PDT (-0700), Palmer Dabbelt wrote:
> On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_liu@c-sky.com wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>>  target/riscv/helper.h                   |  6 ++++
>>  target/riscv/insn32.decode              |  6 ++++
>>  target/riscv/insn_trans/trans_rvp.c.inc |  7 ++++
>>  target/riscv/packed_helper.c            | 46 +++++++++++++++++++++++++
>>  4 files changed, 65 insertions(+)
>>
>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
>> index 0ecd4d53f9..f41f9acccc 100644
>> --- a/target/riscv/helper.h
>> +++ b/target/riscv/helper.h
>> @@ -1202,3 +1202,9 @@ DEF_HELPER_3(sll8, tl, env, tl, tl)
>>  DEF_HELPER_3(ksll8, tl, env, tl, tl)
>>  DEF_HELPER_3(kslra8, tl, env, tl, tl)
>>  DEF_HELPER_3(kslra8_u, tl, env, tl, tl)
>> +
>> +DEF_HELPER_3(cmpeq16, tl, env, tl, tl)
>> +DEF_HELPER_3(scmplt16, tl, env, tl, tl)
>> +DEF_HELPER_3(scmple16, tl, env, tl, tl)
>> +DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
>> +DEF_HELPER_3(ucmple16, tl, env, tl, tl)
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index cc782fcde5..f3cd508396 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -669,3 +669,9 @@ ksll8      0110110  ..... ..... 000 ..... 1111111 @r
>>  kslli8     0111110  01... ..... 000 ..... 1111111 @sh3
>>  kslra8     0101111  ..... ..... 000 ..... 1111111 @r
>>  kslra8_u   0110111  ..... ..... 000 ..... 1111111 @r
>> +
>> +cmpeq16    0100110  ..... ..... 000 ..... 1111111 @r
>> +scmplt16   0000110  ..... ..... 000 ..... 1111111 @r
>> +scmple16   0001110  ..... ..... 000 ..... 1111111 @r
>> +ucmplt16   0010110  ..... ..... 000 ..... 1111111 @r
>> +ucmple16   0011110  ..... ..... 000 ..... 1111111 @r
>> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
>> index 12a64849eb..6438dfb776 100644
>> --- a/target/riscv/insn_trans/trans_rvp.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
>> @@ -369,3 +369,10 @@ GEN_RVP_SHIFTI(slli8, sll8, tcg_gen_vec_shl8i_i64);
>>  GEN_RVP_SHIFTI(srai8_u, sra8_u, NULL);
>>  GEN_RVP_SHIFTI(srli8_u, srl8_u, NULL);
>>  GEN_RVP_SHIFTI(kslli8, ksll8, NULL);
>> +
>> +/* SIMD 16-bit Compare Instructions */
>> +GEN_RVP_R_OOL(cmpeq16);
>> +GEN_RVP_R_OOL(scmplt16);
>> +GEN_RVP_R_OOL(scmple16);
>> +GEN_RVP_R_OOL(ucmplt16);
>> +GEN_RVP_R_OOL(ucmple16);
>> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
>> index ab9ebc472b..30b916b5ad 100644
>> --- a/target/riscv/packed_helper.c
>> +++ b/target/riscv/packed_helper.c
>> @@ -631,3 +631,49 @@ static inline void do_kslra8_u(CPURISCVState *env, void *vd, void *va,
>>  }
>>
>>  RVPR(kslra8_u, 1, 1);
>> +
>> +/* SIMD 16-bit Compare Instructions */
>> +static inline void do_cmpeq16(CPURISCVState *env, void *vd, void *va,
>> +                              void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] == b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(cmpeq16, 1, 2);
>> +
>> +static inline void do_scmplt16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    int16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(scmplt16, 1, 2);
>> +
>> +static inline void do_scmple16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    int16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(scmple16, 1, 2);
>> +
>> +static inline void do_ucmplt16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(ucmplt16, 1, 2);
>> +
>> +static inline void do_ucmple16(CPURISCVState *env, void *vd, void *va,
>> +                               void *vb, uint8_t i)
>> +{
>> +    uint16_t *d = vd, *a = va, *b = vb;
>> +    d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
>> +}
>> +
>> +RVPR(ucmple16, 1, 2);
>
> Thanks, this is on for-next.

Oops, got my threads crossed.


  reply	other threads:[~2021-05-26  5:33 UTC|newest]

Thread overview: 150+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-09 14:08   ` Alistair Francis
2021-03-09 14:08     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-09 14:10   ` Alistair Francis
2021-03-09 14:10     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 18:52   ` Richard Henderson
2021-02-12 18:52     ` Richard Henderson
2021-03-09 14:11   ` Alistair Francis
2021-03-09 14:11     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 18:03   ` Richard Henderson
2021-02-12 18:03     ` Richard Henderson
2021-02-18  8:39     ` LIU Zhiwei
2021-02-18  8:39       ` LIU Zhiwei
2021-02-18 16:20       ` Richard Henderson
2021-02-18 16:20         ` Richard Henderson
2021-02-12 19:02   ` Richard Henderson
2021-02-12 19:02     ` Richard Henderson
2021-02-18  8:47     ` LIU Zhiwei
2021-02-18  8:47       ` LIU Zhiwei
2021-02-18 16:21       ` Richard Henderson
2021-02-18 16:21         ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:22   ` Alistair Francis
2021-03-15 21:22     ` Alistair Francis
2021-05-24  1:00     ` Palmer Dabbelt
2021-05-24  1:00       ` Palmer Dabbelt
2021-05-26  5:43       ` LIU Zhiwei
2021-05-26  5:43         ` LIU Zhiwei
2021-05-26  6:15         ` Palmer Dabbelt
2021-05-26  6:15           ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:25   ` Alistair Francis
2021-03-15 21:25     ` Alistair Francis
2021-03-16  2:40     ` LIU Zhiwei
2021-03-16  2:40       ` LIU Zhiwei
2021-03-16 19:54       ` Alistair Francis
2021-03-16 19:54         ` Alistair Francis
2021-03-17  2:30         ` LIU Zhiwei
2021-03-17  2:30           ` LIU Zhiwei
2021-03-17 20:39           ` Alistair Francis
2021-03-17 20:39             ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:27   ` Alistair Francis
2021-03-15 21:27     ` Alistair Francis
2021-05-24  4:46   ` Palmer Dabbelt
2021-05-24  4:46     ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:28   ` Alistair Francis
2021-03-15 21:28     ` Alistair Francis
2021-05-26  5:30   ` Palmer Dabbelt
2021-05-26  5:30     ` Palmer Dabbelt
2021-05-26  5:31     ` Palmer Dabbelt [this message]
2021-05-26  5:31       ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:31   ` Alistair Francis
2021-03-15 21:31     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:33   ` Alistair Francis
2021-03-15 21:33     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-15 21:35   ` Alistair Francis
2021-03-15 21:35     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:38   ` Alistair Francis
2021-03-16 14:38     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:40   ` Alistair Francis
2021-03-16 14:40     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 14:42   ` Alistair Francis
2021-03-16 14:42     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 16:01   ` Alistair Francis
2021-03-16 16:01     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-16 19:44   ` Alistair Francis
2021-03-16 19:44     ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-02-12 15:02   ` LIU Zhiwei
2021-03-05  6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-03-05  6:14   ` LIU Zhiwei
2021-04-13  3:27 ` LIU Zhiwei
2021-04-13  3:27   ` LIU Zhiwei
2021-04-15  4:46   ` Alistair Francis
2021-04-15  4:46     ` Alistair Francis
2021-04-15  5:50     ` LIU Zhiwei
2021-04-15  5:50       ` LIU Zhiwei

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