From: Andy Lutomirski <luto@kernel.org> To: Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, Mel Gorman <mgorman@suse.de>, "linux-mm@kvack.org" <linux-mm@kvack.org>, Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>, Dave Hansen <dave.hansen@intel.com>, Arjan van de Ven <arjan@linux.intel.com>, Peter Zijlstra <peterz@infradead.org>, Juergen Gross <jgross@suse.com>, Boris Ostrovsky <boris.ostrovsky@oracle.com> Subject: Re: [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems Date: Fri, 23 Jun 2017 08:28:05 -0700 [thread overview] Message-ID: <CALCETrU3AcncCUZacmtdPDAptbWjp+RTQpeBokbspp2e395o7A@mail.gmail.com> (raw) In-Reply-To: <20170623115026.qqy5mpyihymocaet@pd.tnic> On Fri, Jun 23, 2017 at 4:50 AM, Borislav Petkov <bp@alien8.de> wrote: > On Tue, Jun 20, 2017 at 10:22:16PM -0700, Andy Lutomirski wrote: >> We can use PCID if the CPU has PCID and PGE and we're not on Xen. >> >> By itself, this has no effect. The next patch will start using >> PCID. >> >> Cc: Juergen Gross <jgross@suse.com> >> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> >> Signed-off-by: Andy Lutomirski <luto@kernel.org> >> --- >> arch/x86/include/asm/tlbflush.h | 8 ++++++++ >> arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ >> arch/x86/xen/enlighten_pv.c | 6 ++++++ >> 3 files changed, 29 insertions(+) >> >> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h >> index 87b13e51e867..57b305e13c4c 100644 >> --- a/arch/x86/include/asm/tlbflush.h >> +++ b/arch/x86/include/asm/tlbflush.h >> @@ -243,6 +243,14 @@ static inline void __flush_tlb_all(void) >> __flush_tlb_global(); >> else >> __flush_tlb(); >> + >> + /* >> + * Note: if we somehow had PCID but not PGE, then this wouldn't work -- >> + * we'd end up flushing kernel translations for the current ASID but >> + * we might fail to flush kernel translations for other cached ASIDs. >> + * >> + * To avoid this issue, we force PCID off if PGE is off. >> + */ >> } >> >> static inline void __flush_tlb_one(unsigned long addr) >> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c >> index 904485e7b230..01caf66b270f 100644 >> --- a/arch/x86/kernel/cpu/common.c >> +++ b/arch/x86/kernel/cpu/common.c >> @@ -1143,6 +1143,21 @@ static void identify_cpu(struct cpuinfo_x86 *c) >> setup_smep(c); >> setup_smap(c); >> >> + /* Set up PCID */ >> + if (cpu_has(c, X86_FEATURE_PCID)) { >> + if (cpu_has(c, X86_FEATURE_PGE)) { > > What are we protecting ourselves here against? Funny virtualization guests? > > Because PGE should be ubiquitous by now. Or have you heard something? Yes, funny VM guests. I've been known to throw weird options at qemu myself, and I prefer when the system works. In this particular case, I think the failure mode would be stale kernel TLB entries, and that would be really annoying. > >> + cr4_set_bits(X86_CR4_PCIDE); >> + } else { >> + /* >> + * flush_tlb_all(), as currently implemented, won't >> + * work if PCID is on but PGE is not. Since that >> + * combination doesn't exist on real hardware, there's >> + * no reason to try to fully support it. >> + */ >> + clear_cpu_cap(c, X86_FEATURE_PCID); >> + } >> + } > > This whole in setup_pcid() I guess, like the rest of the features. Done.
WARNING: multiple messages have this Message-ID (diff)
From: Andy Lutomirski <luto@kernel.org> To: Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Linus Torvalds <torvalds@linux-foundation.org>, Andrew Morton <akpm@linux-foundation.org>, Mel Gorman <mgorman@suse.de>, "linux-mm@kvack.org" <linux-mm@kvack.org>, Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>, Dave Hansen <dave.hansen@intel.com>, Arjan van de Ven <arjan@linux.intel.com>, Peter Zijlstra <peterz@infradead.org>, Juergen Gross <jgross@suse.com>, Boris Ostrovsky <boris.ostrovsky@oracle.com> Subject: Re: [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems Date: Fri, 23 Jun 2017 08:28:05 -0700 [thread overview] Message-ID: <CALCETrU3AcncCUZacmtdPDAptbWjp+RTQpeBokbspp2e395o7A@mail.gmail.com> (raw) In-Reply-To: <20170623115026.qqy5mpyihymocaet@pd.tnic> On Fri, Jun 23, 2017 at 4:50 AM, Borislav Petkov <bp@alien8.de> wrote: > On Tue, Jun 20, 2017 at 10:22:16PM -0700, Andy Lutomirski wrote: >> We can use PCID if the CPU has PCID and PGE and we're not on Xen. >> >> By itself, this has no effect. The next patch will start using >> PCID. >> >> Cc: Juergen Gross <jgross@suse.com> >> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> >> Signed-off-by: Andy Lutomirski <luto@kernel.org> >> --- >> arch/x86/include/asm/tlbflush.h | 8 ++++++++ >> arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ >> arch/x86/xen/enlighten_pv.c | 6 ++++++ >> 3 files changed, 29 insertions(+) >> >> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h >> index 87b13e51e867..57b305e13c4c 100644 >> --- a/arch/x86/include/asm/tlbflush.h >> +++ b/arch/x86/include/asm/tlbflush.h >> @@ -243,6 +243,14 @@ static inline void __flush_tlb_all(void) >> __flush_tlb_global(); >> else >> __flush_tlb(); >> + >> + /* >> + * Note: if we somehow had PCID but not PGE, then this wouldn't work -- >> + * we'd end up flushing kernel translations for the current ASID but >> + * we might fail to flush kernel translations for other cached ASIDs. >> + * >> + * To avoid this issue, we force PCID off if PGE is off. >> + */ >> } >> >> static inline void __flush_tlb_one(unsigned long addr) >> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c >> index 904485e7b230..01caf66b270f 100644 >> --- a/arch/x86/kernel/cpu/common.c >> +++ b/arch/x86/kernel/cpu/common.c >> @@ -1143,6 +1143,21 @@ static void identify_cpu(struct cpuinfo_x86 *c) >> setup_smep(c); >> setup_smap(c); >> >> + /* Set up PCID */ >> + if (cpu_has(c, X86_FEATURE_PCID)) { >> + if (cpu_has(c, X86_FEATURE_PGE)) { > > What are we protecting ourselves here against? Funny virtualization guests? > > Because PGE should be ubiquitous by now. Or have you heard something? Yes, funny VM guests. I've been known to throw weird options at qemu myself, and I prefer when the system works. In this particular case, I think the failure mode would be stale kernel TLB entries, and that would be really annoying. > >> + cr4_set_bits(X86_CR4_PCIDE); >> + } else { >> + /* >> + * flush_tlb_all(), as currently implemented, won't >> + * work if PCID is on but PGE is not. Since that >> + * combination doesn't exist on real hardware, there's >> + * no reason to try to fully support it. >> + */ >> + clear_cpu_cap(c, X86_FEATURE_PCID); >> + } >> + } > > This whole in setup_pcid() I guess, like the rest of the features. Done. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"dont@kvack.org"> email@kvack.org </a>
next prev parent reply other threads:[~2017-06-23 15:28 UTC|newest] Thread overview: 154+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-06-21 5:22 [PATCH v3 00/11] PCID and improved laziness Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 01/11] x86/mm: Don't reenter flush_tlb_func_common() Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 8:01 ` Thomas Gleixner 2017-06-21 8:01 ` Thomas Gleixner 2017-06-21 8:49 ` Borislav Petkov 2017-06-21 8:49 ` Borislav Petkov 2017-06-21 15:15 ` Andy Lutomirski 2017-06-21 15:15 ` Andy Lutomirski 2017-06-21 23:26 ` Nadav Amit 2017-06-21 23:26 ` Nadav Amit 2017-06-22 2:27 ` Andy Lutomirski 2017-06-22 2:27 ` Andy Lutomirski 2017-06-22 7:32 ` Ingo Molnar 2017-06-22 7:32 ` Ingo Molnar 2017-06-21 5:22 ` [PATCH v3 02/11] x86/ldt: Simplify LDT switching logic Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 8:03 ` Thomas Gleixner 2017-06-21 8:03 ` Thomas Gleixner 2017-06-21 9:40 ` Borislav Petkov 2017-06-21 9:40 ` Borislav Petkov 2017-06-22 11:08 ` [tip:x86/mm] x86/ldt: Simplify the " tip-bot for Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 03/11] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 8:03 ` Thomas Gleixner 2017-06-21 8:03 ` Thomas Gleixner 2017-06-21 9:50 ` Borislav Petkov 2017-06-21 9:50 ` Borislav Petkov 2017-06-22 11:08 ` [tip:x86/mm] " tip-bot for Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 04/11] x86/mm: Give each mm TLB flush generation a unique ID Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 8:05 ` Thomas Gleixner 2017-06-21 8:05 ` Thomas Gleixner 2017-06-21 10:33 ` Borislav Petkov 2017-06-21 10:33 ` Borislav Petkov 2017-06-21 15:23 ` Andy Lutomirski 2017-06-21 15:23 ` Andy Lutomirski 2017-06-21 17:06 ` Borislav Petkov 2017-06-21 17:06 ` Borislav Petkov 2017-06-21 17:43 ` Borislav Petkov 2017-06-21 17:43 ` Borislav Petkov 2017-06-22 2:34 ` Andy Lutomirski 2017-06-22 2:34 ` Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 05/11] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 8:32 ` Thomas Gleixner 2017-06-21 8:32 ` Thomas Gleixner 2017-06-21 15:11 ` Andy Lutomirski 2017-06-21 15:11 ` Andy Lutomirski 2017-06-21 18:44 ` Borislav Petkov 2017-06-21 18:44 ` Borislav Petkov 2017-06-22 2:46 ` Andy Lutomirski 2017-06-22 2:46 ` Andy Lutomirski 2017-06-22 7:24 ` Borislav Petkov 2017-06-22 7:24 ` Borislav Petkov 2017-06-22 14:48 ` Andy Lutomirski 2017-06-22 14:48 ` Andy Lutomirski 2017-06-22 14:59 ` Borislav Petkov 2017-06-22 14:59 ` Borislav Petkov 2017-06-22 15:55 ` Andy Lutomirski 2017-06-22 15:55 ` Andy Lutomirski 2017-06-22 17:22 ` Borislav Petkov 2017-06-22 17:22 ` Borislav Petkov 2017-06-22 18:08 ` Andy Lutomirski 2017-06-22 18:08 ` Andy Lutomirski 2017-06-23 8:42 ` Borislav Petkov 2017-06-23 8:42 ` Borislav Petkov 2017-06-23 15:46 ` Andy Lutomirski 2017-06-23 15:46 ` Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 06/11] x86/mm: Rework lazy TLB mode and TLB freshness tracking Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 9:01 ` Thomas Gleixner 2017-06-21 9:01 ` Thomas Gleixner 2017-06-21 16:04 ` Andy Lutomirski 2017-06-21 16:04 ` Andy Lutomirski 2017-06-21 17:29 ` Borislav Petkov 2017-06-21 17:29 ` Borislav Petkov 2017-06-22 14:50 ` Borislav Petkov 2017-06-22 14:50 ` Borislav Petkov 2017-06-22 17:47 ` Andy Lutomirski 2017-06-22 17:47 ` Andy Lutomirski 2017-06-22 19:05 ` Borislav Petkov 2017-06-22 19:05 ` Borislav Petkov 2017-07-27 19:53 ` Andrew Banman 2017-07-27 19:53 ` Andrew Banman 2017-07-28 2:05 ` Andy Lutomirski 2017-07-28 2:05 ` Andy Lutomirski 2017-06-23 13:34 ` Boris Ostrovsky 2017-06-23 13:34 ` Boris Ostrovsky 2017-06-23 15:22 ` Andy Lutomirski 2017-06-23 15:22 ` Andy Lutomirski 2017-06-21 5:22 ` [PATCH v3 07/11] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 9:22 ` Thomas Gleixner 2017-06-21 9:22 ` Thomas Gleixner 2017-06-21 15:16 ` Andy Lutomirski 2017-06-21 15:16 ` Andy Lutomirski 2017-06-23 9:07 ` Borislav Petkov 2017-06-23 9:07 ` Borislav Petkov 2017-06-21 5:22 ` [PATCH v3 08/11] x86/mm: Disable PCID on 32-bit kernels Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 9:26 ` Thomas Gleixner 2017-06-21 9:26 ` Thomas Gleixner 2017-06-23 9:24 ` Borislav Petkov 2017-06-23 9:24 ` Borislav Petkov 2017-06-21 5:22 ` [PATCH v3 09/11] x86/mm: Add nopcid to turn off PCID Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 9:27 ` Thomas Gleixner 2017-06-21 9:27 ` Thomas Gleixner 2017-06-23 9:34 ` Borislav Petkov 2017-06-23 9:34 ` Borislav Petkov 2017-06-21 5:22 ` [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 9:39 ` Thomas Gleixner 2017-06-21 9:39 ` Thomas Gleixner 2017-06-21 13:40 ` Thomas Gleixner 2017-06-21 13:40 ` Thomas Gleixner 2017-06-21 20:34 ` Andy Lutomirski 2017-06-21 20:34 ` Andy Lutomirski 2017-06-23 11:50 ` Borislav Petkov 2017-06-23 11:50 ` Borislav Petkov 2017-06-23 15:28 ` Andy Lutomirski [this message] 2017-06-23 15:28 ` Andy Lutomirski 2017-06-23 13:35 ` Boris Ostrovsky 2017-06-23 13:35 ` Boris Ostrovsky 2017-06-21 5:22 ` [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski 2017-06-21 5:22 ` Andy Lutomirski 2017-06-21 13:38 ` Thomas Gleixner 2017-06-21 13:38 ` Thomas Gleixner 2017-06-21 13:40 ` Thomas Gleixner 2017-06-21 13:40 ` Thomas Gleixner 2017-06-22 2:57 ` Andy Lutomirski 2017-06-22 2:57 ` Andy Lutomirski 2017-06-22 12:21 ` Thomas Gleixner 2017-06-22 12:21 ` Thomas Gleixner 2017-06-22 18:12 ` Andy Lutomirski 2017-06-22 18:12 ` Andy Lutomirski 2017-06-22 21:22 ` Thomas Gleixner 2017-06-22 21:22 ` Thomas Gleixner 2017-06-23 3:09 ` Andy Lutomirski 2017-06-23 3:09 ` Andy Lutomirski 2017-06-23 7:29 ` Thomas Gleixner 2017-06-23 7:29 ` Thomas Gleixner 2017-06-22 16:09 ` Nadav Amit 2017-06-22 16:09 ` Nadav Amit 2017-06-22 18:10 ` Andy Lutomirski 2017-06-22 18:10 ` Andy Lutomirski 2017-06-26 15:58 ` Borislav Petkov 2017-06-26 15:58 ` Borislav Petkov 2017-06-21 18:23 ` [PATCH v3 00/11] PCID and improved laziness Linus Torvalds 2017-06-21 18:23 ` Linus Torvalds 2017-06-22 5:19 ` Andy Lutomirski 2017-06-22 5:19 ` Andy Lutomirski
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