* PAE mode save/restore broken
@ 2020-06-02 0:11 Jim Mattson
2020-06-04 14:51 ` Paolo Bonzini
0 siblings, 1 reply; 3+ messages in thread
From: Jim Mattson @ 2020-06-02 0:11 UTC (permalink / raw)
To: kvm list, Paolo Bonzini; +Cc: Sean Christopherson
I can only assume that no one cares that KVM_GET_SREGS/KVM_SET_SREGS
is broken for PAE mode guests (i.e. KVM_GET_SREGS doesn't capture the
PDPTRs and KVM_SET_SREGS re-reads them from memory).
Presumably, since AMD's nested paging is broken for PAE mode guests,
the kvm community has made the decision not to get things right for
Intel either. Can anyone confirm? This was all before my time.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PAE mode save/restore broken
2020-06-02 0:11 PAE mode save/restore broken Jim Mattson
@ 2020-06-04 14:51 ` Paolo Bonzini
2020-06-04 16:27 ` Jim Mattson
0 siblings, 1 reply; 3+ messages in thread
From: Paolo Bonzini @ 2020-06-04 14:51 UTC (permalink / raw)
To: Jim Mattson, kvm list; +Cc: Sean Christopherson
On 02/06/20 02:11, Jim Mattson wrote:
> I can only assume that no one cares that KVM_GET_SREGS/KVM_SET_SREGS
> is broken for PAE mode guests (i.e. KVM_GET_SREGS doesn't capture the
> PDPTRs and KVM_SET_SREGS re-reads them from memory).
>
> Presumably, since AMD's nested paging is broken for PAE mode guests,
> the kvm community has made the decision not to get things right for
> Intel either. Can anyone confirm? This was all before my time.
Yes, pretty much. The PDPTRs are not part of the saved state, we just
treat them as a small third level in the radix tree. Of course, for
nested VMX they are properly synced to the VMCS12 and serialized by
KVM_SET_NESTED_STATE.
Out of curiosity are there OSes that rely on the PDPTRs remaining cached
until the next CR3 load?
Paolo
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PAE mode save/restore broken
2020-06-04 14:51 ` Paolo Bonzini
@ 2020-06-04 16:27 ` Jim Mattson
0 siblings, 0 replies; 3+ messages in thread
From: Jim Mattson @ 2020-06-04 16:27 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: kvm list, Sean Christopherson
On Thu, Jun 4, 2020 at 7:51 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 02/06/20 02:11, Jim Mattson wrote:
> > I can only assume that no one cares that KVM_GET_SREGS/KVM_SET_SREGS
> > is broken for PAE mode guests (i.e. KVM_GET_SREGS doesn't capture the
> > PDPTRs and KVM_SET_SREGS re-reads them from memory).
> >
> > Presumably, since AMD's nested paging is broken for PAE mode guests,
> > the kvm community has made the decision not to get things right for
> > Intel either. Can anyone confirm? This was all before my time.
>
> Yes, pretty much. The PDPTRs are not part of the saved state, we just
> treat them as a small third level in the radix tree. Of course, for
> nested VMX they are properly synced to the VMCS12 and serialized by
> KVM_SET_NESTED_STATE.
>
> Out of curiosity are there OSes that rely on the PDPTRs remaining cached
> until the next CR3 load?
None that I know of.
It's interesting that Intel has taken great pains to virtualize the
architected behavior, but AMD just shrugged it off.
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-06-04 16:28 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2020-06-02 0:11 PAE mode save/restore broken Jim Mattson
2020-06-04 14:51 ` Paolo Bonzini
2020-06-04 16:27 ` Jim Mattson
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