* [PATCH v2 00/11] Add USB2.0 support.
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
Greg Kroah-Hartman, linux-phy, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
This patch series aims to add USB PHY Control, USB2.0 Host and USB2.0 device
support for RZ/G2L SoC.
v1->v2
* Updated usb phy control bindings with clock definitions
* Updated generic ohci/ehci bindings to support RZ/G2L SoC
* Incorporated vind's review comment on us phy control driver
* Add support for USB2.0 device and OTG support.
v1:
- https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=498915
Biju Das (11):
dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
drivers: clk: renesas: r9a07g044-cpg: Add USB clocks
phy: renesas: Add RZ/G2L usb phy control driver
arm64: configs: defconfig: Enable RZ/G2L USB PHY control driver
dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
dt-bindings: usb: generic-ehci: Document RZ/G2L SoC bindings
arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
arm64: dts: renesas: r9a07g044: Add USB2.0 device support
.../phy/renesas,rzg2l-usbphyctrl.yaml | 65 ++++++++
.../bindings/phy/renesas,usb2-phy.yaml | 23 +--
.../devicetree/bindings/usb/generic-ehci.yaml | 33 +++-
.../devicetree/bindings/usb/generic-ohci.yaml | 32 +++-
.../bindings/usb/renesas,usbhs.yaml | 44 ++++-
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 119 +++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 12 ++
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63 +++++--
drivers/phy/renesas/phy-rzg2l-usbphyctrl.c | 157 ++++++++++++++++++
12 files changed, 522 insertions(+), 35 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
create mode 100644 drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Add device tree binding document for RZ/G2L USB PHY control driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->V2:
* Add clock properties
---
.../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
new file mode 100644
index 000000000000..8e8ba43f595d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg2l-usbphyctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USB2.0 PHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USB2.0 PHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphyctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#phy-cells':
+ # see phy-bindings.txt in the same directory
+ const: 1
+ description: |
+ The phandle's argument in the PHY specifier is the phy reset control bit
+ of usb phy control.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+ enum: [ 0, 1 ]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ usbphyctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphyctrl",
+ "renesas,rzg2l-usbphyctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>;
+ power-domains = <&cpg>;
+ #phy-cells = <1>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Add device tree binding document for RZ/G2L USB PHY control driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->V2:
* Add clock properties
---
.../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
new file mode 100644
index 000000000000..8e8ba43f595d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg2l-usbphyctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USB2.0 PHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USB2.0 PHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphyctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#phy-cells':
+ # see phy-bindings.txt in the same directory
+ const: 1
+ description: |
+ The phandle's argument in the PHY specifier is the phy reset control bit
+ of usb phy control.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+ enum: [ 0, 1 ]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ usbphyctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphyctrl",
+ "renesas,rzg2l-usbphyctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>;
+ power-domains = <&cpg>;
+ #phy-cells = <1>;
+ };
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 17:40 ` Rob Herring
-1 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-21 17:40 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Chris Paterson, Vinod Koul, linux-renesas-soc,
Kishon Vijay Abraham I, Geert Uytterhoeven, Yoshihiro Shimoda,
linux-phy, Biju Das, Prabhakar Mahadev Lad, devicetree
On Mon, 21 Jun 2021 10:39:33 +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USB PHY control driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
> * Add clock properties
> ---
> .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.example.dts:19:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
19 | #include <dt-bindings/clock/r9a07g044-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494979
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-21 17:40 ` Rob Herring
0 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-21 17:40 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Chris Paterson, Vinod Koul, linux-renesas-soc,
Kishon Vijay Abraham I, Geert Uytterhoeven, Yoshihiro Shimoda,
linux-phy, Biju Das, Prabhakar Mahadev Lad, devicetree
On Mon, 21 Jun 2021 10:39:33 +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USB PHY control driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
> * Add clock properties
> ---
> .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.example.dts:19:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
19 | #include <dt-bindings/clock/r9a07g044-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494979
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-21 9:39 ` Biju Das
@ 2021-06-22 16:58 ` Rob Herring
-1 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-22 16:58 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USB PHY control driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
> * Add clock properties
> ---
> .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> new file mode 100644
> index 000000000000..8e8ba43f595d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/renesas,rzg2l-usbphyctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L USB2.0 PHY Control
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description:
> + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down of the
> + USB/PHY.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> + - const: renesas,rzg2l-usbphyctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + '#phy-cells':
> + # see phy-bindings.txt in the same directory
> + const: 1
> + description: |
> + The phandle's argument in the PHY specifier is the phy reset control bit
> + of usb phy control.
> + 0 = Port 1 Phy reset
> + 1 = Port 2 Phy reset
> + enum: [ 0, 1 ]
You already have the const, so this doesn't do anything.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#phy-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + usbphyctrl@11c40000 {
usb-phy@...
> + compatible = "renesas,r9a07g044-usbphyctrl",
> + "renesas,rzg2l-usbphyctrl";
> + reg = <0x11c40000 0x10000>;
> + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> + resets = <&cpg R9A07G044_USB_PCLK>;
> + power-domains = <&cpg>;
> + #phy-cells = <1>;
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-22 16:58 ` Rob Herring
0 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-22 16:58 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USB PHY control driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
> * Add clock properties
> ---
> .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> new file mode 100644
> index 000000000000..8e8ba43f595d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/renesas,rzg2l-usbphyctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L USB2.0 PHY Control
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description:
> + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down of the
> + USB/PHY.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> + - const: renesas,rzg2l-usbphyctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + '#phy-cells':
> + # see phy-bindings.txt in the same directory
> + const: 1
> + description: |
> + The phandle's argument in the PHY specifier is the phy reset control bit
> + of usb phy control.
> + 0 = Port 1 Phy reset
> + 1 = Port 2 Phy reset
> + enum: [ 0, 1 ]
You already have the const, so this doesn't do anything.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#phy-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + usbphyctrl@11c40000 {
usb-phy@...
> + compatible = "renesas,r9a07g044-usbphyctrl",
> + "renesas,rzg2l-usbphyctrl";
> + reg = <0x11c40000 0x10000>;
> + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> + resets = <&cpg R9A07G044_USB_PCLK>;
> + power-domains = <&cpg>;
> + #phy-cells = <1>;
> + };
> --
> 2.17.1
>
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-22 16:58 ` Rob Herring
@ 2021-06-23 13:38 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 13:38 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > Add device tree binding document for RZ/G2L USB PHY control driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > V1->V2:
> > * Add clock properties
> > ---
> > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> > 1 file changed, 65 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > new file mode 100644
> > index 000000000000..8e8ba43f595d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > +++ aml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&d
> > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9
> > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779421910
> > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5LxTB
> > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIzi4%3
> > +D&reserved=0
> > +
> > +title: Renesas RZ/G2L USB2.0 PHY Control
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description:
> > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down
> > +of the
> > + USB/PHY.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > + - const: renesas,rzg2l-usbphyctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + '#phy-cells':
> > + # see phy-bindings.txt in the same directory
> > + const: 1
> > + description: |
> > + The phandle's argument in the PHY specifier is the phy reset
> control bit
> > + of usb phy control.
> > + 0 = Port 1 Phy reset
> > + 1 = Port 2 Phy reset
> > + enum: [ 0, 1 ]
>
> You already have the const, so this doesn't do anything.
OK, will take out const.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - '#phy-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > + usbphyctrl@11c40000 {
>
> usb-phy@...
The IP is called USBPHY control. It mainly controls reset and power down of the USB2.0/PHY.
So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead. Is it ok? Please let me know.
Cheers,
Biju
> > + compatible = "renesas,r9a07g044-usbphyctrl",
> > + "renesas,rzg2l-usbphyctrl";
> > + reg = <0x11c40000 0x10000>;
> > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > + resets = <&cpg R9A07G044_USB_PCLK>;
> > + power-domains = <&cpg>;
> > + #phy-cells = <1>;
> > + };
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-23 13:38 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 13:38 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > Add device tree binding document for RZ/G2L USB PHY control driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > V1->V2:
> > * Add clock properties
> > ---
> > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> > 1 file changed, 65 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > new file mode 100644
> > index 000000000000..8e8ba43f595d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > +++ aml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&d
> > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9
> > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779421910
> > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5LxTB
> > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIzi4%3
> > +D&reserved=0
> > +
> > +title: Renesas RZ/G2L USB2.0 PHY Control
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description:
> > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down
> > +of the
> > + USB/PHY.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > + - const: renesas,rzg2l-usbphyctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + '#phy-cells':
> > + # see phy-bindings.txt in the same directory
> > + const: 1
> > + description: |
> > + The phandle's argument in the PHY specifier is the phy reset
> control bit
> > + of usb phy control.
> > + 0 = Port 1 Phy reset
> > + 1 = Port 2 Phy reset
> > + enum: [ 0, 1 ]
>
> You already have the const, so this doesn't do anything.
OK, will take out const.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - '#phy-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > + usbphyctrl@11c40000 {
>
> usb-phy@...
The IP is called USBPHY control. It mainly controls reset and power down of the USB2.0/PHY.
So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead. Is it ok? Please let me know.
Cheers,
Biju
> > + compatible = "renesas,r9a07g044-usbphyctrl",
> > + "renesas,rzg2l-usbphyctrl";
> > + reg = <0x11c40000 0x10000>;
> > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > + resets = <&cpg R9A07G044_USB_PCLK>;
> > + power-domains = <&cpg>;
> > + #phy-cells = <1>;
> > + };
> > --
> > 2.17.1
> >
> >
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-23 13:38 ` Biju Das
@ 2021-06-23 14:13 ` Rob Herring
-1 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-23 14:13 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> > USB PHY Control bindings
> >
> > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > V1->V2:
> > > * Add clock properties
> > > ---
> > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > > new file mode 100644
> > > index 000000000000..8e8ba43f595d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > +++ aml
> > > @@ -0,0 +1,65 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&d
> > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9
> > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779421910
> > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5LxTB
> > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > +$schema:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571da19
> > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWFpbGZ
> > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIzi4%3
> > > +D&reserved=0
> > > +
> > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description:
> > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down
> > > +of the
> > > + USB/PHY.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > + - const: renesas,rzg2l-usbphyctrl
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + '#phy-cells':
> > > + # see phy-bindings.txt in the same directory
> > > + const: 1
> > > + description: |
> > > + The phandle's argument in the PHY specifier is the phy reset
> > control bit
> > > + of usb phy control.
> > > + 0 = Port 1 Phy reset
> > > + 1 = Port 2 Phy reset
> > > + enum: [ 0, 1 ]
> >
> > You already have the const, so this doesn't do anything.
>
> OK, will take out const.
No, 'const' is correct. This is the value of '#phy-cells', not the
contents (we don't have a way to express schema for that).
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - clocks
> > > + - '#phy-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > +
> > > + usbphyctrl@11c40000 {
> >
> > usb-phy@...
>
> The IP is called USBPHY control. It mainly controls reset and power down of the USB2.0/PHY.
Sounds like it should be using the reset binding...
>
> So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead. Is it ok? Please let me know.
A node with #phy-cells should use the standard phy node names unless
it has other controls. As I said, this doesn't seem to be a phy, so
using #phy-cells here is what seems wrong.
> > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > + "renesas,rzg2l-usbphyctrl";
> > > + reg = <0x11c40000 0x10000>;
> > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > + power-domains = <&cpg>;
Also, are these all resources of the usbphyctrl block and not just
resources you happen to want in the driver? For example, the
power-domain should be the power island that this block resides in.
> > > + #phy-cells = <1>;
> > > + };
> > > --
> > > 2.17.1
> > >
> > >
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-23 14:13 ` Rob Herring
0 siblings, 0 replies; 50+ messages in thread
From: Rob Herring @ 2021-06-23 14:13 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> > USB PHY Control bindings
> >
> > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > V1->V2:
> > > * Add clock properties
> > > ---
> > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65 +++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yaml
> > > new file mode 100644
> > > index 000000000000..8e8ba43f595d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > +++ aml
> > > @@ -0,0 +1,65 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&d
> > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9
> > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779421910
> > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5LxTB
> > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > +$schema:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571da19
> > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWFpbGZ
> > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIzi4%3
> > > +D&reserved=0
> > > +
> > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description:
> > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power down
> > > +of the
> > > + USB/PHY.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > + - const: renesas,rzg2l-usbphyctrl
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 1
> > > +
> > > + resets:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + '#phy-cells':
> > > + # see phy-bindings.txt in the same directory
> > > + const: 1
> > > + description: |
> > > + The phandle's argument in the PHY specifier is the phy reset
> > control bit
> > > + of usb phy control.
> > > + 0 = Port 1 Phy reset
> > > + 1 = Port 2 Phy reset
> > > + enum: [ 0, 1 ]
> >
> > You already have the const, so this doesn't do anything.
>
> OK, will take out const.
No, 'const' is correct. This is the value of '#phy-cells', not the
contents (we don't have a way to express schema for that).
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - clocks
> > > + - '#phy-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > +
> > > + usbphyctrl@11c40000 {
> >
> > usb-phy@...
>
> The IP is called USBPHY control. It mainly controls reset and power down of the USB2.0/PHY.
Sounds like it should be using the reset binding...
>
> So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead. Is it ok? Please let me know.
A node with #phy-cells should use the standard phy node names unless
it has other controls. As I said, this doesn't seem to be a phy, so
using #phy-cells here is what seems wrong.
> > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > + "renesas,rzg2l-usbphyctrl";
> > > + reg = <0x11c40000 0x10000>;
> > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > + power-domains = <&cpg>;
Also, are these all resources of the usbphyctrl block and not just
resources you happen to want in the driver? For example, the
power-domain should be the power island that this block resides in.
> > > + #phy-cells = <1>;
> > > + };
> > > --
> > > 2.17.1
> > >
> > >
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-23 14:13 ` Rob Herring
@ 2021-06-23 14:29 ` Geert Uytterhoeven
-1 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 14:29 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
On Wed, Jun 23, 2021 at 4:13 PM Rob Herring <robh@kernel.org> wrote:
> On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> > > USB PHY Control bindings
> > >
> > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > + "renesas,rzg2l-usbphyctrl";
> > > > + reg = <0x11c40000 0x10000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > + power-domains = <&cpg>;
>
> Also, are these all resources of the usbphyctrl block and not just
> resources you happen to want in the driver? For example, the
> power-domain should be the power island that this block resides in.
It's a clock domain, not a power area: the block goes into power-save
mode by stopping the module clock controlled by the CPG.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-23 14:29 ` Geert Uytterhoeven
0 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 14:29 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
On Wed, Jun 23, 2021 at 4:13 PM Rob Herring <robh@kernel.org> wrote:
> On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> > > USB PHY Control bindings
> > >
> > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > + "renesas,rzg2l-usbphyctrl";
> > > > + reg = <0x11c40000 0x10000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > + power-domains = <&cpg>;
>
> Also, are these all resources of the usbphyctrl block and not just
> resources you happen to want in the driver? For example, the
> power-domain should be the power island that this block resides in.
It's a clock domain, not a power area: the block goes into power-save
mode by stopping the module clock controlled by the CPG.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-23 14:13 ` Rob Herring
@ 2021-06-23 15:45 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 15:45 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Rob,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > > RZ/G2L USB PHY Control bindings
> > >
> > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > V1->V2:
> > > > * Add clock properties
> > > > ---
> > > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65
> +++++++++++++++++++
> > > > 1 file changed, 65 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yam
> > > > l
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > aml
> > > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > aml
> > > > new file mode 100644
> > > > index 000000000000..8e8ba43f595d
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyct
> > > > +++ rl.y
> > > > +++ aml
> > > > @@ -0,0 +1,65 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&a
> > > > +mp;d
> > > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a
> > > > +08d9
> > > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63759977942
> > > > +1910
> > > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL
> > > > +CJBT
> > > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5
> > > > +LxTB
> > > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > > +$schema:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571
> > > > +da19
> > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWF
> > > > +pbGZ
> > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > +Mn0%
> > > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIz
> > > > +i4%3
> > > > +D&reserved=0
> > > > +
> > > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > > +
> > > > +maintainers:
> > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +description:
> > > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power
> > > > +down of the
> > > > + USB/PHY.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > > + - const: renesas,rzg2l-usbphyctrl
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + clocks:
> > > > + maxItems: 1
> > > > +
> > > > + resets:
> > > > + maxItems: 1
> > > > +
> > > > + power-domains:
> > > > + maxItems: 1
> > > > +
> > > > + '#phy-cells':
> > > > + # see phy-bindings.txt in the same directory
> > > > + const: 1
> > > > + description: |
> > > > + The phandle's argument in the PHY specifier is the phy
> > > > + reset
> > > control bit
> > > > + of usb phy control.
> > > > + 0 = Port 1 Phy reset
> > > > + 1 = Port 2 Phy reset
> > > > + enum: [ 0, 1 ]
> > >
> > > You already have the const, so this doesn't do anything.
> >
> > OK, will take out const.
>
> No, 'const' is correct. This is the value of '#phy-cells', not the
> contents (we don't have a way to express schema for that).
OK.
>
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - clocks
> > > > + - '#phy-cells'
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > +
> > > > + usbphyctrl@11c40000 {
> > >
> > > usb-phy@...
> >
> > The IP is called USBPHY control. It mainly controls reset and power down
> of the USB2.0/PHY.
>
> Sounds like it should be using the reset binding...
This IP has reset, clock control , connection control , clock status and power down setting registers.
Currenty we are using reset registers for turning ON USB/PHY block.
Since it has extra registers I thought of modelling it as a phy device. But we could model as reset device as well.
But it has extra functionalities apart from reset.
So what do you propose here? Model as a reset device or phy device since it is related to phy?
Please share your opinion on this.
Regards,
Biju
> >
> > So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead.
> Is it ok? Please let me know.
>
> A node with #phy-cells should use the standard phy node names unless it
> has other controls.
Apart from reset, it has other controls like clock control , connection control , clock status and powerdown setting registers.
Cheers,
Biju
As I said, this doesn't seem to be a phy, so using
> #phy-cells here is what seems wrong.
>
> > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > + "renesas,rzg2l-usbphyctrl";
> > > > + reg = <0x11c40000 0x10000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > + power-domains = <&cpg>;
>
> Also, are these all resources of the usbphyctrl block and not just
> resources you happen to want in the driver? For example, the power-domain
> should be the power island that this block resides in.
>
> > > > + #phy-cells = <1>;
> > > > + };
> > > > --
> > > > 2.17.1
> > > >
> > > >
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-23 15:45 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 15:45 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Rob,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > > RZ/G2L USB PHY Control bindings
> > >
> > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USB PHY control driver.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > V1->V2:
> > > > * Add clock properties
> > > > ---
> > > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65
> +++++++++++++++++++
> > > > 1 file changed, 65 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.yam
> > > > l
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > aml
> > > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > aml
> > > > new file mode 100644
> > > > index 000000000000..8e8ba43f595d
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyct
> > > > +++ rl.y
> > > > +++ aml
> > > > @@ -0,0 +1,65 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23&a
> > > > +mp;d
> > > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a
> > > > +08d9
> > > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63759977942
> > > > +1910
> > > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiL
> > > > +CJBT
> > > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rmt5
> > > > +LxTB
> > > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > > +$schema:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d82571
> > > > +da19
> > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CTWF
> > > > +pbGZ
> > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > +Mn0%
> > > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0SIz
> > > > +i4%3
> > > > +D&reserved=0
> > > > +
> > > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > > +
> > > > +maintainers:
> > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +description:
> > > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power
> > > > +down of the
> > > > + USB/PHY.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > > + - const: renesas,rzg2l-usbphyctrl
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + clocks:
> > > > + maxItems: 1
> > > > +
> > > > + resets:
> > > > + maxItems: 1
> > > > +
> > > > + power-domains:
> > > > + maxItems: 1
> > > > +
> > > > + '#phy-cells':
> > > > + # see phy-bindings.txt in the same directory
> > > > + const: 1
> > > > + description: |
> > > > + The phandle's argument in the PHY specifier is the phy
> > > > + reset
> > > control bit
> > > > + of usb phy control.
> > > > + 0 = Port 1 Phy reset
> > > > + 1 = Port 2 Phy reset
> > > > + enum: [ 0, 1 ]
> > >
> > > You already have the const, so this doesn't do anything.
> >
> > OK, will take out const.
>
> No, 'const' is correct. This is the value of '#phy-cells', not the
> contents (we don't have a way to express schema for that).
OK.
>
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - clocks
> > > > + - '#phy-cells'
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > +
> > > > + usbphyctrl@11c40000 {
> > >
> > > usb-phy@...
> >
> > The IP is called USBPHY control. It mainly controls reset and power down
> of the USB2.0/PHY.
>
> Sounds like it should be using the reset binding...
This IP has reset, clock control , connection control , clock status and power down setting registers.
Currenty we are using reset registers for turning ON USB/PHY block.
Since it has extra registers I thought of modelling it as a phy device. But we could model as reset device as well.
But it has extra functionalities apart from reset.
So what do you propose here? Model as a reset device or phy device since it is related to phy?
Please share your opinion on this.
Regards,
Biju
> >
> > So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead.
> Is it ok? Please let me know.
>
> A node with #phy-cells should use the standard phy node names unless it
> has other controls.
Apart from reset, it has other controls like clock control , connection control , clock status and powerdown setting registers.
Cheers,
Biju
As I said, this doesn't seem to be a phy, so using
> #phy-cells here is what seems wrong.
>
> > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > + "renesas,rzg2l-usbphyctrl";
> > > > + reg = <0x11c40000 0x10000>;
> > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > + power-domains = <&cpg>;
>
> Also, are these all resources of the usbphyctrl block and not just
> resources you happen to want in the driver? For example, the power-domain
> should be the power island that this block resides in.
>
> > > > + #phy-cells = <1>;
> > > > + };
> > > > --
> > > > 2.17.1
> > > >
> > > >
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
2021-06-23 15:45 ` Biju Das
@ 2021-06-25 10:11 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-25 10:11 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
> Subject: RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > RZ/G2L USB PHY Control bindings
> >
> > On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > > Thanks for the feedback.
> > >
> > > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > > > RZ/G2L USB PHY Control bindings
> > > >
> > > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > > Add device tree binding document for RZ/G2L USB PHY control
> driver.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > V1->V2:
> > > > > * Add clock properties
> > > > > ---
> > > > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65
> > +++++++++++++++++++
> > > > > 1 file changed, 65 insertions(+) create mode 100644
> > > > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > > am
> > > > > l
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl
> > > > > .y
> > > > > aml
> > > > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl
> > > > > .y
> > > > > aml
> > > > > new file mode 100644
> > > > > index 000000000000..8e8ba43f595d
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphy
> > > > > +++ ct
> > > > > +++ rl.y
> > > > > +++ aml
> > > > > @@ -0,0 +1,65 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%
> > > > > +2F
> > > > > +devi
> > > > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23
> > > > > +&a
> > > > > +mp;d
> > > > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa72
> > > > > +2a
> > > > > +08d9
> > > > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779
> > > > > +42
> > > > > +1910
> > > > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzI
> > > > > +iL
> > > > > +CJBT
> > > > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rm
> > > > > +t5
> > > > > +LxTB
> > > > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > > > +$schema:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%
> > > > > +2F
> > > > > +devi
> > > > > +cetree.org%2Fmeta-
> > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d825
> > > > > +71
> > > > > +da19
> > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CT
> > > > > +WF
> > > > > +pbGZ
> > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVC
> > > > > +I6
> > > > > +Mn0%
> > > > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0S
> > > > > +Iz
> > > > > +i4%3
> > > > > +D&reserved=0
> > > > > +
> > > > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > > > +
> > > > > +maintainers:
> > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > +
> > > > > +description:
> > > > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power
> > > > > +down of the
> > > > > + USB/PHY.
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > > > + - const: renesas,rzg2l-usbphyctrl
> > > > > +
> > > > > + reg:
> > > > > + maxItems: 1
> > > > > +
> > > > > + clocks:
> > > > > + maxItems: 1
> > > > > +
> > > > > + resets:
> > > > > + maxItems: 1
> > > > > +
> > > > > + power-domains:
> > > > > + maxItems: 1
> > > > > +
> > > > > + '#phy-cells':
> > > > > + # see phy-bindings.txt in the same directory
> > > > > + const: 1
> > > > > + description: |
> > > > > + The phandle's argument in the PHY specifier is the phy
> > > > > + reset
> > > > control bit
> > > > > + of usb phy control.
> > > > > + 0 = Port 1 Phy reset
> > > > > + 1 = Port 2 Phy reset
> > > > > + enum: [ 0, 1 ]
> > > >
> > > > You already have the const, so this doesn't do anything.
> > >
> > > OK, will take out const.
> >
> > No, 'const' is correct. This is the value of '#phy-cells', not the
> > contents (we don't have a way to express schema for that).
>
> OK.
>
> >
> > > > > +required:
> > > > > + - compatible
> > > > > + - reg
> > > > > + - clocks
> > > > > + - '#phy-cells'
> > > > > +
> > > > > +additionalProperties: false
> > > > > +
> > > > > +examples:
> > > > > + - |
> > > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > +
> > > > > + usbphyctrl@11c40000 {
> > > >
> > > > usb-phy@...
> > >
> > > The IP is called USBPHY control. It mainly controls reset and power
> > > down
> > of the USB2.0/PHY.
> >
> > Sounds like it should be using the reset binding...
OK, Will model this as a reset binding. Since the IP mainly controls reset and power down
Of the USB2.0/PHY. So it is better to have reset binding.
Regards,
Biju
> This IP has reset, clock control , connection control , clock status and
> power down setting registers.
> Currenty we are using reset registers for turning ON USB/PHY block.
>
> Since it has extra registers I thought of modelling it as a phy device.
> But we could model as reset device as well.
> But it has extra functionalities apart from reset.
>
> So what do you propose here? Model as a reset device or phy device since
> it is related to phy?
> Please share your opinion on this.
>
> Regards,
> Biju
>
> > >
> > > So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead.
> > Is it ok? Please let me know.
> >
> > A node with #phy-cells should use the standard phy node names unless
> > it has other controls.
>
> Apart from reset, it has other controls like clock control , connection
> control , clock status and powerdown setting registers.
>
> Cheers,
> Biju
>
> As I said, this doesn't seem to be a phy, so using
> > #phy-cells here is what seems wrong.
> >
> > > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > > + "renesas,rzg2l-usbphyctrl";
> > > > > + reg = <0x11c40000 0x10000>;
> > > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > > + power-domains = <&cpg>;
> >
> > Also, are these all resources of the usbphyctrl block and not just
> > resources you happen to want in the driver? For example, the
> > power-domain should be the power island that this block resides in.
> >
> > > > > + #phy-cells = <1>;
> > > > > + };
> > > > > --
> > > > > 2.17.1
> > > > >
> > > > >
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings
@ 2021-06-25 10:11 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-25 10:11 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
> Subject: RE: [PATCH v2 01/11] dt-bindings: phy: renesas: Document RZ/G2L
> USB PHY Control bindings
>
> Hi Rob,
>
> Thanks for the feedback.
>
> > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > RZ/G2L USB PHY Control bindings
> >
> > On Wed, Jun 23, 2021 at 7:38 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > > Thanks for the feedback.
> > >
> > > > Subject: Re: [PATCH v2 01/11] dt-bindings: phy: renesas: Document
> > > > RZ/G2L USB PHY Control bindings
> > > >
> > > > On Mon, Jun 21, 2021 at 10:39:33AM +0100, Biju Das wrote:
> > > > > Add device tree binding document for RZ/G2L USB PHY control
> driver.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > V1->V2:
> > > > > * Add clock properties
> > > > > ---
> > > > > .../phy/renesas,rzg2l-usbphyctrl.yaml | 65
> > +++++++++++++++++++
> > > > > 1 file changed, 65 insertions(+) create mode 100644
> > > > > Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl.y
> > > > > am
> > > > > l
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl
> > > > > .y
> > > > > aml
> > > > > b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphyctrl
> > > > > .y
> > > > > aml
> > > > > new file mode 100644
> > > > > index 000000000000..8e8ba43f595d
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/phy/renesas,rzg2l-usbphy
> > > > > +++ ct
> > > > > +++ rl.y
> > > > > +++ aml
> > > > > @@ -0,0 +1,65 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%
> > > > > +2F
> > > > > +devi
> > > > > +cetree.org%2Fschemas%2Fphy%2Frenesas%2Crzg2l-usbphyctrl.yaml%23
> > > > > +&a
> > > > > +mp;d
> > > > > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa72
> > > > > +2a
> > > > > +08d9
> > > > > +359f07ad%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599779
> > > > > +42
> > > > > +1910
> > > > > +039%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzI
> > > > > +iL
> > > > > +CJBT
> > > > > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Jcf6Om4DehifCe1KO1rm
> > > > > +t5
> > > > > +LxTB
> > > > > +6jtGoQLD1MoqWGM%2F0%3D&reserved=0
> > > > > +$schema:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%
> > > > > +2F
> > > > > +devi
> > > > > +cetree.org%2Fmeta-
> > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > +jz%40bp.renesas.com%7Cc6bbf5f6ce334eaa722a08d9359f07ad%7C53d825
> > > > > +71
> > > > > +da19
> > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637599779421910039%7CUnknown%7CT
> > > > > +WF
> > > > > +pbGZ
> > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVC
> > > > > +I6
> > > > > +Mn0%
> > > > > +3D%7C1000&sdata=LlqPRLf9%2BGrEdSapxCFhwxVKcXTVh9ECr%2FXPN0S
> > > > > +Iz
> > > > > +i4%3
> > > > > +D&reserved=0
> > > > > +
> > > > > +title: Renesas RZ/G2L USB2.0 PHY Control
> > > > > +
> > > > > +maintainers:
> > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > +
> > > > > +description:
> > > > > + The RZ/G2L USB2.0 PHY Control mainly controls reset and power
> > > > > +down of the
> > > > > + USB/PHY.
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - renesas,r9a07g044-usbphyctrl # RZ/G2{L,LC}
> > > > > + - const: renesas,rzg2l-usbphyctrl
> > > > > +
> > > > > + reg:
> > > > > + maxItems: 1
> > > > > +
> > > > > + clocks:
> > > > > + maxItems: 1
> > > > > +
> > > > > + resets:
> > > > > + maxItems: 1
> > > > > +
> > > > > + power-domains:
> > > > > + maxItems: 1
> > > > > +
> > > > > + '#phy-cells':
> > > > > + # see phy-bindings.txt in the same directory
> > > > > + const: 1
> > > > > + description: |
> > > > > + The phandle's argument in the PHY specifier is the phy
> > > > > + reset
> > > > control bit
> > > > > + of usb phy control.
> > > > > + 0 = Port 1 Phy reset
> > > > > + 1 = Port 2 Phy reset
> > > > > + enum: [ 0, 1 ]
> > > >
> > > > You already have the const, so this doesn't do anything.
> > >
> > > OK, will take out const.
> >
> > No, 'const' is correct. This is the value of '#phy-cells', not the
> > contents (we don't have a way to express schema for that).
>
> OK.
>
> >
> > > > > +required:
> > > > > + - compatible
> > > > > + - reg
> > > > > + - clocks
> > > > > + - '#phy-cells'
> > > > > +
> > > > > +additionalProperties: false
> > > > > +
> > > > > +examples:
> > > > > + - |
> > > > > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > +
> > > > > + usbphyctrl@11c40000 {
> > > >
> > > > usb-phy@...
> > >
> > > The IP is called USBPHY control. It mainly controls reset and power
> > > down
> > of the USB2.0/PHY.
> >
> > Sounds like it should be using the reset binding...
OK, Will model this as a reset binding. Since the IP mainly controls reset and power down
Of the USB2.0/PHY. So it is better to have reset binding.
Regards,
Biju
> This IP has reset, clock control , connection control , clock status and
> power down setting registers.
> Currenty we are using reset registers for turning ON USB/PHY block.
>
> Since it has extra registers I thought of modelling it as a phy device.
> But we could model as reset device as well.
> But it has extra functionalities apart from reset.
>
> So what do you propose here? Model as a reset device or phy device since
> it is related to phy?
> Please share your opinion on this.
>
> Regards,
> Biju
>
> > >
> > > So not sure usb-phy is right one here ? I prefer usb-phy-ctrl instead.
> > Is it ok? Please let me know.
> >
> > A node with #phy-cells should use the standard phy node names unless
> > it has other controls.
>
> Apart from reset, it has other controls like clock control , connection
> control , clock status and powerdown setting registers.
>
> Cheers,
> Biju
>
> As I said, this doesn't seem to be a phy, so using
> > #phy-cells here is what seems wrong.
> >
> > > > > + compatible = "renesas,r9a07g044-usbphyctrl",
> > > > > + "renesas,rzg2l-usbphyctrl";
> > > > > + reg = <0x11c40000 0x10000>;
> > > > > + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > > > > + resets = <&cpg R9A07G044_USB_PCLK>;
> > > > > + power-domains = <&cpg>;
> >
> > Also, are these all resources of the usbphyctrl block and not just
> > resources you happen to want in the driver? For example, the
> > power-domain should be the power island that this block resides in.
> >
> > > > > + #phy-cells = <1>;
> > > > > + };
> > > > > --
> > > > > 2.17.1
> > > > >
> > > > >
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 02/11] drivers: clk: renesas: r9a07g044-cpg: Add USB clocks
2021-06-21 9:39 ` Biju Das
(?)
(?)
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add clock entries for USB PHY control, USB2.0 host and device.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Reworked on clock/reset definitions
---
drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bdede1d28086..0a17cf7cb548 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -108,6 +108,18 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK,
CLK_P1_DIV2,
0x52c, BIT(1), BIT(1)),
+ DEF_MOD("usb_pclk", R9A07G044_USB_PCLK,
+ R9A07G044_CLK_P1,
+ 0x578, BIT(3), BIT(3)),
+ DEF_MOD("usb_function", R9A07G044_USB_U2P_EXR_CPUCLK,
+ R9A07G044_CLK_P1,
+ 0x578, BIT(2), BIT(2)),
+ DEF_MOD("usb_host1", R9A07G044_USB_U2H1_HCLK,
+ R9A07G044_CLK_P1,
+ 0x578, BIT(1), BIT(1)),
+ DEF_MOD("usb_host0", R9A07G044_USB_U2H0_HCLK,
+ R9A07G044_CLK_P1,
+ 0x578, BIT(0), BIT(0)),
DEF_MOD("i2c0", R9A07G044_I2C0_PCLK,
R9A07G044_CLK_P0,
0x580, BIT(0), BIT(0)),
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 03/11] phy: renesas: Add RZ/G2L usb phy control driver
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: Biju Das, linux-phy, Yoshihiro Shimoda, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Add support for RZ/G2L USB PHY Control driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Incorporated vinod's review comments.
---
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rzg2l-usbphyctrl.c | 157 +++++++++++++++++++++
3 files changed, 165 insertions(+)
create mode 100644 drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index 111bdcae775c..2184fba12255 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -32,3 +32,10 @@ config PHY_RCAR_GEN3_USB3
select GENERIC_PHY
help
Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
+
+config PHY_RZG2L_USBPHYCTRL
+ tristate "Renesas RZ/G2L USB PHY control driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for USB PHY Control found on RZ/G2L SoCs.
diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile
index b599ff8a4349..62acc6bde5cb 100644
--- a/drivers/phy/renesas/Makefile
+++ b/drivers/phy/renesas/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
+obj-$(CONFIG_PHY_RZG2L_USBPHYCTRL) += phy-rzg2l-usbphyctrl.o
diff --git a/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c b/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
new file mode 100644
index 000000000000..f0e5555b99fe
--- /dev/null
+++ b/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L USB PHY control driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#define RESET 0x000
+
+#define SEL_PLLRESET BIT(12)
+#define PLL_RESET BIT(8)
+
+#define PHY_RESET_PORT2 (BIT(1) | BIT(5))
+#define PHY_RESET_PORT1 (BIT(0) | BIT(4))
+
+#define NUM_PORTS 2
+
+struct rzg2l_usbphycontrol_drv;
+
+struct rzg2l_phyctrl {
+ struct phy *phy;
+ struct rzg2l_usbphycontrol_drv *drv;
+ u32 phy_reset_port_mask;
+};
+
+struct rzg2l_usbphycontrol_drv {
+ void __iomem *base;
+ struct rzg2l_phyctrl phyctrl[NUM_PORTS];
+};
+
+static int rzg2l_usbphyctrl_init(struct phy *p)
+{
+ struct rzg2l_phyctrl *r = phy_get_drvdata(p);
+ struct rzg2l_usbphycontrol_drv *drv = r->drv;
+ void __iomem *base = drv->base;
+ u32 val = readl(base + RESET);
+
+ val |= SEL_PLLRESET;
+ val &= ~(PLL_RESET | r->phy_reset_port_mask);
+ writel(val, base + RESET);
+
+ return 0;
+}
+
+static int rzg2l_usbphyctrl_exit(struct phy *p)
+{
+ struct rzg2l_phyctrl *r = phy_get_drvdata(p);
+ struct rzg2l_usbphycontrol_drv *drv = r->drv;
+ void __iomem *base = drv->base;
+ u32 val = readl(base + RESET);
+
+ val |= r->phy_reset_port_mask;
+ if ((val & 0xFF) == (PHY_RESET_PORT1 | PHY_RESET_PORT2))
+ val |= PLL_RESET;
+ writel(val, base + RESET);
+ return 0;
+}
+
+static const struct phy_ops rzg2l_usbphyctrl_ops = {
+ .init = rzg2l_usbphyctrl_init,
+ .exit = rzg2l_usbphyctrl_exit,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id rzg2l_usbphyctrl_match_table[] = {
+ { .compatible = "renesas,rzg2l-usbphyctrl" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_usbphyctrl_match_table);
+
+static struct phy *rzg2l_usbphycontrol_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rzg2l_usbphycontrol_drv *drv;
+ struct rzg2l_phyctrl *r;
+
+ drv = dev_get_drvdata(dev);
+ if (!drv)
+ return ERR_PTR(-EINVAL);
+
+ if (args->args[0] >= NUM_PORTS)
+ return ERR_PTR(-ENODEV);
+
+ r = &drv->phyctrl[args->args[0]];
+
+ return r->phy;
+}
+
+static int rzg2l_usbphycontrol_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rzg2l_usbphycontrol_drv *drv;
+ struct phy_provider *provider;
+ u32 val;
+ int n;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+
+ drv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(drv->base))
+ return PTR_ERR(drv->base);
+
+ for (n = 0; n < NUM_PORTS; n++) {
+ struct rzg2l_phyctrl *phy = &drv->phyctrl[n];
+
+ phy->phy = devm_phy_create(dev, NULL, &rzg2l_usbphyctrl_ops);
+ if (IS_ERR(phy->phy)) {
+ dev_err(dev, "Failed to create USBPHY Control\n");
+ return PTR_ERR(phy->phy);
+ }
+
+ if (n == 0)
+ phy->phy_reset_port_mask = PHY_RESET_PORT1;
+ else
+ phy->phy_reset_port_mask = PHY_RESET_PORT2;
+
+ phy->drv = drv;
+ phy_set_drvdata(phy->phy, phy);
+ };
+
+ provider = devm_of_phy_provider_register(dev, rzg2l_usbphycontrol_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "Failed to register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ dev_set_drvdata(dev, drv);
+
+ /* put pll and phy into reset state */
+ val = readl(drv->base + RESET);
+ val |= SEL_PLLRESET | PLL_RESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
+ writel(val, drv->base + RESET);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_usbphyctrl_driver = {
+ .driver = {
+ .name = "rzg2l_usbphyctrl",
+ .of_match_table = rzg2l_usbphyctrl_match_table,
+ },
+ .probe = rzg2l_usbphycontrol_probe,
+};
+module_platform_driver(rzg2l_usbphyctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Renesas RZ/G2L USBPHYControl");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 03/11] phy: renesas: Add RZ/G2L usb phy control driver
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: Biju Das, linux-phy, Yoshihiro Shimoda, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Add support for RZ/G2L USB PHY Control driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Incorporated vinod's review comments.
---
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rzg2l-usbphyctrl.c | 157 +++++++++++++++++++++
3 files changed, 165 insertions(+)
create mode 100644 drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index 111bdcae775c..2184fba12255 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -32,3 +32,10 @@ config PHY_RCAR_GEN3_USB3
select GENERIC_PHY
help
Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
+
+config PHY_RZG2L_USBPHYCTRL
+ tristate "Renesas RZ/G2L USB PHY control driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for USB PHY Control found on RZ/G2L SoCs.
diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile
index b599ff8a4349..62acc6bde5cb 100644
--- a/drivers/phy/renesas/Makefile
+++ b/drivers/phy/renesas/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
+obj-$(CONFIG_PHY_RZG2L_USBPHYCTRL) += phy-rzg2l-usbphyctrl.o
diff --git a/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c b/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
new file mode 100644
index 000000000000..f0e5555b99fe
--- /dev/null
+++ b/drivers/phy/renesas/phy-rzg2l-usbphyctrl.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L USB PHY control driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#define RESET 0x000
+
+#define SEL_PLLRESET BIT(12)
+#define PLL_RESET BIT(8)
+
+#define PHY_RESET_PORT2 (BIT(1) | BIT(5))
+#define PHY_RESET_PORT1 (BIT(0) | BIT(4))
+
+#define NUM_PORTS 2
+
+struct rzg2l_usbphycontrol_drv;
+
+struct rzg2l_phyctrl {
+ struct phy *phy;
+ struct rzg2l_usbphycontrol_drv *drv;
+ u32 phy_reset_port_mask;
+};
+
+struct rzg2l_usbphycontrol_drv {
+ void __iomem *base;
+ struct rzg2l_phyctrl phyctrl[NUM_PORTS];
+};
+
+static int rzg2l_usbphyctrl_init(struct phy *p)
+{
+ struct rzg2l_phyctrl *r = phy_get_drvdata(p);
+ struct rzg2l_usbphycontrol_drv *drv = r->drv;
+ void __iomem *base = drv->base;
+ u32 val = readl(base + RESET);
+
+ val |= SEL_PLLRESET;
+ val &= ~(PLL_RESET | r->phy_reset_port_mask);
+ writel(val, base + RESET);
+
+ return 0;
+}
+
+static int rzg2l_usbphyctrl_exit(struct phy *p)
+{
+ struct rzg2l_phyctrl *r = phy_get_drvdata(p);
+ struct rzg2l_usbphycontrol_drv *drv = r->drv;
+ void __iomem *base = drv->base;
+ u32 val = readl(base + RESET);
+
+ val |= r->phy_reset_port_mask;
+ if ((val & 0xFF) == (PHY_RESET_PORT1 | PHY_RESET_PORT2))
+ val |= PLL_RESET;
+ writel(val, base + RESET);
+ return 0;
+}
+
+static const struct phy_ops rzg2l_usbphyctrl_ops = {
+ .init = rzg2l_usbphyctrl_init,
+ .exit = rzg2l_usbphyctrl_exit,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id rzg2l_usbphyctrl_match_table[] = {
+ { .compatible = "renesas,rzg2l-usbphyctrl" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_usbphyctrl_match_table);
+
+static struct phy *rzg2l_usbphycontrol_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct rzg2l_usbphycontrol_drv *drv;
+ struct rzg2l_phyctrl *r;
+
+ drv = dev_get_drvdata(dev);
+ if (!drv)
+ return ERR_PTR(-EINVAL);
+
+ if (args->args[0] >= NUM_PORTS)
+ return ERR_PTR(-ENODEV);
+
+ r = &drv->phyctrl[args->args[0]];
+
+ return r->phy;
+}
+
+static int rzg2l_usbphycontrol_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rzg2l_usbphycontrol_drv *drv;
+ struct phy_provider *provider;
+ u32 val;
+ int n;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+
+ drv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(drv->base))
+ return PTR_ERR(drv->base);
+
+ for (n = 0; n < NUM_PORTS; n++) {
+ struct rzg2l_phyctrl *phy = &drv->phyctrl[n];
+
+ phy->phy = devm_phy_create(dev, NULL, &rzg2l_usbphyctrl_ops);
+ if (IS_ERR(phy->phy)) {
+ dev_err(dev, "Failed to create USBPHY Control\n");
+ return PTR_ERR(phy->phy);
+ }
+
+ if (n == 0)
+ phy->phy_reset_port_mask = PHY_RESET_PORT1;
+ else
+ phy->phy_reset_port_mask = PHY_RESET_PORT2;
+
+ phy->drv = drv;
+ phy_set_drvdata(phy->phy, phy);
+ };
+
+ provider = devm_of_phy_provider_register(dev, rzg2l_usbphycontrol_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "Failed to register PHY provider\n");
+ return PTR_ERR(provider);
+ }
+
+ dev_set_drvdata(dev, drv);
+
+ /* put pll and phy into reset state */
+ val = readl(drv->base + RESET);
+ val |= SEL_PLLRESET | PLL_RESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
+ writel(val, drv->base + RESET);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_usbphyctrl_driver = {
+ .driver = {
+ .name = "rzg2l_usbphyctrl",
+ .of_match_table = rzg2l_usbphyctrl_match_table,
+ },
+ .probe = rzg2l_usbphycontrol_probe,
+};
+module_platform_driver(rzg2l_usbphyctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Renesas RZ/G2L USBPHYControl");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 04/11] arm64: configs: defconfig: Enable RZ/G2L USB PHY control driver
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Biju Das, Bjorn Andersson, Shawn Guo, Krzysztof Kozlowski,
Geert Uytterhoeven, Guido Günther, Michael Walle,
Dmitry Baryshkov, Enric Balletbo i Serra, Nishanth Menon,
Douglas Anderson, Andrey Zhizhikin, Anson Huang,
linux-arm-kernel, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
RZ/G2L SMARC EVK supports USB PHY control,so enable it in ARM64 defconfig.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5344976e3b27..d96faf4e84f8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1108,6 +1108,7 @@ CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_RZG2L_USBPHYCTRL=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 04/11] arm64: configs: defconfig: Enable RZ/G2L USB PHY control driver
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Biju Das, Bjorn Andersson, Shawn Guo, Krzysztof Kozlowski,
Geert Uytterhoeven, Guido Günther, Michael Walle,
Dmitry Baryshkov, Enric Balletbo i Serra, Nishanth Menon,
Douglas Anderson, Andrey Zhizhikin, Anson Huang,
linux-arm-kernel, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
RZ/G2L SMARC EVK supports USB PHY control,so enable it in ARM64 defconfig.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5344976e3b27..d96faf4e84f8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1108,6 +1108,7 @@ CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_RZG2L_USBPHYCTRL=y
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 05/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Document USB phy bindings for RZ/G2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/phy/renesas,usb2-phy.yaml | 23 ++++++++++---------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 0f358d5b84ef..eebba6c83aec 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -17,17 +17,18 @@ properties:
- items:
- enum:
- - renesas,usb2-phy-r7s9210 # RZ/A2
- - renesas,usb2-phy-r8a774a1 # RZ/G2M
- - renesas,usb2-phy-r8a774b1 # RZ/G2N
- - renesas,usb2-phy-r8a774c0 # RZ/G2E
- - renesas,usb2-phy-r8a774e1 # RZ/G2H
- - renesas,usb2-phy-r8a7795 # R-Car H3
- - renesas,usb2-phy-r8a7796 # R-Car M3-W
- - renesas,usb2-phy-r8a77961 # R-Car M3-W+
- - renesas,usb2-phy-r8a77965 # R-Car M3-N
- - renesas,usb2-phy-r8a77990 # R-Car E3
- - renesas,usb2-phy-r8a77995 # R-Car D3
+ - renesas,usb2-phy-r7s9210 # RZ/A2
+ - renesas,usb2-phy-r8a774a1 # RZ/G2M
+ - renesas,usb2-phy-r8a774b1 # RZ/G2N
+ - renesas,usb2-phy-r8a774c0 # RZ/G2E
+ - renesas,usb2-phy-r8a774e1 # RZ/G2H
+ - renesas,usb2-phy-r8a7795 # R-Car H3
+ - renesas,usb2-phy-r8a7796 # R-Car M3-W
+ - renesas,usb2-phy-r8a77961 # R-Car M3-W+
+ - renesas,usb2-phy-r8a77965 # R-Car M3-N
+ - renesas,usb2-phy-r8a77990 # R-Car E3
+ - renesas,usb2-phy-r8a77995 # R-Car D3
+ - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rcar-gen3-usb2-phy
reg:
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 05/11] dt-bindings: phy: renesas, usb2-phy: Document RZ/G2L phy bindings
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Document USB phy bindings for RZ/G2L SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/phy/renesas,usb2-phy.yaml | 23 ++++++++++---------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 0f358d5b84ef..eebba6c83aec 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -17,17 +17,18 @@ properties:
- items:
- enum:
- - renesas,usb2-phy-r7s9210 # RZ/A2
- - renesas,usb2-phy-r8a774a1 # RZ/G2M
- - renesas,usb2-phy-r8a774b1 # RZ/G2N
- - renesas,usb2-phy-r8a774c0 # RZ/G2E
- - renesas,usb2-phy-r8a774e1 # RZ/G2H
- - renesas,usb2-phy-r8a7795 # R-Car H3
- - renesas,usb2-phy-r8a7796 # R-Car M3-W
- - renesas,usb2-phy-r8a77961 # R-Car M3-W+
- - renesas,usb2-phy-r8a77965 # R-Car M3-N
- - renesas,usb2-phy-r8a77990 # R-Car E3
- - renesas,usb2-phy-r8a77995 # R-Car D3
+ - renesas,usb2-phy-r7s9210 # RZ/A2
+ - renesas,usb2-phy-r8a774a1 # RZ/G2M
+ - renesas,usb2-phy-r8a774b1 # RZ/G2N
+ - renesas,usb2-phy-r8a774c0 # RZ/G2E
+ - renesas,usb2-phy-r8a774e1 # RZ/G2H
+ - renesas,usb2-phy-r8a7795 # R-Car H3
+ - renesas,usb2-phy-r8a7796 # R-Car M3-W
+ - renesas,usb2-phy-r8a77961 # R-Car M3-W+
+ - renesas,usb2-phy-r8a77965 # R-Car M3-N
+ - renesas,usb2-phy-r8a77990 # R-Car E3
+ - renesas,usb2-phy-r8a77995 # R-Car D3
+ - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rcar-gen3-usb2-phy
reg:
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v2 05/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-06-21 9:39 ` [PATCH v2 05/11] dt-bindings: phy: renesas, usb2-phy: " Biju Das
@ 2021-06-22 15:33 ` Geert Uytterhoeven
-1 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-22 15:33 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Kishon Vijay Abraham I, Vinod Koul,
Yoshihiro Shimoda, linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/phy/renesas,usb2-phy.yaml | 23 ++++++++++---------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index 0f358d5b84ef..eebba6c83aec 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -17,17 +17,18 @@ properties:
>
> - items:
> - enum:
> - - renesas,usb2-phy-r7s9210 # RZ/A2
> - - renesas,usb2-phy-r8a774a1 # RZ/G2M
> - - renesas,usb2-phy-r8a774b1 # RZ/G2N
> - - renesas,usb2-phy-r8a774c0 # RZ/G2E
> - - renesas,usb2-phy-r8a774e1 # RZ/G2H
> - - renesas,usb2-phy-r8a7795 # R-Car H3
> - - renesas,usb2-phy-r8a7796 # R-Car M3-W
> - - renesas,usb2-phy-r8a77961 # R-Car M3-W+
> - - renesas,usb2-phy-r8a77965 # R-Car M3-N
> - - renesas,usb2-phy-r8a77990 # R-Car E3
> - - renesas,usb2-phy-r8a77995 # R-Car D3
> + - renesas,usb2-phy-r7s9210 # RZ/A2
> + - renesas,usb2-phy-r8a774a1 # RZ/G2M
> + - renesas,usb2-phy-r8a774b1 # RZ/G2N
> + - renesas,usb2-phy-r8a774c0 # RZ/G2E
> + - renesas,usb2-phy-r8a774e1 # RZ/G2H
> + - renesas,usb2-phy-r8a7795 # R-Car H3
> + - renesas,usb2-phy-r8a7796 # R-Car M3-W
> + - renesas,usb2-phy-r8a77961 # R-Car M3-W+
> + - renesas,usb2-phy-r8a77965 # R-Car M3-N
> + - renesas,usb2-phy-r8a77990 # R-Car E3
> + - renesas,usb2-phy-r8a77995 # R-Car D3
> + - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> - const: renesas,rcar-gen3-usb2-phy
>
> reg:
As some of the register bits are different, cfr. my comments to
[PATCH v2 10/11], I think you want to add a new oneOf instead:
- items:
- enum:
- renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rzg2l-usb2-phy
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 05/11] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
@ 2021-06-22 15:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-22 15:33 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Kishon Vijay Abraham I, Vinod Koul,
Yoshihiro Shimoda, linux-phy,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/phy/renesas,usb2-phy.yaml | 23 ++++++++++---------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index 0f358d5b84ef..eebba6c83aec 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -17,17 +17,18 @@ properties:
>
> - items:
> - enum:
> - - renesas,usb2-phy-r7s9210 # RZ/A2
> - - renesas,usb2-phy-r8a774a1 # RZ/G2M
> - - renesas,usb2-phy-r8a774b1 # RZ/G2N
> - - renesas,usb2-phy-r8a774c0 # RZ/G2E
> - - renesas,usb2-phy-r8a774e1 # RZ/G2H
> - - renesas,usb2-phy-r8a7795 # R-Car H3
> - - renesas,usb2-phy-r8a7796 # R-Car M3-W
> - - renesas,usb2-phy-r8a77961 # R-Car M3-W+
> - - renesas,usb2-phy-r8a77965 # R-Car M3-N
> - - renesas,usb2-phy-r8a77990 # R-Car E3
> - - renesas,usb2-phy-r8a77995 # R-Car D3
> + - renesas,usb2-phy-r7s9210 # RZ/A2
> + - renesas,usb2-phy-r8a774a1 # RZ/G2M
> + - renesas,usb2-phy-r8a774b1 # RZ/G2N
> + - renesas,usb2-phy-r8a774c0 # RZ/G2E
> + - renesas,usb2-phy-r8a774e1 # RZ/G2H
> + - renesas,usb2-phy-r8a7795 # R-Car H3
> + - renesas,usb2-phy-r8a7796 # R-Car M3-W
> + - renesas,usb2-phy-r8a77961 # R-Car M3-W+
> + - renesas,usb2-phy-r8a77965 # R-Car M3-N
> + - renesas,usb2-phy-r8a77990 # R-Car E3
> + - renesas,usb2-phy-r8a77995 # R-Car D3
> + - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> - const: renesas,rcar-gen3-usb2-phy
>
> reg:
As some of the register bits are different, cfr. my comments to
[PATCH v2 10/11], I think you want to add a new oneOf instead:
- items:
- enum:
- renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rzg2l-usb2-phy
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
2021-06-21 9:39 ` Biju Das
` (5 preceding siblings ...)
(?)
@ 2021-06-21 9:39 ` Biju Das
2021-06-21 17:40 ` Rob Herring
2021-06-22 19:30 ` Rob Herring
-1 siblings, 2 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need to
turn on both these phy modules before accessing host registers.
Apart from this, document the optional property dr_mode present on both
RZ/G2 and R-Car Gen3 SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/usb/generic-ohci.yaml | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 0f5f6ea702d0..c0644fae5db9 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -8,6 +8,26 @@ title: USB OHCI Controller Device Tree Bindings
allOf:
- $ref: "usb-hcd.yaml"
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-ohci
+ then:
+ properties:
+ phys:
+ maxItems: 2
+ phy-names:
+ items:
+ - const: usbphyctrl
+ - const: usb
+ else:
+ properties:
+ phys:
+ maxItems: 1
+ phy-names:
+ items:
+ - const: usb
maintainers:
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
@@ -43,6 +63,7 @@ properties:
- brcm,bcm7435-ohci
- ibm,476gtr-ohci
- ingenic,jz4740-ohci
+ - renesas,r9a07g044-ohci
- snps,hsdk-v1.0-ohci
- const: generic-ohci
- const: generic-ohci
@@ -101,14 +122,21 @@ properties:
Overrides the detected port count
phys:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
phy-names:
- const: usb
+ minItems: 1
+ maxItems: 2
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
2021-06-21 9:39 ` [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings Biju Das
@ 2021-06-21 17:40 ` Rob Herring
2021-06-22 10:03 ` Biju Das
2021-06-22 19:30 ` Rob Herring
1 sibling, 1 reply; 50+ messages in thread
From: Rob Herring @ 2021-06-21 17:40 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Yoshihiro Shimoda, Chris Paterson, linux-usb,
Greg Kroah-Hartman, Geert Uytterhoeven, Biju Das,
linux-renesas-soc, Prabhakar Mahadev Lad, devicetree
On Mon, 21 Jun 2021 10:39:38 +0100, Biju Das wrote:
> Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need to
> turn on both these phy modules before accessing host registers.
>
> Apart from this, document the optional property dr_mode present on both
> RZ/G2 and R-Car Gen3 SoCs.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../devicetree/bindings/usb/generic-ohci.yaml | 32 +++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/usb/generic-ohci.yaml:14:13: [warning] wrong indentation: expected 10 but found 12 (indentation)
dtschema/dtc warnings/errors:
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494981
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
2021-06-21 17:40 ` Rob Herring
@ 2021-06-22 10:03 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-22 10:03 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Herring, Yoshihiro Shimoda, Chris Paterson, linux-usb,
Greg Kroah-Hartman, Geert Uytterhoeven, Biju Das,
linux-renesas-soc, Prabhakar Mahadev Lad, devicetree
Hi Rob,
I can reproduce the issue now, after installing 'yamllint' and using "DT_CHECKER_FLAGS=-m dt_binding_check".
I will fix this and send v3.
Regards,
Biju
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 21 June 2021 18:40
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; linux-usb@vger.kernel.org; Greg Kroah-
> Hartman <gregkh@linuxfoundation.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Biju Das <biju.das@bp.renesas.com>; linux-
> renesas-soc@vger.kernel.org; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; devicetree@vger.kernel.org
> Subject: Re: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document
> RZ/G2L SoC bindings
>
> On Mon, 21 Jun 2021 10:39:38 +0100, Biju Das wrote:
> > Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need
> > to turn on both these phy modules before accessing host registers.
> >
> > Apart from this, document the optional property dr_mode present on
> > both
> > RZ/G2 and R-Car Gen3 SoCs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/usb/generic-ohci.yaml | 32
> > +++++++++++++++++--
> > 1 file changed, 30 insertions(+), 2 deletions(-)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/usb/generic-ohci.yaml:14:13: [warning]
> wrong indentation: expected 10 but found 12 (indentation)
>
> dtschema/dtc warnings/errors:
> \ndoc reference errors (make refcheckdocs):
>
> See
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fpatch%2F1494981&data=04%7C01%7Cbiju.das.jz%40bp.renesas
> .com%7C948f485a377b4f12c7ea08d934dba3ba%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C637598940229461664%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=4rFbOwmthR
> BAmn7MNMAHqQD8hm2lgLSKhUNg9i95A5M%3D&reserved=0
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
2021-06-21 9:39 ` [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings Biju Das
2021-06-21 17:40 ` Rob Herring
@ 2021-06-22 19:30 ` Rob Herring
2021-06-23 14:20 ` Biju Das
1 sibling, 1 reply; 50+ messages in thread
From: Rob Herring @ 2021-06-22 19:30 UTC (permalink / raw)
To: Biju Das
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, Jun 21, 2021 at 10:39:38AM +0100, Biju Das wrote:
> Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need to
> turn on both these phy modules before accessing host registers.
>
> Apart from this, document the optional property dr_mode present on both
> RZ/G2 and R-Car Gen3 SoCs.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../devicetree/bindings/usb/generic-ohci.yaml | 32 +++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> index 0f5f6ea702d0..c0644fae5db9 100644
> --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> @@ -8,6 +8,26 @@ title: USB OHCI Controller Device Tree Bindings
>
> allOf:
> - $ref: "usb-hcd.yaml"
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a07g044-ohci
> + then:
> + properties:
> + phys:
> + maxItems: 2
> + phy-names:
> + items:
> + - const: usbphyctrl
> + - const: usb
Why can't your extra thing be last? Then you only need to set
minItems/maxItems in the if/then schema.
Though this seems like an abuse of the phy binding. There's not 2 phys,
right? Just some extra registers related to the phy? Can't it be hidden
in your phy driver?
> + else:
> + properties:
> + phys:
> + maxItems: 1
> + phy-names:
> + items:
> + - const: usb
>
> maintainers:
> - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> @@ -43,6 +63,7 @@ properties:
> - brcm,bcm7435-ohci
> - ibm,476gtr-ohci
> - ingenic,jz4740-ohci
> + - renesas,r9a07g044-ohci
> - snps,hsdk-v1.0-ohci
> - const: generic-ohci
> - const: generic-ohci
> @@ -101,14 +122,21 @@ properties:
> Overrides the detected port count
>
> phys:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> phy-names:
> - const: usb
> + minItems: 1
> + maxItems: 2
>
> iommus:
> maxItems: 1
>
> + dr_mode:
> + enum:
> + - host
> + - otg
> +
> required:
> - compatible
> - reg
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document RZ/G2L SoC bindings
2021-06-22 19:30 ` Rob Herring
@ 2021-06-23 14:20 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 14:20 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v2 06/11] dt-bindings: usb: generic-ohci: Document
> RZ/G2L SoC bindings
>
> On Mon, Jun 21, 2021 at 10:39:38AM +0100, Biju Das wrote:
> > Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need
> > to turn on both these phy modules before accessing host registers.
> >
> > Apart from this, document the optional property dr_mode present on
> > both
> > RZ/G2 and R-Car Gen3 SoCs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/usb/generic-ohci.yaml | 32
> > +++++++++++++++++--
> > 1 file changed, 30 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> > b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> > index 0f5f6ea702d0..c0644fae5db9 100644
> > --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> > +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
> > @@ -8,6 +8,26 @@ title: USB OHCI Controller Device Tree Bindings
> >
> > allOf:
> > - $ref: "usb-hcd.yaml"
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a07g044-ohci
> > + then:
> > + properties:
> > + phys:
> > + maxItems: 2
> > + phy-names:
> > + items:
> > + - const: usbphyctrl
> > + - const: usb
>
> Why can't your extra thing be last? Then you only need to set
> minItems/maxItems in the if/then schema.
OK. will move this to the last and will take out phy-names.
>
> Though this seems like an abuse of the phy binding. There's not 2 phys,
> right? Just some extra registers related to the phy? Can't it be hidden in
> your phy driver?
Usbphyctrl is separate IP block which mainly controls reset and power down of the actual USB/PHY.
This block has separate registers. So modelled as separate driver and device handles port reset
Based on port index.
Will remove phy-names "usbphyctrl" and will just use "usb" like example here[1]. Is it ok?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/usb/usb-hcd.yaml?h=v5.13-rc7
Regards,
Biju
>
> > + else:
> > + properties:
> > + phys:
> > + maxItems: 1
> > + phy-names:
> > + items:
> > + - const: usb
> >
> > maintainers:
> > - Greg Kroah-Hartman <gregkh@linuxfoundation.org> @@ -43,6 +63,7 @@
> > properties:
> > - brcm,bcm7435-ohci
> > - ibm,476gtr-ohci
> > - ingenic,jz4740-ohci
> > + - renesas,r9a07g044-ohci
> > - snps,hsdk-v1.0-ohci
> > - const: generic-ohci
> > - const: generic-ohci
> > @@ -101,14 +122,21 @@ properties:
> > Overrides the detected port count
> >
> > phys:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
> >
> > phy-names:
> > - const: usb
> > + minItems: 1
> > + maxItems: 2
> >
> > iommus:
> > maxItems: 1
> >
> > + dr_mode:
> > + enum:
> > + - host
> > + - otg
> > +
> > required:
> > - compatible
> > - reg
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 07/11] dt-bindings: usb: generic-ehci: Document RZ/G2L SoC bindings
2021-06-21 9:39 ` Biju Das
` (6 preceding siblings ...)
(?)
@ 2021-06-21 9:39 ` Biju Das
2021-06-21 17:40 ` Rob Herring
-1 siblings, 1 reply; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need to
turn on both these phy modules before accessing host registers.
Apart from this, document the optional property dr_mode present on both
RZ/G2 and R-Car Gen3 SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/usb/generic-ehci.yaml | 33 +++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 8089dc956ba3..822e667e28a5 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -22,6 +22,27 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a07g044-ehci
+ then:
+ properties:
+ phys:
+ maxItems: 2
+ phy-names:
+ items:
+ - const: usbphyctrl
+ - const: usb
+ else:
+ properties:
+ phys:
+ maxItems: 1
+ phy-names:
+ items:
+ - const: usb
+
properties:
compatible:
oneOf:
@@ -57,6 +78,7 @@ properties:
- ibm,476gtr-ehci
- nxp,lpc1850-ehci
- qca,ar7100-ehci
+ - renesas,r9a07g044-ehci
- snps,hsdk-v1.0-ehci
- socionext,uniphier-ehci
- const: generic-ehci
@@ -134,14 +156,21 @@ properties:
Phandle of a companion.
phys:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
phy-names:
- const: usb
+ minItems: 1
+ maxItems: 2
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v2 07/11] dt-bindings: usb: generic-ehci: Document RZ/G2L SoC bindings
2021-06-21 9:39 ` [PATCH v2 07/11] dt-bindings: usb: generic-ehci: " Biju Das
@ 2021-06-21 17:40 ` Rob Herring
2021-06-22 10:04 ` Biju Das
0 siblings, 1 reply; 50+ messages in thread
From: Rob Herring @ 2021-06-21 17:40 UTC (permalink / raw)
To: Biju Das
Cc: Prabhakar Mahadev Lad, Yoshihiro Shimoda, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Rob Herring, Greg Kroah-Hartman,
linux-usb, Chris Paterson, Biju Das
On Mon, 21 Jun 2021 10:39:39 +0100, Biju Das wrote:
> Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need to
> turn on both these phy modules before accessing host registers.
>
> Apart from this, document the optional property dr_mode present on both
> RZ/G2 and R-Car Gen3 SoCs.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../devicetree/bindings/usb/generic-ehci.yaml | 33 +++++++++++++++++--
> 1 file changed, 31 insertions(+), 2 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/usb/generic-ehci.yaml:28:13: [warning] wrong indentation: expected 10 but found 12 (indentation)
dtschema/dtc warnings/errors:
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1494982
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 07/11] dt-bindings: usb: generic-ehci: Document RZ/G2L SoC bindings
2021-06-21 17:40 ` Rob Herring
@ 2021-06-22 10:04 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-22 10:04 UTC (permalink / raw)
To: Rob Herring
Cc: Prabhakar Mahadev Lad, Yoshihiro Shimoda, linux-renesas-soc,
devicetree, Geert Uytterhoeven, Rob Herring, Greg Kroah-Hartman,
linux-usb, Chris Paterson, Biju Das
Hi Rob,
I can reproduce the issue now, after installing 'yamllint' and using "DT_CHECKER_FLAGS=-m dt_binding_check".
I will fix this and send v3.
Regards,
Biju
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 21 June 2021 18:40
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>; linux-renesas-
> soc@vger.kernel.org; devicetree@vger.kernel.org; Geert Uytterhoeven
> <geert+renesas@glider.be>; Rob Herring <robh+dt@kernel.org>; Greg Kroah-
> Hartman <gregkh@linuxfoundation.org>; linux-usb@vger.kernel.org; Chris
> Paterson <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>
> Subject: Re: [PATCH v2 07/11] dt-bindings: usb: generic-ehci: Document
> RZ/G2L SoC bindings
>
> On Mon, 21 Jun 2021 10:39:39 +0100, Biju Das wrote:
> > Renesas RZ/G2L SoC has USBPHY Control and USB2.0 PHY module. We need
> > to turn on both these phy modules before accessing host registers.
> >
> > Apart from this, document the optional property dr_mode present on
> > both
> > RZ/G2 and R-Car Gen3 SoCs.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../devicetree/bindings/usb/generic-ehci.yaml | 33
> > +++++++++++++++++--
> > 1 file changed, 31 insertions(+), 2 deletions(-)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/usb/generic-ehci.yaml:28:13: [warning]
> wrong indentation: expected 10 but found 12 (indentation)
>
> dtschema/dtc warnings/errors:
> \ndoc reference errors (make refcheckdocs):
>
> See
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fpatch%2F1494982&data=04%7C01%7Cbiju.das.jz%40bp.renesas
> .com%7Ca5c6e52f8fdc4596558e08d934dba5e6%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C637598940251415158%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=A1oNbFJtcy
> uOHvpE5IDBptxNhyoc5zlCVbPGpgnldIU%3D&reserved=0
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
2021-06-21 9:39 ` Biju Das
` (7 preceding siblings ...)
(?)
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 phy and host support to SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 397e3b182c02..ae71404c6238 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -236,6 +236,106 @@
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ usbphyctrl: usbphyctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphyctrl",
+ "renesas,rzg2l-usbphyctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>;
+ power-domains = <&cpg>;
+ #phy-cells = <1>;
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "renesas,r9a07g044-ohci",
+ "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H0_HCLK>;
+ phys = <&usbphyctrl 0>, <&usb2_phy0 1>;
+ phy-names = "usbphyctrl", "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "renesas,r9a07g044-ohci",
+ "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H1_HCLK>;
+ phys = <&usbphyctrl 1>, <&usb2_phy1 1>;
+ phy-names = "usbphyctrl", "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "renesas,r9a07g044-ehci",
+ "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H0_HCLK>;
+ phys = <&usbphyctrl 0>, <&usb2_phy0 2>;
+ phy-names = "usbphyctrl", "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "renesas,r9a07g044-ehci",
+ "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H1_HCLK>;
+ phys = <&usbphyctrl 1>, <&usb2_phy1 2>;
+ phy-names = "usbphyctrl", "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H0_HCLK>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2H1_HCLK>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 09/11] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-06-21 9:39 ` Biju Das
` (8 preceding siblings ...)
(?)
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document RZ/G2L (R9A07G044L) SoC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/usb/renesas,usbhs.yaml | 44 ++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index e67223d90bb7..d1f4bbf774c6 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -17,7 +17,9 @@ properties:
- const: renesas,rza1-usbhs
- items:
- - const: renesas,usbhs-r7s9210 # RZ/A2
+ - enum:
+ - renesas,usbhs-r7s9210 # RZ/A2
+ - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rza2-usbhs
- items:
@@ -60,7 +62,8 @@ properties:
- description: USB 2.0 clock selector
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
renesas,buswait:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -74,11 +77,12 @@ properties:
enabled.
phys:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
phy-names:
- items:
- - const: usb
+ minItems: 1
+ maxItems: 2
dmas:
minItems: 2
@@ -111,6 +115,36 @@ required:
- clocks
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usbhs-r9a07g044
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: U2P_IXL_INT
+ - description: U2P_INT_DMA[0]
+ - description: U2P_INT_DMA[1]
+ - description: U2P_INT_DMAERR
+ phys:
+ maxItems: 2
+ phy-names:
+ items:
+ - const: usbphyctrl
+ - const: usb
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ phys:
+ maxItems: 1
+ phy-names:
+ items:
+ - const: usb
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-21 9:39 ` Biju Das
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc,
linux-phy, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
This patch adds OTG support for RZ/G2L SoC.
RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
line ctrl register for OTG_ID pin changes. Apart from this
it uses a different OTG-BC interrupt bit for device recognition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63 ++++++++++++++++++------
1 file changed, 48 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index fbc55232120e..aff0749be65d 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -22,6 +22,7 @@
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/string.h>
+#include <linux/sys_soc.h>
#include <linux/usb/of.h>
#include <linux/workqueue.h>
@@ -64,6 +65,7 @@
/* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+#define USB2_VBCTRL_VBOUT BIT(0)
/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN BIT(19)
@@ -78,6 +80,10 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
+/* RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON BIT(0)
+
#define NUM_OF_PHYS 4
enum rcar_gen3_phy_index {
PHY_INDEX_BOTH_HC,
@@ -112,9 +118,11 @@ struct rcar_gen3_chan {
struct mutex lock; /* protects rphys[...].powered */
enum usb_dr_mode dr_mode;
int irq;
+ u32 obint_enable_bits;
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool soc_no_adp_ctrl;
};
/*
@@ -172,14 +180,22 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
void __iomem *usb2_base = ch->base;
- u32 val = readl(usb2_base + USB2_ADPCTRL);
+ u32 vbus_ctrl_reg = USB2_ADPCTRL;
+ u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
+ u32 val;
dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
+ if (ch->soc_no_adp_ctrl) {
+ vbus_ctrl_reg = USB2_VBCTRL;
+ vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+ }
+
+ val = readl(usb2_base + vbus_ctrl_reg);
if (vbus)
- val |= USB2_ADPCTRL_DRVVBUS;
+ val |= vbus_ctrl_val;
else
- val &= ~USB2_ADPCTRL_DRVVBUS;
- writel(val, usb2_base + USB2_ADPCTRL);
+ val &= ~vbus_ctrl_val;
+ writel(val, usb2_base + vbus_ctrl_reg);
}
static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
@@ -188,9 +204,9 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
u32 val = readl(usb2_base + USB2_OBINTEN);
if (ch->uses_otg_pins && enable)
- val |= USB2_OBINT_BITS;
+ val |= ch->obint_enable_bits;
else
- val &= ~USB2_OBINT_BITS;
+ val &= ~ch->obint_enable_bits;
writel(val, usb2_base + USB2_OBINTEN);
}
@@ -252,6 +268,9 @@ static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
if (!ch->uses_otg_pins)
return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
+ if (ch->soc_no_adp_ctrl)
+ return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
+
return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}
@@ -376,16 +395,17 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
writel(val, usb2_base + USB2_LINECTRL1);
- val = readl(usb2_base + USB2_VBCTRL);
- val &= ~USB2_VBCTRL_OCCLREN;
- writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
- val = readl(usb2_base + USB2_ADPCTRL);
- writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
-
+ if (!ch->soc_no_adp_ctrl) {
+ val = readl(usb2_base + USB2_VBCTRL);
+ val &= ~USB2_VBCTRL_OCCLREN;
+ writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
+ val = readl(usb2_base + USB2_ADPCTRL);
+ writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
+ }
msleep(20);
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
rcar_gen3_device_recognition(ch);
}
@@ -397,9 +417,9 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
u32 status = readl(usb2_base + USB2_OBINTSTA);
irqreturn_t ret = IRQ_NONE;
- if (status & USB2_OBINT_BITS) {
+ if (status & ch->obint_enable_bits) {
dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
rcar_gen3_device_recognition(ch);
ret = IRQ_HANDLED;
}
@@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
.owner = THIS_MODULE,
};
+static const struct soc_device_attribute soc_no_adp_ctrl[] = {
+ { .soc_id = "r9a07g044", .data = (void *)true },
+ { /* Sentinel */ }
+};
+
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
{
.compatible = "renesas,usb2-phy-r8a77470",
@@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
struct phy_provider *provider;
const struct phy_ops *phy_usb2_ops;
int ret = 0, i;
+ const struct soc_device_attribute *attr;
if (!dev->of_node) {
dev_err(dev, "This driver needs device tree\n");
@@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (IS_ERR(channel->base))
return PTR_ERR(channel->base);
+ channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
/* get irq number here and request_irq for OTG in phy_init */
channel->irq = platform_get_irq_optional(pdev, 0);
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
@@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
int ret;
channel->is_otg_channel = true;
+ attr = soc_device_match(soc_no_adp_ctrl);
+ if (attr) {
+ channel->soc_no_adp_ctrl = attr->data;
+ channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+ }
+
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
"renesas,no-otg-pins");
channel->extcon = devm_extcon_dev_allocate(dev,
--
2.17.1
^ permalink raw reply related [flat|nested] 50+ messages in thread* [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-21 9:39 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc,
linux-phy, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
This patch adds OTG support for RZ/G2L SoC.
RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
line ctrl register for OTG_ID pin changes. Apart from this
it uses a different OTG-BC interrupt bit for device recognition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63 ++++++++++++++++++------
1 file changed, 48 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index fbc55232120e..aff0749be65d 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -22,6 +22,7 @@
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/string.h>
+#include <linux/sys_soc.h>
#include <linux/usb/of.h>
#include <linux/workqueue.h>
@@ -64,6 +65,7 @@
/* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+#define USB2_VBCTRL_VBOUT BIT(0)
/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN BIT(19)
@@ -78,6 +80,10 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
+/* RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON BIT(0)
+
#define NUM_OF_PHYS 4
enum rcar_gen3_phy_index {
PHY_INDEX_BOTH_HC,
@@ -112,9 +118,11 @@ struct rcar_gen3_chan {
struct mutex lock; /* protects rphys[...].powered */
enum usb_dr_mode dr_mode;
int irq;
+ u32 obint_enable_bits;
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool soc_no_adp_ctrl;
};
/*
@@ -172,14 +180,22 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
void __iomem *usb2_base = ch->base;
- u32 val = readl(usb2_base + USB2_ADPCTRL);
+ u32 vbus_ctrl_reg = USB2_ADPCTRL;
+ u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
+ u32 val;
dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
+ if (ch->soc_no_adp_ctrl) {
+ vbus_ctrl_reg = USB2_VBCTRL;
+ vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+ }
+
+ val = readl(usb2_base + vbus_ctrl_reg);
if (vbus)
- val |= USB2_ADPCTRL_DRVVBUS;
+ val |= vbus_ctrl_val;
else
- val &= ~USB2_ADPCTRL_DRVVBUS;
- writel(val, usb2_base + USB2_ADPCTRL);
+ val &= ~vbus_ctrl_val;
+ writel(val, usb2_base + vbus_ctrl_reg);
}
static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
@@ -188,9 +204,9 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
u32 val = readl(usb2_base + USB2_OBINTEN);
if (ch->uses_otg_pins && enable)
- val |= USB2_OBINT_BITS;
+ val |= ch->obint_enable_bits;
else
- val &= ~USB2_OBINT_BITS;
+ val &= ~ch->obint_enable_bits;
writel(val, usb2_base + USB2_OBINTEN);
}
@@ -252,6 +268,9 @@ static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
if (!ch->uses_otg_pins)
return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
+ if (ch->soc_no_adp_ctrl)
+ return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
+
return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}
@@ -376,16 +395,17 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
writel(val, usb2_base + USB2_LINECTRL1);
- val = readl(usb2_base + USB2_VBCTRL);
- val &= ~USB2_VBCTRL_OCCLREN;
- writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
- val = readl(usb2_base + USB2_ADPCTRL);
- writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
-
+ if (!ch->soc_no_adp_ctrl) {
+ val = readl(usb2_base + USB2_VBCTRL);
+ val &= ~USB2_VBCTRL_OCCLREN;
+ writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
+ val = readl(usb2_base + USB2_ADPCTRL);
+ writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
+ }
msleep(20);
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
rcar_gen3_device_recognition(ch);
}
@@ -397,9 +417,9 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
u32 status = readl(usb2_base + USB2_OBINTSTA);
irqreturn_t ret = IRQ_NONE;
- if (status & USB2_OBINT_BITS) {
+ if (status & ch->obint_enable_bits) {
dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
rcar_gen3_device_recognition(ch);
ret = IRQ_HANDLED;
}
@@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
.owner = THIS_MODULE,
};
+static const struct soc_device_attribute soc_no_adp_ctrl[] = {
+ { .soc_id = "r9a07g044", .data = (void *)true },
+ { /* Sentinel */ }
+};
+
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
{
.compatible = "renesas,usb2-phy-r8a77470",
@@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
struct phy_provider *provider;
const struct phy_ops *phy_usb2_ops;
int ret = 0, i;
+ const struct soc_device_attribute *attr;
if (!dev->of_node) {
dev_err(dev, "This driver needs device tree\n");
@@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (IS_ERR(channel->base))
return PTR_ERR(channel->base);
+ channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
/* get irq number here and request_irq for OTG in phy_init */
channel->irq = platform_get_irq_optional(pdev, 0);
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
@@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
int ret;
channel->is_otg_channel = true;
+ attr = soc_device_match(soc_no_adp_ctrl);
+ if (attr) {
+ channel->soc_no_adp_ctrl = attr->data;
+ channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+ }
+
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
"renesas,no-otg-pins");
channel->extcon = devm_extcon_dev_allocate(dev,
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 50+ messages in thread* Re: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-21 9:39 ` Biju Das
@ 2021-06-22 15:29 ` Geert Uytterhoeven
-1 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-22 15:29 UTC (permalink / raw)
To: Biju Das
Cc: Yoshihiro Shimoda, Kishon Vijay Abraham I, Vinod Koul,
Linux-Renesas, linux-phy, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju,
Thanks for your patch!
On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This patch adds OTG support for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> line ctrl register for OTG_ID pin changes. Apart from this
> it uses a different OTG-BC interrupt bit for device recognition.
So it is not compatible? ;-)
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> + { .soc_id = "r9a07g044", .data = (void *)true },
> + { /* Sentinel */ }
> +};
> +
> static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> {
> .compatible = "renesas,usb2-phy-r8a77470",
> @@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> struct phy_provider *provider;
> const struct phy_ops *phy_usb2_ops;
> int ret = 0, i;
> + const struct soc_device_attribute *attr;
>
> if (!dev->of_node) {
> dev_err(dev, "This driver needs device tree\n");
> @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(channel->base))
> return PTR_ERR(channel->base);
>
> + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
> /* get irq number here and request_irq for OTG in phy_init */
> channel->irq = platform_get_irq_optional(pdev, 0);
> channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> int ret;
>
> channel->is_otg_channel = true;
> + attr = soc_device_match(soc_no_adp_ctrl);
> + if (attr) {
> + channel->soc_no_adp_ctrl = attr->data;
> + channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
> + }
Please don't abuse soc_device_match() for matching with a different
variant that uses a different compatible value. Just add an entry
to rcar_gen3_phy_usb2_match_table[] instead.
I don't know if you can handle RZ/G2L just using a different phy_ops,
or need to extend rcar_gen3_phy_usb2_match_table[].data.
> +
> channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
> "renesas,no-otg-pins");
> channel->extcon = devm_extcon_dev_allocate(dev,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 50+ messages in thread* Re: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-22 15:29 ` Geert Uytterhoeven
0 siblings, 0 replies; 50+ messages in thread
From: Geert Uytterhoeven @ 2021-06-22 15:29 UTC (permalink / raw)
To: Biju Das
Cc: Yoshihiro Shimoda, Kishon Vijay Abraham I, Vinod Koul,
Linux-Renesas, linux-phy, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju,
Thanks for your patch!
On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> This patch adds OTG support for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> line ctrl register for OTG_ID pin changes. Apart from this
> it uses a different OTG-BC interrupt bit for device recognition.
So it is not compatible? ;-)
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> + { .soc_id = "r9a07g044", .data = (void *)true },
> + { /* Sentinel */ }
> +};
> +
> static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> {
> .compatible = "renesas,usb2-phy-r8a77470",
> @@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> struct phy_provider *provider;
> const struct phy_ops *phy_usb2_ops;
> int ret = 0, i;
> + const struct soc_device_attribute *attr;
>
> if (!dev->of_node) {
> dev_err(dev, "This driver needs device tree\n");
> @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(channel->base))
> return PTR_ERR(channel->base);
>
> + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
> /* get irq number here and request_irq for OTG in phy_init */
> channel->irq = platform_get_irq_optional(pdev, 0);
> channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> int ret;
>
> channel->is_otg_channel = true;
> + attr = soc_device_match(soc_no_adp_ctrl);
> + if (attr) {
> + channel->soc_no_adp_ctrl = attr->data;
> + channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
> + }
Please don't abuse soc_device_match() for matching with a different
variant that uses a different compatible value. Just add an entry
to rcar_gen3_phy_usb2_match_table[] instead.
I don't know if you can handle RZ/G2L just using a different phy_ops,
or need to extend rcar_gen3_phy_usb2_match_table[].data.
> +
> channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
> "renesas,no-otg-pins");
> channel->extcon = devm_extcon_dev_allocate(dev,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-22 15:29 ` Geert Uytterhoeven
@ 2021-06-23 7:04 ` Yoshihiro Shimoda
-1 siblings, 0 replies; 50+ messages in thread
From: Yoshihiro Shimoda @ 2021-06-23 7:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Linux-Renesas, linux-phy,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju-san, Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, June 23, 2021 12:29 AM
>
> Hi Biju,
>
> Thanks for your patch!
>
> On Mon, Jun 21, 2021 at 11:40 AM Biju Das wrote:
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> > line ctrl register for OTG_ID pin changes. Apart from this
> > it uses a different OTG-BC interrupt bit for device recognition.
>
> So it is not compatible? ;-)
>
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> > + { .soc_id = "r9a07g044", .data = (void *)true },
> > + { /* Sentinel */ }
> > +};
> > +
> > static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> > {
> > .compatible = "renesas,usb2-phy-r8a77470",
> > @@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > struct phy_provider *provider;
> > const struct phy_ops *phy_usb2_ops;
> > int ret = 0, i;
> > + const struct soc_device_attribute *attr;
> >
> > if (!dev->of_node) {
> > dev_err(dev, "This driver needs device tree\n");
> > @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
> > /* get irq number here and request_irq for OTG in phy_init */
> > channel->irq = platform_get_irq_optional(pdev, 0);
> > channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> > @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > int ret;
> >
> > channel->is_otg_channel = true;
> > + attr = soc_device_match(soc_no_adp_ctrl);
> > + if (attr) {
> > + channel->soc_no_adp_ctrl = attr->data;
> > + channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
> > + }
>
> Please don't abuse soc_device_match() for matching with a different
> variant that uses a different compatible value. Just add an entry
> to rcar_gen3_phy_usb2_match_table[] instead.
> I don't know if you can handle RZ/G2L just using a different phy_ops,
> or need to extend rcar_gen3_phy_usb2_match_table[].data.
Thank you for your comments. I think we need to extend
rcar_gen3_phy_usb2_match_table[].data because we cannot add
any private data into phy_ops.
I'll send further comments for this patch on other email thread.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-23 7:04 ` Yoshihiro Shimoda
0 siblings, 0 replies; 50+ messages in thread
From: Yoshihiro Shimoda @ 2021-06-23 7:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Linux-Renesas, linux-phy,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju-san, Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, June 23, 2021 12:29 AM
>
> Hi Biju,
>
> Thanks for your patch!
>
> On Mon, Jun 21, 2021 at 11:40 AM Biju Das wrote:
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> > line ctrl register for OTG_ID pin changes. Apart from this
> > it uses a different OTG-BC interrupt bit for device recognition.
>
> So it is not compatible? ;-)
>
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> > + { .soc_id = "r9a07g044", .data = (void *)true },
> > + { /* Sentinel */ }
> > +};
> > +
> > static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> > {
> > .compatible = "renesas,usb2-phy-r8a77470",
> > @@ -613,6 +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > struct phy_provider *provider;
> > const struct phy_ops *phy_usb2_ops;
> > int ret = 0, i;
> > + const struct soc_device_attribute *attr;
> >
> > if (!dev->of_node) {
> > dev_err(dev, "This driver needs device tree\n");
> > @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
> > /* get irq number here and request_irq for OTG in phy_init */
> > channel->irq = platform_get_irq_optional(pdev, 0);
> > channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> > @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> > int ret;
> >
> > channel->is_otg_channel = true;
> > + attr = soc_device_match(soc_no_adp_ctrl);
> > + if (attr) {
> > + channel->soc_no_adp_ctrl = attr->data;
> > + channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
> > + }
>
> Please don't abuse soc_device_match() for matching with a different
> variant that uses a different compatible value. Just add an entry
> to rcar_gen3_phy_usb2_match_table[] instead.
> I don't know if you can handle RZ/G2L just using a different phy_ops,
> or need to extend rcar_gen3_phy_usb2_match_table[].data.
Thank you for your comments. I think we need to extend
rcar_gen3_phy_usb2_match_table[].data because we cannot add
any private data into phy_ops.
I'll send further comments for this patch on other email thread.
Best regards,
Yoshihiro Shimoda
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-22 15:29 ` Geert Uytterhoeven
@ 2021-06-23 11:52 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 11:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshihiro Shimoda, Kishon Vijay Abraham I, Vinod Koul,
Linux-Renesas, linux-phy, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG
> support for RZ/G2L
>
> Hi Biju,
>
> Thanks for your patch!
>
> On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses line ctrl
> > register for OTG_ID pin changes. Apart from this it uses a different
> > OTG-BC interrupt bit for device recognition.
>
> So it is not compatible? ;-)
OK. Basically I meant we need some modification in driver to support this SoC.
>
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> > + { .soc_id = "r9a07g044", .data = (void *)true },
> > + { /* Sentinel */ }
> > +};
> > +
> > static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> > {
> > .compatible = "renesas,usb2-phy-r8a77470", @@ -613,6
> > +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
> *pdev)
> > struct phy_provider *provider;
> > const struct phy_ops *phy_usb2_ops;
> > int ret = 0, i;
> > + const struct soc_device_attribute *attr;
> >
> > if (!dev->of_node) {
> > dev_err(dev, "This driver needs device tree\n"); @@
> > -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG |
> > + USB2_OBINT_IDDIGCHG;
> > /* get irq number here and request_irq for OTG in phy_init */
> > channel->irq = platform_get_irq_optional(pdev, 0);
> > channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> > @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > int ret;
> >
> > channel->is_otg_channel = true;
> > + attr = soc_device_match(soc_no_adp_ctrl);
> > + if (attr) {
> > + channel->soc_no_adp_ctrl = attr->data;
> > + channel->obint_enable_bits =
> USB2_OBINT_IDCHG_EN;
> > + }
>
> Please don't abuse soc_device_match() for matching with a different
> variant that uses a different compatible value. Just add an entry to
> rcar_gen3_phy_usb2_match_table[] instead.
OK.
> I don't know if you can handle RZ/G2L just using a different phy_ops, or
> need to extend rcar_gen3_phy_usb2_match_table[].data.
Will try to extend rcar_gen3_phy_usb2_match_table[].data as Shimoda-san suggested.
Regards,
Biju
>
> > +
> > channel->uses_otg_pins = !of_property_read_bool(dev-
> >of_node,
> > "renesas,no-otg-
> pins");
> > channel->extcon = devm_extcon_dev_allocate(dev,
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 50+ messages in thread* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-23 11:52 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 11:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshihiro Shimoda, Kishon Vijay Abraham I, Vinod Koul,
Linux-Renesas, linux-phy, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG
> support for RZ/G2L
>
> Hi Biju,
>
> Thanks for your patch!
>
> On Mon, Jun 21, 2021 at 11:40 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses line ctrl
> > register for OTG_ID pin changes. Apart from this it uses a different
> > OTG-BC interrupt bit for device recognition.
>
> So it is not compatible? ;-)
OK. Basically I meant we need some modification in driver to support this SoC.
>
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > @@ -535,6 +555,11 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct soc_device_attribute soc_no_adp_ctrl[] = {
> > + { .soc_id = "r9a07g044", .data = (void *)true },
> > + { /* Sentinel */ }
> > +};
> > +
> > static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
> > {
> > .compatible = "renesas,usb2-phy-r8a77470", @@ -613,6
> > +638,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device
> *pdev)
> > struct phy_provider *provider;
> > const struct phy_ops *phy_usb2_ops;
> > int ret = 0, i;
> > + const struct soc_device_attribute *attr;
> >
> > if (!dev->of_node) {
> > dev_err(dev, "This driver needs device tree\n"); @@
> > -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG |
> > + USB2_OBINT_IDDIGCHG;
> > /* get irq number here and request_irq for OTG in phy_init */
> > channel->irq = platform_get_irq_optional(pdev, 0);
> > channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
> > @@ -634,6 +661,12 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > int ret;
> >
> > channel->is_otg_channel = true;
> > + attr = soc_device_match(soc_no_adp_ctrl);
> > + if (attr) {
> > + channel->soc_no_adp_ctrl = attr->data;
> > + channel->obint_enable_bits =
> USB2_OBINT_IDCHG_EN;
> > + }
>
> Please don't abuse soc_device_match() for matching with a different
> variant that uses a different compatible value. Just add an entry to
> rcar_gen3_phy_usb2_match_table[] instead.
OK.
> I don't know if you can handle RZ/G2L just using a different phy_ops, or
> need to extend rcar_gen3_phy_usb2_match_table[].data.
Will try to extend rcar_gen3_phy_usb2_match_table[].data as Shimoda-san suggested.
Regards,
Biju
>
> > +
> > channel->uses_otg_pins = !of_property_read_bool(dev-
> >of_node,
> > "renesas,no-otg-
> pins");
> > channel->extcon = devm_extcon_dev_allocate(dev,
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-21 9:39 ` Biju Das
@ 2021-06-23 8:02 ` Yoshihiro Shimoda
-1 siblings, 0 replies; 50+ messages in thread
From: Yoshihiro Shimoda @ 2021-06-23 8:02 UTC (permalink / raw)
To: Biju Das
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc,
linux-phy, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju-san,
Thank you for the patch!
> From: Biju Das, Sent: Monday, June 21, 2021 6:40 PM
>
> This patch adds OTG support for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> line ctrl register for OTG_ID pin changes. Apart from this
> it uses a different OTG-BC interrupt bit for device recognition.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63 ++++++++++++++++++------
> 1 file changed, 48 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> index fbc55232120e..aff0749be65d 100644
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
<snip>
> @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(channel->base))
> return PTR_ERR(channel->base);
>
> + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
Please use USB2_OBINT_BITS instead of USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG.
Sorry, I thought we needed more update when I sent an email before,
but I have this comment only now.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-23 8:02 ` Yoshihiro Shimoda
0 siblings, 0 replies; 50+ messages in thread
From: Yoshihiro Shimoda @ 2021-06-23 8:02 UTC (permalink / raw)
To: Biju Das
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc,
linux-phy, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju-san,
Thank you for the patch!
> From: Biju Das, Sent: Monday, June 21, 2021 6:40 PM
>
> This patch adds OTG support for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses
> line ctrl register for OTG_ID pin changes. Apart from this
> it uses a different OTG-BC interrupt bit for device recognition.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63 ++++++++++++++++++------
> 1 file changed, 48 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> index fbc55232120e..aff0749be65d 100644
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
<snip>
> @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(channel->base))
> return PTR_ERR(channel->base);
>
> + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG;
Please use USB2_OBINT_BITS instead of USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG.
Sorry, I thought we needed more update when I sent an email before,
but I have this comment only now.
Best regards,
Yoshihiro Shimoda
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
2021-06-23 8:02 ` Yoshihiro Shimoda
@ 2021-06-23 11:54 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 11:54 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc, linux-phy,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Shimoda-San,
Thanks for the feedback.
> Subject: RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG
> support for RZ/G2L
>
> Hi Biju-san,
>
> Thank you for the patch!
>
> > From: Biju Das, Sent: Monday, June 21, 2021 6:40 PM
> >
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses line ctrl
> > register for OTG_ID pin changes. Apart from this it uses a different
> > OTG-BC interrupt bit for device recognition.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63
> > ++++++++++++++++++------
> > 1 file changed, 48 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > index fbc55232120e..aff0749be65d 100644
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> <snip>
> > @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG |
> > +USB2_OBINT_IDDIGCHG;
>
> Please use USB2_OBINT_BITS instead of USB2_OBINT_SESSVLDCHG |
> USB2_OBINT_IDDIGCHG.
OK. Will use USB2_OBINT_BITS.
Regards,
Biju
> Sorry, I thought we needed more update when I sent an email before, but I
> have this comment only now.
>
> Best regards,
> Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
@ 2021-06-23 11:54 ` Biju Das
0 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-23 11:54 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc, linux-phy,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Shimoda-San,
Thanks for the feedback.
> Subject: RE: [PATCH v2 10/11] phy: renesas: phy-rcar-gen3-usb2: Add OTG
> support for RZ/G2L
>
> Hi Biju-san,
>
> Thank you for the patch!
>
> > From: Biju Das, Sent: Monday, June 21, 2021 6:40 PM
> >
> > This patch adds OTG support for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy is compatible with rcar gen3, but it uses line ctrl
> > register for OTG_ID pin changes. Apart from this it uses a different
> > OTG-BC interrupt bit for device recognition.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/phy/renesas/phy-rcar-gen3-usb2.c | 63
> > ++++++++++++++++++------
> > 1 file changed, 48 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > index fbc55232120e..aff0749be65d 100644
> > --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> > +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> <snip>
> > @@ -627,6 +653,7 @@ static int rcar_gen3_phy_usb2_probe(struct
> platform_device *pdev)
> > if (IS_ERR(channel->base))
> > return PTR_ERR(channel->base);
> >
> > + channel->obint_enable_bits = USB2_OBINT_SESSVLDCHG |
> > +USB2_OBINT_IDDIGCHG;
>
> Please use USB2_OBINT_BITS instead of USB2_OBINT_SESSVLDCHG |
> USB2_OBINT_IDDIGCHG.
OK. Will use USB2_OBINT_BITS.
Regards,
Biju
> Sorry, I thought we needed more update when I sent an email before, but I
> have this comment only now.
>
> Best regards,
> Yoshihiro Shimoda
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 11/11] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
2021-06-21 9:39 ` Biju Das
` (10 preceding siblings ...)
(?)
@ 2021-06-21 9:39 ` Biju Das
-1 siblings, 0 replies; 50+ messages in thread
From: Biju Das @ 2021-06-21 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 device support to RZ/G2L SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index ae71404c6238..ef48b023b41a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -336,6 +336,25 @@
power-domains = <&cpg>;
status = "disabled";
};
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&cpg R9A07G044_USB_PCLK>,
+ <&cpg R9A07G044_USB_U2P_EXR_CPUCLK>;
+ renesas,buswait = <7>;
+ phys = <&usbphyctrl 0>, <&usb2_phy0 3>;
+ phy-names = "usbphyctrl", "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
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