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* Re: [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
  2019-01-21 17:38   ` Nava kishore Manne
  (?)
@ 2019-01-21 15:46     ` Rob Herring
  -1 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:46 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt,
	Nava kishore Manne, Jolly Shah

On Mon, 21 Jan 2019 23:08:32 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP reset driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Signed-off-by: Jolly Shah <jollys@xilinx.com>
> ---
> Changes for v3:
> 		-Moved reset outputs definitions info into
> 		 a header file(xlnx-zynqmp-resets.h).
> 
>  .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
>  .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
>  2 files changed, 182 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
>  create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
@ 2019-01-21 15:46     ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:46 UTC (permalink / raw)
  Cc: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt,
	Nava kishore Manne, Jolly Shah

On Mon, 21 Jan 2019 23:08:32 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP reset driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Signed-off-by: Jolly Shah <jollys@xilinx.com>
> ---
> Changes for v3:
> 		-Moved reset outputs definitions info into
> 		 a header file(xlnx-zynqmp-resets.h).
> 
>  .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
>  .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
>  2 files changed, 182 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
>  create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
@ 2019-01-21 15:46     ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:46 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, Nava kishore Manne, linux-kernel,
	Jolly Shah, RAJANV, robh+dt, michals, linux-arm-kernel,
	chinnikishore369

On Mon, 21 Jan 2019 23:08:32 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP reset driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Signed-off-by: Jolly Shah <jollys@xilinx.com>
> ---
> Changes for v3:
> 		-Moved reset outputs definitions info into
> 		 a header file(xlnx-zynqmp-resets.h).
> 
>  .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
>  .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
>  2 files changed, 182 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
>  create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  2019-01-21 17:38   ` Nava kishore Manne
  (?)
@ 2019-01-21 15:47     ` Rob Herring
  -1 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:47 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt,
	Nava kishore Manne

On Mon, 21 Jan 2019 23:08:34 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP nvmem driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v3:
> 		-Added nvmem node as child of FW. Since nvmem driver is a provider.
>   
>  .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
@ 2019-01-21 15:47     ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:47 UTC (permalink / raw)
  Cc: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt,
	Nava kishore Manne

On Mon, 21 Jan 2019 23:08:34 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP nvmem driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v3:
> 		-Added nvmem node as child of FW. Since nvmem driver is a provider.
>   
>  .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
@ 2019-01-21 15:47     ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:47 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, Nava kishore Manne, linux-kernel,
	JOLLYS, RAJANV, robh+dt, michals, linux-arm-kernel,
	chinnikishore369

On Mon, 21 Jan 2019 23:08:34 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP nvmem driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v3:
> 		-Added nvmem node as child of FW. Since nvmem driver is a provider.
>   
>  .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-01-21 17:38   ` Nava kishore Manne
@ 2019-01-21 15:49     ` Rob Herring
  -1 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:49 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369

On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v3:
> 		-Removed PCAP as a child node to the FW and Created
> 		an independent node since PCAP driver is a consumer
> 		not a provider. 
> 
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..1f6f58872311
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,13 @@
> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +Example:
> +	zynqmp_pcap: pcap {
> +		compatible = "xlnx,zynqmp-pcap-fpga";
> +	};

There's no need for a DT node. Just make the firware driver create a 
platform device for pcap.

Rob

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-01-21 15:49     ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-01-21 15:49 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, linux-kernel, JOLLYS, RAJANV, michals,
	linux-arm-kernel, chinnikishore369

On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v3:
> 		-Removed PCAP as a child node to the FW and Created
> 		an independent node since PCAP driver is a consumer
> 		not a provider. 
> 
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..1f6f58872311
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,13 @@
> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +Example:
> +	zynqmp_pcap: pcap {
> +		compatible = "xlnx,zynqmp-pcap-fpga";
> +	};

There's no need for a DT node. Just make the firware driver create a 
platform device for pcap.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core
@ 2019-01-21 17:38 ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node bindings. 

Complete firmware DT node example is shown below for ease of understanding:

firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";
		#power-domain-cells = <1>;
		#reset-cells = <1>;

		zynqmp_clk: clock-controller {
			#clock-cells = <1>;
			compatible = "xlnx,zynqmp-clk";
			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
		};

		zynqmp_power: zynqmp-power {
			compatible = "xlnx,zynqmp-power";
			interrupts = <0 35 4>;
		};

		zynqmp_reset: reset-controller {
			compatible = "xlnx,zynqmp-reset";
			#reset-cells = <1>;
		};
	
		nvmem_firmware {
			compatible = "xlnx,zynqmp-nvmem-fw";
			#address-cells = <1>;
			#size-cells = <1>;

			/* Data cells */
			soc_revision: soc_revision {
				reg = <0x0 0x4>;
			};
		};

		pinctrl0: pinctrl@ff180000 {
			compatible = "xlnx,zynqmp-pinctrl";

			pinctrl_uart1_default: uart1-default {
				mux {
					groups = "uart0_4_grp";
					function = "uart0";
				};
	
				conf {
					groups = "uart0_4_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					io-standard = <IO_STANDARD_LVCMOS18>;
				};
	
				conf-rx {
					pins = "MIO18";
					bias-high-impedance;
				};
	
				conf-tx {
					pins = "MIO19";
					bias-disable;
					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
				};
			};
		};
	};
};


Nava kishore Manne (3):
  dt-bindings: reset: Add bindings for ZynqMP reset driver
  dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver

Rajan Vaja (3):
  dt-bindings: power: Add ZynqMP power domain bindings
  dt-bindings: soc: Add ZynqMP PM bindings
  dt-bindings: pinctrl: Add ZynqMP pin controller bindings

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  13 +
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      |  47 +++
 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 .../power/reset/xlnx,zynqmp-power.txt         |  25 ++
 .../bindings/power/xlnx,zynqmp-genpd.txt      |  34 +++
 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 ++++
 include/dt-bindings/power/xlnx-zynqmp-power.h |  39 +++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 +++++++++
 8 files changed, 615 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

-- 
2.18.0


^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core
@ 2019-01-21 17:38 ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node bindings. 

Complete firmware DT node example is shown below for ease of understanding:

firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";
		#power-domain-cells = <1>;
		#reset-cells = <1>;

		zynqmp_clk: clock-controller {
			#clock-cells = <1>;
			compatible = "xlnx,zynqmp-clk";
			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
		};

		zynqmp_power: zynqmp-power {
			compatible = "xlnx,zynqmp-power";
			interrupts = <0 35 4>;
		};

		zynqmp_reset: reset-controller {
			compatible = "xlnx,zynqmp-reset";
			#reset-cells = <1>;
		};
	
		nvmem_firmware {
			compatible = "xlnx,zynqmp-nvmem-fw";
			#address-cells = <1>;
			#size-cells = <1>;

			/* Data cells */
			soc_revision: soc_revision {
				reg = <0x0 0x4>;
			};
		};

		pinctrl0: pinctrl@ff180000 {
			compatible = "xlnx,zynqmp-pinctrl";

			pinctrl_uart1_default: uart1-default {
				mux {
					groups = "uart0_4_grp";
					function = "uart0";
				};
	
				conf {
					groups = "uart0_4_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					io-standard = <IO_STANDARD_LVCMOS18>;
				};
	
				conf-rx {
					pins = "MIO18";
					bias-high-impedance;
				};
	
				conf-tx {
					pins = "MIO19";
					bias-disable;
					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
				};
			};
		};
	};
};


Nava kishore Manne (3):
  dt-bindings: reset: Add bindings for ZynqMP reset driver
  dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver

Rajan Vaja (3):
  dt-bindings: power: Add ZynqMP power domain bindings
  dt-bindings: soc: Add ZynqMP PM bindings
  dt-bindings: pinctrl: Add ZynqMP pin controller bindings

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  13 +
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      |  47 +++
 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 .../power/reset/xlnx,zynqmp-power.txt         |  25 ++
 .../bindings/power/xlnx,zynqmp-genpd.txt      |  34 +++
 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 ++++
 include/dt-bindings/power/xlnx-zynqmp-power.h |  39 +++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 +++++++++
 8 files changed, 615 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

-- 
2.18.0

^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core
@ 2019-01-21 17:38 ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node bindings. 

Complete firmware DT node example is shown below for ease of understanding:

firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";
		#power-domain-cells = <1>;
		#reset-cells = <1>;

		zynqmp_clk: clock-controller {
			#clock-cells = <1>;
			compatible = "xlnx,zynqmp-clk";
			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
		};

		zynqmp_power: zynqmp-power {
			compatible = "xlnx,zynqmp-power";
			interrupts = <0 35 4>;
		};

		zynqmp_reset: reset-controller {
			compatible = "xlnx,zynqmp-reset";
			#reset-cells = <1>;
		};
	
		nvmem_firmware {
			compatible = "xlnx,zynqmp-nvmem-fw";
			#address-cells = <1>;
			#size-cells = <1>;

			/* Data cells */
			soc_revision: soc_revision {
				reg = <0x0 0x4>;
			};
		};

		pinctrl0: pinctrl@ff180000 {
			compatible = "xlnx,zynqmp-pinctrl";

			pinctrl_uart1_default: uart1-default {
				mux {
					groups = "uart0_4_grp";
					function = "uart0";
				};
	
				conf {
					groups = "uart0_4_grp";
					slew-rate = <SLEW_RATE_SLOW>;
					io-standard = <IO_STANDARD_LVCMOS18>;
				};
	
				conf-rx {
					pins = "MIO18";
					bias-high-impedance;
				};
	
				conf-tx {
					pins = "MIO19";
					bias-disable;
					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
				};
			};
		};
	};
};


Nava kishore Manne (3):
  dt-bindings: reset: Add bindings for ZynqMP reset driver
  dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver

Rajan Vaja (3):
  dt-bindings: power: Add ZynqMP power domain bindings
  dt-bindings: soc: Add ZynqMP PM bindings
  dt-bindings: pinctrl: Add ZynqMP pin controller bindings

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  13 +
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      |  47 +++
 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 .../power/reset/xlnx,zynqmp-power.txt         |  25 ++
 .../bindings/power/xlnx,zynqmp-genpd.txt      |  34 +++
 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 ++++
 include/dt-bindings/power/xlnx-zynqmp-power.h |  39 +++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 +++++++++
 8 files changed, 615 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PATCH v3 1/6] dt-bindings: power: Add ZynqMP power domain bindings
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe ZynqMP power domain bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/power/xlnx,zynqmp-genpd.txt      | 34 ++++++++++++++++
 include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h

diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index 000000000000..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+-----------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+-----------------------------------------------------------
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells:	Number of cells in a PM domain specifier. Must be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		...
+		#power-domain-cells = <1>;
+		...
+	};
+};
+
+sata {
+	...
+	power-domains = <&zynqmp_firmware 2>;
+	...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 000000000000..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define		PD_USB_0	0
+#define		PD_USB_1	1
+#define		PD_SATA		2
+#define		PD_SPI_0	3
+#define		PD_SPI_1	4
+#define		PD_UART_0	5
+#define		PD_UART_1	6
+#define		PD_ETH_0	7
+#define		PD_ETH_1	8
+#define		PD_ETH_2	9
+#define		PD_ETH_3	10
+#define		PD_I2C_0	11
+#define		PD_I2C_1	12
+#define		PD_DP		13
+#define		PD_GDMA		14
+#define		PD_ADMA		15
+#define		PD_TTC_0	16
+#define		PD_TTC_1	17
+#define		PD_TTC_2	18
+#define		PD_TTC_3	19
+#define		PD_SD_0		20
+#define		PD_SD_1		21
+#define		PD_NAND		22
+#define		PD_QSPI		23
+#define		PD_GPIO		24
+#define		PD_CAN_0	25
+#define		PD_CAN_1	26
+#define		PD_PCIE		27
+#define		PD_GPU		28
+
+#endif
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 1/6] dt-bindings: power: Add ZynqMP power domain bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe ZynqMP power domain bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/power/xlnx,zynqmp-genpd.txt      | 34 ++++++++++++++++
 include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h

diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index 000000000000..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+-----------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+-----------------------------------------------------------
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells:	Number of cells in a PM domain specifier. Must be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		...
+		#power-domain-cells = <1>;
+		...
+	};
+};
+
+sata {
+	...
+	power-domains = <&zynqmp_firmware 2>;
+	...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 000000000000..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define		PD_USB_0	0
+#define		PD_USB_1	1
+#define		PD_SATA		2
+#define		PD_SPI_0	3
+#define		PD_SPI_1	4
+#define		PD_UART_0	5
+#define		PD_UART_1	6
+#define		PD_ETH_0	7
+#define		PD_ETH_1	8
+#define		PD_ETH_2	9
+#define		PD_ETH_3	10
+#define		PD_I2C_0	11
+#define		PD_I2C_1	12
+#define		PD_DP		13
+#define		PD_GDMA		14
+#define		PD_ADMA		15
+#define		PD_TTC_0	16
+#define		PD_TTC_1	17
+#define		PD_TTC_2	18
+#define		PD_TTC_3	19
+#define		PD_SD_0		20
+#define		PD_SD_1		21
+#define		PD_NAND		22
+#define		PD_QSPI		23
+#define		PD_GPIO		24
+#define		PD_CAN_0	25
+#define		PD_CAN_1	26
+#define		PD_PCIE		27
+#define		PD_GPU		28
+
+#endif
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 1/6] dt-bindings: power: Add ZynqMP power domain bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Jolly Shah, Rajan Vaja

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe ZynqMP power domain bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/power/xlnx,zynqmp-genpd.txt      | 34 ++++++++++++++++
 include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
 create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h

diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index 000000000000..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+-----------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+-----------------------------------------------------------
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells:	Number of cells in a PM domain specifier. Must be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		...
+		#power-domain-cells = <1>;
+		...
+	};
+};
+
+sata {
+	...
+	power-domains = <&zynqmp_firmware 2>;
+	...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 000000000000..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define		PD_USB_0	0
+#define		PD_USB_1	1
+#define		PD_SATA		2
+#define		PD_SPI_0	3
+#define		PD_SPI_1	4
+#define		PD_UART_0	5
+#define		PD_UART_1	6
+#define		PD_ETH_0	7
+#define		PD_ETH_1	8
+#define		PD_ETH_2	9
+#define		PD_ETH_3	10
+#define		PD_I2C_0	11
+#define		PD_I2C_1	12
+#define		PD_DP		13
+#define		PD_GDMA		14
+#define		PD_ADMA		15
+#define		PD_TTC_0	16
+#define		PD_TTC_1	17
+#define		PD_TTC_2	18
+#define		PD_TTC_3	19
+#define		PD_SD_0		20
+#define		PD_SD_1		21
+#define		PD_NAND		22
+#define		PD_QSPI		23
+#define		PD_GPIO		24
+#define		PD_CAN_0	25
+#define		PD_CAN_1	26
+#define		PD_PCIE		27
+#define		PD_GPU		28
+
+#endif
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 2/6] dt-bindings: soc: Add ZynqMP PM bindings
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP power management
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../power/reset/xlnx,zynqmp-power.txt         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt

diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index 000000000000..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+--------------------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+--------------------------------------------------------------------
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible:		Must contain:	"xlnx,zynqmp-power"
+ - interrupts:		Interrupt specifier
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_power: zynqmp-power {
+			compatible = "xlnx,zynqmp-power";
+			interrupts = <0 35 4>;
+		};
+	};
+};
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 2/6] dt-bindings: soc: Add ZynqMP PM bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP power management
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../power/reset/xlnx,zynqmp-power.txt         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt

diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index 000000000000..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+--------------------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+--------------------------------------------------------------------
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible:		Must contain:	"xlnx,zynqmp-power"
+ - interrupts:		Interrupt specifier
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_power: zynqmp-power {
+			compatible = "xlnx,zynqmp-power";
+			interrupts = <0 35 4>;
+		};
+	};
+};
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 2/6] dt-bindings: soc: Add ZynqMP PM bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Jolly Shah, Rajan Vaja

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP power management
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../power/reset/xlnx,zynqmp-power.txt         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt

diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index 000000000000..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+--------------------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+--------------------------------------------------------------------
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible:		Must contain:	"xlnx,zynqmp-power"
+ - interrupts:		Interrupt specifier
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_power: zynqmp-power {
+			compatible = "xlnx,zynqmp-power";
+			interrupts = <0 35 4>;
+		};
+	};
+};
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne, Jolly Shah

Add documentation to describe Xilinx ZynqMP reset driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
---
Changes for v3:
		-Moved reset outputs definitions info into
		 a header file(xlnx-zynqmp-resets.h).

 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
 2 files changed, 182 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index 000000000000..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--------------------------------------------------------------------------
+ =  Zynq UltraScale+ MPSoC reset driver binding =
+--------------------------------------------------------------------------
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible:	"xlnx,zynqmp-reset"
+- #reset-cells:	Specifies the number of cells needed to encode reset
+		line, should be 1
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_reset: reset-controller {
+			compatible = "xlnx,zynqmp-reset";
+			#reset-cells = <1>;
+		};
+	};
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+Example:
+
+serdes: zynqmp_phy@fd400000 {
+	...
+
+	resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
+	reset-names = "sata_rst";
+
+	...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index 000000000000..e295fd5d824e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#define		ZYNQMP_RESET_PCIE_CFG		0
+#define		ZYNQMP_RESET_PCIE_BRIDGE	1
+#define		ZYNQMP_RESET_PCIE_CTRL		2
+#define		ZYNQMP_RESET_DP			3
+#define		ZYNQMP_RESET_SWDT_CRF		4
+#define		ZYNQMP_RESET_AFI_FM5		5
+#define		ZYNQMP_RESET_AFI_FM4		6
+#define		ZYNQMP_RESET_AFI_FM3		7
+#define		ZYNQMP_RESET_AFI_FM2		8
+#define		ZYNQMP_RESET_AFI_FM1		9
+#define		ZYNQMP_RESET_AFI_FM0		10
+#define		ZYNQMP_RESET_GDMA		11
+#define		ZYNQMP_RESET_GPU_PP1		12
+#define		ZYNQMP_RESET_GPU_PP0		13
+#define		ZYNQMP_RESET_GPU		14
+#define		ZYNQMP_RESET_GT			15
+#define		ZYNQMP_RESET_SATA		16
+#define		ZYNQMP_RESET_ACPU3_PWRON	17
+#define		ZYNQMP_RESET_ACPU2_PWRON	18
+#define		ZYNQMP_RESET_ACPU1_PWRON	19
+#define		ZYNQMP_RESET_ACPU0_PWRON	20
+#define		ZYNQMP_RESET_APU_L2		21
+#define		ZYNQMP_RESET_ACPU3		22
+#define		ZYNQMP_RESET_ACPU2		23
+#define		ZYNQMP_RESET_ACPU1		24
+#define		ZYNQMP_RESET_ACPU0		25
+#define		ZYNQMP_RESET_DDR		26
+#define		ZYNQMP_RESET_APM_FPD		27
+#define		ZYNQMP_RESET_SOFT		28
+#define		ZYNQMP_RESET_GEM0		29
+#define		ZYNQMP_RESET_GEM1		30
+#define		ZYNQMP_RESET_GEM2		31
+#define		ZYNQMP_RESET_GEM3		32
+#define		ZYNQMP_RESET_QSPI		33
+#define		ZYNQMP_RESET_UART0		34
+#define		ZYNQMP_RESET_UART1		35
+#define		ZYNQMP_RESET_SPI0		36
+#define		ZYNQMP_RESET_SPI1		37
+#define		ZYNQMP_RESET_SDIO0		38
+#define		ZYNQMP_RESET_SDIO1		39
+#define		ZYNQMP_RESET_CAN0		40
+#define		ZYNQMP_RESET_CAN1		41
+#define		ZYNQMP_RESET_I2C0		42
+#define		ZYNQMP_RESET_I2C1		43
+#define		ZYNQMP_RESET_TTC0		44
+#define		ZYNQMP_RESET_TTC1		45
+#define		ZYNQMP_RESET_TTC2		46
+#define		ZYNQMP_RESET_TTC3		47
+#define		ZYNQMP_RESET_SWDT_CRL		48
+#define		ZYNQMP_RESET_NAND		49
+#define		ZYNQMP_RESET_ADMA		50
+#define		ZYNQMP_RESET_GPIO		51
+#define		ZYNQMP_RESET_IOU_CC		52
+#define		ZYNQMP_RESET_TIMESTAMP		53
+#define		ZYNQMP_RESET_RPU_R50		54
+#define		ZYNQMP_RESET_RPU_R51		55
+#define		ZYNQMP_RESET_RPU_AMBA		56
+#define		ZYNQMP_RESET_OCM		57
+#define		ZYNQMP_RESET_RPU_PGE		58
+#define		ZYNQMP_RESET_USB0_CORERESET	59
+#define		ZYNQMP_RESET_USB1_CORERESET	60
+#define		ZYNQMP_RESET_USB0_HIBERRESET	61
+#define		ZYNQMP_RESET_USB1_HIBERRESET	62
+#define		ZYNQMP_RESET_USB0_APB		63
+#define		ZYNQMP_RESET_USB1_APB		64
+#define		ZYNQMP_RESET_IPI		65
+#define		ZYNQMP_RESET_APM_LPD		66
+#define		ZYNQMP_RESET_RTC		67
+#define		ZYNQMP_RESET_SYSMON		68
+#define		ZYNQMP_RESET_AFI_FM6		69
+#define		ZYNQMP_RESET_LPD_SWDT		70
+#define		ZYNQMP_RESET_FPD		71
+#define		ZYNQMP_RESET_RPU_DBG1		72
+#define		ZYNQMP_RESET_RPU_DBG0		73
+#define		ZYNQMP_RESET_DBG_LPD		74
+#define		ZYNQMP_RESET_DBG_FPD		75
+#define		ZYNQMP_RESET_APLL		76
+#define		ZYNQMP_RESET_DPLL		77
+#define		ZYNQMP_RESET_VPLL		78
+#define		ZYNQMP_RESET_IOPLL		79
+#define		ZYNQMP_RESET_RPLL		80
+#define		ZYNQMP_RESET_GPO3_PL_0		81
+#define		ZYNQMP_RESET_GPO3_PL_1		82
+#define		ZYNQMP_RESET_GPO3_PL_2		83
+#define		ZYNQMP_RESET_GPO3_PL_3		84
+#define		ZYNQMP_RESET_GPO3_PL_4		85
+#define		ZYNQMP_RESET_GPO3_PL_5		86
+#define		ZYNQMP_RESET_GPO3_PL_6		87
+#define		ZYNQMP_RESET_GPO3_PL_7		88
+#define		ZYNQMP_RESET_GPO3_PL_8		89
+#define		ZYNQMP_RESET_GPO3_PL_9		90
+#define		ZYNQMP_RESET_GPO3_PL_10		91
+#define		ZYNQMP_RESET_GPO3_PL_11		92
+#define		ZYNQMP_RESET_GPO3_PL_12		93
+#define		ZYNQMP_RESET_GPO3_PL_13		94
+#define		ZYNQMP_RESET_GPO3_PL_14		95
+#define		ZYNQMP_RESET_GPO3_PL_15		96
+#define		ZYNQMP_RESET_GPO3_PL_16		97
+#define		ZYNQMP_RESET_GPO3_PL_17		98
+#define		ZYNQMP_RESET_GPO3_PL_18		99
+#define		ZYNQMP_RESET_GPO3_PL_19		100
+#define		ZNQMP_RESET_GPO3_PL_20		101
+#define		ZYNQMP_RESET_GPO3_PL_21		102
+#define		ZYNQMP_RESET_GPO3_PL_22		103
+#define		ZYNQMP_RESET_GPO3_PL_23		104
+#define		ZYNQMP_RESET_GPO3_PL_24		105
+#define		ZYNQMP_RESET_GPO3_PL_25		106
+#define		ZYNQMP_RESET_GPO3_PL_26		107
+#define		ZYNQMP_RESET_GPO3_PL_27		108
+#define		ZYNQMP_RESET_GPO3_PL_28		109
+#define		ZYNQMP_RESET_GPO3_PL_29		110
+#define		ZYNQMP_RESET_GPO3_PL_30		111
+#define		ZYNQMP_RESET_GPO3_PL_31		112
+#define		ZYNQMP_RESET_RPU_LS		113
+#define		ZYNQMP_RESET_PS_ONLY		114
+#define		ZYNQMP_RESET_PL			115
+#define		ZYNQMP_RESET_PS_PL0		116
+#define		ZYNQMP_RESET_PS_PL1		117
+#define		ZYNQMP_RESET_PS_PL2		118
+#define		ZYNQMP_RESET_PS_PL3		119
+
+#endif
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne, Jolly Shah

Add documentation to describe Xilinx ZynqMP reset driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
---
Changes for v3:
		-Moved reset outputs definitions info into
		 a header file(xlnx-zynqmp-resets.h).

 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
 2 files changed, 182 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index 000000000000..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--------------------------------------------------------------------------
+ =  Zynq UltraScale+ MPSoC reset driver binding =
+--------------------------------------------------------------------------
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible:	"xlnx,zynqmp-reset"
+- #reset-cells:	Specifies the number of cells needed to encode reset
+		line, should be 1
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_reset: reset-controller {
+			compatible = "xlnx,zynqmp-reset";
+			#reset-cells = <1>;
+		};
+	};
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+Example:
+
+serdes: zynqmp_phy@fd400000 {
+	...
+
+	resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
+	reset-names = "sata_rst";
+
+	...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index 000000000000..e295fd5d824e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#define		ZYNQMP_RESET_PCIE_CFG		0
+#define		ZYNQMP_RESET_PCIE_BRIDGE	1
+#define		ZYNQMP_RESET_PCIE_CTRL		2
+#define		ZYNQMP_RESET_DP			3
+#define		ZYNQMP_RESET_SWDT_CRF		4
+#define		ZYNQMP_RESET_AFI_FM5		5
+#define		ZYNQMP_RESET_AFI_FM4		6
+#define		ZYNQMP_RESET_AFI_FM3		7
+#define		ZYNQMP_RESET_AFI_FM2		8
+#define		ZYNQMP_RESET_AFI_FM1		9
+#define		ZYNQMP_RESET_AFI_FM0		10
+#define		ZYNQMP_RESET_GDMA		11
+#define		ZYNQMP_RESET_GPU_PP1		12
+#define		ZYNQMP_RESET_GPU_PP0		13
+#define		ZYNQMP_RESET_GPU		14
+#define		ZYNQMP_RESET_GT			15
+#define		ZYNQMP_RESET_SATA		16
+#define		ZYNQMP_RESET_ACPU3_PWRON	17
+#define		ZYNQMP_RESET_ACPU2_PWRON	18
+#define		ZYNQMP_RESET_ACPU1_PWRON	19
+#define		ZYNQMP_RESET_ACPU0_PWRON	20
+#define		ZYNQMP_RESET_APU_L2		21
+#define		ZYNQMP_RESET_ACPU3		22
+#define		ZYNQMP_RESET_ACPU2		23
+#define		ZYNQMP_RESET_ACPU1		24
+#define		ZYNQMP_RESET_ACPU0		25
+#define		ZYNQMP_RESET_DDR		26
+#define		ZYNQMP_RESET_APM_FPD		27
+#define		ZYNQMP_RESET_SOFT		28
+#define		ZYNQMP_RESET_GEM0		29
+#define		ZYNQMP_RESET_GEM1		30
+#define		ZYNQMP_RESET_GEM2		31
+#define		ZYNQMP_RESET_GEM3		32
+#define		ZYNQMP_RESET_QSPI		33
+#define		ZYNQMP_RESET_UART0		34
+#define		ZYNQMP_RESET_UART1		35
+#define		ZYNQMP_RESET_SPI0		36
+#define		ZYNQMP_RESET_SPI1		37
+#define		ZYNQMP_RESET_SDIO0		38
+#define		ZYNQMP_RESET_SDIO1		39
+#define		ZYNQMP_RESET_CAN0		40
+#define		ZYNQMP_RESET_CAN1		41
+#define		ZYNQMP_RESET_I2C0		42
+#define		ZYNQMP_RESET_I2C1		43
+#define		ZYNQMP_RESET_TTC0		44
+#define		ZYNQMP_RESET_TTC1		45
+#define		ZYNQMP_RESET_TTC2		46
+#define		ZYNQMP_RESET_TTC3		47
+#define		ZYNQMP_RESET_SWDT_CRL		48
+#define		ZYNQMP_RESET_NAND		49
+#define		ZYNQMP_RESET_ADMA		50
+#define		ZYNQMP_RESET_GPIO		51
+#define		ZYNQMP_RESET_IOU_CC		52
+#define		ZYNQMP_RESET_TIMESTAMP		53
+#define		ZYNQMP_RESET_RPU_R50		54
+#define		ZYNQMP_RESET_RPU_R51		55
+#define		ZYNQMP_RESET_RPU_AMBA		56
+#define		ZYNQMP_RESET_OCM		57
+#define		ZYNQMP_RESET_RPU_PGE		58
+#define		ZYNQMP_RESET_USB0_CORERESET	59
+#define		ZYNQMP_RESET_USB1_CORERESET	60
+#define		ZYNQMP_RESET_USB0_HIBERRESET	61
+#define		ZYNQMP_RESET_USB1_HIBERRESET	62
+#define		ZYNQMP_RESET_USB0_APB		63
+#define		ZYNQMP_RESET_USB1_APB		64
+#define		ZYNQMP_RESET_IPI		65
+#define		ZYNQMP_RESET_APM_LPD		66
+#define		ZYNQMP_RESET_RTC		67
+#define		ZYNQMP_RESET_SYSMON		68
+#define		ZYNQMP_RESET_AFI_FM6		69
+#define		ZYNQMP_RESET_LPD_SWDT		70
+#define		ZYNQMP_RESET_FPD		71
+#define		ZYNQMP_RESET_RPU_DBG1		72
+#define		ZYNQMP_RESET_RPU_DBG0		73
+#define		ZYNQMP_RESET_DBG_LPD		74
+#define		ZYNQMP_RESET_DBG_FPD		75
+#define		ZYNQMP_RESET_APLL		76
+#define		ZYNQMP_RESET_DPLL		77
+#define		ZYNQMP_RESET_VPLL		78
+#define		ZYNQMP_RESET_IOPLL		79
+#define		ZYNQMP_RESET_RPLL		80
+#define		ZYNQMP_RESET_GPO3_PL_0		81
+#define		ZYNQMP_RESET_GPO3_PL_1		82
+#define		ZYNQMP_RESET_GPO3_PL_2		83
+#define		ZYNQMP_RESET_GPO3_PL_3		84
+#define		ZYNQMP_RESET_GPO3_PL_4		85
+#define		ZYNQMP_RESET_GPO3_PL_5		86
+#define		ZYNQMP_RESET_GPO3_PL_6		87
+#define		ZYNQMP_RESET_GPO3_PL_7		88
+#define		ZYNQMP_RESET_GPO3_PL_8		89
+#define		ZYNQMP_RESET_GPO3_PL_9		90
+#define		ZYNQMP_RESET_GPO3_PL_10		91
+#define		ZYNQMP_RESET_GPO3_PL_11		92
+#define		ZYNQMP_RESET_GPO3_PL_12		93
+#define		ZYNQMP_RESET_GPO3_PL_13		94
+#define		ZYNQMP_RESET_GPO3_PL_14		95
+#define		ZYNQMP_RESET_GPO3_PL_15		96
+#define		ZYNQMP_RESET_GPO3_PL_16		97
+#define		ZYNQMP_RESET_GPO3_PL_17		98
+#define		ZYNQMP_RESET_GPO3_PL_18		99
+#define		ZYNQMP_RESET_GPO3_PL_19		100
+#define		ZNQMP_RESET_GPO3_PL_20		101
+#define		ZYNQMP_RESET_GPO3_PL_21		102
+#define		ZYNQMP_RESET_GPO3_PL_22		103
+#define		ZYNQMP_RESET_GPO3_PL_23		104
+#define		ZYNQMP_RESET_GPO3_PL_24		105
+#define		ZYNQMP_RESET_GPO3_PL_25		106
+#define		ZYNQMP_RESET_GPO3_PL_26		107
+#define		ZYNQMP_RESET_GPO3_PL_27		108
+#define		ZYNQMP_RESET_GPO3_PL_28		109
+#define		ZYNQMP_RESET_GPO3_PL_29		110
+#define		ZYNQMP_RESET_GPO3_PL_30		111
+#define		ZYNQMP_RESET_GPO3_PL_31		112
+#define		ZYNQMP_RESET_RPU_LS		113
+#define		ZYNQMP_RESET_PS_ONLY		114
+#define		ZYNQMP_RESET_PL			115
+#define		ZYNQMP_RESET_PS_PL0		116
+#define		ZYNQMP_RESET_PS_PL1		117
+#define		ZYNQMP_RESET_PS_PL2		118
+#define		ZYNQMP_RESET_PS_PL3		119
+
+#endif
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne, Jolly Shah

Add documentation to describe Xilinx ZynqMP reset driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
---
Changes for v3:
		-Moved reset outputs definitions info into
		 a header file(xlnx-zynqmp-resets.h).

 .../bindings/reset/xlnx,zynqmp-reset.txt      |  52 +++++++
 .../dt-bindings/reset/xlnx-zynqmp-resets.h    | 130 ++++++++++++++++++
 2 files changed, 182 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
 create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h

diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index 000000000000..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--------------------------------------------------------------------------
+ =  Zynq UltraScale+ MPSoC reset driver binding =
+--------------------------------------------------------------------------
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible:	"xlnx,zynqmp-reset"
+- #reset-cells:	Specifies the number of cells needed to encode reset
+		line, should be 1
+
+-------
+Example
+-------
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		zynqmp_reset: reset-controller {
+			compatible = "xlnx,zynqmp-reset";
+			#reset-cells = <1>;
+		};
+	};
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+<dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+Example:
+
+serdes: zynqmp_phy@fd400000 {
+	...
+
+	resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
+	reset-names = "sata_rst";
+
+	...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index 000000000000..e295fd5d824e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#define		ZYNQMP_RESET_PCIE_CFG		0
+#define		ZYNQMP_RESET_PCIE_BRIDGE	1
+#define		ZYNQMP_RESET_PCIE_CTRL		2
+#define		ZYNQMP_RESET_DP			3
+#define		ZYNQMP_RESET_SWDT_CRF		4
+#define		ZYNQMP_RESET_AFI_FM5		5
+#define		ZYNQMP_RESET_AFI_FM4		6
+#define		ZYNQMP_RESET_AFI_FM3		7
+#define		ZYNQMP_RESET_AFI_FM2		8
+#define		ZYNQMP_RESET_AFI_FM1		9
+#define		ZYNQMP_RESET_AFI_FM0		10
+#define		ZYNQMP_RESET_GDMA		11
+#define		ZYNQMP_RESET_GPU_PP1		12
+#define		ZYNQMP_RESET_GPU_PP0		13
+#define		ZYNQMP_RESET_GPU		14
+#define		ZYNQMP_RESET_GT			15
+#define		ZYNQMP_RESET_SATA		16
+#define		ZYNQMP_RESET_ACPU3_PWRON	17
+#define		ZYNQMP_RESET_ACPU2_PWRON	18
+#define		ZYNQMP_RESET_ACPU1_PWRON	19
+#define		ZYNQMP_RESET_ACPU0_PWRON	20
+#define		ZYNQMP_RESET_APU_L2		21
+#define		ZYNQMP_RESET_ACPU3		22
+#define		ZYNQMP_RESET_ACPU2		23
+#define		ZYNQMP_RESET_ACPU1		24
+#define		ZYNQMP_RESET_ACPU0		25
+#define		ZYNQMP_RESET_DDR		26
+#define		ZYNQMP_RESET_APM_FPD		27
+#define		ZYNQMP_RESET_SOFT		28
+#define		ZYNQMP_RESET_GEM0		29
+#define		ZYNQMP_RESET_GEM1		30
+#define		ZYNQMP_RESET_GEM2		31
+#define		ZYNQMP_RESET_GEM3		32
+#define		ZYNQMP_RESET_QSPI		33
+#define		ZYNQMP_RESET_UART0		34
+#define		ZYNQMP_RESET_UART1		35
+#define		ZYNQMP_RESET_SPI0		36
+#define		ZYNQMP_RESET_SPI1		37
+#define		ZYNQMP_RESET_SDIO0		38
+#define		ZYNQMP_RESET_SDIO1		39
+#define		ZYNQMP_RESET_CAN0		40
+#define		ZYNQMP_RESET_CAN1		41
+#define		ZYNQMP_RESET_I2C0		42
+#define		ZYNQMP_RESET_I2C1		43
+#define		ZYNQMP_RESET_TTC0		44
+#define		ZYNQMP_RESET_TTC1		45
+#define		ZYNQMP_RESET_TTC2		46
+#define		ZYNQMP_RESET_TTC3		47
+#define		ZYNQMP_RESET_SWDT_CRL		48
+#define		ZYNQMP_RESET_NAND		49
+#define		ZYNQMP_RESET_ADMA		50
+#define		ZYNQMP_RESET_GPIO		51
+#define		ZYNQMP_RESET_IOU_CC		52
+#define		ZYNQMP_RESET_TIMESTAMP		53
+#define		ZYNQMP_RESET_RPU_R50		54
+#define		ZYNQMP_RESET_RPU_R51		55
+#define		ZYNQMP_RESET_RPU_AMBA		56
+#define		ZYNQMP_RESET_OCM		57
+#define		ZYNQMP_RESET_RPU_PGE		58
+#define		ZYNQMP_RESET_USB0_CORERESET	59
+#define		ZYNQMP_RESET_USB1_CORERESET	60
+#define		ZYNQMP_RESET_USB0_HIBERRESET	61
+#define		ZYNQMP_RESET_USB1_HIBERRESET	62
+#define		ZYNQMP_RESET_USB0_APB		63
+#define		ZYNQMP_RESET_USB1_APB		64
+#define		ZYNQMP_RESET_IPI		65
+#define		ZYNQMP_RESET_APM_LPD		66
+#define		ZYNQMP_RESET_RTC		67
+#define		ZYNQMP_RESET_SYSMON		68
+#define		ZYNQMP_RESET_AFI_FM6		69
+#define		ZYNQMP_RESET_LPD_SWDT		70
+#define		ZYNQMP_RESET_FPD		71
+#define		ZYNQMP_RESET_RPU_DBG1		72
+#define		ZYNQMP_RESET_RPU_DBG0		73
+#define		ZYNQMP_RESET_DBG_LPD		74
+#define		ZYNQMP_RESET_DBG_FPD		75
+#define		ZYNQMP_RESET_APLL		76
+#define		ZYNQMP_RESET_DPLL		77
+#define		ZYNQMP_RESET_VPLL		78
+#define		ZYNQMP_RESET_IOPLL		79
+#define		ZYNQMP_RESET_RPLL		80
+#define		ZYNQMP_RESET_GPO3_PL_0		81
+#define		ZYNQMP_RESET_GPO3_PL_1		82
+#define		ZYNQMP_RESET_GPO3_PL_2		83
+#define		ZYNQMP_RESET_GPO3_PL_3		84
+#define		ZYNQMP_RESET_GPO3_PL_4		85
+#define		ZYNQMP_RESET_GPO3_PL_5		86
+#define		ZYNQMP_RESET_GPO3_PL_6		87
+#define		ZYNQMP_RESET_GPO3_PL_7		88
+#define		ZYNQMP_RESET_GPO3_PL_8		89
+#define		ZYNQMP_RESET_GPO3_PL_9		90
+#define		ZYNQMP_RESET_GPO3_PL_10		91
+#define		ZYNQMP_RESET_GPO3_PL_11		92
+#define		ZYNQMP_RESET_GPO3_PL_12		93
+#define		ZYNQMP_RESET_GPO3_PL_13		94
+#define		ZYNQMP_RESET_GPO3_PL_14		95
+#define		ZYNQMP_RESET_GPO3_PL_15		96
+#define		ZYNQMP_RESET_GPO3_PL_16		97
+#define		ZYNQMP_RESET_GPO3_PL_17		98
+#define		ZYNQMP_RESET_GPO3_PL_18		99
+#define		ZYNQMP_RESET_GPO3_PL_19		100
+#define		ZNQMP_RESET_GPO3_PL_20		101
+#define		ZYNQMP_RESET_GPO3_PL_21		102
+#define		ZYNQMP_RESET_GPO3_PL_22		103
+#define		ZYNQMP_RESET_GPO3_PL_23		104
+#define		ZYNQMP_RESET_GPO3_PL_24		105
+#define		ZYNQMP_RESET_GPO3_PL_25		106
+#define		ZYNQMP_RESET_GPO3_PL_26		107
+#define		ZYNQMP_RESET_GPO3_PL_27		108
+#define		ZYNQMP_RESET_GPO3_PL_28		109
+#define		ZYNQMP_RESET_GPO3_PL_29		110
+#define		ZYNQMP_RESET_GPO3_PL_30		111
+#define		ZYNQMP_RESET_GPO3_PL_31		112
+#define		ZYNQMP_RESET_RPU_LS		113
+#define		ZYNQMP_RESET_PS_ONLY		114
+#define		ZYNQMP_RESET_PL			115
+#define		ZYNQMP_RESET_PS_PL0		116
+#define		ZYNQMP_RESET_PS_PL1		117
+#define		ZYNQMP_RESET_PS_PL2		118
+#define		ZYNQMP_RESET_PS_PL3		119
+
+#endif
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP pin controller
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 1 file changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
new file mode 100644
index 000000000000..acf44a5d3778
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
@@ -0,0 +1,275 @@
+	Binding for Xilinx ZynqMP Pinctrl
+
+Required properties:
+- compatible: "xlnx,zynqmp-pinctrl"
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+ZynqMP's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, slew rate, etc.
+
+Each configuration node can consist of multiple nodes describing the pinmux and
+pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required properties for pinmux nodes are:
+ - groups: A list of pinmux groups.
+ - function: The name of a pinmux function to activate for the specified set
+   of groups.
+
+Required properties for configuration nodes:
+One of:
+ - pins: A list of pin names
+ - groups: A list of pinmux groups.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinmux subnode:
+ groups, function
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinconf subnode:
+ groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate
+
+ Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to
+ select between slow and fast respectively.
+
+ Valid values for groups are:
+ ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
+ ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
+ gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
+ mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
+ qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
+ spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
+ spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
+ spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
+ spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
+ spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
+ spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
+ spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
+ spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
+ spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
+ spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
+ spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
+ spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
+ spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
+ spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
+ spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
+ spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
+ sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
+ sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
+ sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
+ sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
+ sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
+ sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
+ sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
+ sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
+ sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
+ sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
+ sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
+ sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
+ sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
+ sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
+ sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
+ sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
+ sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
+ sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
+ sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
+ sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
+ sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
+ sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
+ nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
+ nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
+ can0_1_grp, can0_2_grp, can0_3_grp,
+ can0_4_grp, can0_5_grp, can0_6_grp,
+ can0_7_grp, can0_8_grp, can0_9_grp,
+ can0_10_grp, can0_11_grp, can0_12_grp,
+ can0_13_grp, can0_14_grp, can0_15_grp,
+ can0_16_grp, can0_17_grp, can0_18_grp,
+ can1_0_grp, can1_1_grp, can1_2_grp,
+ can1_3_grp, can1_4_grp, can1_5_grp,
+ can1_6_grp, can1_7_grp, can1_8_grp,
+ can1_9_grp, can1_10_grp, can1_11_grp,
+ can1_12_grp, can1_13_grp, can1_14_grp,
+ can1_15_grp, can1_16_grp, can1_17_grp,
+ can1_18_grp, can1_19_grp, uart0_0_grp,
+ uart0_1_grp, uart0_2_grp, uart0_3_grp,
+ uart0_4_grp, uart0_5_grp, uart0_6_grp,
+ uart0_7_grp, uart0_8_grp, uart0_9_grp,
+ uart0_10_grp, uart0_11_grp, uart0_12_grp,
+ uart0_13_grp, uart0_14_grp, uart0_15_grp,
+ uart0_16_grp, uart0_17_grp, uart0_18_grp,
+ uart1_0_grp, uart1_1_grp, uart1_2_grp,
+ uart1_3_grp, uart1_4_grp, uart1_5_grp,
+ uart1_6_grp, uart1_7_grp, uart1_8_grp,
+ uart1_9_grp, uart1_10_grp, uart1_11_grp,
+ uart1_12_grp, uart1_13_grp, uart1_14_grp,
+ uart1_15_grp, uart1_16_grp, uart1_17_grp,
+ uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
+ i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
+ i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
+ i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
+ i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
+ i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
+ i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
+ i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
+ i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
+ i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
+ i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
+ i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
+ i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
+ i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
+ ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
+ ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
+ ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
+ ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
+ ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
+ ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
+ ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
+ ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
+ ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
+ ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
+ ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
+ ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
+ ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
+ ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
+ ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
+ ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
+ ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
+ ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
+ ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
+ ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
+ ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
+ ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
+ ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
+ ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
+ swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
+ swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
+ swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
+ swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
+ swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
+ swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
+ swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
+ swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
+ swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
+ swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
+ swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
+ swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
+ swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
+ swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
+ swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
+ swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
+ swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
+ gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
+ gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
+ gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
+ gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
+ gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
+ gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
+ gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
+ gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
+ gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
+ gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
+ gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
+ gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
+ gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
+ gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
+ gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
+ gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
+ gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
+ gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
+ gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
+ gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
+ gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
+ gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
+ gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
+ gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
+ gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
+ gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
+ usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
+ pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
+ pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
+ pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
+ pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
+ pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
+ pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
+ csu0_0_grp, csu0_1_grp, csu0_2_grp,
+ csu0_3_grp, csu0_4_grp, csu0_5_grp,
+ csu0_6_grp, csu0_7_grp, csu0_8_grp,
+ csu0_9_grp, csu0_10_grp, csu0_11_grp,
+ dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
+ dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
+ pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
+ pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
+ trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
+ trace0_clk_2_grp, testscan0_0_grp
+
+ Valid values for pins are:
+   MIO0 - MIO77
+
+ Valid values for function are:
+   ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
+   mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
+   spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
+   sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
+   i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
+   ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
+   pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0
+
+The following driver-specific properties as defined here are valid to specify in
+a pin configuration subnode:
+ - io-standard: Configure the pin to use the selected IO standard. Valid
+   arguments are 'IO_STANDARD_LVCMOS33' and 'IO_STANDARD_LVCMOS18'.
+ - schmitt-cmos: Selects either Schmitt or CMOS input for MIO pins. Valid
+   arguments are 'PIN_INPUT_TYPE_SCHMITT' and 'PIN_INPUT_TYPE_CMOS'.
+
+Example:
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		pinctrl0: pinctrl@ff180000 {
+			compatible = "xlnx,zynqmp-pinctrl";
+
+			pinctrl_uart1_default: uart1-default {
+				mux {
+					groups = "uart0_4_grp";
+					function = "uart0";
+				};
+
+				conf {
+					groups = "uart0_4_grp";
+					slew-rate = <SLEW_RATE_SLOW>;
+					io-standard = <IO_STANDARD_LVCMOS18>;
+				};
+
+				conf-rx {
+					pins = "MIO18";
+					bias-high-impedance;
+				};
+
+				conf-tx {
+					pins = "MIO19";
+					bias-disable;
+					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
+				};
+			};
+		};
+	};
+};
+
+uart1 {
+	...
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_default>;
+	...
+
+};
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Rajan Vaja, Jolly Shah

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP pin controller
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 1 file changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
new file mode 100644
index 000000000000..acf44a5d3778
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
@@ -0,0 +1,275 @@
+	Binding for Xilinx ZynqMP Pinctrl
+
+Required properties:
+- compatible: "xlnx,zynqmp-pinctrl"
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+ZynqMP's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, slew rate, etc.
+
+Each configuration node can consist of multiple nodes describing the pinmux and
+pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required properties for pinmux nodes are:
+ - groups: A list of pinmux groups.
+ - function: The name of a pinmux function to activate for the specified set
+   of groups.
+
+Required properties for configuration nodes:
+One of:
+ - pins: A list of pin names
+ - groups: A list of pinmux groups.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinmux subnode:
+ groups, function
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinconf subnode:
+ groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate
+
+ Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to
+ select between slow and fast respectively.
+
+ Valid values for groups are:
+ ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
+ ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
+ gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
+ mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
+ qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
+ spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
+ spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
+ spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
+ spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
+ spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
+ spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
+ spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
+ spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
+ spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
+ spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
+ spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
+ spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
+ spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
+ spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
+ spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
+ spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
+ sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
+ sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
+ sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
+ sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
+ sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
+ sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
+ sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
+ sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
+ sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
+ sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
+ sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
+ sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
+ sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
+ sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
+ sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
+ sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
+ sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
+ sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
+ sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
+ sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
+ sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
+ sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
+ nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
+ nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
+ can0_1_grp, can0_2_grp, can0_3_grp,
+ can0_4_grp, can0_5_grp, can0_6_grp,
+ can0_7_grp, can0_8_grp, can0_9_grp,
+ can0_10_grp, can0_11_grp, can0_12_grp,
+ can0_13_grp, can0_14_grp, can0_15_grp,
+ can0_16_grp, can0_17_grp, can0_18_grp,
+ can1_0_grp, can1_1_grp, can1_2_grp,
+ can1_3_grp, can1_4_grp, can1_5_grp,
+ can1_6_grp, can1_7_grp, can1_8_grp,
+ can1_9_grp, can1_10_grp, can1_11_grp,
+ can1_12_grp, can1_13_grp, can1_14_grp,
+ can1_15_grp, can1_16_grp, can1_17_grp,
+ can1_18_grp, can1_19_grp, uart0_0_grp,
+ uart0_1_grp, uart0_2_grp, uart0_3_grp,
+ uart0_4_grp, uart0_5_grp, uart0_6_grp,
+ uart0_7_grp, uart0_8_grp, uart0_9_grp,
+ uart0_10_grp, uart0_11_grp, uart0_12_grp,
+ uart0_13_grp, uart0_14_grp, uart0_15_grp,
+ uart0_16_grp, uart0_17_grp, uart0_18_grp,
+ uart1_0_grp, uart1_1_grp, uart1_2_grp,
+ uart1_3_grp, uart1_4_grp, uart1_5_grp,
+ uart1_6_grp, uart1_7_grp, uart1_8_grp,
+ uart1_9_grp, uart1_10_grp, uart1_11_grp,
+ uart1_12_grp, uart1_13_grp, uart1_14_grp,
+ uart1_15_grp, uart1_16_grp, uart1_17_grp,
+ uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
+ i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
+ i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
+ i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
+ i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
+ i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
+ i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
+ i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
+ i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
+ i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
+ i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
+ i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
+ i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
+ i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
+ ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
+ ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
+ ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
+ ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
+ ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
+ ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
+ ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
+ ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
+ ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
+ ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
+ ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
+ ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
+ ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
+ ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
+ ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
+ ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
+ ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
+ ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
+ ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
+ ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
+ ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
+ ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
+ ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
+ ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
+ swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
+ swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
+ swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
+ swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
+ swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
+ swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
+ swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
+ swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
+ swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
+ swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
+ swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
+ swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
+ swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
+ swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
+ swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
+ swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
+ swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
+ gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
+ gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
+ gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
+ gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
+ gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
+ gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
+ gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
+ gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
+ gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
+ gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
+ gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
+ gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
+ gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
+ gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
+ gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
+ gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
+ gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
+ gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
+ gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
+ gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
+ gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
+ gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
+ gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
+ gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
+ gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
+ gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
+ usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
+ pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
+ pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
+ pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
+ pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
+ pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
+ pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
+ csu0_0_grp, csu0_1_grp, csu0_2_grp,
+ csu0_3_grp, csu0_4_grp, csu0_5_grp,
+ csu0_6_grp, csu0_7_grp, csu0_8_grp,
+ csu0_9_grp, csu0_10_grp, csu0_11_grp,
+ dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
+ dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
+ pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
+ pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
+ trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
+ trace0_clk_2_grp, testscan0_0_grp
+
+ Valid values for pins are:
+   MIO0 - MIO77
+
+ Valid values for function are:
+   ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
+   mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
+   spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
+   sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
+   i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
+   ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
+   pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0
+
+The following driver-specific properties as defined here are valid to specify in
+a pin configuration subnode:
+ - io-standard: Configure the pin to use the selected IO standard. Valid
+   arguments are 'IO_STANDARD_LVCMOS33' and 'IO_STANDARD_LVCMOS18'.
+ - schmitt-cmos: Selects either Schmitt or CMOS input for MIO pins. Valid
+   arguments are 'PIN_INPUT_TYPE_SCHMITT' and 'PIN_INPUT_TYPE_CMOS'.
+
+Example:
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		pinctrl0: pinctrl@ff180000 {
+			compatible = "xlnx,zynqmp-pinctrl";
+
+			pinctrl_uart1_default: uart1-default {
+				mux {
+					groups = "uart0_4_grp";
+					function = "uart0";
+				};
+
+				conf {
+					groups = "uart0_4_grp";
+					slew-rate = <SLEW_RATE_SLOW>;
+					io-standard = <IO_STANDARD_LVCMOS18>;
+				};
+
+				conf-rx {
+					pins = "MIO18";
+					bias-high-impedance;
+				};
+
+				conf-tx {
+					pins = "MIO19";
+					bias-disable;
+					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
+				};
+			};
+		};
+	};
+};
+
+uart1 {
+	...
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_default>;
+	...
+
+};
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Jolly Shah, Rajan Vaja

From: Rajan Vaja <rajan.vaja@xilinx.com>

Add documentation to describe Xilinx ZynqMP pin controller
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v3:
		-None.

 .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt  | 275 ++++++++++++++++++
 1 file changed, 275 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
new file mode 100644
index 000000000000..acf44a5d3778
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
@@ -0,0 +1,275 @@
+	Binding for Xilinx ZynqMP Pinctrl
+
+Required properties:
+- compatible: "xlnx,zynqmp-pinctrl"
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+ZynqMP's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, slew rate, etc.
+
+Each configuration node can consist of multiple nodes describing the pinmux and
+pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required properties for pinmux nodes are:
+ - groups: A list of pinmux groups.
+ - function: The name of a pinmux function to activate for the specified set
+   of groups.
+
+Required properties for configuration nodes:
+One of:
+ - pins: A list of pin names
+ - groups: A list of pinmux groups.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinmux subnode:
+ groups, function
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pinconf subnode:
+ groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate
+
+ Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to
+ select between slow and fast respectively.
+
+ Valid values for groups are:
+ ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
+ ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
+ gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
+ mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
+ qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
+ spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
+ spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
+ spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
+ spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
+ spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
+ spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
+ spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
+ spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
+ spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
+ spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
+ spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
+ spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
+ spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
+ spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
+ spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
+ spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
+ sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
+ sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
+ sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
+ sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
+ sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
+ sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
+ sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
+ sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
+ sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
+ sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
+ sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
+ sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
+ sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
+ sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
+ sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
+ sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
+ sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
+ sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
+ sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
+ sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
+ sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
+ sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
+ nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
+ nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
+ can0_1_grp, can0_2_grp, can0_3_grp,
+ can0_4_grp, can0_5_grp, can0_6_grp,
+ can0_7_grp, can0_8_grp, can0_9_grp,
+ can0_10_grp, can0_11_grp, can0_12_grp,
+ can0_13_grp, can0_14_grp, can0_15_grp,
+ can0_16_grp, can0_17_grp, can0_18_grp,
+ can1_0_grp, can1_1_grp, can1_2_grp,
+ can1_3_grp, can1_4_grp, can1_5_grp,
+ can1_6_grp, can1_7_grp, can1_8_grp,
+ can1_9_grp, can1_10_grp, can1_11_grp,
+ can1_12_grp, can1_13_grp, can1_14_grp,
+ can1_15_grp, can1_16_grp, can1_17_grp,
+ can1_18_grp, can1_19_grp, uart0_0_grp,
+ uart0_1_grp, uart0_2_grp, uart0_3_grp,
+ uart0_4_grp, uart0_5_grp, uart0_6_grp,
+ uart0_7_grp, uart0_8_grp, uart0_9_grp,
+ uart0_10_grp, uart0_11_grp, uart0_12_grp,
+ uart0_13_grp, uart0_14_grp, uart0_15_grp,
+ uart0_16_grp, uart0_17_grp, uart0_18_grp,
+ uart1_0_grp, uart1_1_grp, uart1_2_grp,
+ uart1_3_grp, uart1_4_grp, uart1_5_grp,
+ uart1_6_grp, uart1_7_grp, uart1_8_grp,
+ uart1_9_grp, uart1_10_grp, uart1_11_grp,
+ uart1_12_grp, uart1_13_grp, uart1_14_grp,
+ uart1_15_grp, uart1_16_grp, uart1_17_grp,
+ uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
+ i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
+ i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
+ i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
+ i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
+ i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
+ i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
+ i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
+ i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
+ i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
+ i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
+ i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
+ i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
+ i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
+ ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
+ ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
+ ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
+ ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
+ ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
+ ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
+ ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
+ ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
+ ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
+ ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
+ ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
+ ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
+ ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
+ ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
+ ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
+ ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
+ ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
+ ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
+ ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
+ ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
+ ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
+ ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
+ ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
+ ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
+ swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
+ swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
+ swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
+ swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
+ swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
+ swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
+ swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
+ swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
+ swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
+ swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
+ swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
+ swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
+ swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
+ swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
+ swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
+ swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
+ swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
+ gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
+ gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
+ gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
+ gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
+ gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
+ gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
+ gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
+ gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
+ gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
+ gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
+ gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
+ gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
+ gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
+ gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
+ gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
+ gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
+ gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
+ gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
+ gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
+ gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
+ gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
+ gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
+ gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
+ gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
+ gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
+ gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
+ usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
+ pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
+ pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
+ pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
+ pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
+ pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
+ pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
+ csu0_0_grp, csu0_1_grp, csu0_2_grp,
+ csu0_3_grp, csu0_4_grp, csu0_5_grp,
+ csu0_6_grp, csu0_7_grp, csu0_8_grp,
+ csu0_9_grp, csu0_10_grp, csu0_11_grp,
+ dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
+ dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
+ pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
+ pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
+ trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
+ trace0_clk_2_grp, testscan0_0_grp
+
+ Valid values for pins are:
+   MIO0 - MIO77
+
+ Valid values for function are:
+   ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
+   mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
+   spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
+   sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
+   i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
+   ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
+   pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0
+
+The following driver-specific properties as defined here are valid to specify in
+a pin configuration subnode:
+ - io-standard: Configure the pin to use the selected IO standard. Valid
+   arguments are 'IO_STANDARD_LVCMOS33' and 'IO_STANDARD_LVCMOS18'.
+ - schmitt-cmos: Selects either Schmitt or CMOS input for MIO pins. Valid
+   arguments are 'PIN_INPUT_TYPE_SCHMITT' and 'PIN_INPUT_TYPE_CMOS'.
+
+Example:
+
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		pinctrl0: pinctrl@ff180000 {
+			compatible = "xlnx,zynqmp-pinctrl";
+
+			pinctrl_uart1_default: uart1-default {
+				mux {
+					groups = "uart0_4_grp";
+					function = "uart0";
+				};
+
+				conf {
+					groups = "uart0_4_grp";
+					slew-rate = <SLEW_RATE_SLOW>;
+					io-standard = <IO_STANDARD_LVCMOS18>;
+				};
+
+				conf-rx {
+					pins = "MIO18";
+					bias-high-impedance;
+				};
+
+				conf-tx {
+					pins = "MIO19";
+					bias-disable;
+					schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
+				};
+			};
+		};
+	};
+};
+
+uart1 {
+	...
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_default>;
+	...
+
+};
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Added nvmem node as child of FW. Since nvmem driver is a provider.
  
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt

diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index 000000000000..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--------------------------------------------------------------------------
+=  Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+-------
+ Example
+-------
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		nvmem_firmware {
+			compatible = "xlnx,zynqmp-nvmem-fw";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Data cells */
+			soc_revision: soc_revision {
+				reg = <0x0 0x4>;
+			};
+		};
+	};
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+	pcap {
+		...
+
+		nvmem-cells = <&soc_revision>;
+		nvmem-cell-names = "soc_revision";
+
+		...
+	};
+
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Added nvmem node as child of FW. Since nvmem driver is a provider.
  
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt

diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index 000000000000..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--------------------------------------------------------------------------
+=  Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+-------
+ Example
+-------
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		nvmem_firmware {
+			compatible = "xlnx,zynqmp-nvmem-fw";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Data cells */
+			soc_revision: soc_revision {
+				reg = <0x0 0x4>;
+			};
+		};
+	};
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+	pcap {
+		...
+
+		nvmem-cells = <&soc_revision>;
+		nvmem-cell-names = "soc_revision";
+
+		...
+	};
+
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Added nvmem node as child of FW. Since nvmem driver is a provider.
  
 .../bindings/nvmem/xlnx,zynqmp-nvmem.txt      | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt

diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index 000000000000..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--------------------------------------------------------------------------
+=  Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+-------
+ Example
+-------
+firmware {
+	zynqmp_firmware: zynqmp-firmware {
+		compatible = "xlnx,zynqmp-firmware";
+		method = "smc";
+
+		nvmem_firmware {
+			compatible = "xlnx,zynqmp-nvmem-fw";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Data cells */
+			soc_revision: soc_revision {
+				reg = <0x0 0x4>;
+			};
+		};
+	};
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+	pcap {
+		...
+
+		nvmem-cells = <&soc_revision>;
+		nvmem-cell-names = "soc_revision";
+
+		...
+	};
+
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-01-21 17:38 ` Nava kishore Manne
  (?)
@ 2019-01-21 17:38   ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-01-21 17:38   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:38 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369, robh+dt
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-01-21 15:49     ` Rob Herring
  (?)
@ 2019-01-22  9:13     ` Nava kishore Manne
  2019-02-22 20:30         ` Rob Herring
  -1 siblings, 1 reply; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-22  9:13 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

[-- Attachment #1: Type: text/plain, Size: 2537 bytes --]

Hi Rob,



Thanks for providing the comments...



> -----Original Message-----

> From: Rob Herring [mailto:robh@kernel.org]

> Sent: Monday, January 21, 2019 9:19 PM

> To: Nava kishore Manne <navam@xilinx.com>

> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja

> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-

> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah

> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com

> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga

> driver

>

> On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:

> > Add documentation to describe Xilinx ZynqMP fpga driver bindings.

> >

> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com<mailto:nava.manne@xilinx.com>>

> > ---

> > Changes for v3:

> >                         -Removed PCAP as a child node to the FW and Created

> >                         an independent node since PCAP driver is a consumer

> >                         not a provider.

> >

> >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++

> >  1 file changed, 13 insertions(+)

> >  create mode 100644

> > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

> >

> > diff --git

> > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

> > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

> > new file mode 100644

> > index 000000000000..1f6f58872311

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

> > @@ -0,0 +1,13 @@

> > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC

> > +controlled using ZynqMP SoC firmware interface For Bitstream

> > +configuration on ZynqMp Soc uses processor configuration

> > +port(PCAP) to configure the programmable logic(PL) through PS by

> > +using FW interface.

> > +

> > +Required properties:

> > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"

> > +

> > +Example:

> > +      zynqmp_pcap: pcap {

> > +                     compatible = "xlnx,zynqmp-pcap-fpga";

> > +      };

>

> There's no need for a DT node. Just make the firware driver create a platform

> device for pcap.

>



This driver being used by the FPGA manager framework(fpga-region) to apply overlay's so this node is needed AFAIK.

Please correct me if I am wrong...



Regards,

Navakishore.

[-- Attachment #2: Type: text/html, Size: 7451 bytes --]

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-01-22  9:13     ` Nava kishore Manne
  2019-02-22 20:30         ` Rob Herring
@ 2019-02-22 20:30         ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-02-22 20:30 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>
>
> Thanks for providing the comments...

Please fix your mailer to send plain text emails to mail lists.


> > -----Original Message-----
>
> > From: Rob Herring [mailto:robh@kernel.org]
>
> > Sent: Monday, January 21, 2019 9:19 PM
>
> > To: Nava kishore Manne <navam@xilinx.com>
>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
>
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
>
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
>
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
>
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
>
> > driver
>
> >
>
> > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
>
> > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
>
> > >
>
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
>
> > > ---
>
> > > Changes for v3:
>
> > >                         -Removed PCAP as a child node to the FW and Created
>
> > >                         an independent node since PCAP driver is a consumer
>
> > >                         not a provider.
>
> > >
>
> > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
>
> > >  1 file changed, 13 insertions(+)
>
> > >  create mode 100644
>
> > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > >
>
> > > diff --git
>
> > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > new file mode 100644
>
> > > index 000000000000..1f6f58872311
>
> > > --- /dev/null
>
> > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > @@ -0,0 +1,13 @@
>
> > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
>
> > > +controlled using ZynqMP SoC firmware interface For Bitstream
>
> > > +configuration on ZynqMp Soc uses processor configuration
>
> > > +port(PCAP) to configure the programmable logic(PL) through PS by
>
> > > +using FW interface.
>
> > > +
>
> > > +Required properties:
>
> > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
>
> > > +
>
> > > +Example:
>
> > > +      zynqmp_pcap: pcap {
>
> > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
>
> > > +      };
>
> >
>
> > There's no need for a DT node. Just make the firware driver create a platform
>
> > device for pcap.
>
> >
>
>
>
> This driver being used by the FPGA manager framework(fpga-region) to apply overlay's so this node is needed AFAIK.

The binding says nothing about child nodes and what they are. Please
define that.

Rob

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-02-22 20:30         ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-02-22 20:30 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>
>
> Thanks for providing the comments...

Please fix your mailer to send plain text emails to mail lists.


> > -----Original Message-----
>
> > From: Rob Herring [mailto:robh@kernel.org]
>
> > Sent: Monday, January 21, 2019 9:19 PM
>
> > To: Nava kishore Manne <navam@xilinx.com>
>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
>
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
>
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
>
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
>
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
>
> > driver
>
> >
>
> > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
>
> > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
>
> > >
>
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
>
> > > ---
>
> > > Changes for v3:
>
> > >                         -Removed PCAP as a child node to the FW and Created
>
> > >                         an independent node since PCAP driver is a consumer
>
> > >                         not a provider.
>
> > >
>
> > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
>
> > >  1 file changed, 13 insertions(+)
>
> > >  create mode 100644
>
> > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > >
>
> > > diff --git
>
> > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > new file mode 100644
>
> > > index 000000000000..1f6f58872311
>
> > > --- /dev/null
>
> > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > @@ -0,0 +1,13 @@
>
> > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
>
> > > +controlled using ZynqMP SoC firmware interface For Bitstream
>
> > > +configuration on ZynqMp Soc uses processor configuration
>
> > > +port(PCAP) to configure the programmable logic(PL) through PS by
>
> > > +using FW interface.
>
> > > +
>
> > > +Required properties:
>
> > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
>
> > > +
>
> > > +Example:
>
> > > +      zynqmp_pcap: pcap {
>
> > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
>
> > > +      };
>
> >
>
> > There's no need for a DT node. Just make the firware driver create a platform
>
> > device for pcap.
>
> >
>
>
>
> This driver being used by the FPGA manager framework(fpga-region) to apply overlay's so this node is needed AFAIK.

The binding says nothing about child nodes and what they are. Please
define that.

Rob

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-02-22 20:30         ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-02-22 20:30 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, linux-kernel, Jolly Shah, Rajan Vaja,
	Michal Simek, linux-arm-kernel, chinnikishore369

On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>
>
> Thanks for providing the comments...

Please fix your mailer to send plain text emails to mail lists.


> > -----Original Message-----
>
> > From: Rob Herring [mailto:robh@kernel.org]
>
> > Sent: Monday, January 21, 2019 9:19 PM
>
> > To: Nava kishore Manne <navam@xilinx.com>
>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
>
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
>
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
>
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
>
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
>
> > driver
>
> >
>
> > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
>
> > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
>
> > >
>
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
>
> > > ---
>
> > > Changes for v3:
>
> > >                         -Removed PCAP as a child node to the FW and Created
>
> > >                         an independent node since PCAP driver is a consumer
>
> > >                         not a provider.
>
> > >
>
> > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
>
> > >  1 file changed, 13 insertions(+)
>
> > >  create mode 100644
>
> > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > >
>
> > > diff --git
>
> > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > new file mode 100644
>
> > > index 000000000000..1f6f58872311
>
> > > --- /dev/null
>
> > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > @@ -0,0 +1,13 @@
>
> > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
>
> > > +controlled using ZynqMP SoC firmware interface For Bitstream
>
> > > +configuration on ZynqMp Soc uses processor configuration
>
> > > +port(PCAP) to configure the programmable logic(PL) through PS by
>
> > > +using FW interface.
>
> > > +
>
> > > +Required properties:
>
> > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
>
> > > +
>
> > > +Example:
>
> > > +      zynqmp_pcap: pcap {
>
> > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
>
> > > +      };
>
> >
>
> > There's no need for a DT node. Just make the firware driver create a platform
>
> > device for pcap.
>
> >
>
>
>
> This driver being used by the FPGA manager framework(fpga-region) to apply overlay's so this node is needed AFAIK.

The binding says nothing about child nodes and what they are. Please
define that.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-02-22 20:30         ` Rob Herring
  (?)
@ 2019-03-04 11:35           ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-04 11:35 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

Hi Rob,

 Thanks for providing the review comments..
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >
> >
> > Thanks for providing the comments...
> 
> Please fix your mailer to send plain text emails to mail lists.
> 
Thanks for pointing it..

> 
> > > -----Original Message-----
> >
> > > From: Rob Herring [mailto:robh@kernel.org]
> >
> > > Sent: Monday, January 21, 2019 9:19 PM
> >
> > > To: Nava kishore Manne <navam@xilinx.com>
> >
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja
> >
> > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> >
> > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> >
> > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> >
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga
> >
> > > driver
> >
> > >
> >
> > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> >
> > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > > >
> >
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> >
> > > > ---
> >
> > > > Changes for v3:
> >
> > > >                         -Removed PCAP as a child node to the FW
> > > > and Created
> >
> > > >                         an independent node since PCAP driver is a
> > > > consumer
> >
> > > >                         not a provider.
> >
> > > >
> >
> > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> >
> > > >  1 file changed, 13 insertions(+)
> >
> > > >  create mode 100644
> >
> > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > >
> >
> > > > diff --git
> >
> > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > new file mode 100644
> >
> > > > index 000000000000..1f6f58872311
> >
> > > > --- /dev/null
> >
> > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > +++ .txt
> >
> > > > @@ -0,0 +1,13 @@
> >
> > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> >
> > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> >
> > > > +configuration on ZynqMp Soc uses processor configuration
> >
> > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> >
> > > > +using FW interface.
> >
> > > > +
> >
> > > > +Required properties:
> >
> > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> >
> > > > +
> >
> > > > +Example:
> >
> > > > +      zynqmp_pcap: pcap {
> >
> > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> >
> > > > +      };
> >
> > >
> >
> > > There's no need for a DT node. Just make the firware driver create a
> > > platform
> >
> > > device for pcap.
> >
> > >
> >
> >
> >
> > This driver being used by the FPGA manager framework(fpga-region) to apply
> overlay's so this node is needed AFAIK.
> 
> The binding says nothing about child nodes and what they are. Please define
> that.
>
Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

Device Tree Example for Full Reconfiguration
============================================

Live Device Tree contains:

        zynqmp_pcap: pcap {
                compatible = "xlnx,zynqmp-pcap-fpga";
        };

        fpga_region0: fpga-region0 {
                compatible = "fpga-region";
                fpga-mgr = <&zynqmp_pcap>;
                #address-cells = <0x1>;
                #size-cells = <0x1>;
                ranges;
        };

DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
        target = <&fpga_region0>;
        #address-cells = <1>;
        #size-cells = <1>;
        __overlay__ {
                #address-cells = <1>;
                #size-cells = <1>;

                firmware-name = "zynqmp-gpio.bin";

                gpio1: gpio@40000000 {
                        compatible = "xlnx,xps-gpio-1.00.a";
                        reg = <0x40000000 0x10000>;
                        gpio-controller;
                        #gpio-cells = <0x2>;
                        xlnx,gpio-width= <0x6>;
                };
        };
};
 
Please correct me if my understanding is wrong.

Regards,
Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-04 11:35           ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-04 11:35 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, linux-kernel, Jolly Shah, Rajan Vaja,
	Michal Simek, linux-arm-kernel, chinnikishore369

Hi Rob,

 Thanks for providing the review comments..
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >
> >
> > Thanks for providing the comments...
> 
> Please fix your mailer to send plain text emails to mail lists.
> 
Thanks for pointing it..

> 
> > > -----Original Message-----
> >
> > > From: Rob Herring [mailto:robh@kernel.org]
> >
> > > Sent: Monday, January 21, 2019 9:19 PM
> >
> > > To: Nava kishore Manne <navam@xilinx.com>
> >
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja
> >
> > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> >
> > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> >
> > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> >
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga
> >
> > > driver
> >
> > >
> >
> > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> >
> > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > > >
> >
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> >
> > > > ---
> >
> > > > Changes for v3:
> >
> > > >                         -Removed PCAP as a child node to the FW
> > > > and Created
> >
> > > >                         an independent node since PCAP driver is a
> > > > consumer
> >
> > > >                         not a provider.
> >
> > > >
> >
> > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> >
> > > >  1 file changed, 13 insertions(+)
> >
> > > >  create mode 100644
> >
> > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > >
> >
> > > > diff --git
> >
> > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > new file mode 100644
> >
> > > > index 000000000000..1f6f58872311
> >
> > > > --- /dev/null
> >
> > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > +++ .txt
> >
> > > > @@ -0,0 +1,13 @@
> >
> > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> >
> > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> >
> > > > +configuration on ZynqMp Soc uses processor configuration
> >
> > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> >
> > > > +using FW interface.
> >
> > > > +
> >
> > > > +Required properties:
> >
> > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> >
> > > > +
> >
> > > > +Example:
> >
> > > > +      zynqmp_pcap: pcap {
> >
> > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> >
> > > > +      };
> >
> > >
> >
> > > There's no need for a DT node. Just make the firware driver create a
> > > platform
> >
> > > device for pcap.
> >
> > >
> >
> >
> >
> > This driver being used by the FPGA manager framework(fpga-region) to apply
> overlay's so this node is needed AFAIK.
> 
> The binding says nothing about child nodes and what they are. Please define
> that.
>
Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

Device Tree Example for Full Reconfiguration
============================================

Live Device Tree contains:

        zynqmp_pcap: pcap {
                compatible = "xlnx,zynqmp-pcap-fpga";
        };

        fpga_region0: fpga-region0 {
                compatible = "fpga-region";
                fpga-mgr = <&zynqmp_pcap>;
                #address-cells = <0x1>;
                #size-cells = <0x1>;
                ranges;
        };

DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
        target = <&fpga_region0>;
        #address-cells = <1>;
        #size-cells = <1>;
        __overlay__ {
                #address-cells = <1>;
                #size-cells = <1>;

                firmware-name = "zynqmp-gpio.bin";

                gpio1: gpio@40000000 {
                        compatible = "xlnx,xps-gpio-1.00.a";
                        reg = <0x40000000 0x10000>;
                        gpio-controller;
                        #gpio-cells = <0x2>;
                        xlnx,gpio-width= <0x6>;
                };
        };
};
 
Please correct me if my understanding is wrong.

Regards,
Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-04 11:35           ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-04 11:35 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, linux-kernel, Jolly Shah, Rajan Vaja,
	Michal Simek, linux-arm-kernel, chinnikishore369

Hi Rob,

 Thanks for providing the review comments..
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >
> >
> > Thanks for providing the comments...
> 
> Please fix your mailer to send plain text emails to mail lists.
> 
Thanks for pointing it..

> 
> > > -----Original Message-----
> >
> > > From: Rob Herring [mailto:robh@kernel.org]
> >
> > > Sent: Monday, January 21, 2019 9:19 PM
> >
> > > To: Nava kishore Manne <navam@xilinx.com>
> >
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja
> >
> > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> >
> > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> >
> > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> >
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga
> >
> > > driver
> >
> > >
> >
> > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> >
> > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > > >
> >
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> >
> > > > ---
> >
> > > > Changes for v3:
> >
> > > >                         -Removed PCAP as a child node to the FW
> > > > and Created
> >
> > > >                         an independent node since PCAP driver is a
> > > > consumer
> >
> > > >                         not a provider.
> >
> > > >
> >
> > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> >
> > > >  1 file changed, 13 insertions(+)
> >
> > > >  create mode 100644
> >
> > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > >
> >
> > > > diff --git
> >
> > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > new file mode 100644
> >
> > > > index 000000000000..1f6f58872311
> >
> > > > --- /dev/null
> >
> > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > +++ .txt
> >
> > > > @@ -0,0 +1,13 @@
> >
> > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> >
> > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> >
> > > > +configuration on ZynqMp Soc uses processor configuration
> >
> > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> >
> > > > +using FW interface.
> >
> > > > +
> >
> > > > +Required properties:
> >
> > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> >
> > > > +
> >
> > > > +Example:
> >
> > > > +      zynqmp_pcap: pcap {
> >
> > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> >
> > > > +      };
> >
> > >
> >
> > > There's no need for a DT node. Just make the firware driver create a
> > > platform
> >
> > > device for pcap.
> >
> > >
> >
> >
> >
> > This driver being used by the FPGA manager framework(fpga-region) to apply
> overlay's so this node is needed AFAIK.
> 
> The binding says nothing about child nodes and what they are. Please define
> that.
>
Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

Device Tree Example for Full Reconfiguration
============================================

Live Device Tree contains:

        zynqmp_pcap: pcap {
                compatible = "xlnx,zynqmp-pcap-fpga";
        };

        fpga_region0: fpga-region0 {
                compatible = "fpga-region";
                fpga-mgr = <&zynqmp_pcap>;
                #address-cells = <0x1>;
                #size-cells = <0x1>;
                ranges;
        };

DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
        target = <&fpga_region0>;
        #address-cells = <1>;
        #size-cells = <1>;
        __overlay__ {
                #address-cells = <1>;
                #size-cells = <1>;

                firmware-name = "zynqmp-gpio.bin";

                gpio1: gpio@40000000 {
                        compatible = "xlnx,xps-gpio-1.00.a";
                        reg = <0x40000000 0x10000>;
                        gpio-controller;
                        #gpio-cells = <0x2>;
                        xlnx,gpio-width= <0x6>;
                };
        };
};
 
Please correct me if my understanding is wrong.

Regards,
Navakishore.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-03-04 11:35           ` Nava kishore Manne
  (?)
@ 2019-03-04 17:27             ` Rob Herring
  -1 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-04 17:27 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>  Thanks for providing the review comments..
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Saturday, February 23, 2019 2:01 AM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver
> >
> > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >
> > >
> > > Thanks for providing the comments...
> >
> > Please fix your mailer to send plain text emails to mail lists.
> >
> Thanks for pointing it..
>
> >
> > > > -----Original Message-----
> > >
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > >
> > > > Sent: Monday, January 21, 2019 9:19 PM
> > >
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > >
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja
> > >
> > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > >
> > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > >
> > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > >
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga
> > >
> > > > driver
> > >
> > > >
> > >
> > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > >
> > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > >
> > > > >
> > >
> > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > >
> > > > > ---
> > >
> > > > > Changes for v3:
> > >
> > > > >                         -Removed PCAP as a child node to the FW
> > > > > and Created
> > >
> > > > >                         an independent node since PCAP driver is a
> > > > > consumer
> > >
> > > > >                         not a provider.
> > >
> > > > >
> > >
> > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > >
> > > > >  1 file changed, 13 insertions(+)
> > >
> > > > >  create mode 100644
> > >
> > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > >
> > >
> > > > > diff --git
> > >
> > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > new file mode 100644
> > >
> > > > > index 000000000000..1f6f58872311
> > >
> > > > > --- /dev/null
> > >
> > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > +++ .txt
> > >
> > > > > @@ -0,0 +1,13 @@
> > >
> > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > >
> > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > >
> > > > > +configuration on ZynqMp Soc uses processor configuration
> > >
> > > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> > >
> > > > > +using FW interface.
> > >
> > > > > +
> > >
> > > > > +Required properties:
> > >
> > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > >
> > > > > +
> > >
> > > > > +Example:
> > >
> > > > > +      zynqmp_pcap: pcap {
> > >
> > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > >
> > > > > +      };
> > >
> > > >
> > >
> > > > There's no need for a DT node. Just make the firware driver create a
> > > > platform
> > >
> > > > device for pcap.
> > >
> > > >
> > >
> > >
> > >
> > > This driver being used by the FPGA manager framework(fpga-region) to apply
> > overlay's so this node is needed AFAIK.
> >
> > The binding says nothing about child nodes and what they are. Please define
> > that.
> >
> Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

You can have an example, but no, I meant you need say something like
"The pcap node may have 1 or more child nodes which have an
'fpga-region' compatible.
>
> Device Tree Example for Full Reconfiguration
> ============================================
>
> Live Device Tree contains:
>
>         zynqmp_pcap: pcap {
>                 compatible = "xlnx,zynqmp-pcap-fpga";
>         };
>
>         fpga_region0: fpga-region0 {

This should be a child of pcap.

>                 compatible = "fpga-region";
>                 fpga-mgr = <&zynqmp_pcap>;
>                 #address-cells = <0x1>;
>                 #size-cells = <0x1>;
>                 ranges;
>         };
>
> DT Overlay contains:

Don't show overlays in examples. Just show a final tree (i.e. base
with overlay applied).

> /dts-v1/ /plugin/;
> / {
> fragment@0 {
>         target = <&fpga_region0>;
>         #address-cells = <1>;
>         #size-cells = <1>;
>         __overlay__ {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>
>                 firmware-name = "zynqmp-gpio.bin";
>
>                 gpio1: gpio@40000000 {
>                         compatible = "xlnx,xps-gpio-1.00.a";
>                         reg = <0x40000000 0x10000>;
>                         gpio-controller;
>                         #gpio-cells = <0x2>;
>                         xlnx,gpio-width= <0x6>;
>                 };
>         };
> };
>
> Please correct me if my understanding is wrong.
>
> Regards,
> Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-04 17:27             ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-04 17:27 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369

On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>  Thanks for providing the review comments..
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Saturday, February 23, 2019 2:01 AM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver
> >
> > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >
> > >
> > > Thanks for providing the comments...
> >
> > Please fix your mailer to send plain text emails to mail lists.
> >
> Thanks for pointing it..
>
> >
> > > > -----Original Message-----
> > >
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > >
> > > > Sent: Monday, January 21, 2019 9:19 PM
> > >
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > >
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja
> > >
> > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > >
> > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > >
> > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > >
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga
> > >
> > > > driver
> > >
> > > >
> > >
> > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > >
> > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > >
> > > > >
> > >
> > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > >
> > > > > ---
> > >
> > > > > Changes for v3:
> > >
> > > > >                         -Removed PCAP as a child node to the FW
> > > > > and Created
> > >
> > > > >                         an independent node since PCAP driver is a
> > > > > consumer
> > >
> > > > >                         not a provider.
> > >
> > > > >
> > >
> > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > >
> > > > >  1 file changed, 13 insertions(+)
> > >
> > > > >  create mode 100644
> > >
> > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > >
> > >
> > > > > diff --git
> > >
> > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > new file mode 100644
> > >
> > > > > index 000000000000..1f6f58872311
> > >
> > > > > --- /dev/null
> > >
> > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > +++ .txt
> > >
> > > > > @@ -0,0 +1,13 @@
> > >
> > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > >
> > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > >
> > > > > +configuration on ZynqMp Soc uses processor configuration
> > >
> > > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> > >
> > > > > +using FW interface.
> > >
> > > > > +
> > >
> > > > > +Required properties:
> > >
> > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > >
> > > > > +
> > >
> > > > > +Example:
> > >
> > > > > +      zynqmp_pcap: pcap {
> > >
> > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > >
> > > > > +      };
> > >
> > > >
> > >
> > > > There's no need for a DT node. Just make the firware driver create a
> > > > platform
> > >
> > > > device for pcap.
> > >
> > > >
> > >
> > >
> > >
> > > This driver being used by the FPGA manager framework(fpga-region) to apply
> > overlay's so this node is needed AFAIK.
> >
> > The binding says nothing about child nodes and what they are. Please define
> > that.
> >
> Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

You can have an example, but no, I meant you need say something like
"The pcap node may have 1 or more child nodes which have an
'fpga-region' compatible.
>
> Device Tree Example for Full Reconfiguration
> ============================================
>
> Live Device Tree contains:
>
>         zynqmp_pcap: pcap {
>                 compatible = "xlnx,zynqmp-pcap-fpga";
>         };
>
>         fpga_region0: fpga-region0 {

This should be a child of pcap.

>                 compatible = "fpga-region";
>                 fpga-mgr = <&zynqmp_pcap>;
>                 #address-cells = <0x1>;
>                 #size-cells = <0x1>;
>                 ranges;
>         };
>
> DT Overlay contains:

Don't show overlays in examples. Just show a final tree (i.e. base
with overlay applied).

> /dts-v1/ /plugin/;
> / {
> fragment@0 {
>         target = <&fpga_region0>;
>         #address-cells = <1>;
>         #size-cells = <1>;
>         __overlay__ {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>
>                 firmware-name = "zynqmp-gpio.bin";
>
>                 gpio1: gpio@40000000 {
>                         compatible = "xlnx,xps-gpio-1.00.a";
>                         reg = <0x40000000 0x10000>;
>                         gpio-controller;
>                         #gpio-cells = <0x2>;
>                         xlnx,gpio-width= <0x6>;
>                 };
>         };
> };
>
> Please correct me if my understanding is wrong.
>
> Regards,
> Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-04 17:27             ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-04 17:27 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, linux-kernel, Jolly Shah, Rajan Vaja,
	Michal Simek, linux-arm-kernel, chinnikishore369

On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
>  Thanks for providing the review comments..
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Saturday, February 23, 2019 2:01 AM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver
> >
> > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >
> > >
> > > Thanks for providing the comments...
> >
> > Please fix your mailer to send plain text emails to mail lists.
> >
> Thanks for pointing it..
>
> >
> > > > -----Original Message-----
> > >
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > >
> > > > Sent: Monday, January 21, 2019 9:19 PM
> > >
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > >
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja
> > >
> > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > >
> > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > >
> > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > >
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga
> > >
> > > > driver
> > >
> > > >
> > >
> > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > >
> > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > >
> > > > >
> > >
> > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > >
> > > > > ---
> > >
> > > > > Changes for v3:
> > >
> > > > >                         -Removed PCAP as a child node to the FW
> > > > > and Created
> > >
> > > > >                         an independent node since PCAP driver is a
> > > > > consumer
> > >
> > > > >                         not a provider.
> > >
> > > > >
> > >
> > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > >
> > > > >  1 file changed, 13 insertions(+)
> > >
> > > > >  create mode 100644
> > >
> > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > >
> > >
> > > > > diff --git
> > >
> > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > new file mode 100644
> > >
> > > > > index 000000000000..1f6f58872311
> > >
> > > > > --- /dev/null
> > >
> > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > +++ .txt
> > >
> > > > > @@ -0,0 +1,13 @@
> > >
> > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > >
> > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > >
> > > > > +configuration on ZynqMp Soc uses processor configuration
> > >
> > > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> > >
> > > > > +using FW interface.
> > >
> > > > > +
> > >
> > > > > +Required properties:
> > >
> > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > >
> > > > > +
> > >
> > > > > +Example:
> > >
> > > > > +      zynqmp_pcap: pcap {
> > >
> > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > >
> > > > > +      };
> > >
> > > >
> > >
> > > > There's no need for a DT node. Just make the firware driver create a
> > > > platform
> > >
> > > > device for pcap.
> > >
> > > >
> > >
> > >
> > >
> > > This driver being used by the FPGA manager framework(fpga-region) to apply
> > overlay's so this node is needed AFAIK.
> >
> > The binding says nothing about child nodes and what they are. Please define
> > that.
> >
> Do you mean I need to add the example usage of the pcap node like as below in the binding doc?

You can have an example, but no, I meant you need say something like
"The pcap node may have 1 or more child nodes which have an
'fpga-region' compatible.
>
> Device Tree Example for Full Reconfiguration
> ============================================
>
> Live Device Tree contains:
>
>         zynqmp_pcap: pcap {
>                 compatible = "xlnx,zynqmp-pcap-fpga";
>         };
>
>         fpga_region0: fpga-region0 {

This should be a child of pcap.

>                 compatible = "fpga-region";
>                 fpga-mgr = <&zynqmp_pcap>;
>                 #address-cells = <0x1>;
>                 #size-cells = <0x1>;
>                 ranges;
>         };
>
> DT Overlay contains:

Don't show overlays in examples. Just show a final tree (i.e. base
with overlay applied).

> /dts-v1/ /plugin/;
> / {
> fragment@0 {
>         target = <&fpga_region0>;
>         #address-cells = <1>;
>         #size-cells = <1>;
>         __overlay__ {
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>
>                 firmware-name = "zynqmp-gpio.bin";
>
>                 gpio1: gpio@40000000 {
>                         compatible = "xlnx,xps-gpio-1.00.a";
>                         reg = <0x40000000 0x10000>;
>                         gpio-controller;
>                         #gpio-cells = <0x2>;
>                         xlnx,gpio-width= <0x6>;
>                 };
>         };
> };
>
> Please correct me if my understanding is wrong.
>
> Regards,
> Navakishore.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-03-04 17:27             ` Rob Herring
  (?)
@ 2019-03-05  9:42               ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-05  9:42 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369,
	Alan Tull, Moritz Fischer

Hi Rob,

Thanks for the quick response.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Monday, March 4, 2019 10:57 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >  Thanks for providing the review comments..
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:robh@kernel.org]
> > > Sent: Saturday, February 23, 2019 2:01 AM
> > > To: Nava kishore Manne <navam@xilinx.com>
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga driver
> > >
> > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > <navam@xilinx.com>
> > > wrote:
> > > >
> > > > Hi Rob,
> > > >
> > > >
> > > >
> > > > Thanks for providing the comments...
> > >
> > > Please fix your mailer to send plain text emails to mail lists.
> > >
> > Thanks for pointing it..
> >
> > >
> > > > > -----Original Message-----
> > > >
> > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > >
> > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > >
> > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > >
> > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > Rajan Vaja
> > > >
> > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > linux-
> > > >
> > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > >
> > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > >
> > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > > ZynqMP fpga
> > > >
> > > > > driver
> > > >
> > > > >
> > > >
> > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > > >
> > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > >
> > > > > >
> > > >
> > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > >
> > > > > > ---
> > > >
> > > > > > Changes for v3:
> > > >
> > > > > >                         -Removed PCAP as a child node to the
> > > > > > FW and Created
> > > >
> > > > > >                         an independent node since PCAP driver
> > > > > > is a consumer
> > > >
> > > > > >                         not a provider.
> > > >
> > > > > >
> > > >
> > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > > >
> > > > > >  1 file changed, 13 insertions(+)
> > > >
> > > > > >  create mode 100644
> > > >
> > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.t
> > > > > > xt
> > > >
> > > > > >
> > > >
> > > > > > diff --git
> > > >
> > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > new file mode 100644
> > > >
> > > > > > index 000000000000..1f6f58872311
> > > >
> > > > > > --- /dev/null
> > > >
> > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-
> > > > > > +++ fpga
> > > > > > +++ .txt
> > > >
> > > > > > @@ -0,0 +1,13 @@
> > > >
> > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > +MPSoC
> > > >
> > > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > > >
> > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > >
> > > > > > +port(PCAP) to configure the programmable logic(PL) through PS
> > > > > > +by
> > > >
> > > > > > +using FW interface.
> > > >
> > > > > > +
> > > >
> > > > > > +Required properties:
> > > >
> > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > >
> > > > > > +
> > > >
> > > > > > +Example:
> > > >
> > > > > > +      zynqmp_pcap: pcap {
> > > >
> > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > >
> > > > > > +      };
> > > >
> > > > >
> > > >
> > > > > There's no need for a DT node. Just make the firware driver
> > > > > create a platform
> > > >
> > > > > device for pcap.
> > > >
> > > > >
> > > >
> > > >
> > > >
> > > > This driver being used by the FPGA manager framework(fpga-region)
> > > > to apply
> > > overlay's so this node is needed AFAIK.
> > >
> > > The binding says nothing about child nodes and what they are. Please
> > > define that.
> > >
> > Do you mean I need to add the example usage of the pcap node like as below
> in the binding doc?
> 
> You can have an example, but no, I meant you need say something like "The
> pcap node may have 1 or more child nodes which have an 'fpga-region'
> compatible.
> >
> > Device Tree Example for Full Reconfiguration
> > ============================================
> >
> > Live Device Tree contains:
> >
> >         zynqmp_pcap: pcap {
> >                 compatible = "xlnx,zynqmp-pcap-fpga";
> >         };
> >
> >         fpga_region0: fpga-region0 {
> 
> This should be a child of pcap.
> 
AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
I have made this changes by looking into the below reference doc.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt 

> >                 compatible = "fpga-region";
> >                 fpga-mgr = <&zynqmp_pcap>;
> >                 #address-cells = <0x1>;
> >                 #size-cells = <0x1>;
> >                 ranges;
> >         };
> >
> > DT Overlay contains:
> 
> Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> applied).

To get a better picture for the users i have added this example node with overlays
I feel it's good to have this info because it will not impact the functionality of PCAP node.
Please let me know if you still  want me to make this example without overlay node.

Regards,
Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-05  9:42               ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-05  9:42 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

Hi Rob,

Thanks for the quick response.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Monday, March 4, 2019 10:57 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >  Thanks for providing the review comments..
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:robh@kernel.org]
> > > Sent: Saturday, February 23, 2019 2:01 AM
> > > To: Nava kishore Manne <navam@xilinx.com>
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga driver
> > >
> > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > <navam@xilinx.com>
> > > wrote:
> > > >
> > > > Hi Rob,
> > > >
> > > >
> > > >
> > > > Thanks for providing the comments...
> > >
> > > Please fix your mailer to send plain text emails to mail lists.
> > >
> > Thanks for pointing it..
> >
> > >
> > > > > -----Original Message-----
> > > >
> > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > >
> > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > >
> > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > >
> > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > Rajan Vaja
> > > >
> > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > linux-
> > > >
> > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > >
> > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > >
> > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > > ZynqMP fpga
> > > >
> > > > > driver
> > > >
> > > > >
> > > >
> > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > > >
> > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > >
> > > > > >
> > > >
> > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > >
> > > > > > ---
> > > >
> > > > > > Changes for v3:
> > > >
> > > > > >                         -Removed PCAP as a child node to the
> > > > > > FW and Created
> > > >
> > > > > >                         an independent node since PCAP driver
> > > > > > is a consumer
> > > >
> > > > > >                         not a provider.
> > > >
> > > > > >
> > > >
> > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > > >
> > > > > >  1 file changed, 13 insertions(+)
> > > >
> > > > > >  create mode 100644
> > > >
> > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.t
> > > > > > xt
> > > >
> > > > > >
> > > >
> > > > > > diff --git
> > > >
> > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > new file mode 100644
> > > >
> > > > > > index 000000000000..1f6f58872311
> > > >
> > > > > > --- /dev/null
> > > >
> > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-
> > > > > > +++ fpga
> > > > > > +++ .txt
> > > >
> > > > > > @@ -0,0 +1,13 @@
> > > >
> > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > +MPSoC
> > > >
> > > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > > >
> > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > >
> > > > > > +port(PCAP) to configure the programmable logic(PL) through PS
> > > > > > +by
> > > >
> > > > > > +using FW interface.
> > > >
> > > > > > +
> > > >
> > > > > > +Required properties:
> > > >
> > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > >
> > > > > > +
> > > >
> > > > > > +Example:
> > > >
> > > > > > +      zynqmp_pcap: pcap {
> > > >
> > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > >
> > > > > > +      };
> > > >
> > > > >
> > > >
> > > > > There's no need for a DT node. Just make the firware driver
> > > > > create a platform
> > > >
> > > > > device for pcap.
> > > >
> > > > >
> > > >
> > > >
> > > >
> > > > This driver being used by the FPGA manager framework(fpga-region)
> > > > to apply
> > > overlay's so this node is needed AFAIK.
> > >
> > > The binding says nothing about child nodes and what they are. Please
> > > define that.
> > >
> > Do you mean I need to add the example usage of the pcap node like as below
> in the binding doc?
> 
> You can have an example, but no, I meant you need say something like "The
> pcap node may have 1 or more child nodes which have an 'fpga-region'
> compatible.
> >
> > Device Tree Example for Full Reconfiguration
> > ============================================
> >
> > Live Device Tree contains:
> >
> >         zynqmp_pcap: pcap {
> >                 compatible = "xlnx,zynqmp-pcap-fpga";
> >         };
> >
> >         fpga_region0: fpga-region0 {
> 
> This should be a child of pcap.
> 
AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
I have made this changes by looking into the below reference doc.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt 

> >                 compatible = "fpga-region";
> >                 fpga-mgr = <&zynqmp_pcap>;
> >                 #address-cells = <0x1>;
> >                 #size-cells = <0x1>;
> >                 ranges;
> >         };
> >
> > DT Overlay contains:
> 
> Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> applied).

To get a better picture for the users i have added this example node with overlays
I feel it's good to have this info because it will not impact the functionality of PCAP node.
Please let me know if you still  want me to make this example without overlay node.

Regards,
Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-05  9:42               ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-05  9:42 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

Hi Rob,

Thanks for the quick response.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Monday, March 4, 2019 10:57 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> wrote:
> >
> > Hi Rob,
> >
> >  Thanks for providing the review comments..
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:robh@kernel.org]
> > > Sent: Saturday, February 23, 2019 2:01 AM
> > > To: Nava kishore Manne <navam@xilinx.com>
> > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga driver
> > >
> > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > <navam@xilinx.com>
> > > wrote:
> > > >
> > > > Hi Rob,
> > > >
> > > >
> > > >
> > > > Thanks for providing the comments...
> > >
> > > Please fix your mailer to send plain text emails to mail lists.
> > >
> > Thanks for pointing it..
> >
> > >
> > > > > -----Original Message-----
> > > >
> > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > >
> > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > >
> > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > >
> > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > Rajan Vaja
> > > >
> > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > linux-
> > > >
> > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > >
> > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > >
> > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > > ZynqMP fpga
> > > >
> > > > > driver
> > > >
> > > > >
> > > >
> > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > > >
> > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > >
> > > > > >
> > > >
> > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > >
> > > > > > ---
> > > >
> > > > > > Changes for v3:
> > > >
> > > > > >                         -Removed PCAP as a child node to the
> > > > > > FW and Created
> > > >
> > > > > >                         an independent node since PCAP driver
> > > > > > is a consumer
> > > >
> > > > > >                         not a provider.
> > > >
> > > > > >
> > > >
> > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
> > > >
> > > > > >  1 file changed, 13 insertions(+)
> > > >
> > > > > >  create mode 100644
> > > >
> > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.t
> > > > > > xt
> > > >
> > > > > >
> > > >
> > > > > > diff --git
> > > >
> > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > new file mode 100644
> > > >
> > > > > > index 000000000000..1f6f58872311
> > > >
> > > > > > --- /dev/null
> > > >
> > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-
> > > > > > +++ fpga
> > > > > > +++ .txt
> > > >
> > > > > > @@ -0,0 +1,13 @@
> > > >
> > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > +MPSoC
> > > >
> > > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > > >
> > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > >
> > > > > > +port(PCAP) to configure the programmable logic(PL) through PS
> > > > > > +by
> > > >
> > > > > > +using FW interface.
> > > >
> > > > > > +
> > > >
> > > > > > +Required properties:
> > > >
> > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > >
> > > > > > +
> > > >
> > > > > > +Example:
> > > >
> > > > > > +      zynqmp_pcap: pcap {
> > > >
> > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > >
> > > > > > +      };
> > > >
> > > > >
> > > >
> > > > > There's no need for a DT node. Just make the firware driver
> > > > > create a platform
> > > >
> > > > > device for pcap.
> > > >
> > > > >
> > > >
> > > >
> > > >
> > > > This driver being used by the FPGA manager framework(fpga-region)
> > > > to apply
> > > overlay's so this node is needed AFAIK.
> > >
> > > The binding says nothing about child nodes and what they are. Please
> > > define that.
> > >
> > Do you mean I need to add the example usage of the pcap node like as below
> in the binding doc?
> 
> You can have an example, but no, I meant you need say something like "The
> pcap node may have 1 or more child nodes which have an 'fpga-region'
> compatible.
> >
> > Device Tree Example for Full Reconfiguration
> > ============================================
> >
> > Live Device Tree contains:
> >
> >         zynqmp_pcap: pcap {
> >                 compatible = "xlnx,zynqmp-pcap-fpga";
> >         };
> >
> >         fpga_region0: fpga-region0 {
> 
> This should be a child of pcap.
> 
AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
I have made this changes by looking into the below reference doc.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt 

> >                 compatible = "fpga-region";
> >                 fpga-mgr = <&zynqmp_pcap>;
> >                 #address-cells = <0x1>;
> >                 #size-cells = <0x1>;
> >                 ranges;
> >         };
> >
> > DT Overlay contains:
> 
> Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> applied).

To get a better picture for the users i have added this example node with overlays
I feel it's good to have this info because it will not impact the functionality of PCAP node.
Please let me know if you still  want me to make this example without overlay node.

Regards,
Navakishore.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-03-04 17:27             ` Rob Herring
  (?)
@ 2019-03-13  5:28               ` Nava kishore Manne
  -1 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-13  5:28 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369,
	Alan Tull, Moritz Fischer

Ping !!

> -----Original Message-----
> From: Nava kishore Manne
> Sent: Tuesday, March 5, 2019 3:12 PM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com; 'Alan Tull'
> <atull@kernel.org>; Moritz Fischer <moritz.fischer@ettus.com>
> Subject: RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> Hi Rob,
> 
> Thanks for the quick response.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP
> > fpga driver
> >
> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >  Thanks for providing the review comments..
> > > Please find my response inline.
> > >
> > > > -----Original Message-----
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > Sent: Saturday, February 23, 2019 2:01 AM
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga driver
> > > >
> > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > > <navam@xilinx.com>
> > > > wrote:
> > > > >
> > > > > Hi Rob,
> > > > >
> > > > >
> > > > >
> > > > > Thanks for providing the comments...
> > > >
> > > > Please fix your mailer to send plain text emails to mail lists.
> > > >
> > > Thanks for pointing it..
> > >
> > > >
> > > > > > -----Original Message-----
> > > > >
> > > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > >
> > > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > > >
> > > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > >
> > > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > > Rajan Vaja
> > > > >
> > > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > > linux-
> > > > >
> > > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > > >
> > > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > >
> > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings
> > > > > > for ZynqMP fpga
> > > > >
> > > > > > driver
> > > > >
> > > > > >
> > > > >
> > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne
> wrote:
> > > > >
> > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > > >
> > > > > > >
> > > > >
> > > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > >
> > > > > > > ---
> > > > >
> > > > > > > Changes for v3:
> > > > >
> > > > > > >                         -Removed PCAP as a child node to the
> > > > > > > FW and Created
> > > > >
> > > > > > >                         an independent node since PCAP
> > > > > > > driver is a consumer
> > > > >
> > > > > > >                         not a provider.
> > > > >
> > > > > > >
> > > > >
> > > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13
> +++++++++++++
> > > > >
> > > > > > >  1 file changed, 13 insertions(+)
> > > > >
> > > > > > >  create mode 100644
> > > > >
> > > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > > .t
> > > > > > > xt
> > > > >
> > > > > > >
> > > > >
> > > > > > > diff --git
> > > > >
> > > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > new file mode 100644
> > > > >
> > > > > > > index 000000000000..1f6f58872311
> > > > >
> > > > > > > --- /dev/null
> > > > >
> > > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pca
> > > > > > > +++ p-
> > > > > > > +++ fpga
> > > > > > > +++ .txt
> > > > >
> > > > > > > @@ -0,0 +1,13 @@
> > > > >
> > > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > > +MPSoC
> > > > >
> > > > > > > +controlled using ZynqMP SoC firmware interface For
> > > > > > > +Bitstream
> > > > >
> > > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > > >
> > > > > > > +port(PCAP) to configure the programmable logic(PL) through
> > > > > > > +PS by
> > > > >
> > > > > > > +using FW interface.
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Required properties:
> > > > >
> > > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Example:
> > > > >
> > > > > > > +      zynqmp_pcap: pcap {
> > > > >
> > > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > > >
> > > > > > > +      };
> > > > >
> > > > > >
> > > > >
> > > > > > There's no need for a DT node. Just make the firware driver
> > > > > > create a platform
> > > > >
> > > > > > device for pcap.
> > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > > > This driver being used by the FPGA manager
> > > > > framework(fpga-region) to apply
> > > > overlay's so this node is needed AFAIK.
> > > >
> > > > The binding says nothing about child nodes and what they are.
> > > > Please define that.
> > > >
> > > Do you mean I need to add the example usage of the pcap node like as
> > > below
> > in the binding doc?
> >
> > You can have an example, but no, I meant you need say something like
> > "The pcap node may have 1 or more child nodes which have an 'fpga-region'
> > compatible.
> > >
> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent
> and they refered to each other using phandlers I have made this changes by
> looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind
> ings/fpga/fpga-region.txt
> 
> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base
> > with overlay applied).
> 
> To get a better picture for the users i have added this example node with
> overlays I feel it's good to have this info because it will not impact the
> functionality of PCAP node.
> Please let me know if you still  want me to make this example without overlay
> node.
> 
> Regards,
> Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-13  5:28               ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-13  5:28 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, Michal Simek, Rajan Vaja, linux-arm-kernel,
	linux-kernel, devicetree, Jolly Shah, chinnikishore369,
	Alan Tull, Moritz Fischer

Ping !!

> -----Original Message-----
> From: Nava kishore Manne
> Sent: Tuesday, March 5, 2019 3:12 PM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com; 'Alan Tull'
> <atull@kernel.org>; Moritz Fischer <moritz.fischer@ettus.com>
> Subject: RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> Hi Rob,
> 
> Thanks for the quick response.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP
> > fpga driver
> >
> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >  Thanks for providing the review comments..
> > > Please find my response inline.
> > >
> > > > -----Original Message-----
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > Sent: Saturday, February 23, 2019 2:01 AM
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga driver
> > > >
> > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > > <navam@xilinx.com>
> > > > wrote:
> > > > >
> > > > > Hi Rob,
> > > > >
> > > > >
> > > > >
> > > > > Thanks for providing the comments...
> > > >
> > > > Please fix your mailer to send plain text emails to mail lists.
> > > >
> > > Thanks for pointing it..
> > >
> > > >
> > > > > > -----Original Message-----
> > > > >
> > > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > >
> > > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > > >
> > > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > >
> > > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > > Rajan Vaja
> > > > >
> > > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > > linux-
> > > > >
> > > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > > >
> > > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > >
> > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings
> > > > > > for ZynqMP fpga
> > > > >
> > > > > > driver
> > > > >
> > > > > >
> > > > >
> > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne
> wrote:
> > > > >
> > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > > >
> > > > > > >
> > > > >
> > > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > >
> > > > > > > ---
> > > > >
> > > > > > > Changes for v3:
> > > > >
> > > > > > >                         -Removed PCAP as a child node to the
> > > > > > > FW and Created
> > > > >
> > > > > > >                         an independent node since PCAP
> > > > > > > driver is a consumer
> > > > >
> > > > > > >                         not a provider.
> > > > >
> > > > > > >
> > > > >
> > > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13
> +++++++++++++
> > > > >
> > > > > > >  1 file changed, 13 insertions(+)
> > > > >
> > > > > > >  create mode 100644
> > > > >
> > > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > > .t
> > > > > > > xt
> > > > >
> > > > > > >
> > > > >
> > > > > > > diff --git
> > > > >
> > > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > new file mode 100644
> > > > >
> > > > > > > index 000000000000..1f6f58872311
> > > > >
> > > > > > > --- /dev/null
> > > > >
> > > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pca
> > > > > > > +++ p-
> > > > > > > +++ fpga
> > > > > > > +++ .txt
> > > > >
> > > > > > > @@ -0,0 +1,13 @@
> > > > >
> > > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > > +MPSoC
> > > > >
> > > > > > > +controlled using ZynqMP SoC firmware interface For
> > > > > > > +Bitstream
> > > > >
> > > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > > >
> > > > > > > +port(PCAP) to configure the programmable logic(PL) through
> > > > > > > +PS by
> > > > >
> > > > > > > +using FW interface.
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Required properties:
> > > > >
> > > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Example:
> > > > >
> > > > > > > +      zynqmp_pcap: pcap {
> > > > >
> > > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > > >
> > > > > > > +      };
> > > > >
> > > > > >
> > > > >
> > > > > > There's no need for a DT node. Just make the firware driver
> > > > > > create a platform
> > > > >
> > > > > > device for pcap.
> > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > > > This driver being used by the FPGA manager
> > > > > framework(fpga-region) to apply
> > > > overlay's so this node is needed AFAIK.
> > > >
> > > > The binding says nothing about child nodes and what they are.
> > > > Please define that.
> > > >
> > > Do you mean I need to add the example usage of the pcap node like as
> > > below
> > in the binding doc?
> >
> > You can have an example, but no, I meant you need say something like
> > "The pcap node may have 1 or more child nodes which have an 'fpga-region'
> > compatible.
> > >
> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent
> and they refered to each other using phandlers I have made this changes by
> looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind
> ings/fpga/fpga-region.txt
> 
> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base
> > with overlay applied).
> 
> To get a better picture for the users i have added this example node with
> overlays I feel it's good to have this info because it will not impact the
> functionality of PCAP node.
> Please let me know if you still  want me to make this example without overlay
> node.
> 
> Regards,
> Navakishore.

^ permalink raw reply	[flat|nested] 51+ messages in thread

* RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-13  5:28               ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-03-13  5:28 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

Ping !!

> -----Original Message-----
> From: Nava kishore Manne
> Sent: Tuesday, March 5, 2019 3:12 PM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> <JOLLYS@xilinx.com>; chinnikishore369@gmail.com; 'Alan Tull'
> <atull@kernel.org>; Moritz Fischer <moritz.fischer@ettus.com>
> Subject: RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> Hi Rob,
> 
> Thanks for the quick response.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP
> > fpga driver
> >
> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >  Thanks for providing the review comments..
> > > Please find my response inline.
> > >
> > > > -----Original Message-----
> > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > Sent: Saturday, February 23, 2019 2:01 AM
> > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan
> > > > Vaja <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > linux- kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly
> > > > Shah <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga driver
> > > >
> > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > > <navam@xilinx.com>
> > > > wrote:
> > > > >
> > > > > Hi Rob,
> > > > >
> > > > >
> > > > >
> > > > > Thanks for providing the comments...
> > > >
> > > > Please fix your mailer to send plain text emails to mail lists.
> > > >
> > > Thanks for pointing it..
> > >
> > > >
> > > > > > -----Original Message-----
> > > > >
> > > > > > From: Rob Herring [mailto:robh@kernel.org]
> > > > >
> > > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > > >
> > > > > > To: Nava kishore Manne <navam@xilinx.com>
> > > > >
> > > > > > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>;
> > > > > > Rajan Vaja
> > > > >
> > > > > > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org;
> > > > > > linux-
> > > > >
> > > > > > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > > > >
> > > > > > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > > > >
> > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings
> > > > > > for ZynqMP fpga
> > > > >
> > > > > > driver
> > > > >
> > > > > >
> > > > >
> > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne
> wrote:
> > > > >
> > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > > >
> > > > > > >
> > > > >
> > > > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > >
> > > > > > > ---
> > > > >
> > > > > > > Changes for v3:
> > > > >
> > > > > > >                         -Removed PCAP as a child node to the
> > > > > > > FW and Created
> > > > >
> > > > > > >                         an independent node since PCAP
> > > > > > > driver is a consumer
> > > > >
> > > > > > >                         not a provider.
> > > > >
> > > > > > >
> > > > >
> > > > > > >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13
> +++++++++++++
> > > > >
> > > > > > >  1 file changed, 13 insertions(+)
> > > > >
> > > > > > >  create mode 100644
> > > > >
> > > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > > .t
> > > > > > > xt
> > > > >
> > > > > > >
> > > > >
> > > > > > > diff --git
> > > > >
> > > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > new file mode 100644
> > > > >
> > > > > > > index 000000000000..1f6f58872311
> > > > >
> > > > > > > --- /dev/null
> > > > >
> > > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pca
> > > > > > > +++ p-
> > > > > > > +++ fpga
> > > > > > > +++ .txt
> > > > >
> > > > > > > @@ -0,0 +1,13 @@
> > > > >
> > > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > > +MPSoC
> > > > >
> > > > > > > +controlled using ZynqMP SoC firmware interface For
> > > > > > > +Bitstream
> > > > >
> > > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > > >
> > > > > > > +port(PCAP) to configure the programmable logic(PL) through
> > > > > > > +PS by
> > > > >
> > > > > > > +using FW interface.
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Required properties:
> > > > >
> > > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Example:
> > > > >
> > > > > > > +      zynqmp_pcap: pcap {
> > > > >
> > > > > > > +                     compatible = "xlnx,zynqmp-pcap-fpga";
> > > > >
> > > > > > > +      };
> > > > >
> > > > > >
> > > > >
> > > > > > There's no need for a DT node. Just make the firware driver
> > > > > > create a platform
> > > > >
> > > > > > device for pcap.
> > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > > > This driver being used by the FPGA manager
> > > > > framework(fpga-region) to apply
> > > > overlay's so this node is needed AFAIK.
> > > >
> > > > The binding says nothing about child nodes and what they are.
> > > > Please define that.
> > > >
> > > Do you mean I need to add the example usage of the pcap node like as
> > > below
> > in the binding doc?
> >
> > You can have an example, but no, I meant you need say something like
> > "The pcap node may have 1 or more child nodes which have an 'fpga-region'
> > compatible.
> > >
> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent
> and they refered to each other using phandlers I have made this changes by
> looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind
> ings/fpga/fpga-region.txt
> 
> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base
> > with overlay applied).
> 
> To get a better picture for the users i have added this example node with
> overlays I feel it's good to have this info because it will not impact the
> functionality of PCAP node.
> Please let me know if you still  want me to make this example without overlay
> node.
> 
> Regards,
> Navakishore.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-03-05  9:42               ` Nava kishore Manne
  (?)
@ 2019-03-13 20:07                 ` Rob Herring
  -1 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-13 20:07 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

On Tue, Mar 5, 2019 at 3:42 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
> Thanks for the quick response.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver

Please fix your mail program to...

> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:

...use this style reply header.

[...]

> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
> I have made this changes by looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt

Indeed. But having them a as child of the firmware node doesn't make
sense either. Putting them at the top level would make more sense. I
don't recall why we didn't make them a child. Maybe regions can span
multiple bridges in the case with bridges.

> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> > applied).
>
> To get a better picture for the users i have added this example node with overlays
> I feel it's good to have this info because it will not impact the functionality of PCAP node.

Then feel free to document this somewhere else. As we move to schema
documents, your examples will have to compile and validate against the
schema. I don't want to add applying overlays to the mix.

Rob

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-13 20:07                 ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-13 20:07 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

On Tue, Mar 5, 2019 at 3:42 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
> Thanks for the quick response.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver

Please fix your mail program to...

> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:

...use this style reply header.

[...]

> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
> I have made this changes by looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt

Indeed. But having them a as child of the firmware node doesn't make
sense either. Putting them at the top level would make more sense. I
don't recall why we didn't make them a child. Maybe regions can span
multiple bridges in the case with bridges.

> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> > applied).
>
> To get a better picture for the users i have added this example node with overlays
> I feel it's good to have this info because it will not impact the functionality of PCAP node.

Then feel free to document this somewhere else. As we move to schema
documents, your examples will have to compile and validate against the
schema. I don't want to add applying overlays to the mix.

Rob

^ permalink raw reply	[flat|nested] 51+ messages in thread

* Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-03-13 20:07                 ` Rob Herring
  0 siblings, 0 replies; 51+ messages in thread
From: Rob Herring @ 2019-03-13 20:07 UTC (permalink / raw)
  To: Nava kishore Manne
  Cc: mark.rutland, devicetree, Moritz Fischer, Alan Tull,
	linux-kernel, Jolly Shah, Rajan Vaja, Michal Simek,
	linux-arm-kernel, chinnikishore369

On Tue, Mar 5, 2019 at 3:42 AM Nava kishore Manne <navam@xilinx.com> wrote:
>
> Hi Rob,
>
> Thanks for the quick response.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <navam@xilinx.com>
> > Cc: mark.rutland@arm.com; Michal Simek <michals@xilinx.com>; Rajan Vaja
> > <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah
> > <JOLLYS@xilinx.com>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver

Please fix your mail program to...

> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <navam@xilinx.com>
> > wrote:

...use this style reply header.

[...]

> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > >         zynqmp_pcap: pcap {
> > >                 compatible = "xlnx,zynqmp-pcap-fpga";
> > >         };
> > >
> > >         fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
> I have made this changes by looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt

Indeed. But having them a as child of the firmware node doesn't make
sense either. Putting them at the top level would make more sense. I
don't recall why we didn't make them a child. Maybe regions can span
multiple bridges in the case with bridges.

> > >                 compatible = "fpga-region";
> > >                 fpga-mgr = <&zynqmp_pcap>;
> > >                 #address-cells = <0x1>;
> > >                 #size-cells = <0x1>;
> > >                 ranges;
> > >         };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> > applied).
>
> To get a better picture for the users i have added this example node with overlays
> I feel it's good to have this info because it will not impact the functionality of PCAP node.

Then feel free to document this somewhere else. As we move to schema
documents, your examples will have to compile and validate against the
schema. I don't want to add applying overlays to the mix.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  2019-01-21 17:24 [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core Nava kishore Manne
  2019-01-21 17:24   ` Nava kishore Manne
@ 2019-01-21 17:24   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:24 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-01-21 17:24   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:24 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

^ permalink raw reply related	[flat|nested] 51+ messages in thread

* [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
@ 2019-01-21 17:24   ` Nava kishore Manne
  0 siblings, 0 replies; 51+ messages in thread
From: Nava kishore Manne @ 2019-01-21 17:24 UTC (permalink / raw)
  To: mark.rutland, michals, RAJANV, linux-arm-kernel, linux-kernel,
	devicetree, JOLLYS, chinnikishore369
  Cc: Nava kishore Manne

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v3:
		-Removed PCAP as a child node to the FW and Created
		an independent node since PCAP driver is a consumer
		not a provider. 

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt         | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 51+ messages in thread

end of thread, other threads:[~2019-03-13 20:07 UTC | newest]

Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-21 17:38 [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core Nava kishore Manne
2019-01-21 17:38 ` Nava kishore Manne
2019-01-21 17:38 ` Nava kishore Manne
2019-01-21 17:38 ` [PATCH v3 1/6] dt-bindings: power: Add ZynqMP power domain bindings Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38 ` [PATCH v3 2/6] dt-bindings: soc: Add ZynqMP PM bindings Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38 ` [PATCH v3 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 15:46   ` Rob Herring
2019-01-21 15:46     ` Rob Herring
2019-01-21 15:46     ` Rob Herring
2019-01-21 17:38 ` [PATCH v3 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38 ` [PATCH v3 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 15:47   ` Rob Herring
2019-01-21 15:47     ` Rob Herring
2019-01-21 15:47     ` Rob Herring
2019-01-21 17:38 ` [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 17:38   ` Nava kishore Manne
2019-01-21 15:49   ` Rob Herring
2019-01-21 15:49     ` Rob Herring
2019-01-22  9:13     ` Nava kishore Manne
2019-02-22 20:30       ` Rob Herring
2019-02-22 20:30         ` Rob Herring
2019-02-22 20:30         ` Rob Herring
2019-03-04 11:35         ` Nava kishore Manne
2019-03-04 11:35           ` Nava kishore Manne
2019-03-04 11:35           ` Nava kishore Manne
2019-03-04 17:27           ` Rob Herring
2019-03-04 17:27             ` Rob Herring
2019-03-04 17:27             ` Rob Herring
2019-03-05  9:42             ` Nava kishore Manne
2019-03-05  9:42               ` Nava kishore Manne
2019-03-05  9:42               ` Nava kishore Manne
2019-03-13 20:07               ` Rob Herring
2019-03-13 20:07                 ` Rob Herring
2019-03-13 20:07                 ` Rob Herring
2019-03-13  5:28             ` Nava kishore Manne
2019-03-13  5:28               ` Nava kishore Manne
2019-03-13  5:28               ` Nava kishore Manne
  -- strict thread matches above, loose matches on Subject: below --
2019-01-21 17:24 [PATCH v3 0/6] dt-bindings: Firmware node binding for ZynqMP core Nava kishore Manne
2019-01-21 17:24 ` [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Nava kishore Manne
2019-01-21 17:24   ` Nava kishore Manne
2019-01-21 17:24   ` Nava kishore Manne

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