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From: Matthew Auld <matthew.william.auld@gmail.com>
To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: "Daniel Vetter" <daniel.vetter@ffwll.ch>,
	"Intel Graphics Development" <intel-gfx@lists.freedesktop.org>,
	"Christian König" <christian.koenig@amd.com>,
	"ML dri-devel" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm
Date: Mon, 24 May 2021 17:45:58 +0100	[thread overview]
Message-ID: <CAM0jSHNqr-kUGsRaBavEvk3w-vr_SRrdSzQb4y-CDYrFnQgXdQ@mail.gmail.com> (raw)
In-Reply-To: <20210521153253.518037-8-thomas.hellstrom@linux.intel.com>

On Fri, 21 May 2021 at 16:33, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> Memcpy from wc will be used as well by TTM memcpy.
> Move it to core drm, and make the interface do the right thing
> even on !X86.
>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Dave Airlie <airlied@gmail.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---

<snip>

> +
> +#ifdef CONFIG_X86
> +bool drm_memcpy_from_wc(void *dst, const void *src, unsigned long len);
> +bool drm_memcpy_from_wc_dbm(struct dma_buf_map *dst,
> +                           const struct dma_buf_map *src,
> +                           unsigned long len);
> +void drm_unaligned_memcpy_from_wc(void *dst, const void *src, unsigned long len);
> +
> +/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
> + * as well as SSE4.1 support. drm_memcpy_from_wc() will report if it cannot
> + * perform the operation. To check beforehand, pass in the parameters to
> + * drm_can_memcpy_from_wc() - since we only care about the low 4 bits,
> + * you only need to pass in the minor offsets, page-aligned pointers are
> + * always valid.
> + *
> + * For just checking for SSE4.1, in the foreknowledge that the future use
> + * will be correctly aligned, just use drm_has_memcpy_from_wc().
> + */
> +#define drm_can_memcpy_from_wc(dst, src, len) \
> +       drm_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
> +
> +#define drm_has_memcpy_from_wc() \
> +       drm_memcpy_from_wc(NULL, NULL, 0)
> +
> +void drm_memcpy_init_early(void);
> +
> +#else
> +
> +#define drm_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_memcpy_from_wc_dbm(_dst, _src, _len) (false)
> +#define drm_can_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_has_memcpy_from_wc() (false)

Does the compiler not complain for these on !x86, if called without
checking the result of the statement? Maybe just make these function
stubs?

Otherwise,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +#define drm_unaligned_memcpy_from_wc(_dst, _src, _len) WARN_ON(1)
> +#define drm_memcpy_init_early() do {} while (0)
> +#endif /* CONFIG_X86 */
> +#endif /* __DRM_MEMCPY_H__ */
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.william.auld@gmail.com>
To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: "Daniel Vetter" <daniel.vetter@ffwll.ch>,
	"Intel Graphics Development" <intel-gfx@lists.freedesktop.org>,
	"Christian König" <christian.koenig@amd.com>,
	"ML dri-devel" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm
Date: Mon, 24 May 2021 17:45:58 +0100	[thread overview]
Message-ID: <CAM0jSHNqr-kUGsRaBavEvk3w-vr_SRrdSzQb4y-CDYrFnQgXdQ@mail.gmail.com> (raw)
In-Reply-To: <20210521153253.518037-8-thomas.hellstrom@linux.intel.com>

On Fri, 21 May 2021 at 16:33, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> Memcpy from wc will be used as well by TTM memcpy.
> Move it to core drm, and make the interface do the right thing
> even on !X86.
>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Dave Airlie <airlied@gmail.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---

<snip>

> +
> +#ifdef CONFIG_X86
> +bool drm_memcpy_from_wc(void *dst, const void *src, unsigned long len);
> +bool drm_memcpy_from_wc_dbm(struct dma_buf_map *dst,
> +                           const struct dma_buf_map *src,
> +                           unsigned long len);
> +void drm_unaligned_memcpy_from_wc(void *dst, const void *src, unsigned long len);
> +
> +/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
> + * as well as SSE4.1 support. drm_memcpy_from_wc() will report if it cannot
> + * perform the operation. To check beforehand, pass in the parameters to
> + * drm_can_memcpy_from_wc() - since we only care about the low 4 bits,
> + * you only need to pass in the minor offsets, page-aligned pointers are
> + * always valid.
> + *
> + * For just checking for SSE4.1, in the foreknowledge that the future use
> + * will be correctly aligned, just use drm_has_memcpy_from_wc().
> + */
> +#define drm_can_memcpy_from_wc(dst, src, len) \
> +       drm_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
> +
> +#define drm_has_memcpy_from_wc() \
> +       drm_memcpy_from_wc(NULL, NULL, 0)
> +
> +void drm_memcpy_init_early(void);
> +
> +#else
> +
> +#define drm_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_memcpy_from_wc_dbm(_dst, _src, _len) (false)
> +#define drm_can_memcpy_from_wc(_dst, _src, _len) (false)
> +#define drm_has_memcpy_from_wc() (false)

Does the compiler not complain for these on !x86, if called without
checking the result of the statement? Maybe just make these function
stubs?

Otherwise,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +#define drm_unaligned_memcpy_from_wc(_dst, _src, _len) WARN_ON(1)
> +#define drm_memcpy_init_early() do {} while (0)
> +#endif /* CONFIG_X86 */
> +#endif /* __DRM_MEMCPY_H__ */
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-05-24 16:46 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-21 15:32 [PATCH v3 00/12] drm/i915: Move LMEM (VRAM) management over to TTM Thomas Hellström
2021-05-21 15:32 ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 01/12] drm/i915: Untangle the vma pages_mutex Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 02/12] drm/i915: Don't free shared locks while shared Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 03/12] drm/i915: Fix i915_sg_page_sizes to record dma segments rather than physical pages Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 04/12] drm/i915/ttm Initialize the ttm device and memory managers Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 05/12] drm/i915/ttm: Embed a ttm buffer object in the i915 gem object Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 06/12] drm/ttm: Add a generic TTM memcpy move for page-based iomem Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-25  9:18   ` Matthew Auld
2021-05-25  9:18     ` Matthew Auld
2021-05-25  9:32     ` Thomas Hellström
2021-05-25  9:32       ` Thomas Hellström
2021-05-25  9:58       ` Matthew Auld
2021-05-25  9:58         ` Matthew Auld
2021-05-25 10:07         ` Thomas Hellström
2021-05-25 10:07           ` Thomas Hellström
2021-05-25 15:48           ` Christian König
2021-05-25 15:48             ` Christian König
2021-05-26  7:39             ` Thomas Hellström
2021-05-26  7:39               ` Thomas Hellström
2021-05-26 10:45               ` Christian König
2021-05-26 10:45                 ` Christian König
2021-05-26 10:57                 ` Thomas Hellström
2021-05-26 10:57                   ` Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 07/12] drm, drm/i915: Move the memcpy_from_wc functionality to core drm Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-24 16:45   ` Matthew Auld [this message]
2021-05-24 16:45     ` Matthew Auld
2021-05-24 18:12     ` Thomas Hellström
2021-05-24 18:12       ` Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 08/12] drm/ttm: Use drm_memcpy_from_wc_dbm for TTM bo moves Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-24 18:16   ` Matthew Auld
2021-05-24 18:16     ` [Intel-gfx] " Matthew Auld
2021-05-24 18:47     ` Thomas Hellström
2021-05-24 18:47       ` [Intel-gfx] " Thomas Hellström
2021-05-26 12:48   ` Christian König
2021-05-26 12:48     ` [Intel-gfx] " Christian König
2021-05-21 15:32 ` [PATCH v3 09/12] drm/ttm: Document and optimize ttm_bo_pipeline_gutting() Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-25 11:00   ` Matthew Auld
2021-05-25 11:00     ` Matthew Auld
2021-05-25 13:37     ` Thomas Hellström
2021-05-25 13:37       ` Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 10/12] drm/ttm, drm/amdgpu: Allow the driver some control over swapping Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 11/12] drm/i915/ttm: Introduce a TTM i915 gem object backend Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 15:32 ` [PATCH v3 12/12] drm/i915/lmem: Verify checks for lmem residency Thomas Hellström
2021-05-21 15:32   ` [Intel-gfx] " Thomas Hellström
2021-05-21 16:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Move LMEM (VRAM) management over to TTM (rev3) Patchwork
2021-05-21 16:09 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-21 16:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-24  0:10 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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