From: Sean Paul <sean@poorly.run> To: dri-devel <dri-devel@lists.freedesktop.org>, Intel Graphics Development <intel-gfx@lists.freedesktop.org> Cc: Sean Paul <seanpaul@chromium.org>, Rodrigo Vivi <rodrigo.vivi@intel.com> Subject: Re: [PATCH v2] drm/i915/hdcp: Add additional R0' wait Date: Wed, 20 May 2020 15:50:15 -0400 [thread overview] Message-ID: <CAMavQK+1f1DUJmCeUa5GvOLUBKiXtXH04VZtStqWmhXGazQD-g@mail.gmail.com> (raw) In-Reply-To: <20200520130808.44095-1-sean@poorly.run> On Wed, May 20, 2020 at 9:08 AM Sean Paul <sean@poorly.run> wrote: > > From: Sean Paul <seanpaul@chromium.org> > > We're seeing some R0' mismatches in the field, particularly with > repeaters. I'm guessing the (already lenient) 300ms wait time isn't > enough for some setups. So add an additional wait when R0' is > mismatched. > I think my guess was wrong and now suspect this issue is fixed with "drm/i915/hdcp: Avoid duplicate HDCP enables". While this patch probably still has some value in cases where R0' is slow to update, I don't have any concrete examples where it helps. Sean > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > Changes in v2: > - Actually add the delay in R0` wait (Ram) > --- > > Apologies, v1 was generated from a forward port from the CrOS kernel and > patch got confused and put the diff in V' wait instead of R0' wait. > > Pay closer attention, Sean. > > drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 2cbc4619b4ce..3c2d8c0a6da6 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector *connector) > if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) > break; > + > + /* Maybe the sink is lazy, give it some more time */ > + usleep_range(10000, 50000); > } > > if (i == tries) { > -- > Sean Paul, Software Engineer, Google / Chromium OS > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Sean Paul <sean@poorly.run> To: dri-devel <dri-devel@lists.freedesktop.org>, Intel Graphics Development <intel-gfx@lists.freedesktop.org> Cc: Sean Paul <seanpaul@chromium.org> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Add additional R0' wait Date: Wed, 20 May 2020 15:50:15 -0400 [thread overview] Message-ID: <CAMavQK+1f1DUJmCeUa5GvOLUBKiXtXH04VZtStqWmhXGazQD-g@mail.gmail.com> (raw) In-Reply-To: <20200520130808.44095-1-sean@poorly.run> On Wed, May 20, 2020 at 9:08 AM Sean Paul <sean@poorly.run> wrote: > > From: Sean Paul <seanpaul@chromium.org> > > We're seeing some R0' mismatches in the field, particularly with > repeaters. I'm guessing the (already lenient) 300ms wait time isn't > enough for some setups. So add an additional wait when R0' is > mismatched. > I think my guess was wrong and now suspect this issue is fixed with "drm/i915/hdcp: Avoid duplicate HDCP enables". While this patch probably still has some value in cases where R0' is slow to update, I don't have any concrete examples where it helps. Sean > Signed-off-by: Sean Paul <seanpaul@chromium.org> > > Changes in v2: > - Actually add the delay in R0` wait (Ram) > --- > > Apologies, v1 was generated from a forward port from the CrOS kernel and > patch got confused and put the diff in V' wait instead of R0' wait. > > Pay closer attention, Sean. > > drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 2cbc4619b4ce..3c2d8c0a6da6 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -743,6 +743,9 @@ static int intel_hdcp_auth(struct intel_connector *connector) > if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) > break; > + > + /* Maybe the sink is lazy, give it some more time */ > + usleep_range(10000, 50000); > } > > if (i == tries) { > -- > Sean Paul, Software Engineer, Google / Chromium OS > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-05-20 19:50 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-19 22:16 [PATCH] drm/i915/hdcp: Add additional R0' wait Sean Paul 2020-05-19 22:16 ` [Intel-gfx] " Sean Paul 2020-05-20 0:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2020-05-20 6:46 ` [PATCH] " Ramalingam C 2020-05-20 6:46 ` [Intel-gfx] " Ramalingam C 2020-05-20 13:08 ` [PATCH v2] " Sean Paul 2020-05-20 13:08 ` [Intel-gfx] " Sean Paul 2020-05-20 19:50 ` Sean Paul [this message] 2020-05-20 19:50 ` Sean Paul 2020-05-21 5:12 ` Ramalingam C 2020-05-21 5:12 ` [Intel-gfx] " Ramalingam C 2020-05-20 13:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork 2020-05-20 14:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: Add additional R0' wait (rev2) Patchwork 2020-05-21 5:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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