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From: Peter Collingbourne <pcc@google.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [PATCH] target/arm: Fix decode of {LD,ST}RA[AB] instructions
Date: Tue, 4 Aug 2020 10:28:05 -0700	[thread overview]
Message-ID: <CAMn1gO5nBvra0saJ53zY5fWYo_Jm0LReHmOSyYwsCGXES66fAA@mail.gmail.com> (raw)
In-Reply-To: <1c14ed0a-da1b-a265-d5bd-2dea42764032@linaro.org>

On Tue, Aug 4, 2020 at 8:41 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/3/20 5:21 PM, Peter Collingbourne wrote:
> > On Mon, Aug 3, 2020 at 3:27 PM Peter Collingbourne <pcc@google.com> wrote:
> >>
> >> These instructions use zero as the discriminator, not SP.
> >
> > Oh, there is no such thing as STRAA/STRAB. I must have been confused
> > by the name of the function, disas_ldst_pac. I will send a v2 with a
> > fixed commit message, and another patch to rename the function to
> > disas_ld_pac.
>
> It's called decode_ldst_pac because the Arm ARM section is called "Load/store
> register (pac)".  Page C4-311 in the F.a revision.
>
> But yes, there are only loads defined in the section.

I see. Arguably the ARM ARM section is misnamed then. There is a
sibling section named "Load register (literal)", so there is precedent
for naming a section after the types of instructions that are actually
supported. I will send mail to errata@arm.com to see if the section
can be renamed.

Peter


      reply	other threads:[~2020-08-04 17:29 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-03 22:26 [PATCH] target/arm: Fix decode of {LD,ST}RA[AB] instructions Peter Collingbourne
2020-08-04  0:21 ` Peter Collingbourne
2020-08-04 15:41   ` Richard Henderson
2020-08-04 17:28     ` Peter Collingbourne [this message]

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