Re: [PATCH] pinctrl: sh-pfc: checker: Fix miscalculation of number of states

From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>
Subject: Re: [PATCH] pinctrl: sh-pfc: checker: Fix miscalculation of number of states
Date: Tue, 22 Feb 2022 16:37:38 +0100	[thread overview]
Message-ID: <CAMuHMdV4Hv4Z2dMJR4riZy=FzXjJfEenWA4RQZhNvtRkno71Hw@mail.gmail.com> (raw)
In-Reply-To: <CACRpkdaJAEivz_RVGCyDvwJtDnb7E+mpxt8a66TicZW=oNttNw@mail.gmail.com>

Hi Linus,

On Tue, Feb 22, 2022 at 4:27 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Mon, Feb 21, 2022 at 5:22 PM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> > The checker failed to validate all enum IDs in the description of a
> > register with fixed-width register fields, due to a miscalculation of
> > the number of described states: each register field of n bits can have
> > "1 << n" possible states, not "1".
> >
> > Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked
> > (SH-Mobile AG5 has more than 4000 enum IDs defined).
> >
> > Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts")
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > To be queued in renesas-pinctrl-for-v5.18.

And obviously I should have done s/sh-pfc/renesas/ in the subject line.
Will fix...

> I certainly trust you to generally do what is best for the Renesas drivers.

Thanks!

> I have a question about this checker infrastructure because it is obviously
> a piece of really valuable code for Renesas.
>
> How general is this checker? Do we have other drivers in the kernel that
> would benefit from it or is it completely Renesas-specific?
>
> If it has general value I think it should be moved to be one floor down,
> with the pinctrl framework, if possible. But I don't know the details.

Unfortunately it is completely Renesas-specific, and relies on the way
pins are configured in most (but not all) Renesas SoCs (both SH and
ARM).

I assume similar checks could be added to other pin control drivers,
especially if they are using groups.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds