From: Pranavkumar Sawargaonkar <psawargaonkar@apm.com> To: Rob Herring <robherring2@gmail.com> Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>, Feng Kan <fkan@apm.com>, Marc Zyngier <marc.zyngier@arm.com>, "jcm@redhat.com" <jcm@redhat.com>, "patches@apm.com" <patches@apm.com>, Will Deacon <will.deacon@arm.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, Tushar Jagad <tjagad@apm.com>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu> Subject: Re: [PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene Date: Tue, 24 Feb 2015 12:04:52 +0530 [thread overview] Message-ID: <CANFfpkQF-8Kzq-UoP=xLpkTafGn6ScyiEb6oCs-Lxygb+ummLA@mail.gmail.com> (raw) In-Reply-To: <CAL_JsqJ6E+05psDCXS7k74Mz-DgSEroQ2ODpe2Bp2_50fL3imA@mail.gmail.com> Hi Rob, On Mon, Feb 23, 2015 at 10:09 PM, Rob Herring <robherring2@gmail.com> wrote: > On Mon, Feb 23, 2015 at 6:07 AM, Christoffer Dall > <christoffer.dall@linaro.org> wrote: >> On Sat, Feb 21, 2015 at 03:56:17PM -0600, Rob Herring wrote: >>> On Thu, Feb 19, 2015 at 1:03 PM, Christoffer Dall >>> <christoffer.dall@linaro.org> wrote: >>> > On Thu, Feb 19, 2015 at 12:23:15PM -0600, Rob Herring wrote: >>> >> On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar >>> >> <psawargaonkar@apm.com> wrote: >>> >> > In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned >>> >> > in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page >>> >> > size due to size alignment checking in vgic driver for VCPU Control and >>> >> > VCPU register. >>> >> > >>> >> > This patch corrects the sizes to be inline with the hardware spec. >>> >> >>> >> This does not make sense. The GIC regions are still only 4 or 8KB and >>> >> the h/w description should reflect that. For implementations using >>> >> gic-400 and the addressing decode trick, the rest of the register >>> >> range is also not safe to access given it is multiple mapped. Also, >>> >> this wastes virtual space, but I guess we don't care on 64-bit. >>> >> >>> >> KVM should be fixed to only check base address alignment. Size >>> >> alignment does not matter (if it does, then you need to fix all >>> >> register blocks). >>> >> >>> > It matters if you want to ensure that the 64K page you are assigning to >>> > a guest for the GIC virtual CPU interface contains only GIC virtual CPU >>> > mappings, and not other random stuff that the guest is not allowed to >>> > touch. >>> >>> Good point. >>> >>> > How else should this be enforced? >>> >>> Rely on correct h/w design? You'll have to repeat this every time you >>> want to do pass-thru of a device. >>> >>> What do you do if 64K mapping is not supported? Fallback to emulation >>> of the CPU interface? >> >> Agree with Peter on these two points. >> >>> >>> Are there other DTSs that need to be fixed? >>> >> Not sure really, AMD Seattle works with 64K pages IIRC. > > Well, looks we have been inconsistent here: > > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- reg = <0x0 > 0xe1110000 0 0x1000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe112f000 0 0x2000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe1140000 0 0x10000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe1160000 0 0x10000>; > > arch/arm64/boot/dts/arm/juno.dts- reg = <0x0 0x2c010000 0 0x1000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c02f000 0 0x2000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c04f000 0 0x2000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c06f000 0 0x2000>; > > If we are going to use 64K sizes, can we have some consistency here > please. Which ranges really need 64KB sizes? It should only be the > VCPU interface. right? Why does XGene need 128K? If XGene is doing > address swizzling, then the CPU and VCPU base addresses are wrong. > Seattle is also wrong for the VCPU, but no one has noticed because we > don't use the DIR register IIRC. > > XGene should also add an "arm,gic-400" compatible string or something > XGene specific if in fact it is not GIC-400. X-Gene has gic-400 as an interrupt controller. Only thing is GIC pages are mapped at 64K boundary (with 64K page size) Hence CPU, VCPU interfaces has a size of 128K (2GIC pages) Regarding GICC_DIR, yes there is a problem which needs to be solved since the first page size is 64K. In XEN we already have a small fix to access GICC_DIR with 64K page offset instead of standard 4K. I remember a small discussion in this regard in past (http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266468.html) which was deferred at that time. Once this patch is accepted we can post RFC patch to address GICC_DIR and discuss further. > > I think perhaps we need a specific compatible property to indicate a > GIC-400 with address swizzling. While we could get away with using the > aliased addresses, that seems to be hard to get right and we may > regret not doing it in the long term. It would indicate at least it is > 64K page safe for example. > > Rob Thanks, Pranav
WARNING: multiple messages have this Message-ID (diff)
From: psawargaonkar@apm.com (Pranavkumar Sawargaonkar) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene Date: Tue, 24 Feb 2015 12:04:52 +0530 [thread overview] Message-ID: <CANFfpkQF-8Kzq-UoP=xLpkTafGn6ScyiEb6oCs-Lxygb+ummLA@mail.gmail.com> (raw) In-Reply-To: <CAL_JsqJ6E+05psDCXS7k74Mz-DgSEroQ2ODpe2Bp2_50fL3imA@mail.gmail.com> Hi Rob, On Mon, Feb 23, 2015 at 10:09 PM, Rob Herring <robherring2@gmail.com> wrote: > On Mon, Feb 23, 2015 at 6:07 AM, Christoffer Dall > <christoffer.dall@linaro.org> wrote: >> On Sat, Feb 21, 2015 at 03:56:17PM -0600, Rob Herring wrote: >>> On Thu, Feb 19, 2015 at 1:03 PM, Christoffer Dall >>> <christoffer.dall@linaro.org> wrote: >>> > On Thu, Feb 19, 2015 at 12:23:15PM -0600, Rob Herring wrote: >>> >> On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar >>> >> <psawargaonkar@apm.com> wrote: >>> >> > In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned >>> >> > in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page >>> >> > size due to size alignment checking in vgic driver for VCPU Control and >>> >> > VCPU register. >>> >> > >>> >> > This patch corrects the sizes to be inline with the hardware spec. >>> >> >>> >> This does not make sense. The GIC regions are still only 4 or 8KB and >>> >> the h/w description should reflect that. For implementations using >>> >> gic-400 and the addressing decode trick, the rest of the register >>> >> range is also not safe to access given it is multiple mapped. Also, >>> >> this wastes virtual space, but I guess we don't care on 64-bit. >>> >> >>> >> KVM should be fixed to only check base address alignment. Size >>> >> alignment does not matter (if it does, then you need to fix all >>> >> register blocks). >>> >> >>> > It matters if you want to ensure that the 64K page you are assigning to >>> > a guest for the GIC virtual CPU interface contains only GIC virtual CPU >>> > mappings, and not other random stuff that the guest is not allowed to >>> > touch. >>> >>> Good point. >>> >>> > How else should this be enforced? >>> >>> Rely on correct h/w design? You'll have to repeat this every time you >>> want to do pass-thru of a device. >>> >>> What do you do if 64K mapping is not supported? Fallback to emulation >>> of the CPU interface? >> >> Agree with Peter on these two points. >> >>> >>> Are there other DTSs that need to be fixed? >>> >> Not sure really, AMD Seattle works with 64K pages IIRC. > > Well, looks we have been inconsistent here: > > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- reg = <0x0 > 0xe1110000 0 0x1000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe112f000 0 0x2000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe1140000 0 0x10000>, > arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi- <0x0 > 0xe1160000 0 0x10000>; > > arch/arm64/boot/dts/arm/juno.dts- reg = <0x0 0x2c010000 0 0x1000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c02f000 0 0x2000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c04f000 0 0x2000>, > arch/arm64/boot/dts/arm/juno.dts- <0x0 0x2c06f000 0 0x2000>; > > If we are going to use 64K sizes, can we have some consistency here > please. Which ranges really need 64KB sizes? It should only be the > VCPU interface. right? Why does XGene need 128K? If XGene is doing > address swizzling, then the CPU and VCPU base addresses are wrong. > Seattle is also wrong for the VCPU, but no one has noticed because we > don't use the DIR register IIRC. > > XGene should also add an "arm,gic-400" compatible string or something > XGene specific if in fact it is not GIC-400. X-Gene has gic-400 as an interrupt controller. Only thing is GIC pages are mapped at 64K boundary (with 64K page size) Hence CPU, VCPU interfaces has a size of 128K (2GIC pages) Regarding GICC_DIR, yes there is a problem which needs to be solved since the first page size is 64K. In XEN we already have a small fix to access GICC_DIR with 64K page offset instead of standard 4K. I remember a small discussion in this regard in past (http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266468.html) which was deferred at that time. Once this patch is accepted we can post RFC patch to address GICC_DIR and discuss further. > > I think perhaps we need a specific compatible property to indicate a > GIC-400 with address swizzling. While we could get away with using the > aliased addresses, that seems to be hard to get right and we may > regret not doing it in the long term. It would indicate at least it is > 64K page safe for example. > > Rob Thanks, Pranav
next prev parent reply other threads:[~2015-02-24 6:34 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-01-27 7:03 [PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene Pranavkumar Sawargaonkar 2015-01-27 7:03 ` Pranavkumar Sawargaonkar 2015-02-19 15:51 ` Christoffer Dall 2015-02-19 15:51 ` Christoffer Dall [not found] ` <1422342206-4750-1-git-send-email-psawargaonkar-qTEPVZfXA3Y@public.gmane.org> 2015-01-27 9:32 ` Jon Masters 2015-01-27 9:32 ` Jon Masters 2015-02-11 4:09 ` Pranavkumar Sawargaonkar 2015-02-11 4:09 ` Pranavkumar Sawargaonkar 2015-02-19 18:23 ` Rob Herring 2015-02-19 18:23 ` Rob Herring [not found] ` <CAL_JsqJQcuX2cp50oHod-QAbhdMg48TaRP+gLGEO2kbFnQ3B+A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-02-19 19:03 ` Christoffer Dall 2015-02-19 19:03 ` Christoffer Dall 2015-02-21 21:56 ` Rob Herring 2015-02-21 21:56 ` Rob Herring [not found] ` <CAL_JsqLcBOC+AnVe7oATjg2g6Fz2vqwacu8QzS4tXMaxxOP_Xg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-02-21 23:58 ` Peter Maydell 2015-02-21 23:58 ` Peter Maydell 2015-02-23 12:07 ` Christoffer Dall 2015-02-23 12:07 ` Christoffer Dall 2015-02-23 12:24 ` Jon Masters 2015-02-23 12:24 ` Jon Masters 2015-02-23 16:39 ` Rob Herring 2015-02-23 16:39 ` Rob Herring 2015-02-24 6:34 ` Pranavkumar Sawargaonkar [this message] 2015-02-24 6:34 ` Pranavkumar Sawargaonkar [not found] ` <CANFfpkQF-8Kzq-UoP=xLpkTafGn6ScyiEb6oCs-Lxygb+ummLA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-02-24 14:30 ` Rob Herring 2015-02-24 14:30 ` Rob Herring [not found] ` <CAL_JsqLs4HdT6N=Vb4s--x3ugXKbWYQ5R2WGbiWFhhnYxnK-xw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-02-27 3:57 ` Pranavkumar Sawargaonkar 2015-02-27 3:57 ` Pranavkumar Sawargaonkar 2015-03-19 18:54 ` Marc Zyngier 2015-03-19 18:54 ` Marc Zyngier 2015-03-11 14:53 ` Marc Zyngier 2015-03-11 14:53 ` Marc Zyngier [not found] ` <550056FD.8060804-5wv7dgnIgG8@public.gmane.org> 2015-03-11 17:19 ` Feng Kan 2015-03-11 17:19 ` Feng Kan [not found] ` <CAL85gmCuB4LfNp+6B8cL9+emFqWPM6W9gevTzibyaAzL+7jVdg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-03-11 17:31 ` Marc Zyngier 2015-03-11 17:31 ` Marc Zyngier 2015-03-11 17:57 ` Feng Kan 2015-03-11 17:57 ` Feng Kan [not found] ` <CAL85gmDVfop1_roHyLTRzFY3BahzTWs7nwbpmZD7emFKcFHyLg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-03-11 18:17 ` Marc Zyngier 2015-03-11 18:17 ` Marc Zyngier [not found] ` <550086B9.4010001-5wv7dgnIgG8@public.gmane.org> 2015-03-12 3:52 ` Pranavkumar Sawargaonkar 2015-03-12 3:52 ` Pranavkumar Sawargaonkar [not found] ` <CANFfpkQ1QyWEGwwQx1g1By=uXvctJjF8AOO+uA5CFUgO4v9DFg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-03-12 9:25 ` Marc Zyngier 2015-03-12 9:25 ` Marc Zyngier
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