[PATCH 0/2] Add test to verify BDW workarounds

[PATCH 0/2] Add test to verify BDW workarounds

[Arun Siluvery]

Currently in BDW, workarounds are initialized in init_clock_gating() but
some of them are lost followed by a gpu reset. The solution is to apply
them in golden render state which keeps them valid when starting with an
uninitialized state after reset.

Arun Siluvery (2):
  tools/null_state_render: Add BDW workarounds to golden render state
  igt/gem_workarounds: igt to test workaround registers

 lib/intel_reg.h                               |  22 +++
 tests/Makefile.sources                        |   1 +
 tests/gem_workarounds.c                       | 238 ++++++++++++++++++++++++++
 tools/null_state_gen/intel_renderstate_gen8.c |  36 ++++
 4 files changed, 297 insertions(+)
 create mode 100644 tests/gem_workarounds.c

-- 
2.0.4

[PATCH 1/2] tools/null_state_render: Add BDW workarounds to golden

[Arun Siluvery]

Some workaround registers are part of register state context and they are
restored with every context switch so initializing them in golden render state
ensures that they are applied even when we start with an uninitialized context
or during hw initialization followed by a reset.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 lib/intel_reg.h                               | 22 ++++++++++++++++
 tools/null_state_gen/intel_renderstate_gen8.c | 36 +++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 4afec45..86175bb 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3599,11 +3599,33 @@ typedef enum {
 #define GEN8_ROW_CHICKEN		0xe4f0
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
 #define INSTRUCTION_SHOOTDOWN_DISABL	(1<<9)
 #define   STALL_DOP_GATING_DISABLE		(1<<5)
 #define FLOW_CONTROL_REGISTER_ENABLE	(1<<15)
 
 #define GEN7_ROW_CHICKEN2		0xe4f4
 #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
 #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
 
+#define HALF_SLICE_CHICKEN3		0xe184
+#define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
+#define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
+
+#define GEN7_HALF_SLICE_CHICKEN1	0xe100
+#define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE	(1<<10)
+
+#define COMMON_SLICE_CHICKEN2			0x7014
+# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
+
+/* GEN8 chicken */
+#define HDC_CHICKEN0				0x7300
+#define  HDC_FORCE_NON_COHERENT			(1<<4)
+
+#define GEN7_CACHE_MODE_1			0x7004 /* IVB+ */
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
+
+#define GEN7_GT_MODE	0x7008
+#define   GEN6_WIZ_HASHING(hi, lo)		(((hi) << 9) | ((lo) << 7))
+#define   GEN6_WIZ_HASHING_16x4			GEN6_WIZ_HASHING(1, 0)
+#define   GEN6_WIZ_HASHING_MASK			(GEN6_WIZ_HASHING(1, 1) << 16)
+
 #endif /* _I810_REG_H */
diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c
index 14690d2..8d61f03 100644
--- a/tools/null_state_gen/intel_renderstate_gen8.c
+++ b/tools/null_state_gen/intel_renderstate_gen8.c
@@ -696,20 +696,56 @@ static void gen8_emit_workarounds(struct intel_batchbuffer *batch)
 	/* WaDisablePartialInstShootdown:bdw */
 	/* WaDisableThreadStallDopClockGating:bdw */
 	/* FIXME: Unclear whether we really need this on production bdw. */
 
 	gen8_emit_write(batch, GEN8_ROW_CHICKEN,
 			_MASKED_BIT_ENABLE(INSTRUCTION_SHOOTDOWN_DISABL | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 					   STALL_DOP_GATING_DISABLE | FLOW_CONTROL_REGISTER_ENABLE));
 
 	/* WaDisableDopClockGating:bdw May not be needed for production */
 	gen8_emit_write(batch, GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
+	/*
+	 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
+	 * pre-production hardware
+	 */
+	gen8_emit_write(batch, HALF_SLICE_CHICKEN3,
+			_MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
+					   | GEN8_SAMPLER_POWER_BYPASS_DIS));
+
+	gen8_emit_write(batch, GEN7_HALF_SLICE_CHICKEN1,
+			_MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
+
+	gen8_emit_write(batch, COMMON_SLICE_CHICKEN2,
+			_MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
+
+	/* Use Force Non-Coherent whenever executing a 3D context. This is a
+	 * workaround for for a possible hang in the unlikely event a TLB
+	 * invalidation occurs during a PSD flush.
+	 */
+	gen8_emit_write(batch, HDC_CHICKEN0,
+			_MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
+
+	/* Wa4x4STCOptimizationDisable:bdw */
+	gen8_emit_write(batch, GEN7_CACHE_MODE_1,
+			_MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
+
+	/*
+	 * BSpec recommends 8x4 when MSAA is used,
+	 * however in practice 16x4 seems fastest.
+	 *
+	 * Note that PS/WM thread counts depend on the WIZ hashing
+	 * disable bit, which we don't touch here, but it's good
+	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+	 */
+	gen8_emit_write(batch, GEN7_GT_MODE,
+			GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 }
 
 int gen8_setup_null_render_state(struct intel_batchbuffer *batch)
 {
 	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
 	uint32_t scissor_state;
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
 	int ret;
 
-- 
2.0.4

[PATCH 2/2] igt/gem_workarounds: igt to test workaround registers

[Arun Siluvery]

Some of the workarounds are lost followed by a gpu reset, suspend/resume;
this patch adds a test which compares register state before and after
the test scenario.

This test currently verifies only bdw workarounds.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 tests/Makefile.sources  |   1 +
 tests/gem_workarounds.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 239 insertions(+)
 create mode 100644 tests/gem_workarounds.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0eb9369..a17acd1 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -127,20 +127,21 @@ TESTS_progs = \
 	gem_storedw_loop_vebox \
 	gem_threaded_access_tiled \
 	gem_tiled_fence_blits \
 	gem_tiled_pread \
 	gem_tiled_pread_pwrite \
 	gem_tiled_swapping \
 	gem_tiling_max_stride \
 	gem_unfence_active_buffers \
 	gem_unref_active_buffers \
 	gem_wait_render_timeout \
+	gem_workarounds \
 	gen3_mixed_blits \
 	gen3_render_linear_blits \
 	gen3_render_mixed_blits \
 	gen3_render_tiledx_blits \
 	gen3_render_tiledy_blits \
 	gen7_forcewake_mt \
 	kms_force_connector \
 	kms_sink_crc_basic \
 	kms_fence_pin_leak \
 	pm_psr \
diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
new file mode 100644
index 0000000..56bf4b1
--- /dev/null
+++ b/tests/gem_workarounds.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *  Arun Siluvery <arun.siluvery@linux.intel.com>
+ *
+ */
+
+#define _GNU_SOURCE
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <time.h>
+#include <signal.h>
+
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_aux.h"
+#include "intel_chipset.h"
+#include "intel_io.h"
+
+enum operation {
+	GPU_RESET = 0x01,
+	SUSPEND_RESUME = 0x02,
+};
+
+struct intel_wa_reg {
+	uint32_t addr;
+	uint32_t value;
+	uint32_t mask;
+};
+
+int drm_fd;
+uint32_t devid;
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+int num_wa;
+struct intel_wa_reg *wa_regs;
+
+
+static void test_hang_gpu(void)
+{
+	int retry_count = 30;
+	enum stop_ring_flags flags;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 gem_exec;
+	uint32_t b[2] = {MI_BATCH_BUFFER_END};
+
+	igt_assert(retry_count);
+	igt_set_stop_rings(STOP_RING_DEFAULTS);
+
+	memset(&gem_exec, 0, sizeof(gem_exec));
+	gem_exec.handle = gem_create(drm_fd, 4096);
+	gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = (uintptr_t)&gem_exec;
+	execbuf.buffer_count = 1;
+	execbuf.batch_len = sizeof(b);
+
+	drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
+
+	while(retry_count--) {
+		flags = igt_get_stop_rings();
+		if (flags == 0)
+			break;
+		printf("gpu hang not yet cleared, retries left %d\n", retry_count);
+		sleep(1);
+	}
+
+	flags = igt_get_stop_rings();
+	if (flags)
+		igt_set_stop_rings(STOP_RING_NONE);
+}
+
+static void test_suspend_resume(void)
+{
+	printf("Suspending the device ...\n");
+	igt_system_suspend_autoresume();
+}
+
+static void get_current_wa_data(struct intel_wa_reg **curr, int num)
+{
+	int i;
+	struct intel_wa_reg *ptr = NULL;
+
+	ptr = *curr;
+
+	intel_register_access_init(intel_get_pci_device(), 0);
+
+	for (i = 0; i < num; ++i) {
+		ptr[i].addr = wa_regs[i].addr;
+		ptr[i].value = intel_register_read(wa_regs[i].addr);
+		ptr[i].mask = wa_regs[i].mask;
+	}
+
+	intel_register_access_fini();
+}
+
+static void check_workarounds(enum operation op, int num)
+{
+	int i;
+	int fail_count = 0;
+	int status = 0;
+	struct intel_wa_reg *current_wa = NULL;
+
+	switch (op) {
+	case GPU_RESET:
+		test_hang_gpu();
+		break;
+
+	case SUSPEND_RESUME:
+		test_suspend_resume();
+		break;
+
+	default:
+		fail_count = 1;
+		goto out;
+	}
+
+	current_wa = malloc(num * sizeof(*current_wa));
+	igt_assert(current_wa);
+	get_current_wa_data(&current_wa, num);
+
+	printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
+	for (i = 0; i < num; ++i) {
+		status = (current_wa[i].value & current_wa[i].mask) !=
+			(wa_regs[i].value & wa_regs[i].mask);
+		if (status)
+			++fail_count;
+
+		printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
+		       current_wa[i].addr, wa_regs[i].value,
+		       current_wa[i].value, current_wa[i].mask,
+		       status ? "fail" : "success");
+	}
+
+out:
+	free(current_wa);
+	igt_assert(fail_count == 0);
+}
+
+int main(int argc, char **argv)
+{
+	igt_subtest_init(argc, argv);
+
+	igt_fixture {
+		int i;
+		int ret;
+		FILE *file;
+		int card_index;
+		const char *dri_path = "/sys/kernel/debug/dri";
+		char *filename = NULL;
+		char *line = NULL;
+		size_t line_size;
+
+		drm_fd = drm_open_any();
+
+		bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+		devid = intel_get_drm_devid(drm_fd);
+		batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+		card_index = drm_get_card();
+		igt_assert(card_index != -1);
+
+		ret = asprintf(&filename, "%s/%d/intel_wa_registers",
+			       dri_path, card_index);
+		igt_assert(ret > 0);
+
+		file = fopen(filename, "r");
+		igt_assert(file > 0);
+
+		ret = getline(&line, &line_size, file);
+		igt_assert(ret > 0);
+		sscanf(line, "Workarounds applied: %d", &num_wa);
+		igt_assert(num_wa > 0);
+
+		wa_regs = malloc(num_wa * sizeof(*wa_regs));
+
+		i = 0;
+		while(getline(&line, &line_size, file) > 0) {
+			sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
+			       &wa_regs[i].addr, &wa_regs[i].value,
+			       &wa_regs[i].mask);
+			++i;
+		}
+
+		free(line);
+		fclose(file);
+	}
+
+	igt_subtest("check-workaround-data-after-reset") {
+		if (IS_BROADWELL(devid))
+			check_workarounds(GPU_RESET, num_wa);
+		else
+			igt_skip_on("No Workaround table available!!\n");
+	}
+
+	igt_subtest("check-workaround-data-after-suspend-resume") {
+		if (IS_BROADWELL(devid))
+			check_workarounds(SUSPEND_RESUME, num_wa);
+		else
+			igt_skip_on("No Workaround table available!!\n");
+	}
+
+	free(wa_regs);
+
+	close(drm_fd);
+	igt_exit();
+}
-- 
2.0.4

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Re: [PATCH 2/2] igt/gem_workarounds: igt to test workaround registers

[Thomas Wood]

On 20 August 2014 15:52, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
> Some of the workarounds are lost followed by a gpu reset, suspend/resume;
> this patch adds a test which compares register state before and after
> the test scenario.
>
> This test currently verifies only bdw workarounds.

Just a few points from an igt perspective: could you add the binary to
tests/.gitignore and perhaps consider using igt_debug or igt_info
instead of printf? There are also some debugfs helpers in igt_debugfs
to open/fopen debugfs files. There are also a few other tests that
implement GPU hangs, so it would be good to share code to do this
between them, but not essential for this patch.


>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  tests/Makefile.sources  |   1 +
>  tests/gem_workarounds.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 239 insertions(+)
>  create mode 100644 tests/gem_workarounds.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0eb9369..a17acd1 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -127,20 +127,21 @@ TESTS_progs = \
>         gem_storedw_loop_vebox \
>         gem_threaded_access_tiled \
>         gem_tiled_fence_blits \
>         gem_tiled_pread \
>         gem_tiled_pread_pwrite \
>         gem_tiled_swapping \
>         gem_tiling_max_stride \
>         gem_unfence_active_buffers \
>         gem_unref_active_buffers \
>         gem_wait_render_timeout \
> +       gem_workarounds \
>         gen3_mixed_blits \
>         gen3_render_linear_blits \
>         gen3_render_mixed_blits \
>         gen3_render_tiledx_blits \
>         gen3_render_tiledy_blits \
>         gen7_forcewake_mt \
>         kms_force_connector \
>         kms_sink_crc_basic \
>         kms_fence_pin_leak \
>         pm_psr \
> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
> new file mode 100644
> index 0000000..56bf4b1
> --- /dev/null
> +++ b/tests/gem_workarounds.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *  Arun Siluvery <arun.siluvery@linux.intel.com>
> + *
> + */
> +
> +#define _GNU_SOURCE
> +#include <stdbool.h>
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <fcntl.h>
> +#include <inttypes.h>
> +#include <errno.h>
> +#include <sys/stat.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <time.h>
> +#include <signal.h>
> +
> +#include "ioctl_wrappers.h"
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_aux.h"
> +#include "intel_chipset.h"
> +#include "intel_io.h"
> +
> +enum operation {
> +       GPU_RESET = 0x01,
> +       SUSPEND_RESUME = 0x02,
> +};
> +
> +struct intel_wa_reg {
> +       uint32_t addr;
> +       uint32_t value;
> +       uint32_t mask;
> +};
> +
> +int drm_fd;
> +uint32_t devid;
> +static drm_intel_bufmgr *bufmgr;
> +struct intel_batchbuffer *batch;
> +int num_wa;
> +struct intel_wa_reg *wa_regs;
> +
> +
> +static void test_hang_gpu(void)
> +{
> +       int retry_count = 30;
> +       enum stop_ring_flags flags;
> +       struct drm_i915_gem_execbuffer2 execbuf;
> +       struct drm_i915_gem_exec_object2 gem_exec;
> +       uint32_t b[2] = {MI_BATCH_BUFFER_END};
> +
> +       igt_assert(retry_count);
> +       igt_set_stop_rings(STOP_RING_DEFAULTS);
> +
> +       memset(&gem_exec, 0, sizeof(gem_exec));
> +       gem_exec.handle = gem_create(drm_fd, 4096);
> +       gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
> +
> +       memset(&execbuf, 0, sizeof(execbuf));
> +       execbuf.buffers_ptr = (uintptr_t)&gem_exec;
> +       execbuf.buffer_count = 1;
> +       execbuf.batch_len = sizeof(b);
> +
> +       drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
> +
> +       while(retry_count--) {
> +               flags = igt_get_stop_rings();
> +               if (flags == 0)
> +                       break;
> +               printf("gpu hang not yet cleared, retries left %d\n", retry_count);
> +               sleep(1);
> +       }
> +
> +       flags = igt_get_stop_rings();
> +       if (flags)
> +               igt_set_stop_rings(STOP_RING_NONE);
> +}
> +
> +static void test_suspend_resume(void)
> +{
> +       printf("Suspending the device ...\n");
> +       igt_system_suspend_autoresume();
> +}
> +
> +static void get_current_wa_data(struct intel_wa_reg **curr, int num)
> +{
> +       int i;
> +       struct intel_wa_reg *ptr = NULL;
> +
> +       ptr = *curr;
> +
> +       intel_register_access_init(intel_get_pci_device(), 0);
> +
> +       for (i = 0; i < num; ++i) {
> +               ptr[i].addr = wa_regs[i].addr;
> +               ptr[i].value = intel_register_read(wa_regs[i].addr);
> +               ptr[i].mask = wa_regs[i].mask;
> +       }
> +
> +       intel_register_access_fini();
> +}
> +
> +static void check_workarounds(enum operation op, int num)
> +{
> +       int i;
> +       int fail_count = 0;
> +       int status = 0;
> +       struct intel_wa_reg *current_wa = NULL;
> +
> +       switch (op) {
> +       case GPU_RESET:
> +               test_hang_gpu();
> +               break;
> +
> +       case SUSPEND_RESUME:
> +               test_suspend_resume();
> +               break;
> +
> +       default:
> +               fail_count = 1;
> +               goto out;
> +       }
> +
> +       current_wa = malloc(num * sizeof(*current_wa));
> +       igt_assert(current_wa);
> +       get_current_wa_data(&current_wa, num);
> +
> +       printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
> +       for (i = 0; i < num; ++i) {
> +               status = (current_wa[i].value & current_wa[i].mask) !=
> +                       (wa_regs[i].value & wa_regs[i].mask);
> +               if (status)
> +                       ++fail_count;
> +
> +               printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
> +                      current_wa[i].addr, wa_regs[i].value,
> +                      current_wa[i].value, current_wa[i].mask,
> +                      status ? "fail" : "success");
> +       }
> +
> +out:
> +       free(current_wa);
> +       igt_assert(fail_count == 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> +       igt_subtest_init(argc, argv);
> +
> +       igt_fixture {
> +               int i;
> +               int ret;
> +               FILE *file;
> +               int card_index;
> +               const char *dri_path = "/sys/kernel/debug/dri";
> +               char *filename = NULL;
> +               char *line = NULL;
> +               size_t line_size;
> +
> +               drm_fd = drm_open_any();
> +
> +               bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +               devid = intel_get_drm_devid(drm_fd);
> +               batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> +               card_index = drm_get_card();
> +               igt_assert(card_index != -1);
> +
> +               ret = asprintf(&filename, "%s/%d/intel_wa_registers",
> +                              dri_path, card_index);
> +               igt_assert(ret > 0);
> +
> +               file = fopen(filename, "r");
> +               igt_assert(file > 0);
> +
> +               ret = getline(&line, &line_size, file);
> +               igt_assert(ret > 0);
> +               sscanf(line, "Workarounds applied: %d", &num_wa);
> +               igt_assert(num_wa > 0);
> +
> +               wa_regs = malloc(num_wa * sizeof(*wa_regs));
> +
> +               i = 0;
> +               while(getline(&line, &line_size, file) > 0) {
> +                       sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
> +                              &wa_regs[i].addr, &wa_regs[i].value,
> +                              &wa_regs[i].mask);
> +                       ++i;
> +               }
> +
> +               free(line);
> +               fclose(file);
> +       }
> +
> +       igt_subtest("check-workaround-data-after-reset") {
> +               if (IS_BROADWELL(devid))
> +                       check_workarounds(GPU_RESET, num_wa);
> +               else
> +                       igt_skip_on("No Workaround table available!!\n");
> +       }
> +
> +       igt_subtest("check-workaround-data-after-suspend-resume") {
> +               if (IS_BROADWELL(devid))
> +                       check_workarounds(SUSPEND_RESUME, num_wa);
> +               else
> +                       igt_skip_on("No Workaround table available!!\n");
> +       }
> +
> +       free(wa_regs);
> +
> +       close(drm_fd);
> +       igt_exit();
> +}
> --
> 2.0.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 2/2] igt/gem_workarounds: igt to test workaround registers

[Siluvery, Arun]

On 20/08/2014 16:37, Thomas Wood wrote:
> On 20 August 2014 15:52, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
>> Some of the workarounds are lost followed by a gpu reset, suspend/resume;
>> this patch adds a test which compares register state before and after
>> the test scenario.
>>
>> This test currently verifies only bdw workarounds.
>
> Just a few points from an igt perspective: could you add the binary to
> tests/.gitignore and perhaps consider using igt_debug or igt_info
> instead of printf? There are also some debugfs helpers in igt_debugfs

Thank you for the comments, corrected the patch locally, will send the 
updated version along with any other comments.

regards
Arun

> to open/fopen debugfs files. There are also a few other tests that
> implement GPU hangs, so it would be good to share code to do this
> between them, but not essential for this patch.
>

>
>>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   tests/Makefile.sources  |   1 +
>>   tests/gem_workarounds.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 239 insertions(+)
>>   create mode 100644 tests/gem_workarounds.c
>>
>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>> index 0eb9369..a17acd1 100644
>> --- a/tests/Makefile.sources
>> +++ b/tests/Makefile.sources
>> @@ -127,20 +127,21 @@ TESTS_progs = \
>>          gem_storedw_loop_vebox \
>>          gem_threaded_access_tiled \
>>          gem_tiled_fence_blits \
>>          gem_tiled_pread \
>>          gem_tiled_pread_pwrite \
>>          gem_tiled_swapping \
>>          gem_tiling_max_stride \
>>          gem_unfence_active_buffers \
>>          gem_unref_active_buffers \
>>          gem_wait_render_timeout \
>> +       gem_workarounds \
>>          gen3_mixed_blits \
>>          gen3_render_linear_blits \
>>          gen3_render_mixed_blits \
>>          gen3_render_tiledx_blits \
>>          gen3_render_tiledy_blits \
>>          gen7_forcewake_mt \
>>          kms_force_connector \
>>          kms_sink_crc_basic \
>>          kms_fence_pin_leak \
>>          pm_psr \
>> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
>> new file mode 100644
>> index 0000000..56bf4b1
>> --- /dev/null
>> +++ b/tests/gem_workarounds.c
>> @@ -0,0 +1,238 @@
>> +/*
>> + * Copyright © 2014 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + * Authors:
>> + *  Arun Siluvery <arun.siluvery@linux.intel.com>
>> + *
>> + */
>> +
>> +#define _GNU_SOURCE
>> +#include <stdbool.h>
>> +#include <unistd.h>
>> +#include <stdlib.h>
>> +#include <stdio.h>
>> +#include <string.h>
>> +#include <fcntl.h>
>> +#include <inttypes.h>
>> +#include <errno.h>
>> +#include <sys/stat.h>
>> +#include <sys/ioctl.h>
>> +#include <sys/mman.h>
>> +#include <time.h>
>> +#include <signal.h>
>> +
>> +#include "ioctl_wrappers.h"
>> +#include "drmtest.h"
>> +#include "igt_debugfs.h"
>> +#include "igt_aux.h"
>> +#include "intel_chipset.h"
>> +#include "intel_io.h"
>> +
>> +enum operation {
>> +       GPU_RESET = 0x01,
>> +       SUSPEND_RESUME = 0x02,
>> +};
>> +
>> +struct intel_wa_reg {
>> +       uint32_t addr;
>> +       uint32_t value;
>> +       uint32_t mask;
>> +};
>> +
>> +int drm_fd;
>> +uint32_t devid;
>> +static drm_intel_bufmgr *bufmgr;
>> +struct intel_batchbuffer *batch;
>> +int num_wa;
>> +struct intel_wa_reg *wa_regs;
>> +
>> +
>> +static void test_hang_gpu(void)
>> +{
>> +       int retry_count = 30;
>> +       enum stop_ring_flags flags;
>> +       struct drm_i915_gem_execbuffer2 execbuf;
>> +       struct drm_i915_gem_exec_object2 gem_exec;
>> +       uint32_t b[2] = {MI_BATCH_BUFFER_END};
>> +
>> +       igt_assert(retry_count);
>> +       igt_set_stop_rings(STOP_RING_DEFAULTS);
>> +
>> +       memset(&gem_exec, 0, sizeof(gem_exec));
>> +       gem_exec.handle = gem_create(drm_fd, 4096);
>> +       gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
>> +
>> +       memset(&execbuf, 0, sizeof(execbuf));
>> +       execbuf.buffers_ptr = (uintptr_t)&gem_exec;
>> +       execbuf.buffer_count = 1;
>> +       execbuf.batch_len = sizeof(b);
>> +
>> +       drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
>> +
>> +       while(retry_count--) {
>> +               flags = igt_get_stop_rings();
>> +               if (flags == 0)
>> +                       break;
>> +               printf("gpu hang not yet cleared, retries left %d\n", retry_count);
>> +               sleep(1);
>> +       }
>> +
>> +       flags = igt_get_stop_rings();
>> +       if (flags)
>> +               igt_set_stop_rings(STOP_RING_NONE);
>> +}
>> +
>> +static void test_suspend_resume(void)
>> +{
>> +       printf("Suspending the device ...\n");
>> +       igt_system_suspend_autoresume();
>> +}
>> +
>> +static void get_current_wa_data(struct intel_wa_reg **curr, int num)
>> +{
>> +       int i;
>> +       struct intel_wa_reg *ptr = NULL;
>> +
>> +       ptr = *curr;
>> +
>> +       intel_register_access_init(intel_get_pci_device(), 0);
>> +
>> +       for (i = 0; i < num; ++i) {
>> +               ptr[i].addr = wa_regs[i].addr;
>> +               ptr[i].value = intel_register_read(wa_regs[i].addr);
>> +               ptr[i].mask = wa_regs[i].mask;
>> +       }
>> +
>> +       intel_register_access_fini();
>> +}
>> +
>> +static void check_workarounds(enum operation op, int num)
>> +{
>> +       int i;
>> +       int fail_count = 0;
>> +       int status = 0;
>> +       struct intel_wa_reg *current_wa = NULL;
>> +
>> +       switch (op) {
>> +       case GPU_RESET:
>> +               test_hang_gpu();
>> +               break;
>> +
>> +       case SUSPEND_RESUME:
>> +               test_suspend_resume();
>> +               break;
>> +
>> +       default:
>> +               fail_count = 1;
>> +               goto out;
>> +       }
>> +
>> +       current_wa = malloc(num * sizeof(*current_wa));
>> +       igt_assert(current_wa);
>> +       get_current_wa_data(&current_wa, num);
>> +
>> +       printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
>> +       for (i = 0; i < num; ++i) {
>> +               status = (current_wa[i].value & current_wa[i].mask) !=
>> +                       (wa_regs[i].value & wa_regs[i].mask);
>> +               if (status)
>> +                       ++fail_count;
>> +
>> +               printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
>> +                      current_wa[i].addr, wa_regs[i].value,
>> +                      current_wa[i].value, current_wa[i].mask,
>> +                      status ? "fail" : "success");
>> +       }
>> +
>> +out:
>> +       free(current_wa);
>> +       igt_assert(fail_count == 0);
>> +}
>> +
>> +int main(int argc, char **argv)
>> +{
>> +       igt_subtest_init(argc, argv);
>> +
>> +       igt_fixture {
>> +               int i;
>> +               int ret;
>> +               FILE *file;
>> +               int card_index;
>> +               const char *dri_path = "/sys/kernel/debug/dri";
>> +               char *filename = NULL;
>> +               char *line = NULL;
>> +               size_t line_size;
>> +
>> +               drm_fd = drm_open_any();
>> +
>> +               bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
>> +               devid = intel_get_drm_devid(drm_fd);
>> +               batch = intel_batchbuffer_alloc(bufmgr, devid);
>> +
>> +               card_index = drm_get_card();
>> +               igt_assert(card_index != -1);
>> +
>> +               ret = asprintf(&filename, "%s/%d/intel_wa_registers",
>> +                              dri_path, card_index);
>> +               igt_assert(ret > 0);
>> +
>> +               file = fopen(filename, "r");
>> +               igt_assert(file > 0);
>> +
>> +               ret = getline(&line, &line_size, file);
>> +               igt_assert(ret > 0);
>> +               sscanf(line, "Workarounds applied: %d", &num_wa);
>> +               igt_assert(num_wa > 0);
>> +
>> +               wa_regs = malloc(num_wa * sizeof(*wa_regs));
>> +
>> +               i = 0;
>> +               while(getline(&line, &line_size, file) > 0) {
>> +                       sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
>> +                              &wa_regs[i].addr, &wa_regs[i].value,
>> +                              &wa_regs[i].mask);
>> +                       ++i;
>> +               }
>> +
>> +               free(line);
>> +               fclose(file);
>> +       }
>> +
>> +       igt_subtest("check-workaround-data-after-reset") {
>> +               if (IS_BROADWELL(devid))
>> +                       check_workarounds(GPU_RESET, num_wa);
>> +               else
>> +                       igt_skip_on("No Workaround table available!!\n");
>> +       }
>> +
>> +       igt_subtest("check-workaround-data-after-suspend-resume") {
>> +               if (IS_BROADWELL(devid))
>> +                       check_workarounds(SUSPEND_RESUME, num_wa);
>> +               else
>> +                       igt_skip_on("No Workaround table available!!\n");
>> +       }
>> +
>> +       free(wa_regs);
>> +
>> +       close(drm_fd);
>> +       igt_exit();
>> +}
>> --
>> 2.0.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>

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Re: [PATCH 2/2] igt/gem_workarounds: igt to test workaround registers

[Daniel Vetter]

On Wed, Aug 20, 2014 at 03:52:12PM +0100, Arun Siluvery wrote:
> Some of the workarounds are lost followed by a gpu reset, suspend/resume;
> this patch adds a test which compares register state before and after
> the test scenario.
> 
> This test currently verifies only bdw workarounds.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

On top of Thomas' comments about using igt infrastructure some more below.

> ---
>  tests/Makefile.sources  |   1 +
>  tests/gem_workarounds.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 239 insertions(+)
>  create mode 100644 tests/gem_workarounds.c
> 
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0eb9369..a17acd1 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -127,20 +127,21 @@ TESTS_progs = \
>  	gem_storedw_loop_vebox \
>  	gem_threaded_access_tiled \
>  	gem_tiled_fence_blits \
>  	gem_tiled_pread \
>  	gem_tiled_pread_pwrite \
>  	gem_tiled_swapping \
>  	gem_tiling_max_stride \
>  	gem_unfence_active_buffers \
>  	gem_unref_active_buffers \
>  	gem_wait_render_timeout \
> +	gem_workarounds \
>  	gen3_mixed_blits \
>  	gen3_render_linear_blits \
>  	gen3_render_mixed_blits \
>  	gen3_render_tiledx_blits \
>  	gen3_render_tiledy_blits \
>  	gen7_forcewake_mt \
>  	kms_force_connector \
>  	kms_sink_crc_basic \
>  	kms_fence_pin_leak \
>  	pm_psr \
> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
> new file mode 100644
> index 0000000..56bf4b1
> --- /dev/null
> +++ b/tests/gem_workarounds.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *  Arun Siluvery <arun.siluvery@linux.intel.com>
> + *
> + */
> +
> +#define _GNU_SOURCE
> +#include <stdbool.h>
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <fcntl.h>
> +#include <inttypes.h>
> +#include <errno.h>
> +#include <sys/stat.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <time.h>
> +#include <signal.h>
> +
> +#include "ioctl_wrappers.h"
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_aux.h"
> +#include "intel_chipset.h"
> +#include "intel_io.h"
> +
> +enum operation {
> +	GPU_RESET = 0x01,
> +	SUSPEND_RESUME = 0x02,
> +};
> +
> +struct intel_wa_reg {
> +	uint32_t addr;
> +	uint32_t value;
> +	uint32_t mask;
> +};
> +
> +int drm_fd;
> +uint32_t devid;
> +static drm_intel_bufmgr *bufmgr;
> +struct intel_batchbuffer *batch;
> +int num_wa;
> +struct intel_wa_reg *wa_regs;
> +
> +
> +static void test_hang_gpu(void)
> +{
> +	int retry_count = 30;
> +	enum stop_ring_flags flags;
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct drm_i915_gem_exec_object2 gem_exec;
> +	uint32_t b[2] = {MI_BATCH_BUFFER_END};
> +
> +	igt_assert(retry_count);
> +	igt_set_stop_rings(STOP_RING_DEFAULTS);
> +
> +	memset(&gem_exec, 0, sizeof(gem_exec));
> +	gem_exec.handle = gem_create(drm_fd, 4096);
> +	gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = (uintptr_t)&gem_exec;
> +	execbuf.buffer_count = 1;
> +	execbuf.batch_len = sizeof(b);
> +
> +	drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
> +
> +	while(retry_count--) {
> +		flags = igt_get_stop_rings();
> +		if (flags == 0)
> +			break;
> +		printf("gpu hang not yet cleared, retries left %d\n", retry_count);
> +		sleep(1);
> +	}
> +
> +	flags = igt_get_stop_rings();
> +	if (flags)
> +		igt_set_stop_rings(STOP_RING_NONE);
> +}
> +
> +static void test_suspend_resume(void)
> +{
> +	printf("Suspending the device ...\n");
> +	igt_system_suspend_autoresume();
> +}
> +
> +static void get_current_wa_data(struct intel_wa_reg **curr, int num)
> +{
> +	int i;
> +	struct intel_wa_reg *ptr = NULL;
> +
> +	ptr = *curr;
> +
> +	intel_register_access_init(intel_get_pci_device(), 0);
> +
> +	for (i = 0; i < num; ++i) {
> +		ptr[i].addr = wa_regs[i].addr;
> +		ptr[i].value = intel_register_read(wa_regs[i].addr);
> +		ptr[i].mask = wa_regs[i].mask;
> +	}
> +
> +	intel_register_access_fini();
> +}
> +
> +static void check_workarounds(enum operation op, int num)
> +{
> +	int i;
> +	int fail_count = 0;
> +	int status = 0;
> +	struct intel_wa_reg *current_wa = NULL;
> +
> +	switch (op) {
> +	case GPU_RESET:
> +		test_hang_gpu();
> +		break;
> +
> +	case SUSPEND_RESUME:
> +		test_suspend_resume();
> +		break;
> +
> +	default:
> +		fail_count = 1;
> +		goto out;
> +	}
> +
> +	current_wa = malloc(num * sizeof(*current_wa));
> +	igt_assert(current_wa);
> +	get_current_wa_data(&current_wa, num);
> +
> +	printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
> +	for (i = 0; i < num; ++i) {
> +		status = (current_wa[i].value & current_wa[i].mask) !=
> +			(wa_regs[i].value & wa_regs[i].mask);
> +		if (status)
> +			++fail_count;
> +
> +		printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
> +		       current_wa[i].addr, wa_regs[i].value,
> +		       current_wa[i].value, current_wa[i].mask,
> +		       status ? "fail" : "success");
> +	}
> +
> +out:
> +	free(current_wa);
> +	igt_assert(fail_count == 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> +	igt_subtest_init(argc, argv);

Just use an igt_main block.

> +
> +	igt_fixture {
> +		int i;
> +		int ret;
> +		FILE *file;
> +		int card_index;
> +		const char *dri_path = "/sys/kernel/debug/dri";
> +		char *filename = NULL;
> +		char *line = NULL;
> +		size_t line_size;
> +
> +		drm_fd = drm_open_any();
> +
> +		bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +		devid = intel_get_drm_devid(drm_fd);
> +		batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> +		card_index = drm_get_card();
> +		igt_assert(card_index != -1);
> +
> +		ret = asprintf(&filename, "%s/%d/intel_wa_registers",
> +			       dri_path, card_index);
> +		igt_assert(ret > 0);
> +
> +		file = fopen(filename, "r");
> +		igt_assert(file > 0);
> +
> +		ret = getline(&line, &line_size, file);
> +		igt_assert(ret > 0);
> +		sscanf(line, "Workarounds applied: %d", &num_wa);
> +		igt_assert(num_wa > 0);
> +
> +		wa_regs = malloc(num_wa * sizeof(*wa_regs));
> +
> +		i = 0;
> +		while(getline(&line, &line_size, file) > 0) {
> +			sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
> +			       &wa_regs[i].addr, &wa_regs[i].value,
> +			       &wa_regs[i].mask);
> +			++i;
> +		}
> +
> +		free(line);
> +		fclose(file);
> +	}
> +
> +	igt_subtest("check-workaround-data-after-reset") {
> +		if (IS_BROADWELL(devid))
> +			check_workarounds(GPU_RESET, num_wa);
> +		else
> +			igt_skip_on("No Workaround table available!!\n");
> +	}
> +
> +	igt_subtest("check-workaround-data-after-suspend-resume") {
> +		if (IS_BROADWELL(devid))
> +			check_workarounds(SUSPEND_RESUME, num_wa);
> +		else
> +			igt_skip_on("No Workaround table available!!\n");
> +	}
> +
> +	free(wa_regs);
> +
> +	close(drm_fd);

The above two need to be in an igt_fixture. Otherwise you break test
enumeration a bit - run the test with <binary> --list-subtests. We
probably need a basic acceptance test for this stuff ...
-Daniel


> +	igt_exit();
> +}
> -- 
> 2.0.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch