[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

Issues were found during internal QA phase.

Stefan Chulski (10):
  net: mvpp2x: Add GPIO configuration support
  net: mvpp2x: fix phy connected to wrong mdio issue
  net: mvpp2x: Enable GoP packet padding in TX
  net: mvpp2x: fix BM configuration overrun issue
  net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
  net: mvpp2x: remove MBUS configurations from MvPP22 driver
  net: mvpp2x: Remove IRQ configuration from u-boot
  net: mvpp2x: Set BM pool high address
  net: mvpp2x: remove TX drain from transmit routine
  net: mvpp2x: Set BM poll size once during priv probe

 drivers/net/mvpp2.c | 189 ++++++++++++++++++++++++++--------------------------
 1 file changed, 94 insertions(+), 95 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH 01/10] net: mvpp2x: Add GPIO configuration support

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.

Change-Id: I3165545b276a3590399d1ac66b1e20d4544212c6
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39023
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1b46218..2198b73 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -30,6 +30,7 @@
 #include <asm/arch/soc.h>
 #include <linux/compat.h>
 #include <linux/mbus.h>
+#include <asm-generic/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -985,6 +986,10 @@ struct mvpp2_port {
 	phy_interface_t phy_interface;
 	int phy_node;
 	int phyaddr;
+#ifdef CONFIG_DM_GPIO
+	struct gpio_desc phy_reset_gpio;
+	struct gpio_desc phy_tx_disable_gpio;
+#endif
 	int init;
 	unsigned int link;
 	unsigned int duplex;
@@ -4765,6 +4770,13 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_DM_GPIO
+	gpio_request_by_name(dev, "phy-reset-gpios", 0,
+			     &port->phy_reset_gpio, GPIOD_IS_OUT);
+	gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
+			     &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
+#endif
+
 	/*
 	 * ToDo:
 	 * Not sure if this DT property "phy-speed" will get accepted, so
@@ -4786,6 +4798,21 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 	return 0;
 }
 
+#ifdef CONFIG_DM_GPIO
+/* Port GPIO initialization */
+static void mvpp2_gpio_init(struct mvpp2_port *port)
+{
+	if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
+		dm_gpio_set_value(&port->phy_reset_gpio, 0);
+		udelay(1000);
+		dm_gpio_set_value(&port->phy_reset_gpio, 1);
+	}
+
+	if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
+		dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
+}
+#endif
+
 /* Ports initialization */
 static int mvpp2_port_probe(struct udevice *dev,
 			    struct mvpp2_port *port,
@@ -4804,6 +4831,10 @@ static int mvpp2_port_probe(struct udevice *dev,
 	}
 	mvpp2_port_power_up(port);
 
+#ifdef CONFIG_DM_GPIO
+	mvpp2_gpio_init(port);
+#endif
+
 	priv->port_list[port->id] = port;
 	return 0;
 }
-- 
1.9.1

[U-Boot] [PATCH 01/10] net: mvpp2x: Add GPIO configuration support

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> This patch add GPIO configuration support in mvpp2x driver.
> Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
> be set in device tree.
>
> Change-Id: I3165545b276a3590399d1ac66b1e20d4544212c6
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39023
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 02/10] net: mvpp2x: fix phy connected to wrong mdio issue

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

This WA for mdio issue. U-boot 2017 don't have mdio driver
and on MACHIATOBin board ports from CP1 connected to mdio on
CP0. WA is to get mdio address from phy handler parent base address.
WA should be removed after mdio driver implementation.

Change-Id: Ice33c318a2872e750c8a2004763e6b2198c0537e
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39032
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2198b73..1264f14 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -31,6 +31,7 @@
 #include <linux/compat.h>
 #include <linux/mbus.h>
 #include <asm-generic/gpio.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -4739,10 +4740,11 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 {
 	int port_node = dev_of_offset(dev);
 	const char *phy_mode_str;
-	int phy_node;
+	int phy_node, mdio_off, cp_node;
 	u32 id;
 	u32 phyaddr = 0;
 	int phy_mode = -1;
+	u64 mdio_addr;
 
 	phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
 
@@ -4752,6 +4754,28 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
 			dev_err(&pdev->dev, "could not find phy address\n");
 			return -1;
 		}
+		mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
+
+		/* TODO: This WA for mdio issue. U-boot 2017 don't have
+		 * mdio driver and on MACHIATOBin board ports from CP1
+		 * connected to mdio on CP0.
+		 * WA is to get mdio address from phy handler parent
+		 * base address. WA should be removed after
+		 * mdio driver implementation.
+		 */
+		mdio_addr = fdtdec_get_uint(gd->fdt_blob,
+					    mdio_off, "reg", 0);
+
+		cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
+		mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
+						  cp_node);
+
+		port->priv->mdio_base = (void *)mdio_addr;
+
+		if (port->priv->mdio_base < 0) {
+			dev_err(&pdev->dev, "could not find mdio base address\n");
+			return -1;
+		}
 	} else {
 		phy_node = 0;
 	}
-- 
1.9.1

[U-Boot] [PATCH 02/10] net: mvpp2x: fix phy connected to wrong mdio issue

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> This WA for mdio issue. U-boot 2017 don't have mdio driver
> and on MACHIATOBin board ports from CP1 connected to mdio on
> CP0. WA is to get mdio address from phy handler parent base address.
> WA should be removed after mdio driver implementation.
>
> Change-Id: Ice33c318a2872e750c8a2004763e6b2198c0537e
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39032
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Igal Liberman <igall@marvell.com>

This is a pretty bad commit message. Any chance of fixing the grammar
and removing unknown (to me) acronyms? What is "WA"?

Also, drop the internal references (Change-Id and Reviewed-on).

Thanks,
-Joe

[U-Boot] [PATCH 03/10] net: mvpp2x: Enable GoP packet padding in TX

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

This patch enable padding of packets shorter than 64B in TX(set by default).
Disabling of padding cause crushes on MACCIATO board.
Regarding to GoP instruction padding should be enabled.

Change-Id: Iceaa1bd8a3543795463938d1a8d561f4ecc29234
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39270
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1264f14..3083111 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3063,10 +3063,6 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
 	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
 	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
 
-	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
-	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
-	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
 	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
 	/*
 	 * Configure GIG MAC to 1000Base-X mode connected to a fiber
@@ -3109,10 +3105,6 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
 	val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
 	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
 
-	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
-	val |= MVPP2_GMAC_PORT_DIS_PADING_MASK;
-	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
 	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
 	/* configure GIG MAC to SGMII mode */
 	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
@@ -3151,10 +3143,6 @@ static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
 	val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
 	writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
 
-	val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
-	val &= ~MVPP2_GMAC_PORT_DIS_PADING_MASK;
-	writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
-
 	val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
 	/* configure GIG MAC to SGMII mode */
 	val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
-- 
1.9.1

[U-Boot] [PATCH 03/10] net: mvpp2x: Enable GoP packet padding in TX

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> This patch enable padding of packets shorter than 64B in TX(set by default).

enable -> enables

> Disabling of padding cause crushes on MACCIATO board.

cause -> causes
crushes -> crashes

> Regarding to GoP instruction padding should be enabled.

Huh?

>
> Change-Id: Iceaa1bd8a3543795463938d1a8d561f4ecc29234
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39270
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Igal Liberman <igall@marvell.com>
> ---
>  drivers/net/mvpp2.c | 12 ------------
>  1 file changed, 12 deletions(-)

[U-Boot] [PATCH 04/10] net: mvpp2x: fix BM configuration overrun issue

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

Issue:
BM counters were overran by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.

Fix:
Add CP level flags to call init and remove procedure once per CP.

Change-Id: I7fa24704e1feadb079d7dc3a19a0b92b3b69b238
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39400
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 3083111..af3c3ef 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -67,6 +67,12 @@ do {									\
 
 #define NET_SKB_PAD	max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
 
+#define MV_EMAC_F_REMOVE_BIT	0
+#define MVPP2_F_PROBE_BIT	1
+
+#define MVPP2_F_PROBE		BIT(MV_EMAC_F_REMOVE_BIT)
+#define MVPP2_F_REMOVE		BIT(MVPP2_F_PROBE_BIT)
+
 #define CONFIG_NR_CPUS		1
 #define ETH_HLEN		ETHER_HDR_SIZE	/* Total octets in header */
 
@@ -942,6 +948,9 @@ struct mvpp2 {
 	struct mii_dev *bus;
 
 	int probe_done;
+
+	/* Flags */
+	u64 flags;
 };
 
 struct mvpp2_pcpu_stats {
@@ -5553,11 +5562,14 @@ static int mvpp2_probe(struct udevice *dev)
 		gop_port_init(port);
 	}
 
-	/* Initialize network controller */
-	err = mvpp2_init(dev, priv);
-	if (err < 0) {
-		dev_err(&pdev->dev, "failed to initialize controller\n");
-		return err;
+	if (!(priv->flags & MVPP2_F_PROBE)) {
+		/* Initialize network controller */
+		err = mvpp2_init(dev, priv);
+		if (err < 0) {
+			dev_err(&pdev->dev, "failed to initialize controller\n");
+			return err;
+		}
+		priv->flags |= MVPP2_F_PROBE;
 	}
 
 	err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
@@ -5585,9 +5597,14 @@ static int mvpp2_remove(struct udevice *dev)
 	struct mvpp2 *priv = port->priv;
 	int i;
 
+	if (priv->flags & MVPP2_F_REMOVE)
+		return 0;
+
 	for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
 		mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
 
+	priv->flags |= MVPP2_F_REMOVE;
+
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 04/10] net: mvpp2x: fix BM configuration overrun issue

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> Issue:
> BM counters were overran by probe that called per Network interface and

overran -> overrun

> caused release of wrong number of buffers during remove procedure.
>
> Fix:
> Add CP level flags to call init and remove procedure once per CP.

CP?

>
> Change-Id: I7fa24704e1feadb079d7dc3a19a0b92b3b69b238
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39400
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Igal Liberman <igall@marvell.com>
> ---
>  drivers/net/mvpp2.c | 27 ++++++++++++++++++++++-----
>  1 file changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 3083111..af3c3ef 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -67,6 +67,12 @@ do {                                                                 \
>
>  #define NET_SKB_PAD    max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
>
> +#define MV_EMAC_F_REMOVE_BIT   0
> +#define MVPP2_F_PROBE_BIT      1

Drop the "BIT" definitions - they are never used except immediately below.

> +
> +#define MVPP2_F_PROBE          BIT(MV_EMAC_F_REMOVE_BIT)

PROBE -> PROBED

> +#define MVPP2_F_REMOVE         BIT(MVPP2_F_PROBE_BIT)

REMOVE -> REMOVED

> +
>  #define CONFIG_NR_CPUS         1
>  #define ETH_HLEN               ETHER_HDR_SIZE  /* Total octets in header */
>
> @@ -942,6 +948,9 @@ struct mvpp2 {
>         struct mii_dev *bus;
>
>         int probe_done;
> +
> +       /* Flags */
> +       u64 flags;
>  };
>
>  struct mvpp2_pcpu_stats {
> @@ -5553,11 +5562,14 @@ static int mvpp2_probe(struct udevice *dev)
>                 gop_port_init(port);
>         }
>
> -       /* Initialize network controller */
> -       err = mvpp2_init(dev, priv);
> -       if (err < 0) {
> -               dev_err(&pdev->dev, "failed to initialize controller\n");
> -               return err;
> +       if (!(priv->flags & MVPP2_F_PROBE)) {
> +               /* Initialize network controller */
> +               err = mvpp2_init(dev, priv);
> +               if (err < 0) {
> +                       dev_err(&pdev->dev, "failed to initialize controller\n");
> +                       return err;
> +               }
> +               priv->flags |= MVPP2_F_PROBE;
>         }
>
>         err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
> @@ -5585,9 +5597,14 @@ static int mvpp2_remove(struct udevice *dev)
>         struct mvpp2 *priv = port->priv;
>         int i;
>
> +       if (priv->flags & MVPP2_F_REMOVE)
> +               return 0;

This seems wrong. Wouldn't you want to remove on the last instance,
not the first?

> +
>         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
>                 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
>
> +       priv->flags |= MVPP2_F_REMOVE;
> +
>         return 0;
>  }
>
> --
> 1.9.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 05/10] net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.

Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.

Change-Id: I22c759a9bcf533ecddbdc495cd48d72e8761764e
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39964
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39658
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index af3c3ef..901e9d8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -623,10 +623,10 @@ enum mv_netc_lanes {
 #define MVPP2_MAX_TXD			16
 
 /* Amount of Tx descriptors that can be reserved at once by CPU */
-#define MVPP2_CPU_DESC_CHUNK		64
+#define MVPP2_CPU_DESC_CHUNK		16
 
 /* Max number of Tx descriptors in each aggregated queue */
-#define MVPP2_AGGR_TXQ_SIZE		256
+#define MVPP2_AGGR_TXQ_SIZE		16
 
 /* Descriptor aligned size */
 #define MVPP2_DESC_ALIGNED_SIZE		32
-- 
1.9.1

[U-Boot] [PATCH 05/10] net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> U-boot use single physical tx queue with size 16 descriptors.
> So aggregated tx queue size should be equal to physical tx queue
> and cpu descriptor chunk(number of descriptors delivered from
> physical tx queue to aggregated tx queue by one chunk) shouldn't be
> larger than physical tx queue.
>
> Fix:
> Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
> physical TXQ.
>
> Change-Id: I22c759a9bcf533ecddbdc495cd48d72e8761764e

Drop internal tags in whole series.

> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39964
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39658
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 06/10] net: mvpp2x: remove MBUS configurations from MvPP22 driver

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.

Change-Id: Iafb42f121d0ad2d8bc99a42e7ed671cd7b754b42
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39965
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39951
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 901e9d8..e74421f 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5021,13 +5021,14 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 		return -EINVAL;
 	}
 
-	/* MBUS windows configuration */
-	dram_target_info = mvebu_mbus_dram_info();
-	if (dram_target_info)
-		mvpp2_conf_mbus_windows(dram_target_info, priv);
-
 	if (priv->hw_version == MVPP22)
 		mvpp2_axi_init(priv);
+	else {
+		/* MBUS windows configuration */
+		dram_target_info = mvebu_mbus_dram_info();
+		if (dram_target_info)
+			mvpp2_conf_mbus_windows(dram_target_info, priv);
+	}
 
 	if (priv->hw_version == MVPP21) {
 		/* Disable HW PHY polling */
-- 
1.9.1

[U-Boot] [PATCH 06/10] net: mvpp2x: remove MBUS configurations from MvPP22 driver

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> MBUS driver were replaced by AXI in PPv22 and relevant
> only for PPv21.
>
> Change-Id: Iafb42f121d0ad2d8bc99a42e7ed671cd7b754b42
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39965
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39951
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 07/10] net: mvpp2x: Remove IRQ configuration from u-boot

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

Remove IRQ configuration from u-boot PP driver.
U-BOOT don't use interupts and coniguration of IRQ in u-boot
caused crushes in Linux interupt shared mode.
Also interput cause is redundant in RX routine since single RXQ
used.

Change-Id: Ie7dda9bc57accb24c2e58c63de31f359711e71e5
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39966
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39952
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 46 +---------------------------------------------
 1 file changed, 1 insertion(+), 45 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index e74421f..2cdf934 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4689,20 +4689,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
 		port->rxqs[queue] = rxq;
 	}
 
-	/* Configure Rx queue group interrupt for this port */
-	if (priv->hw_version == MVPP21) {
-		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
-			    CONFIG_MV_ETH_RXQ);
-	} else {
-		u32 val;
-
-		val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-		val = (CONFIG_MV_ETH_RXQ <<
-		       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-	}
 
 	/* Create Rx descriptor rings */
 	for (queue = 0; queue < rxq_number; queue++) {
@@ -5065,25 +5051,6 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
 	if (priv->hw_version == MVPP22)
 		mvpp2_tx_fifo_init(priv);
 
-	/* Reset Rx queue group interrupt configuration */
-	for (i = 0; i < MVPP2_MAX_PORTS; i++) {
-		if (priv->hw_version == MVPP21) {
-			mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
-				    CONFIG_MV_ETH_RXQ);
-			continue;
-		} else {
-			u32 val;
-
-			val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
-			mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
-
-			val = (CONFIG_MV_ETH_RXQ <<
-			       MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
-			mvpp2_write(priv,
-				    MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
-		}
-	}
-
 	if (priv->hw_version == MVPP21)
 		writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
 		       priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
@@ -5229,21 +5196,10 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	int pool, rx_bytes, err;
 	int rx_received;
 	struct mvpp2_rx_queue *rxq;
-	u32 cause_rx_tx, cause_rx, cause_misc;
 	u8 *data;
 
-	cause_rx_tx = mvpp2_read(port->priv,
-				 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
-	cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
-	cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
-	if (!cause_rx_tx && !cause_misc)
-		return 0;
-
-	cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
-
 	/* Process RX packets */
-	cause_rx |= port->pending_cause_rx;
-	rxq = mvpp2_get_rx_queue(port, cause_rx);
+	rxq = port->rxqs[0];
 
 	/* Get number of received packets and clamp the to-do */
 	rx_received = mvpp2_rxq_received(port, rxq->id);
-- 
1.9.1

[U-Boot] [PATCH 07/10] net: mvpp2x: Remove IRQ configuration from u-boot

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> Remove IRQ configuration from u-boot PP driver.
> U-BOOT don't use interupts and coniguration of IRQ in u-boot

interupts -> interrupts
coniguration -> configuration
u-boot -> U-Boot

> caused crushes in Linux interupt shared mode.

crushes -> crashes
interupt shared -> shared interrupt

> Also interput cause is redundant in RX routine since single RXQ

interput -> interrupt
cause -> use
single RXQ -> a single RX queue is

> used.
>
> Change-Id: Ie7dda9bc57accb24c2e58c63de31f359711e71e5
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39966
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39952
> Reviewed-by: Igal Liberman <igall@marvell.com>

After fixing commit log,
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 08/10] net: mvpp2x: Set BM pool high address

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.

Change-Id: I04417b8cc081ea75e43b230d5ba1cc5c0071ce25
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39967
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39953
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2cdf934..931047e 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -322,6 +322,8 @@ do {									\
 #define	    MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK	0xff00
 #define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT	8
 #define MVPP22_BM_MC_RLS_REG			0x64d4
+#define MVPP22_BM_POOL_BASE_HIGH_REG		0x6310
+#define MVPP22_BM_POOL_BASE_HIGH_MASK		0xff
 
 /* TX Scheduler registers */
 #define MVPP2_TXP_SCHED_PORT_INDEX_REG		0x8000
@@ -2602,6 +2604,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
 
 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 		    lower_32_bits(bm_pool->dma_addr));
+	if (priv->hw_version == MVPP22)
+		mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
+			    (upper_32_bits(bm_pool->dma_addr) &
+			    MVPP22_BM_POOL_BASE_HIGH_MASK));
 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 
 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
-- 
1.9.1

[U-Boot] [PATCH 08/10] net: mvpp2x: Set BM pool high address

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> MVPP22 driver support 64 Bit arch and require BM pool
> high address configuration.
>
> Change-Id: I04417b8cc081ea75e43b230d5ba1cc5c0071ce25
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39967
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39953
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 09/10] net: mvpp2x: remove TX drain from transmit routine

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ be cleared before moving to Linux by stop procedure.

Change-Id: I1d52cf087505d35d8a10e0249f78d0177a569658
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39968
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39955
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 931047e..8168539 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5261,21 +5261,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
 	return rx_bytes;
 }
 
-/* Drain Txq */
-static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
-			    int enable)
-{
-	u32 val;
-
-	mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
-	val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
-	if (enable)
-		val |= MVPP2_TXQ_DRAIN_EN_MASK;
-	else
-		val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
-	mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
-}
-
 static int mvpp2_send(struct udevice *dev, void *packet, int length)
 {
 	struct mvpp2_port *port = dev_get_priv(dev);
@@ -5319,9 +5304,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 		tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
 	} while (tx_done);
 
-	/* Enable TXQ drain */
-	mvpp2_txq_drain(port, txq, 1);
-
 	timeout = 0;
 	do {
 		if (timeout++ > 10000) {
@@ -5331,9 +5313,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
 		tx_done = mvpp2_txq_sent_desc_proc(port, txq);
 	} while (!tx_done);
 
-	/* Disable TXQ drain */
-	mvpp2_txq_drain(port, txq, 0);
-
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 09/10] net: mvpp2x: remove TX drain from transmit routine

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> TX drain in transmit procedure could cause issues due
> to race between drain procedure and transmition of descriptor
> between AGGR TXQ and physical TXQ.
> TXQ be cleared before moving to Linux by stop procedure.

TXQ be cleared -> TXQ will be cleared

>
> Change-Id: I1d52cf087505d35d8a10e0249f78d0177a569658
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39968
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39955
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

> ---
>  drivers/net/mvpp2.c | 21 ---------------------
>  1 file changed, 21 deletions(-)
>
> diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
> index 931047e..8168539 100644
> --- a/drivers/net/mvpp2.c
> +++ b/drivers/net/mvpp2.c
> @@ -5261,21 +5261,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
>         return rx_bytes;
>  }
>
> -/* Drain Txq */
> -static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
> -                           int enable)
> -{
> -       u32 val;
> -
> -       mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
> -       val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
> -       if (enable)
> -               val |= MVPP2_TXQ_DRAIN_EN_MASK;
> -       else
> -               val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
> -       mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
> -}
> -
>  static int mvpp2_send(struct udevice *dev, void *packet, int length)
>  {
>         struct mvpp2_port *port = dev_get_priv(dev);
> @@ -5319,9 +5304,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
>                 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
>         } while (tx_done);
>
> -       /* Enable TXQ drain */
> -       mvpp2_txq_drain(port, txq, 1);
> -
>         timeout = 0;
>         do {
>                 if (timeout++ > 10000) {
> @@ -5331,9 +5313,6 @@ static int mvpp2_send(struct udevice *dev, void *packet, int length)
>                 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
>         } while (!tx_done);
>
> -       /* Disable TXQ drain */
> -       mvpp2_txq_drain(port, txq, 0);
> -
>         return 0;
>  }
>
> --
> 1.9.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 10/10] net: mvpp2x: Set BM poll size once during priv probe

[stefanc at malvell.com]

From: Stefan Chulski <stefanc@marvell.com>

Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.

Change-Id: Icf8c2be3f9cc653c132365e918044713accef335
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39969
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39956
Reviewed-by: Igal Liberman <igall@marvell.com>
---
 drivers/net/mvpp2.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 8168539..8bc7b08 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2683,7 +2683,7 @@ static int mvpp2_bm_pools_init(struct udevice *dev,
 		err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
 		if (err)
 			goto err_unroll_pools;
-		mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
+		mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
 	}
 	return 0;
 
@@ -2869,9 +2869,6 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
 		}
 	}
 
-	mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
-				  MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
-
 	return new_pool;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 10/10] net: mvpp2x: Set BM poll size once during priv probe

[Joe Hershberger]

On Wed, Jun 21, 2017 at 3:31 AM,  <stefanc@malvell.com> wrote:
> From: Stefan Chulski <stefanc@marvell.com>
>
> Set BM poll size once during priv probe and do not
> overwrite it during port probe procedure. Pool is common for
> all CP ports.
>
> Change-Id: Icf8c2be3f9cc653c132365e918044713accef335
> Signed-off-by: Stefan Chulski <stefanc@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39969
> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
> Reviewed-on: http://vgitil04.il.marvell.com:8080/39956
> Reviewed-by: Igal Liberman <igall@marvell.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Stefan Roese]

Hi Joe,

On 21.06.2017 10:31, stefanc at malvell.com wrote:
> From: Stefan Chulski <stefanc@marvell.com>
> 
> Issues were found during internal QA phase.
> 
> Stefan Chulski (10):
>    net: mvpp2x: Add GPIO configuration support
>    net: mvpp2x: fix phy connected to wrong mdio issue
>    net: mvpp2x: Enable GoP packet padding in TX
>    net: mvpp2x: fix BM configuration overrun issue
>    net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>    net: mvpp2x: remove MBUS configurations from MvPP22 driver
>    net: mvpp2x: Remove IRQ configuration from u-boot
>    net: mvpp2x: Set BM pool high address
>    net: mvpp2x: remove TX drain from transmit routine
>    net: mvpp2x: Set BM poll size once during priv probe
> 
>   drivers/net/mvpp2.c | 189 ++++++++++++++++++++++++++--------------------------
>   1 file changed, 94 insertions(+), 95 deletions(-)

Joe, do you have any comments on these mvpp2 patches?

Thanks,
Stefan

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Stefan Roese]

Hi Joe,

On 11.07.2017 10:04, Stefan Roese wrote:
> On 21.06.2017 10:31, stefanc at malvell.com wrote:
>> From: Stefan Chulski <stefanc@marvell.com>
>>
>> Issues were found during internal QA phase.
>>
>> Stefan Chulski (10):
>>    net: mvpp2x: Add GPIO configuration support
>>    net: mvpp2x: fix phy connected to wrong mdio issue
>>    net: mvpp2x: Enable GoP packet padding in TX
>>    net: mvpp2x: fix BM configuration overrun issue
>>    net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>>    net: mvpp2x: remove MBUS configurations from MvPP22 driver
>>    net: mvpp2x: Remove IRQ configuration from u-boot
>>    net: mvpp2x: Set BM pool high address
>>    net: mvpp2x: remove TX drain from transmit routine
>>    net: mvpp2x: Set BM poll size once during priv probe
>>
>>   drivers/net/mvpp2.c | 189 
>> ++++++++++++++++++++++++++--------------------------
>>   1 file changed, 94 insertions(+), 95 deletions(-)
> 
> Joe, do you have any comments on these mvpp2 patches?

Gently ping on these patches again. Joe, do you have any comments
on these? Do you want to take these patches via your tree? Or
should I push them if you don't have any objections?

Thanks,
Stefan

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Joe Hershberger]

Hi Stefan (and Stefan),

On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese <sr@denx.de> wrote:
> Hi Joe,
>
> On 11.07.2017 10:04, Stefan Roese wrote:
>>
>> On 21.06.2017 10:31, stefanc at malvell.com wrote:

Huh? Sent from a typo email address? That's pretty tedious. I
recommend fixing your git config. And if that's fine, I recommend
using patman so this won't happen again.

>>>
>>> From: Stefan Chulski <stefanc@marvell.com>
>>>
>>> Issues were found during internal QA phase.
>>>
>>> Stefan Chulski (10):
>>>    net: mvpp2x: Add GPIO configuration support
>>>    net: mvpp2x: fix phy connected to wrong mdio issue
>>>    net: mvpp2x: Enable GoP packet padding in TX
>>>    net: mvpp2x: fix BM configuration overrun issue
>>>    net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>>>    net: mvpp2x: remove MBUS configurations from MvPP22 driver
>>>    net: mvpp2x: Remove IRQ configuration from u-boot
>>>    net: mvpp2x: Set BM pool high address
>>>    net: mvpp2x: remove TX drain from transmit routine
>>>    net: mvpp2x: Set BM poll size once during priv probe
>>>
>>>   drivers/net/mvpp2.c | 189
>>> ++++++++++++++++++++++++++--------------------------
>>>   1 file changed, 94 insertions(+), 95 deletions(-)
>>
>>
>> Joe, do you have any comments on these mvpp2 patches?
>
>
> Gently ping on these patches again. Joe, do you have any comments
> on these? Do you want to take these patches via your tree? Or
> should I push them if you don't have any objections?

Reviewing now. I generally use patchwork to remember what I have to
do. I guess if I didn't rely on that I would set up better work queue
email filters. Sorry for the delay.

I figured since the series is assigned to you in PW, that you wanted
it through your tree. I'm fine either way.

Cheers,
-Joe

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Stefan Roese]

Hi Joe,

On 08.08.2017 17:57, Joe Hershberger wrote:
> Hi Stefan (and Stefan),
> 
> On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese <sr@denx.de> wrote:
>> Hi Joe,
>>
>> On 11.07.2017 10:04, Stefan Roese wrote:
>>>
>>> On 21.06.2017 10:31, stefanc at malvell.com wrote:
> 
> Huh? Sent from a typo email address?

Where is the problem with the Stefan Chulski's email address?
Sorry, I can't spot it.

> That's pretty tedious. I
> recommend fixing your git config. And if that's fine, I recommend
> using patman so this won't happen again.
> 
>>>>
>>>> From: Stefan Chulski <stefanc@marvell.com>
>>>>
>>>> Issues were found during internal QA phase.
>>>>
>>>> Stefan Chulski (10):
>>>>     net: mvpp2x: Add GPIO configuration support
>>>>     net: mvpp2x: fix phy connected to wrong mdio issue
>>>>     net: mvpp2x: Enable GoP packet padding in TX
>>>>     net: mvpp2x: fix BM configuration overrun issue
>>>>     net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>>>>     net: mvpp2x: remove MBUS configurations from MvPP22 driver
>>>>     net: mvpp2x: Remove IRQ configuration from u-boot
>>>>     net: mvpp2x: Set BM pool high address
>>>>     net: mvpp2x: remove TX drain from transmit routine
>>>>     net: mvpp2x: Set BM poll size once during priv probe
>>>>
>>>>    drivers/net/mvpp2.c | 189
>>>> ++++++++++++++++++++++++++--------------------------
>>>>    1 file changed, 94 insertions(+), 95 deletions(-)
>>>
>>>
>>> Joe, do you have any comments on these mvpp2 patches?
>>
>>
>> Gently ping on these patches again. Joe, do you have any comments
>> on these? Do you want to take these patches via your tree? Or
>> should I push them if you don't have any objections?
> 
> Reviewing now. I generally use patchwork to remember what I have to
> do. I guess if I didn't rely on that I would set up better work queue
> email filters. Sorry for the delay.
> 
> I figured since the series is assigned to you in PW, that you wanted
> it through your tree. I'm fine either way.

I assume that Tom assigned them to me (I didn't do it at least).
But I can definitely pull these patches via the Marvell tree, once
all open issues are resolved and all patches have your Acked-by
tag.

Thanks for the review!

Thanks,
Stefan

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Joe Hershberger]

On Wed, Aug 9, 2017 at 12:56 AM, Stefan Roese <sr@denx.de> wrote:
> Hi Joe,
>
> On 08.08.2017 17:57, Joe Hershberger wrote:
>>
>> Hi Stefan (and Stefan),
>>
>> On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese <sr@denx.de> wrote:
>>>
>>> Hi Joe,
>>>
>>> On 11.07.2017 10:04, Stefan Roese wrote:
>>>>
>>>>
>>>> On 21.06.2017 10:31, stefanc at malvell.com wrote:
>>
>>
>> Huh? Sent from a typo email address?
>
>
> Where is the problem with the Stefan Chulski's email address?
> Sorry, I can't spot it.

Just above and in the reply-to of the messages: stefanc at ma>l<vell.com

>> That's pretty tedious. I
>> recommend fixing your git config. And if that's fine, I recommend
>> using patman so this won't happen again.
>>
>>>>>
>>>>> From: Stefan Chulski <stefanc@marvell.com>
>>>>>
>>>>> Issues were found during internal QA phase.
>>>>>
>>>>> Stefan Chulski (10):
>>>>>     net: mvpp2x: Add GPIO configuration support
>>>>>     net: mvpp2x: fix phy connected to wrong mdio issue
>>>>>     net: mvpp2x: Enable GoP packet padding in TX
>>>>>     net: mvpp2x: fix BM configuration overrun issue
>>>>>     net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>>>>>     net: mvpp2x: remove MBUS configurations from MvPP22 driver
>>>>>     net: mvpp2x: Remove IRQ configuration from u-boot
>>>>>     net: mvpp2x: Set BM pool high address
>>>>>     net: mvpp2x: remove TX drain from transmit routine
>>>>>     net: mvpp2x: Set BM poll size once during priv probe
>>>>>
>>>>>    drivers/net/mvpp2.c | 189
>>>>> ++++++++++++++++++++++++++--------------------------
>>>>>    1 file changed, 94 insertions(+), 95 deletions(-)
>>>>
>>>>
>>>>
>>>> Joe, do you have any comments on these mvpp2 patches?
>>>
>>>
>>>
>>> Gently ping on these patches again. Joe, do you have any comments
>>> on these? Do you want to take these patches via your tree? Or
>>> should I push them if you don't have any objections?
>>
>>
>> Reviewing now. I generally use patchwork to remember what I have to
>> do. I guess if I didn't rely on that I would set up better work queue
>> email filters. Sorry for the delay.
>>
>> I figured since the series is assigned to you in PW, that you wanted
>> it through your tree. I'm fine either way.
>
>
> I assume that Tom assigned them to me (I didn't do it at least).
> But I can definitely pull these patches via the Marvell tree, once
> all open issues are resolved and all patches have your Acked-by
> tag.

Sounds good!

> Thanks for the review!
>
> Thanks,
> Stefan

[U-Boot] [PATCH 00/10] This patch set represent Marvell mvpp2 driver fixes

[Stefan Roese]

Hi Joe,

On 09.08.2017 17:24, Joe Hershberger wrote:
> On Wed, Aug 9, 2017 at 12:56 AM, Stefan Roese <sr@denx.de> wrote:
>> Hi Joe,
>>
>> On 08.08.2017 17:57, Joe Hershberger wrote:
>>>
>>> Hi Stefan (and Stefan),
>>>
>>> On Tue, Aug 8, 2017 at 7:05 AM, Stefan Roese <sr@denx.de> wrote:
>>>>
>>>> Hi Joe,
>>>>
>>>> On 11.07.2017 10:04, Stefan Roese wrote:
>>>>>
>>>>>
>>>>> On 21.06.2017 10:31, stefanc at malvell.com wrote:
>>>
>>>
>>> Huh? Sent from a typo email address?
>>
>>
>> Where is the problem with the Stefan Chulski's email address?
>> Sorry, I can't spot it.
> 
> Just above and in the reply-to of the messages: stefanc at ma>l<vell.com

Ah, thanks.

>>> That's pretty tedious. I
>>> recommend fixing your git config. And if that's fine, I recommend
>>> using patman so this won't happen again.
>>>
>>>>>>
>>>>>> From: Stefan Chulski <stefanc@marvell.com>
>>>>>>
>>>>>> Issues were found during internal QA phase.
>>>>>>
>>>>>> Stefan Chulski (10):
>>>>>>      net: mvpp2x: Add GPIO configuration support
>>>>>>      net: mvpp2x: fix phy connected to wrong mdio issue
>>>>>>      net: mvpp2x: Enable GoP packet padding in TX
>>>>>>      net: mvpp2x: fix BM configuration overrun issue
>>>>>>      net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK
>>>>>>      net: mvpp2x: remove MBUS configurations from MvPP22 driver
>>>>>>      net: mvpp2x: Remove IRQ configuration from u-boot
>>>>>>      net: mvpp2x: Set BM pool high address
>>>>>>      net: mvpp2x: remove TX drain from transmit routine
>>>>>>      net: mvpp2x: Set BM poll size once during priv probe
>>>>>>
>>>>>>     drivers/net/mvpp2.c | 189
>>>>>> ++++++++++++++++++++++++++--------------------------
>>>>>>     1 file changed, 94 insertions(+), 95 deletions(-)
>>>>>
>>>>>
>>>>>
>>>>> Joe, do you have any comments on these mvpp2 patches?
>>>>
>>>>
>>>>
>>>> Gently ping on these patches again. Joe, do you have any comments
>>>> on these? Do you want to take these patches via your tree? Or
>>>> should I push them if you don't have any objections?
>>>
>>>
>>> Reviewing now. I generally use patchwork to remember what I have to
>>> do. I guess if I didn't rely on that I would set up better work queue
>>> email filters. Sorry for the delay.
>>>
>>> I figured since the series is assigned to you in PW, that you wanted
>>> it through your tree. I'm fine either way.
>>
>>
>> I assume that Tom assigned them to me (I didn't do it at least).
>> But I can definitely pull these patches via the Marvell tree, once
>> all open issues are resolved and all patches have your Acked-by
>> tag.
> 
> Sounds good!

Great. I'm build testing right now and will send the pull request, once
this has finished without any issues.

Thanks,
Stefan