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From: Fabio Estevam <festevam@gmail.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: "BOUGH CHEN" <haibo.chen@nxp.com>,
	"Angus Ainslie" <angus@akkea.ca>,
	"Leonard Crestez" <leonard.crestez@nxp.com>,
	"Peng Fan" <peng.fan@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Guido Günther" <agx@sigxcpu.org>,
	linux-mmc <linux-mmc@vger.kernel.org>,
	"Adrian Hunter" <adrian.hunter@intel.com>,
	dl-linux-imx <linux-imx@nxp.com>,
	"Sascha Hauer" <kernel@pengutronix.de>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: sdhci timeout on imx8mq
Date: Wed, 6 Jan 2021 15:56:43 -0300	[thread overview]
Message-ID: <CAOMZO5BzAw8CjvaOzH_Ynr2eapO1MViTOWN5yZ5i_BcAhv3tWA@mail.gmail.com> (raw)
In-Reply-To: <cd99776c0107833d69c9c7fc4c8d6ba1a41ea3d7.camel@pengutronix.de>

Hi Lucas,

On Tue, Jan 5, 2021 at 12:06 PM Lucas Stach <l.stach@pengutronix.de> wrote:

> The reference manual states about this situation: "For any clock, its
> source must be left on when it is kept on. Behavior is undefined if
> this rule is violated."
> And it seems this is exactly what's happening here: some kind of glitch
> is introduced in the nand_usdhc_bus clock, which prevents the SDHCI
> controller from working, even though the clock branch is properly
> enabled later on. On my system the SDHCI timeout and following runtime
> suspend/resume cycle on the nand_usdhc_bus clock seem to get it back
> into a working state.

I think your analysis is correct and I recall helping a customer with
a similar issue:
https://community.nxp.com/t5/i-MX-Processors/External-clock-that-provide-root-clock-for-SAI3-and-SPDIF/m-p/1019834

Regards,

Fabio Estevam

WARNING: multiple messages have this Message-ID
From: Fabio Estevam <festevam@gmail.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: "Peng Fan" <peng.fan@nxp.com>, "Abel Vesa" <abel.vesa@nxp.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Angus Ainslie" <angus@akkea.ca>,
	linux-mmc <linux-mmc@vger.kernel.org>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"BOUGH CHEN" <haibo.chen@nxp.com>,
	"Adrian Hunter" <adrian.hunter@intel.com>,
	dl-linux-imx <linux-imx@nxp.com>,
	"Sascha Hauer" <kernel@pengutronix.de>,
	"Leonard Crestez" <leonard.crestez@nxp.com>,
	"Guido Günther" <agx@sigxcpu.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: sdhci timeout on imx8mq
Date: Wed, 6 Jan 2021 15:56:43 -0300	[thread overview]
Message-ID: <CAOMZO5BzAw8CjvaOzH_Ynr2eapO1MViTOWN5yZ5i_BcAhv3tWA@mail.gmail.com> (raw)
In-Reply-To: <cd99776c0107833d69c9c7fc4c8d6ba1a41ea3d7.camel@pengutronix.de>

Hi Lucas,

On Tue, Jan 5, 2021 at 12:06 PM Lucas Stach <l.stach@pengutronix.de> wrote:

> The reference manual states about this situation: "For any clock, its
> source must be left on when it is kept on. Behavior is undefined if
> this rule is violated."
> And it seems this is exactly what's happening here: some kind of glitch
> is introduced in the nand_usdhc_bus clock, which prevents the SDHCI
> controller from working, even though the clock branch is properly
> enabled later on. On my system the SDHCI timeout and following runtime
> suspend/resume cycle on the nand_usdhc_bus clock seem to get it back
> into a working state.

I think your analysis is correct and I recall helping a customer with
a similar issue:
https://community.nxp.com/t5/i-MX-Processors/External-clock-that-provide-root-clock-for-SAI3-and-SPDIF/m-p/1019834

Regards,

Fabio Estevam

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-01-06 18:57 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-03 19:19 Fabio Estevam
2020-02-03 19:19 ` Fabio Estevam
2020-02-05  9:26 ` Guido Günther
2020-02-05  9:26   ` Guido Günther
2020-02-05 13:18   ` Fabio Estevam
2020-02-05 13:18     ` Fabio Estevam
2020-02-07  2:11     ` BOUGH CHEN
2020-02-07  2:11       ` BOUGH CHEN
     [not found]       ` <VI1PR04MB504091C7991353F6092A8D91901A0@VI1PR04MB5040.eurprd04.prod.outlook.com>
2020-02-13 10:53         ` Fabio Estevam
2020-02-13 10:53           ` Fabio Estevam
2020-06-30 19:39           ` Angus Ainslie
2020-06-30 19:39             ` Angus Ainslie
2020-07-07 12:44             ` Fabio Estevam
2020-07-07 12:44               ` Fabio Estevam
2020-07-08  1:32               ` BOUGH CHEN
2020-07-08  1:32                 ` BOUGH CHEN
2020-12-18 20:07                 ` Lucas Stach
2020-12-18 20:07                   ` Lucas Stach
2020-12-18 20:45                   ` Angus Ainslie
2020-12-18 20:45                     ` Angus Ainslie
2020-12-23 21:06                   ` Angus Ainslie
2020-12-23 21:06                     ` Angus Ainslie
2021-01-05 15:06                 ` Lucas Stach
2021-01-05 15:06                   ` Lucas Stach
2021-01-06  9:29                   ` Bough Chen
2021-01-06  9:29                     ` Bough Chen
2021-01-06 15:09                     ` Lucas Stach
2021-01-06 15:09                       ` Lucas Stach
2021-01-07  1:47                       ` Bough Chen
2021-01-07  1:47                         ` Bough Chen
2021-01-06 18:56                   ` Fabio Estevam [this message]
2021-01-06 18:56                     ` Fabio Estevam
2021-01-07  1:30                     ` Jacky Bai
2021-01-07  1:30                       ` Jacky Bai
2021-01-07 11:26                       ` Lucas Stach
2021-01-07 11:26                         ` Lucas Stach
2021-01-08  1:27                         ` Jacky Bai
2021-01-08  1:27                           ` Jacky Bai
2021-03-09  7:35                         ` Heiko Thiery
2021-03-09  7:35                           ` Heiko Thiery
2021-01-19  2:35                   ` Peng Fan
2021-01-19  2:35                     ` Peng Fan

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