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From: Stijn Devriendt <highguy@gmail.com>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@ozlabs.org, b35362@freescale.com,
	dwmw2@infradead.org, linux-mtd@lists.infradead.org,
	dedekind1@gmail.com
Subject: Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
Date: Fri, 2 Sep 2011 09:10:13 +0200	[thread overview]
Message-ID: <CAOY=C6Fgkwvi90BrPE=meBP_71TraDGSGJFU5PtK2Bm8QR0Uhw@mail.gmail.com> (raw)
In-Reply-To: <4E494520.7050509@freescale.com>

On Mon, Aug 15, 2011 at 6:11 PM, Scott Wood <scottwood@freescale.com> wrote=
:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
>> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>>> + =A0 =A0/*
>>> + =A0 =A0 * Hack for supporting the flash chip whose writesize is
>>> + =A0 =A0 * larger than 2K bytes.
>>> + =A0 =A0 */
>>> + =A0 =A0if (mtd->writesize > 2048) {
>>> + =A0 =A0 =A0 =A0 =A0 =A0elbc_fcm_ctrl->subpage_shift =3D ffs(mtd->writ=
esize >> 11) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0elbc_fcm_ctrl->subpage_mask =3D
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(1 << elbc_fcm_ctrl->subpage_s=
hift) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0/*
>>> + =A0 =A0 =A0 =A0 =A0 =A0 * Rewrite mtd->writesize, mtd->oobsize, chip-=
>page_shift
>>> + =A0 =A0 =A0 =A0 =A0 =A0 * and chip->pagemask.
>>> + =A0 =A0 =A0 =A0 =A0 =A0 */
>>> + =A0 =A0 =A0 =A0 =A0 =A0mtd->writesize =3D 2048;
>>> + =A0 =A0 =A0 =A0 =A0 =A0mtd->oobsize =3D 64;
>>> + =A0 =A0 =A0 =A0 =A0 =A0chip->page_shift =3D ffs(mtd->writesize) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0chip->pagemask =3D (chip->chipsize >> chip->pa=
ge_shift) - 1;
>>> + =A0 =A0}
>>
>> So basically if the flash has 4KiB NAND pages, you are considering it as
>> a flash with 2KiB NAND pages. But surely this will work only if the
>> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
>> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
>> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
>
> Right. =A0The set of chips that work with this controller is still larger
> with this than without this.
>
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
>
I currently have the fsl_elbc_nand driver working with BCH codes in softwar=
e.
The patch is fairly small (although I'm just hardcoding the required ECC
configuration). I'll see if I can clean it up and push it upstream soon.

Regards,
Stijn

WARNING: multiple messages have this Message-ID (diff)
From: Stijn Devriendt <highguy@gmail.com>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@ozlabs.org, b35362@freescale.com,
	dwmw2@infradead.org, linux-mtd@lists.infradead.org,
	dedekind1@gmail.com
Subject: Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
Date: Fri, 2 Sep 2011 09:10:13 +0200	[thread overview]
Message-ID: <CAOY=C6Fgkwvi90BrPE=meBP_71TraDGSGJFU5PtK2Bm8QR0Uhw@mail.gmail.com> (raw)
In-Reply-To: <4E494520.7050509@freescale.com>

On Mon, Aug 15, 2011 at 6:11 PM, Scott Wood <scottwood@freescale.com> wrote:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
>> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>>> +    /*
>>> +     * Hack for supporting the flash chip whose writesize is
>>> +     * larger than 2K bytes.
>>> +     */
>>> +    if (mtd->writesize > 2048) {
>>> +            elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
>>> +            elbc_fcm_ctrl->subpage_mask =
>>> +                    (1 << elbc_fcm_ctrl->subpage_shift) - 1;
>>> +            /*
>>> +             * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
>>> +             * and chip->pagemask.
>>> +             */
>>> +            mtd->writesize = 2048;
>>> +            mtd->oobsize = 64;
>>> +            chip->page_shift = ffs(mtd->writesize) - 1;
>>> +            chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
>>> +    }
>>
>> So basically if the flash has 4KiB NAND pages, you are considering it as
>> a flash with 2KiB NAND pages. But surely this will work only if the
>> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
>> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
>> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
>
> Right.  The set of chips that work with this controller is still larger
> with this than without this.
>
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
>
I currently have the fsl_elbc_nand driver working with BCH codes in software.
The patch is fairly small (although I'm just hardcoding the required ECC
configuration). I'll see if I can clean it up and push it upstream soon.

Regards,
Stijn

  parent reply	other threads:[~2011-09-02  7:10 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-07-12  4:48 [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip b35362
2011-07-12  4:48 ` b35362
2011-08-03  6:15 ` Li Yang-R58472
2011-08-03  6:15   ` Li Yang-R58472
2011-08-15 15:59 ` Artem Bityutskiy
2011-08-15 15:59   ` Artem Bityutskiy
2011-08-15 16:11   ` Scott Wood
2011-08-15 16:11     ` Scott Wood
2011-08-15 16:24     ` Artem Bityutskiy
2011-08-15 16:24       ` Artem Bityutskiy
2011-09-02  7:10     ` Stijn Devriendt [this message]
2011-09-02  7:10       ` Stijn Devriendt

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