[PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[b35362]

From: Liu Shuo <b35362@freescale.com>

Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we divide a page into multi-2K pages for MTD layer driver. In that case,
we force to set the page size to 2K bytes. We convert the page address of
MTD layer driver to a real page address in flash chips and a column index
in fsl_elbc driver. We can issue any column address by UA instruction of
elbc controller.

Signed-off-by: Liu Shuo <b35362@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 drivers/mtd/nand/fsl_elbc_nand.c |   66 ++++++++++++++++++++++++++++++-------
 1 files changed, 53 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index a212116..884a9f1 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -76,6 +76,13 @@ struct fsl_elbc_fcm_ctrl {
 	unsigned int oob;        /* Non zero if operating on OOB data     */
 	unsigned int counter;	 /* counter for the initializations	  */
 	char *oob_poi;           /* Place to write ECC after read back    */
+
+	/*
+	 * If writesize > 2048, these two members are used to calculate
+	 * the real page address and real column address.
+	 */
+	int subpage_shift;
+	int subpage_mask;
 };
 
 /* These map to the positions used by the FCM hardware ECC generator */
@@ -164,18 +171,27 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 	int buf_num;
+	u32 real_ca = column;
 
-	elbc_fcm_ctrl->page = page_addr;
+	if (priv->page_size && elbc_fcm_ctrl->subpage_shift) {
+		real_ca = (page_addr & elbc_fcm_ctrl->subpage_mask) * 2112;
+		page_addr >>= elbc_fcm_ctrl->subpage_shift;
+	}
 
-	out_be32(&lbc->fbar,
-	         page_addr >> (chip->phys_erase_shift - chip->page_shift));
+	elbc_fcm_ctrl->page = page_addr;
 
 	if (priv->page_size) {
+		real_ca += (oob ? 2048 : 0);
+		elbc_fcm_ctrl->use_mdr = 1;
+		elbc_fcm_ctrl->mdr = real_ca;
+
+		out_be32(&lbc->fbar, page_addr >> 6);
 		out_be32(&lbc->fpar,
 		         ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 		         (oob ? FPAR_LP_MS : 0) | column);
 		buf_num = (page_addr & 1) << 2;
 	} else {
+		out_be32(&lbc->fbar, page_addr >> 5);
 		out_be32(&lbc->fpar,
 		         ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 		         (oob ? FPAR_SP_MS : 0) | column);
@@ -256,10 +272,11 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 	if (priv->page_size) {
 		out_be32(&lbc->fir,
 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
-		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
-		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
-		         (FIR_OP_CM1 << FIR_OP3_SHIFT) |
-		         (FIR_OP_RBW << FIR_OP4_SHIFT));
+		         (FIR_OP_UA  << FIR_OP1_SHIFT) |
+		         (FIR_OP_UA  << FIR_OP2_SHIFT) |
+		         (FIR_OP_PA  << FIR_OP3_SHIFT) |
+		         (FIR_OP_CM1 << FIR_OP4_SHIFT) |
+		         (FIR_OP_RBW << FIR_OP5_SHIFT));
 
 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 		                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
@@ -399,12 +416,13 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		if (priv->page_size) {
 			out_be32(&lbc->fir,
 			         (FIR_OP_CM2 << FIR_OP0_SHIFT) |
-			         (FIR_OP_CA  << FIR_OP1_SHIFT) |
-			         (FIR_OP_PA  << FIR_OP2_SHIFT) |
-			         (FIR_OP_WB  << FIR_OP3_SHIFT) |
-			         (FIR_OP_CM3 << FIR_OP4_SHIFT) |
-			         (FIR_OP_CW1 << FIR_OP5_SHIFT) |
-			         (FIR_OP_RS  << FIR_OP6_SHIFT));
+			         (FIR_OP_UA  << FIR_OP1_SHIFT) |
+			         (FIR_OP_UA  << FIR_OP2_SHIFT) |
+			         (FIR_OP_PA  << FIR_OP3_SHIFT) |
+			         (FIR_OP_WB  << FIR_OP4_SHIFT) |
+			         (FIR_OP_CM3 << FIR_OP5_SHIFT) |
+			         (FIR_OP_CW1 << FIR_OP6_SHIFT) |
+			         (FIR_OP_RS  << FIR_OP7_SHIFT));
 		} else {
 			out_be32(&lbc->fir,
 			         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
@@ -453,6 +471,9 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			full_page = 1;
 		}
 
+		if (priv->page_size)
+			elbc_fcm_ctrl->use_mdr = 1;
+
 		fsl_elbc_run_command(mtd);
 
 		/* Read back the page in order to fill in the ECC for the
@@ -654,9 +675,28 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	unsigned int al;
 
+	/*
+	 * Hack for supporting the flash chip whose writesize is
+	 * larger than 2K bytes.
+	 */
+	if (mtd->writesize > 2048) {
+		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
+		elbc_fcm_ctrl->subpage_mask =
+			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
+		/*
+		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
+		 * and chip->pagemask.
+		 */
+		mtd->writesize = 2048;
+		mtd->oobsize = 64;
+		chip->page_shift = ffs(mtd->writesize) - 1;
+		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+	}
+
 	/* calculate FMR Address Length field */
 	al = 0;
 	if (chip->pagemask & 0xffff0000)
-- 
1.7.1

[PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[b35362]

From: Liu Shuo <b35362@freescale.com>

Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we divide a page into multi-2K pages for MTD layer driver. In that case,
we force to set the page size to 2K bytes. We convert the page address of
MTD layer driver to a real page address in flash chips and a column index
in fsl_elbc driver. We can issue any column address by UA instruction of
elbc controller.

Signed-off-by: Liu Shuo <b35362@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
 drivers/mtd/nand/fsl_elbc_nand.c |   66 ++++++++++++++++++++++++++++++-------
 1 files changed, 53 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index a212116..884a9f1 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -76,6 +76,13 @@ struct fsl_elbc_fcm_ctrl {
 	unsigned int oob;        /* Non zero if operating on OOB data     */
 	unsigned int counter;	 /* counter for the initializations	  */
 	char *oob_poi;           /* Place to write ECC after read back    */
+
+	/*
+	 * If writesize > 2048, these two members are used to calculate
+	 * the real page address and real column address.
+	 */
+	int subpage_shift;
+	int subpage_mask;
 };
 
 /* These map to the positions used by the FCM hardware ECC generator */
@@ -164,18 +171,27 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 	int buf_num;
+	u32 real_ca = column;
 
-	elbc_fcm_ctrl->page = page_addr;
+	if (priv->page_size && elbc_fcm_ctrl->subpage_shift) {
+		real_ca = (page_addr & elbc_fcm_ctrl->subpage_mask) * 2112;
+		page_addr >>= elbc_fcm_ctrl->subpage_shift;
+	}
 
-	out_be32(&lbc->fbar,
-	         page_addr >> (chip->phys_erase_shift - chip->page_shift));
+	elbc_fcm_ctrl->page = page_addr;
 
 	if (priv->page_size) {
+		real_ca += (oob ? 2048 : 0);
+		elbc_fcm_ctrl->use_mdr = 1;
+		elbc_fcm_ctrl->mdr = real_ca;
+
+		out_be32(&lbc->fbar, page_addr >> 6);
 		out_be32(&lbc->fpar,
 		         ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 		         (oob ? FPAR_LP_MS : 0) | column);
 		buf_num = (page_addr & 1) << 2;
 	} else {
+		out_be32(&lbc->fbar, page_addr >> 5);
 		out_be32(&lbc->fpar,
 		         ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 		         (oob ? FPAR_SP_MS : 0) | column);
@@ -256,10 +272,11 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 	if (priv->page_size) {
 		out_be32(&lbc->fir,
 		         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
-		         (FIR_OP_CA  << FIR_OP1_SHIFT) |
-		         (FIR_OP_PA  << FIR_OP2_SHIFT) |
-		         (FIR_OP_CM1 << FIR_OP3_SHIFT) |
-		         (FIR_OP_RBW << FIR_OP4_SHIFT));
+		         (FIR_OP_UA  << FIR_OP1_SHIFT) |
+		         (FIR_OP_UA  << FIR_OP2_SHIFT) |
+		         (FIR_OP_PA  << FIR_OP3_SHIFT) |
+		         (FIR_OP_CM1 << FIR_OP4_SHIFT) |
+		         (FIR_OP_RBW << FIR_OP5_SHIFT));
 
 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 		                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
@@ -399,12 +416,13 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 		if (priv->page_size) {
 			out_be32(&lbc->fir,
 			         (FIR_OP_CM2 << FIR_OP0_SHIFT) |
-			         (FIR_OP_CA  << FIR_OP1_SHIFT) |
-			         (FIR_OP_PA  << FIR_OP2_SHIFT) |
-			         (FIR_OP_WB  << FIR_OP3_SHIFT) |
-			         (FIR_OP_CM3 << FIR_OP4_SHIFT) |
-			         (FIR_OP_CW1 << FIR_OP5_SHIFT) |
-			         (FIR_OP_RS  << FIR_OP6_SHIFT));
+			         (FIR_OP_UA  << FIR_OP1_SHIFT) |
+			         (FIR_OP_UA  << FIR_OP2_SHIFT) |
+			         (FIR_OP_PA  << FIR_OP3_SHIFT) |
+			         (FIR_OP_WB  << FIR_OP4_SHIFT) |
+			         (FIR_OP_CM3 << FIR_OP5_SHIFT) |
+			         (FIR_OP_CW1 << FIR_OP6_SHIFT) |
+			         (FIR_OP_RS  << FIR_OP7_SHIFT));
 		} else {
 			out_be32(&lbc->fir,
 			         (FIR_OP_CM0 << FIR_OP0_SHIFT) |
@@ -453,6 +471,9 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			full_page = 1;
 		}
 
+		if (priv->page_size)
+			elbc_fcm_ctrl->use_mdr = 1;
+
 		fsl_elbc_run_command(mtd);
 
 		/* Read back the page in order to fill in the ECC for the
@@ -654,9 +675,28 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_elbc_mtd *priv = chip->priv;
 	struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+	struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 	unsigned int al;
 
+	/*
+	 * Hack for supporting the flash chip whose writesize is
+	 * larger than 2K bytes.
+	 */
+	if (mtd->writesize > 2048) {
+		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
+		elbc_fcm_ctrl->subpage_mask =
+			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
+		/*
+		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
+		 * and chip->pagemask.
+		 */
+		mtd->writesize = 2048;
+		mtd->oobsize = 64;
+		chip->page_shift = ffs(mtd->writesize) - 1;
+		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+	}
+
 	/* calculate FMR Address Length field */
 	al = 0;
 	if (chip->pagemask & 0xffff0000)
-- 
1.7.1

RE: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Li Yang-R58472]

>-----Original Message-----
>From: Liu Shuo-B35362
>Sent: Tuesday, July 12, 2011 12:49 PM
>To: dwmw2@infradead.org
>Cc: linux-mtd@lists.infradead.org; linuxppc-dev@ozlabs.org; Liu Shuo-
>B35362; Li Yang-R58472
>Subject: [PATCH v2] mtd/nand : workaround for Freescale FCM to support
>large-page Nand chip
>
>From: Liu Shuo <b35362@freescale.com>
>
>Freescale FCM controller has a 2K size limitation of buffer RAM. In order
>to support the Nand flash chip whose page size is larger than 2K bytes, we
>divide a page into multi-2K pages for MTD layer driver. In that case, we
>force to set the page size to 2K bytes. We convert the page address of MTD
>layer driver to a real page address in flash chips and a column index in
>fsl_elbc driver. We can issue any column address by UA instruction of elbc
>controller.
>
>Signed-off-by: Liu Shuo <b35362@freescale.com>
>Signed-off-by: Li Yang <leoli@freescale.com>
>---

Hi David and Artem,

We have fixed the multi-line comment style problem.  Could you help to pick=
 the patch?

- Leo

RE: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Li Yang-R58472]

>-----Original Message-----
>From: Liu Shuo-B35362
>Sent: Tuesday, July 12, 2011 12:49 PM
>To: dwmw2@infradead.org
>Cc: linux-mtd@lists.infradead.org; linuxppc-dev@ozlabs.org; Liu Shuo-
>B35362; Li Yang-R58472
>Subject: [PATCH v2] mtd/nand : workaround for Freescale FCM to support
>large-page Nand chip
>
>From: Liu Shuo <b35362@freescale.com>
>
>Freescale FCM controller has a 2K size limitation of buffer RAM. In order
>to support the Nand flash chip whose page size is larger than 2K bytes, we
>divide a page into multi-2K pages for MTD layer driver. In that case, we
>force to set the page size to 2K bytes. We convert the page address of MTD
>layer driver to a real page address in flash chips and a column index in
>fsl_elbc driver. We can issue any column address by UA instruction of elbc
>controller.
>
>Signed-off-by: Liu Shuo <b35362@freescale.com>
>Signed-off-by: Li Yang <leoli@freescale.com>
>---

Hi David and Artem,

We have fixed the multi-line comment style problem.  Could you help to pick the patch?

- Leo

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Artem Bityutskiy]

On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> +	/*
> +	 * Hack for supporting the flash chip whose writesize is
> +	 * larger than 2K bytes.
> +	 */
> +	if (mtd->writesize > 2048) {
> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> +		elbc_fcm_ctrl->subpage_mask =
> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
> +		/*
> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> +		 * and chip->pagemask.
> +		 */
> +		mtd->writesize = 2048;
> +		mtd->oobsize = 64;
> +		chip->page_shift = ffs(mtd->writesize) - 1;
> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> +	}

So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes? Isn't it
an ugly hack?

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Artem Bityutskiy]

On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> +	/*
> +	 * Hack for supporting the flash chip whose writesize is
> +	 * larger than 2K bytes.
> +	 */
> +	if (mtd->writesize > 2048) {
> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> +		elbc_fcm_ctrl->subpage_mask =
> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
> +		/*
> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> +		 * and chip->pagemask.
> +		 */
> +		mtd->writesize = 2048;
> +		mtd->oobsize = 64;
> +		chip->page_shift = ffs(mtd->writesize) - 1;
> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> +	}

So basically if the flash has 4KiB NAND pages, you are considering it as
a flash with 2KiB NAND pages. But surely this will work only if the
underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes? Isn't it
an ugly hack?

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Scott Wood]

On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>> +	/*
>> +	 * Hack for supporting the flash chip whose writesize is
>> +	 * larger than 2K bytes.
>> +	 */
>> +	if (mtd->writesize > 2048) {
>> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
>> +		elbc_fcm_ctrl->subpage_mask =
>> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
>> +		/*
>> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
>> +		 * and chip->pagemask.
>> +		 */
>> +		mtd->writesize = 2048;
>> +		mtd->oobsize = 64;
>> +		chip->page_shift = ffs(mtd->writesize) - 1;
>> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
>> +	}
> 
> So basically if the flash has 4KiB NAND pages, you are considering it as
> a flash with 2KiB NAND pages. But surely this will work only if the
> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?

Right.  The set of chips that work with this controller is still larger
with this than without this.

It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
MLC with this controller anyway as it only does 1-bit ECC.

> Isn't it an ugly hack?

Less ugly than some other approaches that were considered. :-)

But yes, it's a hack (even says so in the comment).  The other option is
"it doesn't work".

-Scott

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Scott Wood]

On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>> +	/*
>> +	 * Hack for supporting the flash chip whose writesize is
>> +	 * larger than 2K bytes.
>> +	 */
>> +	if (mtd->writesize > 2048) {
>> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
>> +		elbc_fcm_ctrl->subpage_mask =
>> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
>> +		/*
>> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
>> +		 * and chip->pagemask.
>> +		 */
>> +		mtd->writesize = 2048;
>> +		mtd->oobsize = 64;
>> +		chip->page_shift = ffs(mtd->writesize) - 1;
>> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
>> +	}
> 
> So basically if the flash has 4KiB NAND pages, you are considering it as
> a flash with 2KiB NAND pages. But surely this will work only if the
> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?

Right.  The set of chips that work with this controller is still larger
with this than without this.

It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
MLC with this controller anyway as it only does 1-bit ECC.

> Isn't it an ugly hack?

Less ugly than some other approaches that were considered. :-)

But yes, it's a hack (even says so in the comment).  The other option is
"it doesn't work".

-Scott

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Artem Bityutskiy]

On Mon, 2011-08-15 at 11:11 -0500, Scott Wood wrote:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> > On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> >> +	/*
> >> +	 * Hack for supporting the flash chip whose writesize is
> >> +	 * larger than 2K bytes.
> >> +	 */
> >> +	if (mtd->writesize > 2048) {
> >> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> >> +		elbc_fcm_ctrl->subpage_mask =
> >> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
> >> +		/*
> >> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> >> +		 * and chip->pagemask.
> >> +		 */
> >> +		mtd->writesize = 2048;
> >> +		mtd->oobsize = 64;
> >> +		chip->page_shift = ffs(mtd->writesize) - 1;
> >> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> >> +	}
> > 
> > So basically if the flash has 4KiB NAND pages, you are considering it as
> > a flash with 2KiB NAND pages. But surely this will work only if the
> > underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> > and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> > writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
> 
> Right.  The set of chips that work with this controller is still larger
> with this than without this.
> 
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
> 
> > Isn't it an ugly hack?
> 
> Less ugly than some other approaches that were considered. :-)
> 
> But yes, it's a hack (even says so in the comment).  The other option is
> "it doesn't work".

Could there be at least a fat comment that NANDs with 4KiB pages have to
be at least NOP4? And probably NANDs with 8KiB pages and larger should
simply be rejected?

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Artem Bityutskiy]

On Mon, 2011-08-15 at 11:11 -0500, Scott Wood wrote:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
> > On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
> >> +	/*
> >> +	 * Hack for supporting the flash chip whose writesize is
> >> +	 * larger than 2K bytes.
> >> +	 */
> >> +	if (mtd->writesize > 2048) {
> >> +		elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
> >> +		elbc_fcm_ctrl->subpage_mask =
> >> +			(1 << elbc_fcm_ctrl->subpage_shift) - 1;
> >> +		/*
> >> +		 * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
> >> +		 * and chip->pagemask.
> >> +		 */
> >> +		mtd->writesize = 2048;
> >> +		mtd->oobsize = 64;
> >> +		chip->page_shift = ffs(mtd->writesize) - 1;
> >> +		chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
> >> +	}
> > 
> > So basically if the flash has 4KiB NAND pages, you are considering it as
> > a flash with 2KiB NAND pages. But surely this will work only if the
> > underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
> > and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
> > writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
> 
> Right.  The set of chips that work with this controller is still larger
> with this than without this.
> 
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
> 
> > Isn't it an ugly hack?
> 
> Less ugly than some other approaches that were considered. :-)
> 
> But yes, it's a hack (even says so in the comment).  The other option is
> "it doesn't work".

Could there be at least a fat comment that NANDs with 4KiB pages have to
be at least NOP4? And probably NANDs with 8KiB pages and larger should
simply be rejected?

-- 
Best Regards,
Artem Bityutskiy

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Stijn Devriendt]

On Mon, Aug 15, 2011 at 6:11 PM, Scott Wood <scottwood@freescale.com> wrote=
:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
>> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>>> + =A0 =A0/*
>>> + =A0 =A0 * Hack for supporting the flash chip whose writesize is
>>> + =A0 =A0 * larger than 2K bytes.
>>> + =A0 =A0 */
>>> + =A0 =A0if (mtd->writesize > 2048) {
>>> + =A0 =A0 =A0 =A0 =A0 =A0elbc_fcm_ctrl->subpage_shift =3D ffs(mtd->writ=
esize >> 11) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0elbc_fcm_ctrl->subpage_mask =3D
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(1 << elbc_fcm_ctrl->subpage_s=
hift) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0/*
>>> + =A0 =A0 =A0 =A0 =A0 =A0 * Rewrite mtd->writesize, mtd->oobsize, chip-=
>page_shift
>>> + =A0 =A0 =A0 =A0 =A0 =A0 * and chip->pagemask.
>>> + =A0 =A0 =A0 =A0 =A0 =A0 */
>>> + =A0 =A0 =A0 =A0 =A0 =A0mtd->writesize =3D 2048;
>>> + =A0 =A0 =A0 =A0 =A0 =A0mtd->oobsize =3D 64;
>>> + =A0 =A0 =A0 =A0 =A0 =A0chip->page_shift =3D ffs(mtd->writesize) - 1;
>>> + =A0 =A0 =A0 =A0 =A0 =A0chip->pagemask =3D (chip->chipsize >> chip->pa=
ge_shift) - 1;
>>> + =A0 =A0}
>>
>> So basically if the flash has 4KiB NAND pages, you are considering it as
>> a flash with 2KiB NAND pages. But surely this will work only if the
>> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
>> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
>> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
>
> Right. =A0The set of chips that work with this controller is still larger
> with this than without this.
>
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
>
I currently have the fsl_elbc_nand driver working with BCH codes in softwar=
e.
The patch is fairly small (although I'm just hardcoding the required ECC
configuration). I'll see if I can clean it up and push it upstream soon.

Regards,
Stijn

Re: [PATCH v2] mtd/nand : workaround for Freescale FCM to support large-page Nand chip

[Stijn Devriendt]

On Mon, Aug 15, 2011 at 6:11 PM, Scott Wood <scottwood@freescale.com> wrote:
> On 08/15/2011 10:59 AM, Artem Bityutskiy wrote:
>> On Tue, 2011-07-12 at 12:48 +0800, b35362@freescale.com wrote:
>>> +    /*
>>> +     * Hack for supporting the flash chip whose writesize is
>>> +     * larger than 2K bytes.
>>> +     */
>>> +    if (mtd->writesize > 2048) {
>>> +            elbc_fcm_ctrl->subpage_shift = ffs(mtd->writesize >> 11) - 1;
>>> +            elbc_fcm_ctrl->subpage_mask =
>>> +                    (1 << elbc_fcm_ctrl->subpage_shift) - 1;
>>> +            /*
>>> +             * Rewrite mtd->writesize, mtd->oobsize, chip->page_shift
>>> +             * and chip->pagemask.
>>> +             */
>>> +            mtd->writesize = 2048;
>>> +            mtd->oobsize = 64;
>>> +            chip->page_shift = ffs(mtd->writesize) - 1;
>>> +            chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
>>> +    }
>>
>> So basically if the flash has 4KiB NAND pages, you are considering it as
>> a flash with 2KiB NAND pages. But surely this will work only if the
>> underlying flash has NOP 2 at least. Or even, if you consider that JFFS2
>> and YAFFS want to write to OOB, you need NOP 4 (2 ECC writes and 2
>> writes from YAFFS/JFFS2) ? So this won't work for NOP1 flashes?
>
> Right.  The set of chips that work with this controller is still larger
> with this than without this.
>
> It looks like NOP1 tends to be MLC -- you probably wouldn't want to use
> MLC with this controller anyway as it only does 1-bit ECC.
>
I currently have the fsl_elbc_nand driver working with BCH codes in software.
The patch is fairly small (although I'm just hardcoding the required ECC
configuration). I'll see if I can clean it up and push it upstream soon.

Regards,
Stijn