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From: Atish Patra <atishp@atishpatra.org>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ard Biesheuvel <ardb@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Atish Patra <atishp@rivosinc.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Anup Patel <apatel@ventanamicro.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	linux-efi <linux-efi@vger.kernel.org>,
	Sunil V L <sunil.vl@gmail.com>
Subject: Re: [PATCH V2 3/5] riscv: smp: Support for 64bit hartid
Date: Thu, 26 May 2022 15:57:46 -0700	[thread overview]
Message-ID: <CAOnJCU+a7fHisvS55Kj2=4pGapxtf8SvaPZmcnvy16M32tRztw@mail.gmail.com> (raw)
In-Reply-To: <20220526101131.2340729-4-sunilvl@ventanamicro.com>

On Thu, May 26, 2022 at 3:12 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> The hartid can be a 64bit value on RV64 platforms. This patch
> modifies the hartid parameter in riscv_hartid_to_cpuid() as
> unsigned long so that it can hold 64bit value on RV64 platforms.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  arch/riscv/include/asm/smp.h | 4 ++--
>  arch/riscv/kernel/smp.c      | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> index 23170c933d73..d3443be7eedc 100644
> --- a/arch/riscv/include/asm/smp.h
> +++ b/arch/riscv/include/asm/smp.h
> @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask);
>  /* Hook for the generic smp_call_function_single() routine. */
>  void arch_send_call_function_single_ipi(int cpu);
>
> -int riscv_hartid_to_cpuid(int hartid);
> +int riscv_hartid_to_cpuid(unsigned long hartid);
>
>  /* Set custom IPI operations */
>  void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
> @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int prec)
>  {
>  }
>
> -static inline int riscv_hartid_to_cpuid(int hartid)
> +static inline int riscv_hartid_to_cpuid(unsigned long hartid)
>  {
>         if (hartid == boot_cpu_hartid)
>                 return 0;
> diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
> index b5d30ea92292..018e7dc45df6 100644
> --- a/arch/riscv/kernel/smp.c
> +++ b/arch/riscv/kernel/smp.c
> @@ -47,7 +47,7 @@ static struct {
>         unsigned long bits ____cacheline_aligned;
>  } ipi_data[NR_CPUS] __cacheline_aligned;
>
> -int riscv_hartid_to_cpuid(int hartid)
> +int riscv_hartid_to_cpuid(unsigned long hartid)
>  {
>         int i;
>
> @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid)
>                 if (cpuid_to_hartid_map(i) == hartid)
>                         return i;
>
> -       pr_err("Couldn't find cpu id for hartid [%d]\n", hartid);
> +       pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid);
>         return -ENOENT;
>  }
>
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp@rivosinc.com>
-- 
Regards,
Atish

WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@atishpatra.org>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	 Thomas Gleixner <tglx@linutronix.de>,
	Ard Biesheuvel <ardb@kernel.org>, Marc Zyngier <maz@kernel.org>,
	 Atish Patra <atishp@rivosinc.com>,
	 Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Anup Patel <apatel@ventanamicro.com>,
	 linux-riscv <linux-riscv@lists.infradead.org>,
	 "linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	linux-efi <linux-efi@vger.kernel.org>,
	 Sunil V L <sunil.vl@gmail.com>
Subject: Re: [PATCH V2 3/5] riscv: smp: Support for 64bit hartid
Date: Thu, 26 May 2022 15:57:46 -0700	[thread overview]
Message-ID: <CAOnJCU+a7fHisvS55Kj2=4pGapxtf8SvaPZmcnvy16M32tRztw@mail.gmail.com> (raw)
In-Reply-To: <20220526101131.2340729-4-sunilvl@ventanamicro.com>

On Thu, May 26, 2022 at 3:12 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> The hartid can be a 64bit value on RV64 platforms. This patch
> modifies the hartid parameter in riscv_hartid_to_cpuid() as
> unsigned long so that it can hold 64bit value on RV64 platforms.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  arch/riscv/include/asm/smp.h | 4 ++--
>  arch/riscv/kernel/smp.c      | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> index 23170c933d73..d3443be7eedc 100644
> --- a/arch/riscv/include/asm/smp.h
> +++ b/arch/riscv/include/asm/smp.h
> @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask);
>  /* Hook for the generic smp_call_function_single() routine. */
>  void arch_send_call_function_single_ipi(int cpu);
>
> -int riscv_hartid_to_cpuid(int hartid);
> +int riscv_hartid_to_cpuid(unsigned long hartid);
>
>  /* Set custom IPI operations */
>  void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
> @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int prec)
>  {
>  }
>
> -static inline int riscv_hartid_to_cpuid(int hartid)
> +static inline int riscv_hartid_to_cpuid(unsigned long hartid)
>  {
>         if (hartid == boot_cpu_hartid)
>                 return 0;
> diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
> index b5d30ea92292..018e7dc45df6 100644
> --- a/arch/riscv/kernel/smp.c
> +++ b/arch/riscv/kernel/smp.c
> @@ -47,7 +47,7 @@ static struct {
>         unsigned long bits ____cacheline_aligned;
>  } ipi_data[NR_CPUS] __cacheline_aligned;
>
> -int riscv_hartid_to_cpuid(int hartid)
> +int riscv_hartid_to_cpuid(unsigned long hartid)
>  {
>         int i;
>
> @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid)
>                 if (cpuid_to_hartid_map(i) == hartid)
>                         return i;
>
> -       pr_err("Couldn't find cpu id for hartid [%d]\n", hartid);
> +       pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid);
>         return -ENOENT;
>  }
>
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp@rivosinc.com>
-- 
Regards,
Atish

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-05-26 22:58 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-26 10:11 [PATCH V2 0/5] Support for 64bit hartid on RV64 platforms Sunil V L
2022-05-26 10:11 ` Sunil V L
2022-05-26 10:11 ` [PATCH V2 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid Sunil V L
2022-05-26 10:11   ` Sunil V L
2022-05-26 22:54   ` Atish Patra
2022-05-26 22:54     ` Atish Patra
2022-05-26 10:11 ` [PATCH V2 2/5] riscv: spinwait: Fix hartid variable type Sunil V L
2022-05-26 10:11   ` Sunil V L
2022-05-26 22:56   ` Atish Patra
2022-05-26 22:56     ` Atish Patra
2022-05-26 10:11 ` [PATCH V2 3/5] riscv: smp: Support for 64bit hartid Sunil V L
2022-05-26 10:11   ` Sunil V L
2022-05-26 22:57   ` Atish Patra [this message]
2022-05-26 22:57     ` Atish Patra
2022-05-26 10:11 ` [PATCH V2 4/5] riscv: cpu: " Sunil V L
2022-05-26 10:11   ` Sunil V L
2022-05-26 23:10   ` Atish Patra
2022-05-26 23:10     ` Atish Patra
2022-05-27  4:30     ` Sunil V L
2022-05-27  4:30       ` Sunil V L
2022-05-26 10:11 ` [PATCH V2 5/5] riscv/efi_stub: Support for 64bit boot-hartid Sunil V L
2022-05-26 10:11   ` Sunil V L

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