* [PATCH 1/2] spi: ich: Limit slave->max_read_size
@ 2021-07-28 10:28 Bin Meng
2021-07-28 10:28 ` [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS Bin Meng
2021-07-29 1:32 ` [PATCH 1/2] spi: ich: Limit slave->max_read_size Simon Glass
0 siblings, 2 replies; 6+ messages in thread
From: Bin Meng @ 2021-07-28 10:28 UTC (permalink / raw)
To: u-boot, Simon Glass, Jagan Teki
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
(in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
in software sequencer mode.
ICH controller can only transfer a small number of bytes at once.
Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes
is limited to slave->max_write_size but after commit 43c145b8b3ee
data.nbytes is no longer limited because slave->max_read_size is not
initialized with a valid number.
Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/spi/ich.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 3d49c22a9d..08d54e86f4 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -918,12 +918,14 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
struct spi_slave *slave = dev_get_parent_priv(dev);
/*
- * Yes this controller can only write a small number of bytes at
+ * Yes this controller can only transfer a small number of bytes at
* once! The limit is typically 64 bytes. For hardware sequencing a
* a loop is used to get around this.
*/
- if (!plat->hwseq)
+ if (!plat->hwseq) {
+ slave->max_read_size = priv->databytes;
slave->max_write_size = priv->databytes;
+ }
/*
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS
2021-07-28 10:28 [PATCH 1/2] spi: ich: Limit slave->max_read_size Bin Meng
@ 2021-07-28 10:28 ` Bin Meng
2021-07-29 1:45 ` Simon Glass
2021-07-29 1:32 ` [PATCH 1/2] spi: ich: Limit slave->max_read_size Simon Glass
1 sibling, 1 reply; 6+ messages in thread
From: Bin Meng @ 2021-07-28 10:28 UTC (permalink / raw)
To: u-boot, Simon Glass, Jagan Teki
Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to
the spi-nor core.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
configs/crownbay_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index af8fb0d805..1208aad42f 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -47,6 +47,7 @@ CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_E1000=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] spi: ich: Limit slave->max_read_size
2021-07-28 10:28 [PATCH 1/2] spi: ich: Limit slave->max_read_size Bin Meng
2021-07-28 10:28 ` [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS Bin Meng
@ 2021-07-29 1:32 ` Simon Glass
2021-07-29 12:04 ` Bin Meng
1 sibling, 1 reply; 6+ messages in thread
From: Simon Glass @ 2021-07-29 1:32 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, Jagan Teki
On Wed, 28 Jul 2021 at 04:29, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
> (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
> in software sequencer mode.
>
> ICH controller can only transfer a small number of bytes at once.
> Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes
> is limited to slave->max_write_size but after commit 43c145b8b3ee
> data.nbytes is no longer limited because slave->max_read_size is not
> initialized with a valid number.
>
> Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> drivers/spi/ich.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS
2021-07-28 10:28 ` [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS Bin Meng
@ 2021-07-29 1:45 ` Simon Glass
2021-07-29 12:04 ` Bin Meng
0 siblings, 1 reply; 6+ messages in thread
From: Simon Glass @ 2021-07-29 1:45 UTC (permalink / raw)
To: Bin Meng; +Cc: U-Boot Mailing List, Jagan Teki
On Wed, 28 Jul 2021 at 04:29, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
> SPI flash on Intel Crown Bay board does not work anymore.
>
> Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to
> the spi-nor core.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> configs/crownbay_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] spi: ich: Limit slave->max_read_size
2021-07-29 1:32 ` [PATCH 1/2] spi: ich: Limit slave->max_read_size Simon Glass
@ 2021-07-29 12:04 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-07-29 12:04 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Jagan Teki
On Thu, Jul 29, 2021 at 9:32 AM Simon Glass <sjg@chromium.org> wrote:
>
> On Wed, 28 Jul 2021 at 04:29, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
> > (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller
> > in software sequencer mode.
> >
> > ICH controller can only transfer a small number of bytes at once.
> > Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes
> > is limited to slave->max_write_size but after commit 43c145b8b3ee
> > data.nbytes is no longer limited because slave->max_read_size is not
> > initialized with a valid number.
> >
> > Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()")
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > drivers/spi/ich.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS
2021-07-29 1:45 ` Simon Glass
@ 2021-07-29 12:04 ` Bin Meng
0 siblings, 0 replies; 6+ messages in thread
From: Bin Meng @ 2021-07-29 12:04 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Jagan Teki
On Thu, Jul 29, 2021 at 9:45 AM Simon Glass <sjg@chromium.org> wrote:
>
> On Wed, 28 Jul 2021 at 04:29, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection")
> > SPI flash on Intel Crown Bay board does not work anymore.
> >
> > Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to
> > the spi-nor core.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > configs/crownbay_defconfig | 1 +
> > 1 file changed, 1 insertion(+)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-07-29 12:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-28 10:28 [PATCH 1/2] spi: ich: Limit slave->max_read_size Bin Meng
2021-07-28 10:28 ` [PATCH 2/2] x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS Bin Meng
2021-07-29 1:45 ` Simon Glass
2021-07-29 12:04 ` Bin Meng
2021-07-29 1:32 ` [PATCH 1/2] spi: ich: Limit slave->max_read_size Simon Glass
2021-07-29 12:04 ` Bin Meng
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