* [U-Boot] [PATCH 1/9] pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 2/9] pinctrl: Add pinctrl driver support for Exynos7420 SoC Thomas Abraham
` (8 subsequent siblings)
9 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
It is possible to have multiple pin controllers in the system. Use the
DM_UC_FLAG_SEQ_ALIAS flag so that the pinctrl instances are assigned
a sequence number.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
drivers/pinctrl/pinctrl-uclass.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index ccc5d30..fd04b26 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -287,5 +287,6 @@ static int pinctrl_post_bind(struct udevice *dev)
UCLASS_DRIVER(pinctrl) = {
.id = UCLASS_PINCTRL,
.post_bind = pinctrl_post_bind,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
.name = "pinctrl",
};
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 2/9] pinctrl: Add pinctrl driver support for Exynos7420 SoC
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 1/9] pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 3/9] clk: fixed_rate: allow driver usage prior to relocation Thomas Abraham
` (7 subsequent siblings)
9 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.
The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/exynos/Kconfig | 10 ++
drivers/pinctrl/exynos/Makefile | 9 ++
drivers/pinctrl/exynos/pinctrl-exynos.c | 141 +++++++++++++++++++++++++++
drivers/pinctrl/exynos/pinctrl-exynos.h | 77 +++++++++++++++
drivers/pinctrl/exynos/pinctrl-exynos7420.c | 121 +++++++++++++++++++++++
7 files changed, 360 insertions(+), 0 deletions(-)
create mode 100644 drivers/pinctrl/exynos/Kconfig
create mode 100644 drivers/pinctrl/exynos/Makefile
create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.c
create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.h
create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos7420.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 2a69bab..bdf8931 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,5 +145,6 @@ endif
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/exynos/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 37dc904..19beb04 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
+obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
new file mode 100644
index 0000000..84b6aaa
--- /dev/null
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -0,0 +1,10 @@
+config PINCTRL_EXYNOS
+ bool
+
+config PINCTRL_EXYNOS7420
+ bool "Samsung Exynos7420 pinctrl driver"
+ depends on ARCH_EXYNOS && PINCTRL_FULL
+ select PINCTRL_EXYNOS
+ help
+ Support pin multiplexing and pin configuration control on
+ Samsung's Exynos7420 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
new file mode 100644
index 0000000..d9b941a
--- /dev/null
+++ b/drivers/pinctrl/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c
new file mode 100644
index 0000000..a28405f
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -0,0 +1,141 @@
+/*
+ * Exynos pinctrl driver common code.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
+ * conf: soc specific pin configuration data array
+ * num_conf: number of configurations in the conf array.
+ * base: base address of the pin controller.
+ */
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+ unsigned int num_conf, unsigned long base)
+{
+ unsigned int idx, val;
+
+ for (idx = 0; idx < num_conf; idx++) {
+ val = readl(base + conf[idx].offset);
+ val &= ~(conf[idx].mask);
+ val |= conf[idx].value;
+ writel(val, base + conf[idx].offset);
+ }
+}
+
+/* given a pin-name, return the address of pin config registers */
+static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
+ u32 *pin)
+{
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl;
+ const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks;
+ u32 nr_banks = pin_ctrl->nr_banks, idx = 0;
+ char bank[10];
+
+ /*
+ * The format of the pin name is <bank name>-<pin_number>.
+ * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
+ */
+ while (pin_name[idx] != '-') {
+ bank[idx] = pin_name[idx];
+ idx++;
+ }
+ bank[idx] = '\0';
+ *pin = pin_name[++idx] - '0';
+
+ /* lookup the pin bank data using the pin bank name */
+ for (idx = 0; idx < nr_banks; idx++)
+ if (!strcmp(bank, bank_data[idx].name))
+ break;
+
+ return priv->base + bank_data[idx].offset;
+}
+
+/**
+ * exynos_pinctrl_set_state: configure a pin state.
+ * dev: the pinctrl device to be configured.
+ * config: the state to be configured.
+ */
+int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ const void *fdt = gd->fdt_blob;
+ int node = config->of_offset;
+ unsigned int count, idx, pin_num, ret;
+ unsigned int pinfunc, pinpud, pindrv;
+ unsigned long reg, value;
+ const char *name;
+
+ /*
+ * refer to the following document for the pinctrl bindings
+ * linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+ */
+ count = fdt_count_strings(fdt, node, "samsung,pins");
+ if (count <= 0)
+ return -EINVAL;
+
+ pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
+ pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
+ pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+
+ for (idx = 0; idx < count; idx++) {
+ ret = fdt_get_string_index(fdt, node, "samsung,pins",
+ idx, &name);
+ if (ret < 0)
+ continue;
+ reg = pin_to_bank_base(dev, name, &pin_num);
+
+ if (pinfunc != -1) {
+ value = readl(reg + PIN_CON);
+ value &= ~(0xf << (pin_num << 2));
+ value |= (pinfunc << (pin_num << 2));
+ writel(value, reg + PIN_CON);
+ }
+
+ if (pinpud != -1) {
+ value = readl(reg + PIN_PUD);
+ value &= ~(0x3 << (pin_num << 1));
+ value |= (pinpud << (pin_num << 1));
+ writel(value, reg + PIN_PUD);
+ }
+
+ if (pindrv != -1) {
+ value = readl(reg + PIN_DRV);
+ value &= ~(0x3 << (pin_num << 1));
+ value |= (pindrv << (pin_num << 1));
+ writel(value, reg + PIN_DRV);
+ }
+ }
+
+ return 0;
+}
+
+int exynos_pinctrl_probe(struct udevice *dev)
+{
+ struct exynos_pinctrl_priv *priv;
+ fdt_addr_t base;
+
+ priv = dev_get_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = base;
+ priv->pin_ctrl = (struct samsung_pin_ctrl *)dev_get_driver_data(dev) +
+ dev->req_seq;
+
+ return 0;
+}
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h
new file mode 100644
index 0000000..abd582d
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -0,0 +1,77 @@
+/*
+ * Exynos pinctrl driver header.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PINCTRL_EXYNOS_H_
+#define __PINCTRL_EXYNOS__H_
+
+#define PIN_CON 0x00 /* Offset of pin function register */
+#define PIN_DAT 0x04 /* Offset of pin data register */
+#define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
+#define PIN_DRV 0x0C /* Offset of pin drive strength register */
+
+/**
+ * struct samsung_pin_bank_data: represent a controller pin-bank data.
+ * @offset: starting offset of the pin-bank registers.
+ * @nr_pins: number of pins included in this bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank_data {
+ u32 offset;
+ u8 nr_pins;
+ const char *name;
+};
+
+#define EXYNOS_PIN_BANK(pins, reg, id) \
+ { \
+ .offset = reg, \
+ .nr_pins = pins, \
+ .name = id \
+ }
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ */
+struct samsung_pin_ctrl {
+ const struct samsung_pin_bank_data *pin_banks;
+ u32 nr_banks;
+};
+
+/**
+ * struct exynos_pinctrl_priv: exynos pin controller driver private data
+ * @pin_ctrl: pin controller bank information.
+ * @base: base address of the pin controller instance.
+ * @num_banks: number of pin banks included in the pin controller.
+ */
+struct exynos_pinctrl_priv {
+ const struct samsung_pin_ctrl *pin_ctrl;
+ unsigned long base;
+ int num_banks;
+};
+
+/**
+ * struct exynos_pinctrl_config_data: configuration for a peripheral.
+ * @offset: offset of the config registers in the controller.
+ * @mask: value of the register to be masked with.
+ * @value: new value to be programmed.
+ */
+struct exynos_pinctrl_config_data {
+ const unsigned int offset;
+ const unsigned int mask;
+ const unsigned int value;
+};
+
+
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+ unsigned int num_conf, unsigned long base);
+int exynos_pinctrl_set_state(struct udevice *dev,
+ struct udevice *config);
+int exynos_pinctrl_probe(struct udevice *dev);
+
+#endif /* __PINCTRL_EXYNOS_H_ */
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
new file mode 100644
index 0000000..aca0677
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
@@ -0,0 +1,120 @@
+/*
+ * Exynos7420 pinctrl driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPD1_OFFSET 0xc0
+
+static struct exynos_pinctrl_config_data serial2_conf[] = {
+ {
+ .offset = GPD1_OFFSET + PIN_CON,
+ .mask = 0x00ff0000,
+ .value = 0x00220000,
+ }, {
+ .offset = GPD1_OFFSET + PIN_PUD,
+ .mask = 0x00000f00,
+ .value = 0x00000f00,
+ },
+};
+
+static int exynos7420_pinctrl_request(struct udevice *dev, int peripheral,
+ int flags)
+{
+ struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned long base = priv->base;
+
+ switch (PERIPH_ID_UART2) {
+ case PERIPH_ID_UART2:
+ exynos_pinctrl_setup_peri(serial2_conf,
+ ARRAY_SIZE(serial2_conf), base);
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops exynos7420_pinctrl_ops = {
+ .set_state = exynos_pinctrl_set_state,
+ .request = exynos7420_pinctrl_request,
+};
+
+/* pin banks of Exynos7420 pin-controller - BUS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks0[] = {
+ EXYNOS_PIN_BANK(5, 0x000, "gpb0"),
+ EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
+ EXYNOS_PIN_BANK(2, 0x040, "gpc1"),
+ EXYNOS_PIN_BANK(6, 0x060, "gpc2"),
+ EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
+ EXYNOS_PIN_BANK(4, 0x0a0, "gpd0"),
+ EXYNOS_PIN_BANK(6, 0x0c0, "gpd1"),
+ EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
+ EXYNOS_PIN_BANK(5, 0x100, "gpd4"),
+ EXYNOS_PIN_BANK(4, 0x120, "gpd5"),
+ EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
+ EXYNOS_PIN_BANK(3, 0x160, "gpd7"),
+ EXYNOS_PIN_BANK(2, 0x180, "gpd8"),
+ EXYNOS_PIN_BANK(2, 0x1a0, "gpg0"),
+ EXYNOS_PIN_BANK(4, 0x1c0, "gpg3"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks1[] = {
+ EXYNOS_PIN_BANK(7, 0x000, "gpr4"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS1 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks2[] = {
+ EXYNOS_PIN_BANK(4, 0x000, "gpr0"),
+ EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
+ EXYNOS_PIN_BANK(5, 0x040, "gpr2"),
+ EXYNOS_PIN_BANK(8, 0x060, "gpr3"),
+};
+
+const struct samsung_pin_ctrl exynos7420_pin_ctrl[] = {
+ {
+ /* pin-controller instance BUS0 data */
+ .pin_banks = exynos7420_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos7420_pin_banks0),
+ }, {
+ /* pin-controller instance FSYS0 data */
+ .pin_banks = exynos7420_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos7420_pin_banks1),
+ }, {
+ /* pin-controller instance FSYS1 data */
+ .pin_banks = exynos7420_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos7420_pin_banks2),
+ },
+};
+
+static const struct udevice_id exynos7420_pinctrl_ids[] = {
+ { .compatible = "samsung,exynos7420-pinctrl",
+ .data = (ulong)exynos7420_pin_ctrl },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos7420) = {
+ .name = "pinctrl_exynos7420",
+ .id = UCLASS_PINCTRL,
+ .of_match = exynos7420_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
+ .ops = &exynos7420_pinctrl_ops,
+ .probe = exynos_pinctrl_probe,
+ .flags = DM_FLAG_PRE_RELOC
+};
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/9] clk: fixed_rate: allow driver usage prior to relocation
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 1/9] pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 2/9] pinctrl: Add pinctrl driver support for Exynos7420 SoC Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-20 14:40 ` Simon Glass
2016-04-13 10:43 ` [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc Thomas Abraham
` (6 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
The fixed rate clock driver could be used to represent oscillator
clocks. Platforms that need to determine the rate of the oscillator
clock frequency would require that the fixed rate clock driver
be available for use prior to relocation. So add the
DM_FLAG_PRE_RELOC property to the driver flags.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
drivers/clk/clk_fixed_rate.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 8beda9c..070e568 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -54,4 +54,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
.ops = &clk_fixed_rate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 3/9] clk: fixed_rate: allow driver usage prior to relocation
2016-04-13 10:43 ` [U-Boot] [PATCH 3/9] clk: fixed_rate: allow driver usage prior to relocation Thomas Abraham
@ 2016-04-20 14:40 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:40 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> The fixed rate clock driver could be used to represent oscillator
> clocks. Platforms that need to determine the rate of the oscillator
> clock frequency would require that the fixed rate clock driver
> be available for use prior to relocation. So add the
> DM_FLAG_PRE_RELOC property to the driver flags.
>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Simon Glass <sjg@chromium.org>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> drivers/clk/clk_fixed_rate.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
Can you instead use the u-boot,dm-pre-reloc property in the DT? This
change will affect everyone.
>
> diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
> index 8beda9c..070e568 100644
> --- a/drivers/clk/clk_fixed_rate.c
> +++ b/drivers/clk/clk_fixed_rate.c
> @@ -54,4 +54,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
> .ops = &clk_fixed_rate_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> };
> --
> 1.6.6.rc2
>
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (2 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 3/9] clk: fixed_rate: allow driver usage prior to relocation Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-20 14:41 ` Simon Glass
2016-04-13 10:43 ` [U-Boot] [PATCH 5/9] serial: s5p: get the port id number from the alias of the device node Thomas Abraham
` (5 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
are added in this initial version of the driver.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/exynos/Kconfig | 18 +++
drivers/clk/exynos/Makefile | 9 +
drivers/clk/exynos/clk-exynos7420.c | 227 ++++++++++++++++++++++++++++
drivers/clk/exynos/clk-pll.c | 35 +++++
drivers/clk/exynos/clk-pll.h | 9 +
include/dt-bindings/clock/exynos7420-clk.h | 207 +++++++++++++++++++++++++
8 files changed, 507 insertions(+), 0 deletions(-)
create mode 100644 drivers/clk/exynos/Kconfig
create mode 100644 drivers/clk/exynos/Makefile
create mode 100644 drivers/clk/exynos/clk-exynos7420.c
create mode 100644 drivers/clk/exynos/clk-pll.c
create mode 100644 drivers/clk/exynos/clk-pll.h
create mode 100644 include/dt-bindings/clock/exynos7420-clk.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a98b74b..6eee8eb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -21,5 +21,6 @@ config SPL_CLK
used as U-Boot proper.
source "drivers/clk/uniphier/Kconfig"
+source "drivers/clk/exynos/Kconfig"
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c51db15..81fe600 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
new file mode 100644
index 0000000..eb0efa9
--- /dev/null
+++ b/drivers/clk/exynos/Kconfig
@@ -0,0 +1,18 @@
+config CLK_EXYNOS
+ bool
+ select CLK
+ help
+ This enables support for common clock driver API on Samsung
+ Exynos SoCs.
+
+menu "Clock drivers for Exynos SoCs"
+ depends on CLK_EXYNOS
+
+config CLK_EXYNOS7420
+ bool "Clock driver for Samsung's Exynos7420 SoC"
+ default y
+ help
+ This enables common clock driver support for platforms based
+ on Samsung Exynos7420 SoC.
+
+endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
new file mode 100644
index 0000000..1df10fe
--- /dev/null
+++ b/drivers/clk/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
new file mode 100644
index 0000000..1feaea4
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -0,0 +1,226 @@
+/*
+ * Samsung Exynos7420 clock driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <clk.h>
+#include "clk-pll.h"
+#include <dt-bindings/clock/exynos7420-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIVIDER(reg, shift, mask) \
+ (((readl(reg) >> shift) & mask) + 1)
+
+struct exynos7420_clk_cmu_topc {
+ unsigned int rsvd1[68];
+ unsigned int bus0_pll_con[2];
+ unsigned int rsvd2[2];
+ unsigned int bus1_pll_con[2];
+ unsigned int rsvd3[54];
+ unsigned int mux_sel[6];
+ unsigned int rsvd4[250];
+ unsigned int div[4];
+};
+
+struct exynos7420_clk_topc_priv {
+ struct exynos7420_clk_cmu_topc *topc;
+ unsigned long fin_freq;
+ unsigned long sclk_bus0_pll_a;
+ unsigned long sclk_bus1_pll_a;
+};
+
+static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+{
+ struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+
+ switch (periph) {
+ case DOUT_SCLK_BUS0_PLL:
+ case SCLK_BUS0_PLL_A:
+ case SCLK_BUS0_PLL_B:
+ return priv->sclk_bus0_pll_a;
+ case DOUT_SCLK_BUS1_PLL:
+ case SCLK_BUS1_PLL_A:
+ case SCLK_BUS1_PLL_B:
+ return priv->sclk_bus1_pll_a;
+ default:
+ return 0;
+ }
+}
+
+static struct clk_ops exynos7420_clk_topc_ops = {
+ .get_periph_rate = exynos7420_topc_get_periph_rate,
+};
+
+static int exynos7420_clk_topc_probe(struct udevice *dev)
+{
+ struct exynos7420_clk_topc_priv *priv;
+ struct exynos7420_clk_cmu_topc *topc;
+ struct udevice *clk_dev;
+ unsigned long rate;
+ fdt_addr_t base;
+ int ret;
+
+ priv = dev_get_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ topc = (struct exynos7420_clk_cmu_topc *)base;
+ priv->topc = topc;
+
+ ret = clk_get_by_index(dev, 0, &clk_dev);
+ if (ret >= 0)
+ priv->fin_freq = clk_get_rate(clk_dev);
+
+ rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
+ if (readl(&topc->mux_sel[1]) & (1 << 16))
+ rate >>= 1;
+ rate /= DIVIDER(&topc->div[3], 0, 0xf);
+ priv->sclk_bus0_pll_a = rate;
+
+ rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
+ DIVIDER(&topc->div[3], 8, 0xf);
+ priv->sclk_bus1_pll_a = rate;
+
+ return 0;
+}
+
+static const struct udevice_id exynos7420_clk_topc_compat[] = {
+ { .compatible = "samsung,exynos7-clock-topc" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_topc) = {
+ .name = "exynos7420-clock-topc",
+ .id = UCLASS_CLK,
+ .of_match = exynos7420_clk_topc_compat,
+ .probe = exynos7420_clk_topc_probe,
+ .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+ .ops = &exynos7420_clk_topc_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+struct exynos7420_clk_cmu_top0 {
+ unsigned int rsvd0[128];
+ unsigned int mux_sel[7];
+ unsigned int rsvd1[261];
+ unsigned int div_peric[5];
+};
+
+struct exynos7420_clk_top0_priv {
+ struct exynos7420_clk_cmu_top0 *top0;
+ unsigned long mout_top0_bus0_pll_half;
+ unsigned long sclk_uart2;
+};
+
+static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+{
+ struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+ struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
+
+ switch (periph) {
+ case CLK_SCLK_UART2:
+ return priv->mout_top0_bus0_pll_half /
+ DIVIDER(&top0->div_peric[3], 8, 0xf);
+ default:
+ return 0;
+ }
+}
+
+static struct clk_ops exynos7420_clk_top0_ops = {
+ .get_periph_rate = exynos7420_top0_get_periph_rate,
+};
+
+static int exynos7420_clk_top0_probe(struct udevice *dev)
+{
+ struct exynos7420_clk_top0_priv *priv;
+ struct exynos7420_clk_cmu_top0 *top0;
+ struct udevice *clk_dev;
+ fdt_addr_t base;
+ int ret;
+
+ priv = dev_get_priv(dev);
+ if (!priv)
+ return -EINVAL;
+
+ base = dev_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ top0 = (struct exynos7420_clk_cmu_top0 *)base;
+ priv->top0 = top0;
+
+ ret = clk_get_by_index(dev, 1, &clk_dev);
+ if (ret >= 0) {
+ priv->mout_top0_bus0_pll_half =
+ clk_get_periph_rate(clk_dev, ret);
+ if (readl(&top0->mux_sel[1]) & (1 << 16))
+ priv->mout_top0_bus0_pll_half >>= 1;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id exynos7420_clk_top0_compat[] = {
+ { .compatible = "samsung,exynos7-clock-top0" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_top0) = {
+ .name = "exynos7420-clock-top0",
+ .id = UCLASS_CLK,
+ .of_match = exynos7420_clk_top0_compat,
+ .probe = exynos7420_clk_top0_probe,
+ .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+ .ops = &exynos7420_clk_top0_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+{
+ struct udevice *clk_dev;
+ unsigned int ret;
+
+ switch (periph) {
+ case SCLK_UART2:
+ ret = clk_get_by_index(dev, 3, &clk_dev);
+ if (ret >= 0)
+ return clk_get_periph_rate(clk_dev, ret);
+ default:
+ return 0;
+ }
+}
+
+static struct clk_ops exynos7420_clk_peric1_ops = {
+ .get_periph_rate = exynos7420_peric1_get_periph_rate,
+};
+
+static int exynos7420_clk_peric1_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct udevice_id exynos7420_clk_peric1_compat[] = {
+ { .compatible = "samsung,exynos7-clock-peric1" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_peric1) = {
+ .name = "exynos7420-clock-peric1",
+ .id = UCLASS_CLK,
+ .of_match = exynos7420_clk_peric1_compat,
+ .probe = exynos7420_clk_peric1_probe,
+ .ops = &exynos7420_clk_peric1_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
new file mode 100644
index 0000000..dd11268
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.c
@@ -0,0 +1,33 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define PLL145X_MDIV_SHIFT 16
+#define PLL145X_MDIV_MASK 0x3ff
+#define PLL145X_PDIV_SHIFT 8
+#define PLL145X_PDIV_MASK 0x3f
+#define PLL145X_SDIV_SHIFT 0
+#define PLL145X_SDIV_MASK 0x7
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+{
+ unsigned long pll_con1 = readl(con1);
+ unsigned long mdiv, sdiv, pdiv;
+ uint64_t fvco = fin_freq;
+
+ mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+ pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+ sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
new file mode 100644
index 0000000..631d035
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.h
@@ -0,0 +1,9 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
new file mode 100644
index 0000000..10c5586
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7420-clk.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS 1
+#define DOUT_SCLK_BUS0_PLL 2
+#define DOUT_SCLK_BUS1_PLL 3
+#define DOUT_SCLK_CC_PLL 4
+#define DOUT_SCLK_MFC_PLL 5
+#define DOUT_ACLK_CCORE_133 6
+#define DOUT_ACLK_MSCL_532 7
+#define ACLK_MSCL_532 8
+#define DOUT_SCLK_AUD_PLL 9
+#define FOUT_AUD_PLL 10
+#define SCLK_AUD_PLL 11
+#define SCLK_MFC_PLL_B 12
+#define SCLK_MFC_PLL_A 13
+#define SCLK_BUS1_PLL_B 14
+#define SCLK_BUS1_PLL_A 15
+#define SCLK_BUS0_PLL_B 16
+#define SCLK_BUS0_PLL_A 17
+#define SCLK_CC_PLL_B 18
+#define SCLK_CC_PLL_A 19
+#define ACLK_CCORE_133 20
+#define ACLK_PERIS_66 21
+#define TOPC_NR_CLK 22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1 1
+#define DOUT_ACLK_PERIC0 2
+#define CLK_SCLK_UART0 3
+#define CLK_SCLK_UART1 4
+#define CLK_SCLK_UART2 5
+#define CLK_SCLK_UART3 6
+#define CLK_SCLK_SPI0 7
+#define CLK_SCLK_SPI1 8
+#define CLK_SCLK_SPI2 9
+#define CLK_SCLK_SPI3 10
+#define CLK_SCLK_SPI4 11
+#define CLK_SCLK_SPDIF 12
+#define CLK_SCLK_PCM1 13
+#define CLK_SCLK_I2S1 14
+#define CLK_ACLK_PERIC0_66 15
+#define CLK_ACLK_PERIC1_66 16
+#define TOP0_NR_CLK 17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200 1
+#define DOUT_ACLK_FSYS0_200 2
+#define DOUT_SCLK_MMC2 3
+#define DOUT_SCLK_MMC1 4
+#define DOUT_SCLK_MMC0 5
+#define CLK_SCLK_MMC2 6
+#define CLK_SCLK_MMC1 7
+#define CLK_SCLK_MMC0 8
+#define CLK_ACLK_FSYS0_200 9
+#define CLK_ACLK_FSYS1_200 10
+#define CLK_SCLK_PHY_FSYS1 11
+#define CLK_SCLK_PHY_FSYS1_26M 12
+#define MOUT_SCLK_UFSUNIPRO20 13
+#define DOUT_SCLK_UFSUNIPRO20 14
+#define CLK_SCLK_UFSUNIPRO20 15
+#define DOUT_SCLK_PHY_FSYS1 16
+#define DOUT_SCLK_PHY_FSYS1_26M 17
+#define TOP1_NR_CLK 18
+
+/* CCORE */
+#define PCLK_RTC 1
+#define CCORE_NR_CLK 2
+
+/* PERIC0 */
+#define PCLK_UART0 1
+#define SCLK_UART0 2
+#define PCLK_HSI2C0 3
+#define PCLK_HSI2C1 4
+#define PCLK_HSI2C4 5
+#define PCLK_HSI2C5 6
+#define PCLK_HSI2C9 7
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PCLK_ADCIF 12
+#define PERIC0_NR_CLK 13
+
+/* PERIC1 */
+#define PCLK_UART1 1
+#define PCLK_UART2 2
+#define PCLK_UART3 3
+#define SCLK_UART1 4
+#define SCLK_UART2 5
+#define SCLK_UART3 6
+#define PCLK_HSI2C2 7
+#define PCLK_HSI2C3 8
+#define PCLK_HSI2C6 9
+#define PCLK_HSI2C7 10
+#define PCLK_HSI2C8 11
+#define PCLK_SPI0 12
+#define PCLK_SPI1 13
+#define PCLK_SPI2 14
+#define PCLK_SPI3 15
+#define PCLK_SPI4 16
+#define SCLK_SPI0 17
+#define SCLK_SPI1 18
+#define SCLK_SPI2 19
+#define SCLK_SPI3 20
+#define SCLK_SPI4 21
+#define PCLK_I2S1 22
+#define PCLK_PCM1 23
+#define PCLK_SPDIF 24
+#define SCLK_I2S1 25
+#define SCLK_PCM1 26
+#define SCLK_SPDIF 27
+#define PERIC1_NR_CLK 28
+
+/* PERIS */
+#define PCLK_CHIPID 1
+#define SCLK_CHIPID 2
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
+
+/* FSYS0 */
+#define ACLK_MMC2 1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
+#define ACLK_USBDRD300 3
+#define SCLK_USBDRD300_SUSPENDCLK 4
+#define SCLK_USBDRD300_REFCLK 5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK 11
+
+/* FSYS1 */
+#define ACLK_MMC1 1
+#define ACLK_MMC0 2
+#define PHYCLK_UFS20_TX0_SYMBOL 3
+#define PHYCLK_UFS20_RX0_SYMBOL 4
+#define PHYCLK_UFS20_RX1_SYMBOL 5
+#define ACLK_UFS20_LINK 6
+#define SCLK_UFSUNIPRO20_USER 7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
+#define SCLK_COMBO_PHY_EMBEDDED_26M 12
+#define DOUT_PCLK_FSYS1 13
+#define PCLK_GPIO_FSYS1 14
+#define MOUT_FSYS1_PHYCLK_SEL1 15
+#define FSYS1_NR_CLK 16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532 1
+#define DOUT_PCLK_MSCL 2
+#define ACLK_MSCL_0 3
+#define ACLK_MSCL_1 4
+#define ACLK_JPEG 5
+#define ACLK_G2D 6
+#define ACLK_LH_ASYNC_SI_MSCL_0 7
+#define ACLK_LH_ASYNC_SI_MSCL_1 8
+#define ACLK_AXI2ACEL_BRIDGE 9
+#define ACLK_XIU_MSCLX_0 10
+#define ACLK_XIU_MSCLX_1 11
+#define ACLK_QE_MSCL_0 12
+#define ACLK_QE_MSCL_1 13
+#define ACLK_QE_JPEG 14
+#define ACLK_QE_G2D 15
+#define ACLK_PPMU_MSCL_0 16
+#define ACLK_PPMU_MSCL_1 17
+#define ACLK_MSCLNP_133 18
+#define ACLK_AHB2APB_MSCL0P 19
+#define ACLK_AHB2APB_MSCL1P 20
+
+#define PCLK_MSCL_0 21
+#define PCLK_MSCL_1 22
+#define PCLK_JPEG 23
+#define PCLK_G2D 24
+#define PCLK_QE_MSCL_0 25
+#define PCLK_QE_MSCL_1 26
+#define PCLK_QE_JPEG 27
+#define PCLK_QE_G2D 28
+#define PCLK_PPMU_MSCL_0 29
+#define PCLK_PPMU_MSCL_1 30
+#define PCLK_AXI2ACEL_BRIDGE 31
+#define PCLK_PMU_MSCL 32
+#define MSCL_NR_CLK 33
+
+/* AUD */
+#define SCLK_I2S 1
+#define SCLK_PCM 2
+#define PCLK_I2S 3
+#define PCLK_PCM 4
+#define ACLK_ADMA 5
+#define AUD_NR_CLK 6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc
2016-04-13 10:43 ` [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc Thomas Abraham
@ 2016-04-20 14:41 ` Simon Glass
2016-04-23 15:24 ` Thomas Abraham
0 siblings, 1 reply; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:41 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
> blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
> are added in this initial version of the driver.
>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Cc: Simon Glass <sjg@chromium.org>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/exynos/Kconfig | 18 +++
> drivers/clk/exynos/Makefile | 9 +
> drivers/clk/exynos/clk-exynos7420.c | 227 ++++++++++++++++++++++++++++
> drivers/clk/exynos/clk-pll.c | 35 +++++
> drivers/clk/exynos/clk-pll.h | 9 +
> include/dt-bindings/clock/exynos7420-clk.h | 207 +++++++++++++++++++++++++
> 8 files changed, 507 insertions(+), 0 deletions(-)
> create mode 100644 drivers/clk/exynos/Kconfig
> create mode 100644 drivers/clk/exynos/Makefile
> create mode 100644 drivers/clk/exynos/clk-exynos7420.c
> create mode 100644 drivers/clk/exynos/clk-pll.c
> create mode 100644 drivers/clk/exynos/clk-pll.h
> create mode 100644 include/dt-bindings/clock/exynos7420-clk.h
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index a98b74b..6eee8eb 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -21,5 +21,6 @@ config SPL_CLK
> used as U-Boot proper.
>
> source "drivers/clk/uniphier/Kconfig"
> +source "drivers/clk/exynos/Kconfig"
>
> endmenu
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index c51db15..81fe600 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
> obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
> obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
> +obj-$(CONFIG_CLK_EXYNOS) += exynos/
> diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
> new file mode 100644
> index 0000000..eb0efa9
> --- /dev/null
> +++ b/drivers/clk/exynos/Kconfig
> @@ -0,0 +1,18 @@
> +config CLK_EXYNOS
> + bool
> + select CLK
> + help
> + This enables support for common clock driver API on Samsung
> + Exynos SoCs.
> +
> +menu "Clock drivers for Exynos SoCs"
> + depends on CLK_EXYNOS
> +
> +config CLK_EXYNOS7420
> + bool "Clock driver for Samsung's Exynos7420 SoC"
> + default y
> + help
> + This enables common clock driver support for platforms based
> + on Samsung Exynos7420 SoC.
> +
> +endmenu
> diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
> new file mode 100644
> index 0000000..1df10fe
> --- /dev/null
> +++ b/drivers/clk/exynos/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# Copyright (C) 2016 Samsung Electronics
> +# Thomas Abraham <thomas.ab@samsung.com>
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += clk-pll.o
> +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
> diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
> new file mode 100644
> index 0000000..1feaea4
> --- /dev/null
> +++ b/drivers/clk/exynos/clk-exynos7420.c
> @@ -0,0 +1,226 @@
> +/*
> + * Samsung Exynos7420 clock driver.
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <clk.h>
> +#include "clk-pll.h"
> +#include <dt-bindings/clock/exynos7420-clk.h>
Please see include order.
http://www.denx.de/wiki/U-Boot/CodingStyle
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DIVIDER(reg, shift, mask) \
> + (((readl(reg) >> shift) & mask) + 1)
> +
> +struct exynos7420_clk_cmu_topc {
> + unsigned int rsvd1[68];
> + unsigned int bus0_pll_con[2];
> + unsigned int rsvd2[2];
> + unsigned int bus1_pll_con[2];
> + unsigned int rsvd3[54];
> + unsigned int mux_sel[6];
> + unsigned int rsvd4[250];
> + unsigned int div[4];
> +};
> +
> +struct exynos7420_clk_topc_priv {
> + struct exynos7420_clk_cmu_topc *topc;
> + unsigned long fin_freq;
> + unsigned long sclk_bus0_pll_a;
> + unsigned long sclk_bus1_pll_a;
Comments on these members please.
> +};
> +
> +static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
> +{
> + struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
> +
> + switch (periph) {
> + case DOUT_SCLK_BUS0_PLL:
> + case SCLK_BUS0_PLL_A:
> + case SCLK_BUS0_PLL_B:
> + return priv->sclk_bus0_pll_a;
> + case DOUT_SCLK_BUS1_PLL:
> + case SCLK_BUS1_PLL_A:
> + case SCLK_BUS1_PLL_B:
> + return priv->sclk_bus1_pll_a;
> + default:
> + return 0;
> + }
> +}
> +
> +static struct clk_ops exynos7420_clk_topc_ops = {
> + .get_periph_rate = exynos7420_topc_get_periph_rate,
> +};
> +
> +static int exynos7420_clk_topc_probe(struct udevice *dev)
> +{
> + struct exynos7420_clk_topc_priv *priv;
> + struct exynos7420_clk_cmu_topc *topc;
> + struct udevice *clk_dev;
> + unsigned long rate;
> + fdt_addr_t base;
> + int ret;
> +
> + priv = dev_get_priv(dev);
> + if (!priv)
This cannot happen as it is auto-allocated.
> + return -EINVAL;
> +
> + base = dev_get_addr(dev);
> + if (base == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + topc = (struct exynos7420_clk_cmu_topc *)base;
> + priv->topc = topc;
> +
> + ret = clk_get_by_index(dev, 0, &clk_dev);
> + if (ret >= 0)
> + priv->fin_freq = clk_get_rate(clk_dev);
> +
> + rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
> + if (readl(&topc->mux_sel[1]) & (1 << 16))
> + rate >>= 1;
> + rate /= DIVIDER(&topc->div[3], 0, 0xf);
> + priv->sclk_bus0_pll_a = rate;
> +
> + rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
> + DIVIDER(&topc->div[3], 8, 0xf);
> + priv->sclk_bus1_pll_a = rate;
> +
> + return 0;
> +}
> +
> +static const struct udevice_id exynos7420_clk_topc_compat[] = {
> + { .compatible = "samsung,exynos7-clock-topc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(exynos7420_clk_topc) = {
> + .name = "exynos7420-clock-topc",
> + .id = UCLASS_CLK,
> + .of_match = exynos7420_clk_topc_compat,
> + .probe = exynos7420_clk_topc_probe,
> + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
> + .ops = &exynos7420_clk_topc_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +struct exynos7420_clk_cmu_top0 {
> + unsigned int rsvd0[128];
> + unsigned int mux_sel[7];
> + unsigned int rsvd1[261];
> + unsigned int div_peric[5];
> +};
> +
> +struct exynos7420_clk_top0_priv {
> + struct exynos7420_clk_cmu_top0 *top0;
> + unsigned long mout_top0_bus0_pll_half;
> + unsigned long sclk_uart2;
> +};
> +
> +static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
> +{
> + struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
> + struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
> +
> + switch (periph) {
> + case CLK_SCLK_UART2:
> + return priv->mout_top0_bus0_pll_half /
> + DIVIDER(&top0->div_peric[3], 8, 0xf);
> + default:
> + return 0;
> + }
> +}
> +
> +static struct clk_ops exynos7420_clk_top0_ops = {
> + .get_periph_rate = exynos7420_top0_get_periph_rate,
> +};
> +
> +static int exynos7420_clk_top0_probe(struct udevice *dev)
> +{
> + struct exynos7420_clk_top0_priv *priv;
> + struct exynos7420_clk_cmu_top0 *top0;
> + struct udevice *clk_dev;
> + fdt_addr_t base;
> + int ret;
> +
> + priv = dev_get_priv(dev);
> + if (!priv)
> + return -EINVAL;
> +
> + base = dev_get_addr(dev);
> + if (base == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + top0 = (struct exynos7420_clk_cmu_top0 *)base;
> + priv->top0 = top0;
> +
> + ret = clk_get_by_index(dev, 1, &clk_dev);
> + if (ret >= 0) {
> + priv->mout_top0_bus0_pll_half =
> + clk_get_periph_rate(clk_dev, ret);
> + if (readl(&top0->mux_sel[1]) & (1 << 16))
> + priv->mout_top0_bus0_pll_half >>= 1;
> + }
> +
> + return 0;
> +}
> +
> +static const struct udevice_id exynos7420_clk_top0_compat[] = {
> + { .compatible = "samsung,exynos7-clock-top0" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(exynos7420_clk_top0) = {
It might be better to put all the U_BOOT_DRIVER() and compatible stuff
at the end of the file?
> + .name = "exynos7420-clock-top0",
> + .id = UCLASS_CLK,
> + .of_match = exynos7420_clk_top0_compat,
> + .probe = exynos7420_clk_top0_probe,
> + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
> + .ops = &exynos7420_clk_top0_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> +
> +static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
> +{
> + struct udevice *clk_dev;
> + unsigned int ret;
> +
> + switch (periph) {
> + case SCLK_UART2:
> + ret = clk_get_by_index(dev, 3, &clk_dev);
Shouldn't this be:
if (ret < 0)
return ret;
> + if (ret >= 0)
> + return clk_get_periph_rate(clk_dev, ret);
> + default:
> + return 0;
> + }
> +}
> +
> +static struct clk_ops exynos7420_clk_peric1_ops = {
> + .get_periph_rate = exynos7420_peric1_get_periph_rate,
> +};
> +
> +static int exynos7420_clk_peric1_probe(struct udevice *dev)
> +{
> + return 0;
Then you can omit this function.
> +}
> +
> +static const struct udevice_id exynos7420_clk_peric1_compat[] = {
> + { .compatible = "samsung,exynos7-clock-peric1" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(exynos7420_clk_peric1) = {
> + .name = "exynos7420-clock-peric1",
> + .id = UCLASS_CLK,
> + .of_match = exynos7420_clk_peric1_compat,
> + .probe = exynos7420_clk_peric1_probe,
> + .ops = &exynos7420_clk_peric1_ops,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
> new file mode 100644
> index 0000000..dd11268
> --- /dev/null
> +++ b/drivers/clk/exynos/clk-pll.c
> @@ -0,0 +1,33 @@
> +/*
> + * Exynos PLL helper functions for clock drivers.
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <div64.h>
> +
> +#define PLL145X_MDIV_SHIFT 16
> +#define PLL145X_MDIV_MASK 0x3ff
> +#define PLL145X_PDIV_SHIFT 8
> +#define PLL145X_PDIV_MASK 0x3f
> +#define PLL145X_SDIV_SHIFT 0
> +#define PLL145X_SDIV_MASK 0x7
> +
> +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
> +{
> + unsigned long pll_con1 = readl(con1);
> + unsigned long mdiv, sdiv, pdiv;
> + uint64_t fvco = fin_freq;
> +
> + mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
> + pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
> + sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
> +
> + fvco *= mdiv;
> + do_div(fvco, (pdiv << sdiv));
> + return (unsigned long)fvco;
> +}
> diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
> new file mode 100644
> index 0000000..631d035
> --- /dev/null
> +++ b/drivers/clk/exynos/clk-pll.h
> @@ -0,0 +1,9 @@
> +/*
> + * Exynos PLL helper functions for clock drivers.
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
> diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
> new file mode 100644
> index 0000000..10c5586
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos7420-clk.h
> @@ -0,0 +1,207 @@
> +/*
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS7_H
> +
> +/* TOPC */
> +#define DOUT_ACLK_PERIS 1
> +#define DOUT_SCLK_BUS0_PLL 2
> +#define DOUT_SCLK_BUS1_PLL 3
> +#define DOUT_SCLK_CC_PLL 4
> +#define DOUT_SCLK_MFC_PLL 5
> +#define DOUT_ACLK_CCORE_133 6
> +#define DOUT_ACLK_MSCL_532 7
> +#define ACLK_MSCL_532 8
> +#define DOUT_SCLK_AUD_PLL 9
> +#define FOUT_AUD_PLL 10
> +#define SCLK_AUD_PLL 11
> +#define SCLK_MFC_PLL_B 12
> +#define SCLK_MFC_PLL_A 13
> +#define SCLK_BUS1_PLL_B 14
> +#define SCLK_BUS1_PLL_A 15
> +#define SCLK_BUS0_PLL_B 16
> +#define SCLK_BUS0_PLL_A 17
> +#define SCLK_CC_PLL_B 18
> +#define SCLK_CC_PLL_A 19
> +#define ACLK_CCORE_133 20
> +#define ACLK_PERIS_66 21
> +#define TOPC_NR_CLK 22
> +
> +/* TOP0 */
> +#define DOUT_ACLK_PERIC1 1
> +#define DOUT_ACLK_PERIC0 2
> +#define CLK_SCLK_UART0 3
> +#define CLK_SCLK_UART1 4
> +#define CLK_SCLK_UART2 5
> +#define CLK_SCLK_UART3 6
> +#define CLK_SCLK_SPI0 7
> +#define CLK_SCLK_SPI1 8
> +#define CLK_SCLK_SPI2 9
> +#define CLK_SCLK_SPI3 10
> +#define CLK_SCLK_SPI4 11
> +#define CLK_SCLK_SPDIF 12
> +#define CLK_SCLK_PCM1 13
> +#define CLK_SCLK_I2S1 14
> +#define CLK_ACLK_PERIC0_66 15
> +#define CLK_ACLK_PERIC1_66 16
> +#define TOP0_NR_CLK 17
> +
> +/* TOP1 */
> +#define DOUT_ACLK_FSYS1_200 1
> +#define DOUT_ACLK_FSYS0_200 2
> +#define DOUT_SCLK_MMC2 3
> +#define DOUT_SCLK_MMC1 4
> +#define DOUT_SCLK_MMC0 5
> +#define CLK_SCLK_MMC2 6
> +#define CLK_SCLK_MMC1 7
> +#define CLK_SCLK_MMC0 8
> +#define CLK_ACLK_FSYS0_200 9
> +#define CLK_ACLK_FSYS1_200 10
> +#define CLK_SCLK_PHY_FSYS1 11
> +#define CLK_SCLK_PHY_FSYS1_26M 12
> +#define MOUT_SCLK_UFSUNIPRO20 13
> +#define DOUT_SCLK_UFSUNIPRO20 14
> +#define CLK_SCLK_UFSUNIPRO20 15
> +#define DOUT_SCLK_PHY_FSYS1 16
> +#define DOUT_SCLK_PHY_FSYS1_26M 17
> +#define TOP1_NR_CLK 18
> +
> +/* CCORE */
> +#define PCLK_RTC 1
> +#define CCORE_NR_CLK 2
> +
> +/* PERIC0 */
> +#define PCLK_UART0 1
> +#define SCLK_UART0 2
> +#define PCLK_HSI2C0 3
> +#define PCLK_HSI2C1 4
> +#define PCLK_HSI2C4 5
> +#define PCLK_HSI2C5 6
> +#define PCLK_HSI2C9 7
> +#define PCLK_HSI2C10 8
> +#define PCLK_HSI2C11 9
> +#define PCLK_PWM 10
> +#define SCLK_PWM 11
> +#define PCLK_ADCIF 12
> +#define PERIC0_NR_CLK 13
> +
> +/* PERIC1 */
> +#define PCLK_UART1 1
> +#define PCLK_UART2 2
> +#define PCLK_UART3 3
> +#define SCLK_UART1 4
> +#define SCLK_UART2 5
> +#define SCLK_UART3 6
> +#define PCLK_HSI2C2 7
> +#define PCLK_HSI2C3 8
> +#define PCLK_HSI2C6 9
> +#define PCLK_HSI2C7 10
> +#define PCLK_HSI2C8 11
> +#define PCLK_SPI0 12
> +#define PCLK_SPI1 13
> +#define PCLK_SPI2 14
> +#define PCLK_SPI3 15
> +#define PCLK_SPI4 16
> +#define SCLK_SPI0 17
> +#define SCLK_SPI1 18
> +#define SCLK_SPI2 19
> +#define SCLK_SPI3 20
> +#define SCLK_SPI4 21
> +#define PCLK_I2S1 22
> +#define PCLK_PCM1 23
> +#define PCLK_SPDIF 24
> +#define SCLK_I2S1 25
> +#define SCLK_PCM1 26
> +#define SCLK_SPDIF 27
> +#define PERIC1_NR_CLK 28
> +
> +/* PERIS */
> +#define PCLK_CHIPID 1
> +#define SCLK_CHIPID 2
> +#define PCLK_WDT 3
> +#define PCLK_TMU 4
> +#define SCLK_TMU 5
> +#define PERIS_NR_CLK 6
> +
> +/* FSYS0 */
> +#define ACLK_MMC2 1
> +#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
> +#define ACLK_USBDRD300 3
> +#define SCLK_USBDRD300_SUSPENDCLK 4
> +#define SCLK_USBDRD300_REFCLK 5
> +#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
> +#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
> +#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
> +#define ACLK_PDMA0 9
> +#define ACLK_PDMA1 10
> +#define FSYS0_NR_CLK 11
> +
> +/* FSYS1 */
> +#define ACLK_MMC1 1
> +#define ACLK_MMC0 2
> +#define PHYCLK_UFS20_TX0_SYMBOL 3
> +#define PHYCLK_UFS20_RX0_SYMBOL 4
> +#define PHYCLK_UFS20_RX1_SYMBOL 5
> +#define ACLK_UFS20_LINK 6
> +#define SCLK_UFSUNIPRO20_USER 7
> +#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
> +#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
> +#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
> +#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
> +#define SCLK_COMBO_PHY_EMBEDDED_26M 12
> +#define DOUT_PCLK_FSYS1 13
> +#define PCLK_GPIO_FSYS1 14
> +#define MOUT_FSYS1_PHYCLK_SEL1 15
> +#define FSYS1_NR_CLK 16
> +
> +/* MSCL */
> +#define USERMUX_ACLK_MSCL_532 1
> +#define DOUT_PCLK_MSCL 2
> +#define ACLK_MSCL_0 3
> +#define ACLK_MSCL_1 4
> +#define ACLK_JPEG 5
> +#define ACLK_G2D 6
> +#define ACLK_LH_ASYNC_SI_MSCL_0 7
> +#define ACLK_LH_ASYNC_SI_MSCL_1 8
> +#define ACLK_AXI2ACEL_BRIDGE 9
> +#define ACLK_XIU_MSCLX_0 10
> +#define ACLK_XIU_MSCLX_1 11
> +#define ACLK_QE_MSCL_0 12
> +#define ACLK_QE_MSCL_1 13
> +#define ACLK_QE_JPEG 14
> +#define ACLK_QE_G2D 15
> +#define ACLK_PPMU_MSCL_0 16
> +#define ACLK_PPMU_MSCL_1 17
> +#define ACLK_MSCLNP_133 18
> +#define ACLK_AHB2APB_MSCL0P 19
> +#define ACLK_AHB2APB_MSCL1P 20
> +
> +#define PCLK_MSCL_0 21
> +#define PCLK_MSCL_1 22
> +#define PCLK_JPEG 23
> +#define PCLK_G2D 24
> +#define PCLK_QE_MSCL_0 25
> +#define PCLK_QE_MSCL_1 26
> +#define PCLK_QE_JPEG 27
> +#define PCLK_QE_G2D 28
> +#define PCLK_PPMU_MSCL_0 29
> +#define PCLK_PPMU_MSCL_1 30
> +#define PCLK_AXI2ACEL_BRIDGE 31
> +#define PCLK_PMU_MSCL 32
> +#define MSCL_NR_CLK 33
> +
> +/* AUD */
> +#define SCLK_I2S 1
> +#define SCLK_PCM 2
> +#define PCLK_I2S 3
> +#define PCLK_PCM 4
> +#define ACLK_ADMA 5
> +#define AUD_NR_CLK 6
> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
> --
> 1.6.6.rc2
>
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc
2016-04-20 14:41 ` Simon Glass
@ 2016-04-23 15:24 ` Thomas Abraham
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-23 15:24 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, Apr 20, 2016 at 8:11 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Thomas,
>
> On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
>> blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
>> are added in this initial version of the driver.
>>
>> Cc: Minkyu Kang <mk7.kang@samsung.com>
>> Cc: Simon Glass <sjg@chromium.org>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> drivers/clk/Kconfig | 1 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/exynos/Kconfig | 18 +++
>> drivers/clk/exynos/Makefile | 9 +
>> drivers/clk/exynos/clk-exynos7420.c | 227 ++++++++++++++++++++++++++++
>> drivers/clk/exynos/clk-pll.c | 35 +++++
>> drivers/clk/exynos/clk-pll.h | 9 +
>> include/dt-bindings/clock/exynos7420-clk.h | 207 +++++++++++++++++++++++++
>> 8 files changed, 507 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/clk/exynos/Kconfig
>> create mode 100644 drivers/clk/exynos/Makefile
>> create mode 100644 drivers/clk/exynos/clk-exynos7420.c
>> create mode 100644 drivers/clk/exynos/clk-pll.c
>> create mode 100644 drivers/clk/exynos/clk-pll.h
>> create mode 100644 include/dt-bindings/clock/exynos7420-clk.h
>>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index a98b74b..6eee8eb 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -21,5 +21,6 @@ config SPL_CLK
>> used as U-Boot proper.
>>
>> source "drivers/clk/uniphier/Kconfig"
>> +source "drivers/clk/exynos/Kconfig"
>>
>> endmenu
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index c51db15..81fe600 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
>> obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
>> obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
>> +obj-$(CONFIG_CLK_EXYNOS) += exynos/
>> diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
>> new file mode 100644
>> index 0000000..eb0efa9
>> --- /dev/null
>> +++ b/drivers/clk/exynos/Kconfig
>> @@ -0,0 +1,18 @@
>> +config CLK_EXYNOS
>> + bool
>> + select CLK
>> + help
>> + This enables support for common clock driver API on Samsung
>> + Exynos SoCs.
>> +
>> +menu "Clock drivers for Exynos SoCs"
>> + depends on CLK_EXYNOS
>> +
>> +config CLK_EXYNOS7420
>> + bool "Clock driver for Samsung's Exynos7420 SoC"
>> + default y
>> + help
>> + This enables common clock driver support for platforms based
>> + on Samsung Exynos7420 SoC.
>> +
>> +endmenu
>> diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
>> new file mode 100644
>> index 0000000..1df10fe
>> --- /dev/null
>> +++ b/drivers/clk/exynos/Makefile
>> @@ -0,0 +1,9 @@
>> +#
>> +# Copyright (C) 2016 Samsung Electronics
>> +# Thomas Abraham <thomas.ab@samsung.com>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y += clk-pll.o
>> +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
>> diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
>> new file mode 100644
>> index 0000000..1feaea4
>> --- /dev/null
>> +++ b/drivers/clk/exynos/clk-exynos7420.c
>> @@ -0,0 +1,226 @@
>> +/*
>> + * Samsung Exynos7420 clock driver.
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <errno.h>
>> +#include <asm/io.h>
>> +#include <clk.h>
>> +#include "clk-pll.h"
>> +#include <dt-bindings/clock/exynos7420-clk.h>
>
> Please see include order.
>
>
> http://www.denx.de/wiki/U-Boot/CodingStyle
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define DIVIDER(reg, shift, mask) \
>> + (((readl(reg) >> shift) & mask) + 1)
>> +
>> +struct exynos7420_clk_cmu_topc {
>> + unsigned int rsvd1[68];
>> + unsigned int bus0_pll_con[2];
>> + unsigned int rsvd2[2];
>> + unsigned int bus1_pll_con[2];
>> + unsigned int rsvd3[54];
>> + unsigned int mux_sel[6];
>> + unsigned int rsvd4[250];
>> + unsigned int div[4];
>> +};
>> +
>> +struct exynos7420_clk_topc_priv {
>> + struct exynos7420_clk_cmu_topc *topc;
>> + unsigned long fin_freq;
>> + unsigned long sclk_bus0_pll_a;
>> + unsigned long sclk_bus1_pll_a;
>
> Comments on these members please.
>
>> +};
>> +
>> +static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
>> +{
>> + struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
>> +
>> + switch (periph) {
>> + case DOUT_SCLK_BUS0_PLL:
>> + case SCLK_BUS0_PLL_A:
>> + case SCLK_BUS0_PLL_B:
>> + return priv->sclk_bus0_pll_a;
>> + case DOUT_SCLK_BUS1_PLL:
>> + case SCLK_BUS1_PLL_A:
>> + case SCLK_BUS1_PLL_B:
>> + return priv->sclk_bus1_pll_a;
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> +static struct clk_ops exynos7420_clk_topc_ops = {
>> + .get_periph_rate = exynos7420_topc_get_periph_rate,
>> +};
>> +
>> +static int exynos7420_clk_topc_probe(struct udevice *dev)
>> +{
>> + struct exynos7420_clk_topc_priv *priv;
>> + struct exynos7420_clk_cmu_topc *topc;
>> + struct udevice *clk_dev;
>> + unsigned long rate;
>> + fdt_addr_t base;
>> + int ret;
>> +
>> + priv = dev_get_priv(dev);
>> + if (!priv)
>
> This cannot happen as it is auto-allocated.
Ok. This check will be removed.
>
>> + return -EINVAL;
>
>> +
>> + base = dev_get_addr(dev);
>> + if (base == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + topc = (struct exynos7420_clk_cmu_topc *)base;
>> + priv->topc = topc;
>> +
>> + ret = clk_get_by_index(dev, 0, &clk_dev);
>> + if (ret >= 0)
>> + priv->fin_freq = clk_get_rate(clk_dev);
>> +
>> + rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
>> + if (readl(&topc->mux_sel[1]) & (1 << 16))
>> + rate >>= 1;
>> + rate /= DIVIDER(&topc->div[3], 0, 0xf);
>> + priv->sclk_bus0_pll_a = rate;
>> +
>> + rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
>> + DIVIDER(&topc->div[3], 8, 0xf);
>> + priv->sclk_bus1_pll_a = rate;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct udevice_id exynos7420_clk_topc_compat[] = {
>> + { .compatible = "samsung,exynos7-clock-topc" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(exynos7420_clk_topc) = {
>> + .name = "exynos7420-clock-topc",
>> + .id = UCLASS_CLK,
>> + .of_match = exynos7420_clk_topc_compat,
>> + .probe = exynos7420_clk_topc_probe,
>> + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
>> + .ops = &exynos7420_clk_topc_ops,
>> + .flags = DM_FLAG_PRE_RELOC,
>> +};
>> +
>> +struct exynos7420_clk_cmu_top0 {
>> + unsigned int rsvd0[128];
>> + unsigned int mux_sel[7];
>> + unsigned int rsvd1[261];
>> + unsigned int div_peric[5];
>> +};
>> +
>> +struct exynos7420_clk_top0_priv {
>> + struct exynos7420_clk_cmu_top0 *top0;
>> + unsigned long mout_top0_bus0_pll_half;
>> + unsigned long sclk_uart2;
>> +};
>> +
>> +static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
>> +{
>> + struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
>> + struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
>> +
>> + switch (periph) {
>> + case CLK_SCLK_UART2:
>> + return priv->mout_top0_bus0_pll_half /
>> + DIVIDER(&top0->div_peric[3], 8, 0xf);
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> +static struct clk_ops exynos7420_clk_top0_ops = {
>> + .get_periph_rate = exynos7420_top0_get_periph_rate,
>> +};
>> +
>> +static int exynos7420_clk_top0_probe(struct udevice *dev)
>> +{
>> + struct exynos7420_clk_top0_priv *priv;
>> + struct exynos7420_clk_cmu_top0 *top0;
>> + struct udevice *clk_dev;
>> + fdt_addr_t base;
>> + int ret;
>> +
>> + priv = dev_get_priv(dev);
>> + if (!priv)
>> + return -EINVAL;
>> +
>> + base = dev_get_addr(dev);
>> + if (base == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + top0 = (struct exynos7420_clk_cmu_top0 *)base;
>> + priv->top0 = top0;
>> +
>> + ret = clk_get_by_index(dev, 1, &clk_dev);
>> + if (ret >= 0) {
>> + priv->mout_top0_bus0_pll_half =
>> + clk_get_periph_rate(clk_dev, ret);
>> + if (readl(&top0->mux_sel[1]) & (1 << 16))
>> + priv->mout_top0_bus0_pll_half >>= 1;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct udevice_id exynos7420_clk_top0_compat[] = {
>> + { .compatible = "samsung,exynos7-clock-top0" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(exynos7420_clk_top0) = {
>
> It might be better to put all the U_BOOT_DRIVER() and compatible stuff
> at the end of the file?
Ok, will do this in the next version of the patch.
>
>> + .name = "exynos7420-clock-top0",
>> + .id = UCLASS_CLK,
>> + .of_match = exynos7420_clk_top0_compat,
>> + .probe = exynos7420_clk_top0_probe,
>> + .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
>> + .ops = &exynos7420_clk_top0_ops,
>> + .flags = DM_FLAG_PRE_RELOC,
>> +};
>> +
>> +static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
>> +{
>> + struct udevice *clk_dev;
>> + unsigned int ret;
>> +
>> + switch (periph) {
>> + case SCLK_UART2:
>> + ret = clk_get_by_index(dev, 3, &clk_dev);
>
> Shouldn't this be:
>
> if (ret < 0)
> return ret;
Ok.
Thanks,
Thomas.
>
>> + if (ret >= 0)
>> + return clk_get_periph_rate(clk_dev, ret);
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> +static struct clk_ops exynos7420_clk_peric1_ops = {
>> + .get_periph_rate = exynos7420_peric1_get_periph_rate,
>> +};
>> +
>> +static int exynos7420_clk_peric1_probe(struct udevice *dev)
>> +{
>> + return 0;
>
> Then you can omit this function.
>
>> +}
>> +
>> +static const struct udevice_id exynos7420_clk_peric1_compat[] = {
>> + { .compatible = "samsung,exynos7-clock-peric1" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(exynos7420_clk_peric1) = {
>> + .name = "exynos7420-clock-peric1",
>> + .id = UCLASS_CLK,
>> + .of_match = exynos7420_clk_peric1_compat,
>> + .probe = exynos7420_clk_peric1_probe,
>> + .ops = &exynos7420_clk_peric1_ops,
>> + .flags = DM_FLAG_PRE_RELOC,
>> +};
>> diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
>> new file mode 100644
>> index 0000000..dd11268
>> --- /dev/null
>> +++ b/drivers/clk/exynos/clk-pll.c
>> @@ -0,0 +1,33 @@
>> +/*
>> + * Exynos PLL helper functions for clock drivers.
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <div64.h>
>> +
>> +#define PLL145X_MDIV_SHIFT 16
>> +#define PLL145X_MDIV_MASK 0x3ff
>> +#define PLL145X_PDIV_SHIFT 8
>> +#define PLL145X_PDIV_MASK 0x3f
>> +#define PLL145X_SDIV_SHIFT 0
>> +#define PLL145X_SDIV_MASK 0x7
>> +
>> +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
>> +{
>> + unsigned long pll_con1 = readl(con1);
>> + unsigned long mdiv, sdiv, pdiv;
>> + uint64_t fvco = fin_freq;
>> +
>> + mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
>> + pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
>> + sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
>> +
>> + fvco *= mdiv;
>> + do_div(fvco, (pdiv << sdiv));
>> + return (unsigned long)fvco;
>> +}
>> diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
>> new file mode 100644
>> index 0000000..631d035
>> --- /dev/null
>> +++ b/drivers/clk/exynos/clk-pll.h
>> @@ -0,0 +1,9 @@
>> +/*
>> + * Exynos PLL helper functions for clock drivers.
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +u-boot,dm-pre-reloc
>> +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
>> diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
>> new file mode 100644
>> index 0000000..10c5586
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/exynos7420-clk.h
>> @@ -0,0 +1,207 @@
>> +/*
>> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
>> + * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
>> +#define _DT_BINDINGS_CLOCK_EXYNOS7_H
>> +
>> +/* TOPC */
>> +#define DOUT_ACLK_PERIS 1
>> +#define DOUT_SCLK_BUS0_PLL 2
>> +#define DOUT_SCLK_BUS1_PLL 3
>> +#define DOUT_SCLK_CC_PLL 4
>> +#define DOUT_SCLK_MFC_PLL 5
>> +#define DOUT_ACLK_CCORE_133 6
>> +#define DOUT_ACLK_MSCL_532 7
>> +#define ACLK_MSCL_532 8
>> +#define DOUT_SCLK_AUD_PLL 9
>> +#define FOUT_AUD_PLL 10
>> +#define SCLK_AUD_PLL 11
>> +#define SCLK_MFC_PLL_B 12
>> +#define SCLK_MFC_PLL_A 13
>> +#define SCLK_BUS1_PLL_B 14
>> +#define SCLK_BUS1_PLL_A 15
>> +#define SCLK_BUS0_PLL_B 16
>> +#define SCLK_BUS0_PLL_A 17
>> +#define SCLK_CC_PLL_B 18
>> +#define SCLK_CC_PLL_A 19
>> +#define ACLK_CCORE_133 20
>> +#define ACLK_PERIS_66 21
>> +#define TOPC_NR_CLK 22
>> +
>> +/* TOP0 */
>> +#define DOUT_ACLK_PERIC1 1
>> +#define DOUT_ACLK_PERIC0 2
>> +#define CLK_SCLK_UART0 3
>> +#define CLK_SCLK_UART1 4
>> +#define CLK_SCLK_UART2 5
>> +#define CLK_SCLK_UART3 6
>> +#define CLK_SCLK_SPI0 7
>> +#define CLK_SCLK_SPI1 8
>> +#define CLK_SCLK_SPI2 9
>> +#define CLK_SCLK_SPI3 10
>> +#define CLK_SCLK_SPI4 11
>> +#define CLK_SCLK_SPDIF 12
>> +#define CLK_SCLK_PCM1 13
>> +#define CLK_SCLK_I2S1 14
>> +#define CLK_ACLK_PERIC0_66 15
>> +#define CLK_ACLK_PERIC1_66 16
>> +#define TOP0_NR_CLK 17
>> +
>> +/* TOP1 */
>> +#define DOUT_ACLK_FSYS1_200 1
>> +#define DOUT_ACLK_FSYS0_200 2
>> +#define DOUT_SCLK_MMC2 3
>> +#define DOUT_SCLK_MMC1 4
>> +#define DOUT_SCLK_MMC0 5
>> +#define CLK_SCLK_MMC2 6
>> +#define CLK_SCLK_MMC1 7
>> +#define CLK_SCLK_MMC0 8
>> +#define CLK_ACLK_FSYS0_200 9
>> +#define CLK_ACLK_FSYS1_200 10
>> +#define CLK_SCLK_PHY_FSYS1 11
>> +#define CLK_SCLK_PHY_FSYS1_26M 12
>> +#define MOUT_SCLK_UFSUNIPRO20 13
>> +#define DOUT_SCLK_UFSUNIPRO20 14
>> +#define CLK_SCLK_UFSUNIPRO20 15
>> +#define DOUT_SCLK_PHY_FSYS1 16
>> +#define DOUT_SCLK_PHY_FSYS1_26M 17
>> +#define TOP1_NR_CLK 18
>> +
>> +/* CCORE */
>> +#define PCLK_RTC 1
>> +#define CCORE_NR_CLK 2
>> +
>> +/* PERIC0 */
>> +#define PCLK_UART0 1
>> +#define SCLK_UART0 2
>> +#define PCLK_HSI2C0 3
>> +#define PCLK_HSI2C1 4
>> +#define PCLK_HSI2C4 5
>> +#define PCLK_HSI2C5 6
>> +#define PCLK_HSI2C9 7
>> +#define PCLK_HSI2C10 8
>> +#define PCLK_HSI2C11 9
>> +#define PCLK_PWM 10
>> +#define SCLK_PWM 11
>> +#define PCLK_ADCIF 12
>> +#define PERIC0_NR_CLK 13
>> +
>> +/* PERIC1 */
>> +#define PCLK_UART1 1
>> +#define PCLK_UART2 2
>> +#define PCLK_UART3 3
>> +#define SCLK_UART1 4
>> +#define SCLK_UART2 5
>> +#define SCLK_UART3 6
>> +#define PCLK_HSI2C2 7
>> +#define PCLK_HSI2C3 8
>> +#define PCLK_HSI2C6 9
>> +#define PCLK_HSI2C7 10
>> +#define PCLK_HSI2C8 11
>> +#define PCLK_SPI0 12
>> +#define PCLK_SPI1 13
>> +#define PCLK_SPI2 14
>> +#define PCLK_SPI3 15
>> +#define PCLK_SPI4 16
>> +#define SCLK_SPI0 17
>> +#define SCLK_SPI1 18
>> +#define SCLK_SPI2 19
>> +#define SCLK_SPI3 20
>> +#define SCLK_SPI4 21
>> +#define PCLK_I2S1 22
>> +#define PCLK_PCM1 23
>> +#define PCLK_SPDIF 24
>> +#define SCLK_I2S1 25
>> +#define SCLK_PCM1 26
>> +#define SCLK_SPDIF 27
>> +#define PERIC1_NR_CLK 28
>> +
>> +/* PERIS */
>> +#define PCLK_CHIPID 1
>> +#define SCLK_CHIPID 2
>> +#define PCLK_WDT 3
>> +#define PCLK_TMU 4
>> +#define SCLK_TMU 5
>> +#define PERIS_NR_CLK 6
>> +
>> +/* FSYS0 */
>> +#define ACLK_MMC2 1
>> +#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
>> +#define ACLK_USBDRD300 3
>> +#define SCLK_USBDRD300_SUSPENDCLK 4
>> +#define SCLK_USBDRD300_REFCLK 5
>> +#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
>> +#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
>> +#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
>> +#define ACLK_PDMA0 9
>> +#define ACLK_PDMA1 10
>> +#define FSYS0_NR_CLK 11
>> +
>> +/* FSYS1 */
>> +#define ACLK_MMC1 1
>> +#define ACLK_MMC0 2
>> +#define PHYCLK_UFS20_TX0_SYMBOL 3
>> +#define PHYCLK_UFS20_RX0_SYMBOL 4
>> +#define PHYCLK_UFS20_RX1_SYMBOL 5
>> +#define ACLK_UFS20_LINK 6
>> +#define SCLK_UFSUNIPRO20_USER 7
>> +#define PHYCLK_UFS20_RX1_SYMBOL_USER 8
>> +#define PHYCLK_UFS20_RX0_SYMBOL_USER 9
>> +#define PHYCLK_UFS20_TX0_SYMBOL_USER 10
>> +#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
>> +#define SCLK_COMBO_PHY_EMBEDDED_26M 12
>> +#define DOUT_PCLK_FSYS1 13
>> +#define PCLK_GPIO_FSYS1 14
>> +#define MOUT_FSYS1_PHYCLK_SEL1 15
>> +#define FSYS1_NR_CLK 16
>> +
>> +/* MSCL */
>> +#define USERMUX_ACLK_MSCL_532 1
>> +#define DOUT_PCLK_MSCL 2
>> +#define ACLK_MSCL_0 3
>> +#define ACLK_MSCL_1 4
>> +#define ACLK_JPEG 5
>> +#define ACLK_G2D 6
>> +#define ACLK_LH_ASYNC_SI_MSCL_0 7
>> +#define ACLK_LH_ASYNC_SI_MSCL_1 8
>> +#define ACLK_AXI2ACEL_BRIDGE 9
>> +#define ACLK_XIU_MSCLX_0 10
>> +#define ACLK_XIU_MSCLX_1 11
>> +#define ACLK_QE_MSCL_0 12
>> +#define ACLK_QE_MSCL_1 13
>> +#define ACLK_QE_JPEG 14
>> +#define ACLK_QE_G2D 15
>> +#define ACLK_PPMU_MSCL_0 16
>> +#define ACLK_PPMU_MSCL_1 17
>> +#define ACLK_MSCLNP_133 18
>> +#define ACLK_AHB2APB_MSCL0P 19
>> +#define ACLK_AHB2APB_MSCL1P 20
>> +
>> +#define PCLK_MSCL_0 21
>> +#define PCLK_MSCL_1 22
>> +#define PCLK_JPEG 23
>> +#define PCLK_G2D 24
>> +#define PCLK_QE_MSCL_0 25
>> +#define PCLK_QE_MSCL_1 26
>> +#define PCLK_QE_JPEG 27
>> +#define PCLK_QE_G2D 28
>> +#define PCLK_PPMU_MSCL_0 29
>> +#define PCLK_PPMU_MSCL_1 30
>> +#define PCLK_AXI2ACEL_BRIDGE 31
>> +#define PCLK_PMU_MSCL 32
>> +#define MSCL_NR_CLK 33
>> +
>> +/* AUD */
>> +#define SCLK_I2S 1
>> +#define SCLK_PCM 2
>> +#define PCLK_I2S 3
>> +#define PCLK_PCM 4
>> +#define ACLK_ADMA 5
>> +#define AUD_NR_CLK 6
>> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
>> --
>> 1.6.6.rc2
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 5/9] serial: s5p: get the port id number from the alias of the device node
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (3 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 4/9] clk: exynos: add clock driver for Exynos7420 Soc Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-20 14:41 ` Simon Glass
2016-04-13 10:43 ` [U-Boot] [PATCH 6/9] serial: s5p: use clock api to get clock rate Thomas Abraham
` (4 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
The port id, if not specified in the device node, can be obtained from
the alias of the device node listed in the aliases node.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
drivers/serial/serial_s5p.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index feba467..038d9b6 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -175,6 +175,8 @@ static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
plat->reg = (struct s5p_uart *)addr;
plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
+ if (plat->port_id == -1)
+ plat->port_id = dev->seq;
return 0;
}
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 5/9] serial: s5p: get the port id number from the alias of the device node
2016-04-13 10:43 ` [U-Boot] [PATCH 5/9] serial: s5p: get the port id number from the alias of the device node Thomas Abraham
@ 2016-04-20 14:41 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:41 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> The port id, if not specified in the device node, can be obtained from
> the alias of the device node listed in the aliases node.
>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> drivers/serial/serial_s5p.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
> index feba467..038d9b6 100644
> --- a/drivers/serial/serial_s5p.c
> +++ b/drivers/serial/serial_s5p.c
> @@ -175,6 +175,8 @@ static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
>
> plat->reg = (struct s5p_uart *)addr;
> plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
> + if (plat->port_id == -1)
> + plat->port_id = dev->seq;
Then why not:
plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"id", dev->seq);
>
> return 0;
> }
> --
> 1.6.6.rc2
>
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 6/9] serial: s5p: use clock api to get clock rate
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (4 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 5/9] serial: s5p: get the port id number from the alias of the device node Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-20 14:41 ` Simon Glass
2016-04-13 10:43 ` [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms Thomas Abraham
` (3 subsequent siblings)
9 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
On Exynos platforms that support clock driver API, allow the driver to
use clock api get the SCLK clock rate.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
drivers/serial/serial_s5p.c | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 038d9b6..cf5b4f0 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -17,6 +17,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <serial.h>
+#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -90,7 +91,19 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
struct s5p_serial_platdata *plat = dev->platdata;
struct s5p_uart *const uart = plat->reg;
- u32 uclk = get_uart_clk(plat->port_id);
+ u32 uclk;
+
+#ifdef CONFIG_CLK_EXYNOS
+ struct udevice *clk_dev;
+ u32 ret;
+
+ ret = clk_get_by_index(dev, 1, &clk_dev);
+ if (ret < 0)
+ return ret;
+ uclk = clk_get_periph_rate(clk_dev, ret);
+#else
+ uclk = get_uart_clk(plat->port_id);
+#endif
s5p_serial_baud(uart, uclk, baudrate);
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (5 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 6/9] serial: s5p: use clock api to get clock rate Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-18 11:09 ` Minkyu Kang
2016-04-18 16:58 ` [U-Boot] [PATCH v2 " Thomas Abraham
2016-04-13 10:43 ` [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC Thomas Abraham
` (2 subsequent siblings)
9 siblings, 2 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
The existing Exynos 32-bit platform support needs to be realigned in
order to support newer 64-bit Exynos platforms. The driver model will
be utlized for drivers on the 64-bit Exynos platforms and so some of
the older platform support code would not be required for the newer
64-bit Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 -
arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
arch/arm/mach-exynos/Makefile | 7 +++++--
arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
arch/arm/mach-exynos/soc.c | 2 ++
6 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b82ec18..ee22a3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
config ARCH_EXYNOS
bool "Samsung EXYNOS"
- select CPU_V7
select DM
select DM_SPI_FLASH
select DM_SERIAL
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a6a7597..acab947 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -7,30 +7,38 @@ choice
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
+ select CPU_V7
select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
+ select CPU_V7
config TARGET_S5PC210_UNIVERSAL
bool "EXYNOS4210 Universal C210 board"
+ select CPU_V7
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
+ select CPU_V7
config TARGET_ODROID
bool "Exynos4412 Odroid board"
+ select CPU_V7
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
+ select CPU_V7
select OF_CONTROL
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
@@ -38,32 +46,38 @@ config TARGET_ARNDALE
config TARGET_SMDK5250
bool "SMDK5250 board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_SPRING
bool "Spring board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8542f89..be5912e 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -5,7 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y += soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y += spl_boot.o
+obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o
endif
diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index 14a1692..f12e3d6 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5422, 0x5422)
#define SAMSUNG_BASE(device, base) \
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
samsung_get_base_##device(void) \
{ \
if (cpu_is_exynos4()) { \
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 7fc8e61..81363bd 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
};
struct gpio_info {
- unsigned int reg_addr; /* Address of register for this part */
+ unsigned long reg_addr; /* Address of register for this part */
unsigned int max_gpio; /* Maximum GPIO in this part */
};
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 0f116b1..5cea5ed 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -11,7 +11,9 @@
void reset_cpu(ulong addr)
{
+#ifndef CONFIG_OF_CONTROL
writel(0x1, samsung_get_base_swreset());
+#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-13 10:43 ` [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms Thomas Abraham
@ 2016-04-18 11:09 ` Minkyu Kang
2016-04-18 14:11 ` Thomas Abraham
2016-04-18 16:58 ` [U-Boot] [PATCH v2 " Thomas Abraham
1 sibling, 1 reply; 28+ messages in thread
From: Minkyu Kang @ 2016-04-18 11:09 UTC (permalink / raw)
To: u-boot
Dear Thomas Abraham,
On 13/04/16 19:43, Thomas Abraham wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> The existing Exynos 32-bit platform support needs to be realigned in
> order to support newer 64-bit Exynos platforms. The driver model will
> be utlized for drivers on the 64-bit Exynos platforms and so some of
> the older platform support code would not be required for the newer
> 64-bit Exynos platforms.
>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 -
> arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
> arch/arm/mach-exynos/Makefile | 7 +++++--
> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
> arch/arm/mach-exynos/soc.c | 2 ++
> 6 files changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b82ec18..ee22a3c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -426,7 +426,6 @@ config TARGET_BCMNSP
>
> config ARCH_EXYNOS
> bool "Samsung EXYNOS"
> - select CPU_V7
> select DM
> select DM_SPI_FLASH
> select DM_SERIAL
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index a6a7597..acab947 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -7,30 +7,38 @@ choice
> config TARGET_SMDKV310
> select SUPPORT_SPL
> bool "Exynos4210 SMDKV310 board"
> + select CPU_V7
> select OF_CONTROL
>
> config TARGET_TRATS
> bool "Exynos4210 Trats board"
> + select CPU_V7
>
> config TARGET_S5PC210_UNIVERSAL
> bool "EXYNOS4210 Universal C210 board"
> + select CPU_V7
>
> config TARGET_ORIGEN
> bool "Exynos4412 Origen board"
> + select CPU_V7
> select SUPPORT_SPL
>
> config TARGET_TRATS2
> bool "Exynos4412 Trat2 board"
> + select CPU_V7
>
> config TARGET_ODROID
> bool "Exynos4412 Odroid board"
> + select CPU_V7
>
> config TARGET_ODROID_XU3
> bool "Exynos5422 Odroid board"
> + select CPU_V7
> select OF_CONTROL
>
> config TARGET_ARNDALE
> bool "Exynos5250 Arndale board"
> + select CPU_V7
> select CPU_V7_HAS_NONSEC
> select CPU_V7_HAS_VIRT
> select SUPPORT_SPL
> @@ -38,32 +46,38 @@ config TARGET_ARNDALE
>
> config TARGET_SMDK5250
> bool "SMDK5250 board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_SNOW
> bool "Snow board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_SPRING
> bool "Spring board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
> select SPL_DISABLE_OF_CONTROL
>
> config TARGET_SMDK5420
> bool "SMDK5420 board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_PEACH_PI
> bool "Peach Pi board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_PEACH_PIT
> bool "Peach Pit board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64?
What do you think?
>
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 8542f89..be5912e 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -5,7 +5,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
> +obj-y += soc.o
> +obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
soc.o, duplicated?
>
> obj-$(CONFIG_EXYNOS5420) += sec_boot.o
>
> @@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
> obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
> obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
> -obj-y += spl_boot.o
> +obj-y += spl_boot.o tzpc.o
> obj-y += lowlevel_init.o
> endif
> diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
> index 14a1692..f12e3d6 100644
> --- a/arch/arm/mach-exynos/include/mach/cpu.h
> +++ b/arch/arm/mach-exynos/include/mach/cpu.h
> @@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
> IS_EXYNOS_TYPE(exynos5422, 0x5422)
>
> #define SAMSUNG_BASE(device, base) \
> -static inline unsigned int __attribute__((no_instrument_function)) \
> +static inline unsigned long __attribute__((no_instrument_function)) \
> samsung_get_base_##device(void) \
> { \
> if (cpu_is_exynos4()) { \
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index 7fc8e61..81363bd 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
> };
>
> struct gpio_info {
> - unsigned int reg_addr; /* Address of register for this part */
> + unsigned long reg_addr; /* Address of register for this part */
> unsigned int max_gpio; /* Maximum GPIO in this part */
> };
>
> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
> index 0f116b1..5cea5ed 100644
> --- a/arch/arm/mach-exynos/soc.c
> +++ b/arch/arm/mach-exynos/soc.c
> @@ -11,7 +11,9 @@
>
> void reset_cpu(ulong addr)
> {
> +#ifndef CONFIG_OF_CONTROL
> writel(0x1, samsung_get_base_swreset());
> +#endif
Is it related change?
> }
>
> #ifndef CONFIG_SYS_DCACHE_OFF
>
Thanks,
Minkyu Kang.
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-18 11:09 ` Minkyu Kang
@ 2016-04-18 14:11 ` Thomas Abraham
2016-04-21 13:51 ` Minkyu Kang
0 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-18 14:11 UTC (permalink / raw)
To: u-boot
Hi Mr. Kang,
On Mon, Apr 18, 2016 at 4:39 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
> Dear Thomas Abraham,
>
> On 13/04/16 19:43, Thomas Abraham wrote:
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> The existing Exynos 32-bit platform support needs to be realigned in
>> order to support newer 64-bit Exynos platforms. The driver model will
>> be utlized for drivers on the 64-bit Exynos platforms and so some of
>> the older platform support code would not be required for the newer
>> 64-bit Exynos platforms.
>>
>> Cc: Minkyu Kang <mk7.kang@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> arch/arm/Kconfig | 1 -
>> arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
>> arch/arm/mach-exynos/Makefile | 7 +++++--
>> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
>> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
>> arch/arm/mach-exynos/soc.c | 2 ++
>> 6 files changed, 23 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index b82ec18..ee22a3c 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -426,7 +426,6 @@ config TARGET_BCMNSP
>>
>> config ARCH_EXYNOS
>> bool "Samsung EXYNOS"
>> - select CPU_V7
>> select DM
>> select DM_SPI_FLASH
>> select DM_SERIAL
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index a6a7597..acab947 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -7,30 +7,38 @@ choice
>> config TARGET_SMDKV310
>> select SUPPORT_SPL
>> bool "Exynos4210 SMDKV310 board"
>> + select CPU_V7
>> select OF_CONTROL
>>
>> config TARGET_TRATS
>> bool "Exynos4210 Trats board"
>> + select CPU_V7
>>
>> config TARGET_S5PC210_UNIVERSAL
>> bool "EXYNOS4210 Universal C210 board"
>> + select CPU_V7
>>
>> config TARGET_ORIGEN
>> bool "Exynos4412 Origen board"
>> + select CPU_V7
>> select SUPPORT_SPL
>>
>> config TARGET_TRATS2
>> bool "Exynos4412 Trat2 board"
>> + select CPU_V7
>>
>> config TARGET_ODROID
>> bool "Exynos4412 Odroid board"
>> + select CPU_V7
>>
>> config TARGET_ODROID_XU3
>> bool "Exynos5422 Odroid board"
>> + select CPU_V7
>> select OF_CONTROL
>>
>> config TARGET_ARNDALE
>> bool "Exynos5250 Arndale board"
>> + select CPU_V7
>> select CPU_V7_HAS_NONSEC
>> select CPU_V7_HAS_VIRT
>> select SUPPORT_SPL
>> @@ -38,32 +46,38 @@ config TARGET_ARNDALE
>>
>> config TARGET_SMDK5250
>> bool "SMDK5250 board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>>
>> config TARGET_SNOW
>> bool "Snow board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>>
>> config TARGET_SPRING
>> bool "Spring board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>> select SPL_DISABLE_OF_CONTROL
>>
>> config TARGET_SMDK5420
>> bool "SMDK5420 board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>>
>> config TARGET_PEACH_PI
>> bool "Peach Pi board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>>
>> config TARGET_PEACH_PIT
>> bool "Peach Pit board"
>> + select CPU_V7
>> select SUPPORT_SPL
>> select OF_CONTROL
>
> I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64?
> What do you think?
I was infact thinking to avoid adding a new ARCH type as much as
possible and reuse ARCH_EXYNOS for 64-bit as well. Eventually, the
code in mach-exynos has to move into respective driver folders
(atleast for ARM64 platforms) and have as little as possible in
mach-exynos directory.
>
>>
>> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
>> index 8542f89..be5912e 100644
>> --- a/arch/arm/mach-exynos/Makefile
>> +++ b/arch/arm/mach-exynos/Makefile
>> @@ -5,7 +5,8 @@
>> # SPDX-License-Identifier: GPL-2.0+
>> #
>>
>> -obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
>> +obj-y += soc.o
>> +obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
>
> soc.o, duplicated?
Right, will fix and resend.
>
>>
>> obj-$(CONFIG_EXYNOS5420) += sec_boot.o
>>
>> @@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
>> obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
>> obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
>> obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
>> -obj-y += spl_boot.o
>> +obj-y += spl_boot.o tzpc.o
>> obj-y += lowlevel_init.o
>> endif
>> diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
>> index 14a1692..f12e3d6 100644
>> --- a/arch/arm/mach-exynos/include/mach/cpu.h
>> +++ b/arch/arm/mach-exynos/include/mach/cpu.h
>> @@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
>> IS_EXYNOS_TYPE(exynos5422, 0x5422)
>>
>> #define SAMSUNG_BASE(device, base) \
>> -static inline unsigned int __attribute__((no_instrument_function)) \
>> +static inline unsigned long __attribute__((no_instrument_function)) \
>> samsung_get_base_##device(void) \
>> { \
>> if (cpu_is_exynos4()) { \
>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
>> index 7fc8e61..81363bd 100644
>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>> @@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
>> };
>>
>> struct gpio_info {
>> - unsigned int reg_addr; /* Address of register for this part */
>> + unsigned long reg_addr; /* Address of register for this part */
>> unsigned int max_gpio; /* Maximum GPIO in this part */
>> };
>>
>> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
>> index 0f116b1..5cea5ed 100644
>> --- a/arch/arm/mach-exynos/soc.c
>> +++ b/arch/arm/mach-exynos/soc.c
>> @@ -11,7 +11,9 @@
>>
>> void reset_cpu(ulong addr)
>> {
>> +#ifndef CONFIG_OF_CONTROL
>> writel(0x1, samsung_get_base_swreset());
>> +#endif
>
> Is it related change?
Yes, it is but I now realize that this is incorrect since some of the
exynos ARMv7 platforms are OF based. The intent was to not have this
executed for Exynos 64-bit platforms but instead use the reset-uclass
driver (by adding a reset driver for exynos sometime later). Probably,
this has to be changed to "#ifdef CONFIG_CPU_V7" for now.
Thanks for your review.
Regards,
Thomas.
>
>> }
>>
>> #ifndef CONFIG_SYS_DCACHE_OFF
>>
>
> Thanks,
> Minkyu Kang.
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-18 14:11 ` Thomas Abraham
@ 2016-04-21 13:51 ` Minkyu Kang
2016-04-23 15:28 ` Thomas Abraham
0 siblings, 1 reply; 28+ messages in thread
From: Minkyu Kang @ 2016-04-21 13:51 UTC (permalink / raw)
To: u-boot
Hi,
On 18/04/16 23:11, Thomas Abraham wrote:
> Hi Mr. Kang,
>
> On Mon, Apr 18, 2016 at 4:39 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
>> Dear Thomas Abraham,
>>
>> On 13/04/16 19:43, Thomas Abraham wrote:
>>> From: Thomas Abraham <thomas.ab@samsung.com>
>>>
>>> The existing Exynos 32-bit platform support needs to be realigned in
>>> order to support newer 64-bit Exynos platforms. The driver model will
>>> be utlized for drivers on the 64-bit Exynos platforms and so some of
>>> the older platform support code would not be required for the newer
>>> 64-bit Exynos platforms.
>>>
>>> Cc: Minkyu Kang <mk7.kang@samsung.com>
>>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>>> ---
>>> arch/arm/Kconfig | 1 -
>>> arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
>>> arch/arm/mach-exynos/Makefile | 7 +++++--
>>> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
>>> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
>>> arch/arm/mach-exynos/soc.c | 2 ++
>>> 6 files changed, 23 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index b82ec18..ee22a3c 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -426,7 +426,6 @@ config TARGET_BCMNSP
>>>
>>> config ARCH_EXYNOS
>>> bool "Samsung EXYNOS"
>>> - select CPU_V7
>>> select DM
>>> select DM_SPI_FLASH
>>> select DM_SERIAL
>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>> index a6a7597..acab947 100644
>>> --- a/arch/arm/mach-exynos/Kconfig
>>> +++ b/arch/arm/mach-exynos/Kconfig
>>> @@ -7,30 +7,38 @@ choice
>>> config TARGET_SMDKV310
>>> select SUPPORT_SPL
>>> bool "Exynos4210 SMDKV310 board"
>>> + select CPU_V7
>>> select OF_CONTROL
>>>
>>> config TARGET_TRATS
>>> bool "Exynos4210 Trats board"
>>> + select CPU_V7
>>>
>>> config TARGET_S5PC210_UNIVERSAL
>>> bool "EXYNOS4210 Universal C210 board"
>>> + select CPU_V7
>>>
>>> config TARGET_ORIGEN
>>> bool "Exynos4412 Origen board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>>
>>> config TARGET_TRATS2
>>> bool "Exynos4412 Trat2 board"
>>> + select CPU_V7
>>>
>>> config TARGET_ODROID
>>> bool "Exynos4412 Odroid board"
>>> + select CPU_V7
>>>
>>> config TARGET_ODROID_XU3
>>> bool "Exynos5422 Odroid board"
>>> + select CPU_V7
>>> select OF_CONTROL
>>>
>>> config TARGET_ARNDALE
>>> bool "Exynos5250 Arndale board"
>>> + select CPU_V7
>>> select CPU_V7_HAS_NONSEC
>>> select CPU_V7_HAS_VIRT
>>> select SUPPORT_SPL
>>> @@ -38,32 +46,38 @@ config TARGET_ARNDALE
>>>
>>> config TARGET_SMDK5250
>>> bool "SMDK5250 board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>>
>>> config TARGET_SNOW
>>> bool "Snow board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>>
>>> config TARGET_SPRING
>>> bool "Spring board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>> select SPL_DISABLE_OF_CONTROL
>>>
>>> config TARGET_SMDK5420
>>> bool "SMDK5420 board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>>
>>> config TARGET_PEACH_PI
>>> bool "Peach Pi board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>>
>>> config TARGET_PEACH_PIT
>>> bool "Peach Pit board"
>>> + select CPU_V7
>>> select SUPPORT_SPL
>>> select OF_CONTROL
>>
>> I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64?
>> What do you think?
>
> I was infact thinking to avoid adding a new ARCH type as much as
> possible and reuse ARCH_EXYNOS for 64-bit as well. Eventually, the
> code in mach-exynos has to move into respective driver folders
> (atleast for ARM64 platforms) and have as little as possible in
> mach-exynos directory.
I understood what you want.
But I think, we can reuse mach-exynos code even if we make new ARCH type.
And the cpu type should have a dependency with ARCH, not boards.
I don't believe that we should add a cpu type to every boards.
Please consider again.
Thanks,
Minkyu Kang.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-21 13:51 ` Minkyu Kang
@ 2016-04-23 15:28 ` Thomas Abraham
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-23 15:28 UTC (permalink / raw)
To: u-boot
Hi Mr. Kang,
On Thu, Apr 21, 2016 at 7:21 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
> Hi,
>
> On 18/04/16 23:11, Thomas Abraham wrote:
>> Hi Mr. Kang,
>>
>> On Mon, Apr 18, 2016 at 4:39 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
>>> Dear Thomas Abraham,
>>>
>>> On 13/04/16 19:43, Thomas Abraham wrote:
>>>> From: Thomas Abraham <thomas.ab@samsung.com>
>>>>
>>>> The existing Exynos 32-bit platform support needs to be realigned in
>>>> order to support newer 64-bit Exynos platforms. The driver model will
>>>> be utlized for drivers on the 64-bit Exynos platforms and so some of
>>>> the older platform support code would not be required for the newer
>>>> 64-bit Exynos platforms.
>>>>
>>>> Cc: Minkyu Kang <mk7.kang@samsung.com>
>>>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>>>> ---
>>>> arch/arm/Kconfig | 1 -
>>>> arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
>>>> arch/arm/mach-exynos/Makefile | 7 +++++--
>>>> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
>>>> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
>>>> arch/arm/mach-exynos/soc.c | 2 ++
>>>> 6 files changed, 23 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>>> index b82ec18..ee22a3c 100644
>>>> --- a/arch/arm/Kconfig
>>>> +++ b/arch/arm/Kconfig
>>>> @@ -426,7 +426,6 @@ config TARGET_BCMNSP
>>>>
>>>> config ARCH_EXYNOS
>>>> bool "Samsung EXYNOS"
>>>> - select CPU_V7
>>>> select DM
>>>> select DM_SPI_FLASH
>>>> select DM_SERIAL
>>>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>>>> index a6a7597..acab947 100644
>>>> --- a/arch/arm/mach-exynos/Kconfig
>>>> +++ b/arch/arm/mach-exynos/Kconfig
>>>> @@ -7,30 +7,38 @@ choice
>>>> config TARGET_SMDKV310
>>>> select SUPPORT_SPL
>>>> bool "Exynos4210 SMDKV310 board"
>>>> + select CPU_V7
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_TRATS
>>>> bool "Exynos4210 Trats board"
>>>> + select CPU_V7
>>>>
>>>> config TARGET_S5PC210_UNIVERSAL
>>>> bool "EXYNOS4210 Universal C210 board"
>>>> + select CPU_V7
>>>>
>>>> config TARGET_ORIGEN
>>>> bool "Exynos4412 Origen board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>>
>>>> config TARGET_TRATS2
>>>> bool "Exynos4412 Trat2 board"
>>>> + select CPU_V7
>>>>
>>>> config TARGET_ODROID
>>>> bool "Exynos4412 Odroid board"
>>>> + select CPU_V7
>>>>
>>>> config TARGET_ODROID_XU3
>>>> bool "Exynos5422 Odroid board"
>>>> + select CPU_V7
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_ARNDALE
>>>> bool "Exynos5250 Arndale board"
>>>> + select CPU_V7
>>>> select CPU_V7_HAS_NONSEC
>>>> select CPU_V7_HAS_VIRT
>>>> select SUPPORT_SPL
>>>> @@ -38,32 +46,38 @@ config TARGET_ARNDALE
>>>>
>>>> config TARGET_SMDK5250
>>>> bool "SMDK5250 board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_SNOW
>>>> bool "Snow board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_SPRING
>>>> bool "Spring board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>> select SPL_DISABLE_OF_CONTROL
>>>>
>>>> config TARGET_SMDK5420
>>>> bool "SMDK5420 board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_PEACH_PI
>>>> bool "Peach Pi board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>>
>>>> config TARGET_PEACH_PIT
>>>> bool "Peach Pit board"
>>>> + select CPU_V7
>>>> select SUPPORT_SPL
>>>> select OF_CONTROL
>>>
>>> I think it's better to split to new architecture type for 64bit exynos platform - ARCH_EXYNOS64?
>>> What do you think?
>>
>> I was infact thinking to avoid adding a new ARCH type as much as
>> possible and reuse ARCH_EXYNOS for 64-bit as well. Eventually, the
>> code in mach-exynos has to move into respective driver folders
>> (atleast for ARM64 platforms) and have as little as possible in
>> mach-exynos directory.
>
> I understood what you want.
> But I think, we can reuse mach-exynos code even if we make new ARCH type.
> And the cpu type should have a dependency with ARCH, not boards.
> I don't believe that we should add a cpu type to every boards.
> Please consider again.
Ok, I understand your point. There is one more approach without adding
a new ARCH_EXYNOS64. This will be posted in the next version of the
patch. I hope that would resolve the concern here.
Thanks,
Thomas.
>
> Thanks,
> Minkyu Kang.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH v2 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-13 10:43 ` [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms Thomas Abraham
2016-04-18 11:09 ` Minkyu Kang
@ 2016-04-18 16:58 ` Thomas Abraham
2016-04-20 14:41 ` Simon Glass
1 sibling, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-18 16:58 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
The existing Exynos 32-bit platform support needs to be realigned in
order to support newer 64-bit Exynos platforms. The driver model will
be utlized for drivers on the 64-bit Exynos platforms and so some of
the older platform support code would not be required for the newer
64-bit Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/Kconfig | 1 -
arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
arch/arm/mach-exynos/Makefile | 5 +++--
arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
arch/arm/mach-exynos/soc.c | 2 ++
6 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b82ec18..ee22a3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -426,7 +426,6 @@ config TARGET_BCMNSP
config ARCH_EXYNOS
bool "Samsung EXYNOS"
- select CPU_V7
select DM
select DM_SPI_FLASH
select DM_SERIAL
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a6a7597..acab947 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -7,30 +7,38 @@ choice
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
+ select CPU_V7
select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
+ select CPU_V7
config TARGET_S5PC210_UNIVERSAL
bool "EXYNOS4210 Universal C210 board"
+ select CPU_V7
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
+ select CPU_V7
select SUPPORT_SPL
config TARGET_TRATS2
bool "Exynos4412 Trat2 board"
+ select CPU_V7
config TARGET_ODROID
bool "Exynos4412 Odroid board"
+ select CPU_V7
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
+ select CPU_V7
select OF_CONTROL
config TARGET_ARNDALE
bool "Exynos5250 Arndale board"
+ select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
@@ -38,32 +46,38 @@ config TARGET_ARNDALE
config TARGET_SMDK5250
bool "SMDK5250 board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_SPRING
bool "Spring board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
select SPL_DISABLE_OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
+ select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8542f89..f3c07b7 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -5,7 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y += soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
@@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y += spl_boot.o
+obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o
endif
diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index 14a1692..f12e3d6 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5422, 0x5422)
#define SAMSUNG_BASE(device, base) \
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
samsung_get_base_##device(void) \
{ \
if (cpu_is_exynos4()) { \
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 7fc8e61..81363bd 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
};
struct gpio_info {
- unsigned int reg_addr; /* Address of register for this part */
+ unsigned long reg_addr; /* Address of register for this part */
unsigned int max_gpio; /* Maximum GPIO in this part */
};
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 0f116b1..737a8dd 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -11,7 +11,9 @@
void reset_cpu(ulong addr)
{
+#ifdef CONFIG_CPU_V7
writel(0x1, samsung_get_base_swreset());
+#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH v2 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms
2016-04-18 16:58 ` [U-Boot] [PATCH v2 " Thomas Abraham
@ 2016-04-20 14:41 ` Simon Glass
0 siblings, 0 replies; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:41 UTC (permalink / raw)
To: u-boot
On 18 April 2016 at 10:58, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> The existing Exynos 32-bit platform support needs to be realigned in
> order to support newer 64-bit Exynos platforms. The driver model will
> be utlized for drivers on the 64-bit Exynos platforms and so some of
> the older platform support code would not be required for the newer
> 64-bit Exynos platforms.
>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> arch/arm/Kconfig | 1 -
> arch/arm/mach-exynos/Kconfig | 14 ++++++++++++++
> arch/arm/mach-exynos/Makefile | 5 +++--
> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
> arch/arm/mach-exynos/soc.c | 2 ++
> 6 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b82ec18..ee22a3c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -426,7 +426,6 @@ config TARGET_BCMNSP
>
> config ARCH_EXYNOS
> bool "Samsung EXYNOS"
> - select CPU_V7
> select DM
> select DM_SPI_FLASH
> select DM_SERIAL
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index a6a7597..acab947 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -7,30 +7,38 @@ choice
> config TARGET_SMDKV310
> select SUPPORT_SPL
> bool "Exynos4210 SMDKV310 board"
> + select CPU_V7
> select OF_CONTROL
>
> config TARGET_TRATS
> bool "Exynos4210 Trats board"
> + select CPU_V7
>
> config TARGET_S5PC210_UNIVERSAL
> bool "EXYNOS4210 Universal C210 board"
> + select CPU_V7
>
> config TARGET_ORIGEN
> bool "Exynos4412 Origen board"
> + select CPU_V7
> select SUPPORT_SPL
>
> config TARGET_TRATS2
> bool "Exynos4412 Trat2 board"
> + select CPU_V7
>
> config TARGET_ODROID
> bool "Exynos4412 Odroid board"
> + select CPU_V7
>
> config TARGET_ODROID_XU3
> bool "Exynos5422 Odroid board"
> + select CPU_V7
> select OF_CONTROL
>
> config TARGET_ARNDALE
> bool "Exynos5250 Arndale board"
> + select CPU_V7
> select CPU_V7_HAS_NONSEC
> select CPU_V7_HAS_VIRT
> select SUPPORT_SPL
> @@ -38,32 +46,38 @@ config TARGET_ARNDALE
>
> config TARGET_SMDK5250
> bool "SMDK5250 board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_SNOW
> bool "Snow board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_SPRING
> bool "Spring board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
> select SPL_DISABLE_OF_CONTROL
>
> config TARGET_SMDK5420
> bool "SMDK5420 board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_PEACH_PI
> bool "Peach Pi board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> config TARGET_PEACH_PIT
> bool "Peach Pit board"
> + select CPU_V7
> select SUPPORT_SPL
> select OF_CONTROL
>
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 8542f89..f3c07b7 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -5,7 +5,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
> +obj-y += soc.o
> +obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
>
> obj-$(CONFIG_EXYNOS5420) += sec_boot.o
>
> @@ -13,6 +14,6 @@ ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
> obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
> obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
> -obj-y += spl_boot.o
> +obj-y += spl_boot.o tzpc.o
> obj-y += lowlevel_init.o
> endif
> diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
> index 14a1692..f12e3d6 100644
> --- a/arch/arm/mach-exynos/include/mach/cpu.h
> +++ b/arch/arm/mach-exynos/include/mach/cpu.h
> @@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
> IS_EXYNOS_TYPE(exynos5422, 0x5422)
>
> #define SAMSUNG_BASE(device, base) \
> -static inline unsigned int __attribute__((no_instrument_function)) \
> +static inline unsigned long __attribute__((no_instrument_function)) \
> samsung_get_base_##device(void) \
> { \
> if (cpu_is_exynos4()) { \
> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index 7fc8e61..81363bd 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
> };
>
> struct gpio_info {
> - unsigned int reg_addr; /* Address of register for this part */
> + unsigned long reg_addr; /* Address of register for this part */
> unsigned int max_gpio; /* Maximum GPIO in this part */
> };
>
> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
> index 0f116b1..737a8dd 100644
> --- a/arch/arm/mach-exynos/soc.c
> +++ b/arch/arm/mach-exynos/soc.c
> @@ -11,7 +11,9 @@
>
> void reset_cpu(ulong addr)
> {
> +#ifdef CONFIG_CPU_V7
> writel(0x1, samsung_get_base_swreset());
> +#endif
> }
>
> #ifndef CONFIG_SYS_DCACHE_OFF
> --
> 1.6.6.rc2
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (6 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 7/9] arm: exynos: realign the code to allow support for newer 64-bit platforms Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-18 17:01 ` [U-Boot] [PATCH v2 " Thomas Abraham
2016-04-20 14:41 ` [U-Boot] [PATCH " Simon Glass
2016-04-13 10:43 ` [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support Thomas Abraham
2016-04-20 9:17 ` [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Alim Akhtar
9 siblings, 2 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
and four Cortex-A53 CPUs and includes various peripheral controllers.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/dts/exynos7420.dtsi | 82 ++++++++++++++++++++++++
arch/arm/mach-exynos/Kconfig | 11 +++
arch/arm/mach-exynos/Makefile | 1 +
arch/arm/mach-exynos/mmu-arm64.c | 35 ++++++++++
arch/arm/mach-exynos/soc.c | 8 +++
include/configs/espresso7420.h | 35 ++++++++++
include/configs/exynos7420-common.h | 117 +++++++++++++++++++++++++++++++++++
7 files changed, 289 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/dts/exynos7420.dtsi
create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
create mode 100644 include/configs/espresso7420.h
create mode 100644 include/configs/exynos7420-common.h
diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
new file mode 100644
index 0000000..990f8a1
--- /dev/null
+++ b/arch/arm/dts/exynos7420.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+ compatible = "samsung,exynos7420";
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ };
+
+ clock_topc: clock-controller at 10570000 {
+ compatible = "samsung,exynos7-clock-topc";
+ reg = <0x10570000 0x10000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ };
+
+ clock_top0: clock-controller at 105d0000 {
+ compatible = "samsung,exynos7-clock-top0";
+ reg = <0x105d0000 0xb000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+ <&clock_topc DOUT_SCLK_BUS1_PLL>,
+ <&clock_topc DOUT_SCLK_CC_PLL>,
+ <&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_peric1: clock-controller at 14c80000 {
+ compatible = "samsung,exynos7-clock-peric1";
+ reg = <0x14c80000 0xd00>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+ <&clock_top0 CLK_SCLK_UART1>,
+ <&clock_top0 CLK_SCLK_UART2>,
+ <&clock_top0 CLK_SCLK_UART3>;
+ clock-names = "fin_pll", "dout_aclk_peric1_66",
+ "sclk_uart1", "sclk_uart2", "sclk_uart3";
+ };
+
+ pinctrl at 13470000 {
+ compatible = "samsung,exynos7420-pinctrl";
+ reg = <0x13470000 0x1000>;
+ u-boot,dm-pre-reloc;
+
+ serial2_bus: serial2-bus {
+ samsung,pins = "gpd1-4", "gpd1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ serial at 14C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x14C30000 0x100>;
+ u-boot,dm-pre-reloc;
+ clocks = <&clock_peric1 PCLK_UART2>,
+ <&clock_peric1 SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial2_bus>;
+ };
+};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index acab947..52a5a30 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
select SUPPORT_SPL
select OF_CONTROL
+config TARGET_ESPRESSO7420
+ bool "ESPRESSO7420 board"
+ select ARM64
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS7420
+ select CLK_EXYNOS
+
endchoice
config SYS_SOC
@@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
source "board/samsung/arndale/Kconfig"
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index be5912e..a238a98 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -7,6 +7,7 @@
obj-y += soc.o
obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
+obj-$(CONFIG_ARM64) += mmu-arm64.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
new file mode 100644
index 0000000..ba6d99d
--- /dev/null
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+ {
+ .base = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ .base = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* List terminator */
+ .base = 0,
+ .size = 0,
+ .attrs = 0,
+ },
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 5cea5ed..0706f5d 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -23,3 +23,11 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+ armv8_switch_to_el2();
+ armv8_switch_to_el1();
+}
+#endif
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
new file mode 100644
index 0000000..2af33e7
--- /dev/null
+++ b/include/configs/espresso7420.h
@@ -0,0 +1,35 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define CONFIG_SPL_STACK CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING " for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+
+#endif /* __CONFIG_ESPRESSO7420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
new file mode 100644
index 0000000..9a7e193
--- /dev/null
+++ b/include/configs/exynos7420-common.h
@@ -0,0 +1,117 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420 /* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY 24000000
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE 0x11001000
+#define GICC_BASE 0x11002000
+
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE 0x02100000
+#define CONFIG_IRAM_SIZE 0x58000
+#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT 0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "ramdisk_addr_r=0x43300000\0" \
+ "scriptaddr=0x50000000\0" \
+ "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS
+
+#endif /* __CONFIG_EXYNOS7420_COMMON_H */
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH v2 8/9] arm: exynos: add support for Exynos7420 SoC
2016-04-13 10:43 ` [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC Thomas Abraham
@ 2016-04-18 17:01 ` Thomas Abraham
2016-04-20 14:41 ` [U-Boot] [PATCH " Simon Glass
1 sibling, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-18 17:01 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
and four Cortex-A53 CPUs and includes various peripheral controllers.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/dts/exynos7420.dtsi | 82 ++++++++++++++++++++++++
arch/arm/mach-exynos/Kconfig | 11 +++
arch/arm/mach-exynos/Makefile | 1 +
arch/arm/mach-exynos/mmu-arm64.c | 35 ++++++++++
arch/arm/mach-exynos/soc.c | 8 +++
include/configs/espresso7420.h | 35 ++++++++++
include/configs/exynos7420-common.h | 117 +++++++++++++++++++++++++++++++++++
7 files changed, 289 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/dts/exynos7420.dtsi
create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
create mode 100644 include/configs/espresso7420.h
create mode 100644 include/configs/exynos7420-common.h
diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
new file mode 100644
index 0000000..990f8a1
--- /dev/null
+++ b/arch/arm/dts/exynos7420.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+ compatible = "samsung,exynos7420";
+
+ fin_pll: xxti {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ u-boot,dm-pre-reloc;
+ #clock-cells = <0>;
+ };
+
+ clock_topc: clock-controller at 10570000 {
+ compatible = "samsung,exynos7-clock-topc";
+ reg = <0x10570000 0x10000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ };
+
+ clock_top0: clock-controller at 105d0000 {
+ compatible = "samsung,exynos7-clock-top0";
+ reg = <0x105d0000 0xb000>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+ <&clock_topc DOUT_SCLK_BUS1_PLL>,
+ <&clock_topc DOUT_SCLK_CC_PLL>,
+ <&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll", "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
+
+ clock_peric1: clock-controller at 14c80000 {
+ compatible = "samsung,exynos7-clock-peric1";
+ reg = <0x14c80000 0xd00>;
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+ <&clock_top0 CLK_SCLK_UART1>,
+ <&clock_top0 CLK_SCLK_UART2>,
+ <&clock_top0 CLK_SCLK_UART3>;
+ clock-names = "fin_pll", "dout_aclk_peric1_66",
+ "sclk_uart1", "sclk_uart2", "sclk_uart3";
+ };
+
+ pinctrl at 13470000 {
+ compatible = "samsung,exynos7420-pinctrl";
+ reg = <0x13470000 0x1000>;
+ u-boot,dm-pre-reloc;
+
+ serial2_bus: serial2-bus {
+ samsung,pins = "gpd1-4", "gpd1-5";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+ };
+
+ serial at 14C30000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x14C30000 0x100>;
+ u-boot,dm-pre-reloc;
+ clocks = <&clock_peric1 PCLK_UART2>,
+ <&clock_peric1 SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial2_bus>;
+ };
+};
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index acab947..52a5a30 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
select SUPPORT_SPL
select OF_CONTROL
+config TARGET_ESPRESSO7420
+ bool "ESPRESSO7420 board"
+ select ARM64
+ select SUPPORT_SPL
+ select OF_CONTROL
+ select SPL_DISABLE_OF_CONTROL
+ select PINCTRL
+ select PINCTRL_EXYNOS7420
+ select CLK_EXYNOS
+
endchoice
config SYS_SOC
@@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
source "board/samsung/arndale/Kconfig"
source "board/samsung/smdk5250/Kconfig"
source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f3c07b7..0cc6c32 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -7,6 +7,7 @@
obj-y += soc.o
obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
+obj-$(CONFIG_ARM64) += mmu-arm64.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
new file mode 100644
index 0000000..ba6d99d
--- /dev/null
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+ {
+ .base = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ .base = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* List terminator */
+ .base = 0,
+ .size = 0,
+ .attrs = 0,
+ },
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 737a8dd..f9c7468 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -23,3 +23,11 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+ armv8_switch_to_el2();
+ armv8_switch_to_el1();
+}
+#endif
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
new file mode 100644
index 0000000..2af33e7
--- /dev/null
+++ b/include/configs/espresso7420.h
@@ -0,0 +1,35 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+#define CONFIG_SPL_STACK CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING " for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+
+#endif /* __CONFIG_ESPRESSO7420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
new file mode 100644
index 0000000..9a7e193
--- /dev/null
+++ b/include/configs/exynos7420-common.h
@@ -0,0 +1,117 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420 /* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY 24000000
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE 0x11001000
+#define GICC_BASE 0x11002000
+
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE 0x02100000
+#define CONFIG_IRAM_SIZE 0x58000
+#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT 0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "bootm_size=0x10000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "ramdisk_addr_r=0x43300000\0" \
+ "scriptaddr=0x50000000\0" \
+ "pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS \
+ EXYNOS_FDTFILE_SETTING \
+ MEM_LAYOUT_ENV_SETTINGS
+
+#endif /* __CONFIG_EXYNOS7420_COMMON_H */
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC
2016-04-13 10:43 ` [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC Thomas Abraham
2016-04-18 17:01 ` [U-Boot] [PATCH v2 " Thomas Abraham
@ 2016-04-20 14:41 ` Simon Glass
2016-04-23 15:31 ` Thomas Abraham
1 sibling, 1 reply; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:41 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
> and four Cortex-A53 CPUs and includes various peripheral controllers.
>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> arch/arm/dts/exynos7420.dtsi | 82 ++++++++++++++++++++++++
> arch/arm/mach-exynos/Kconfig | 11 +++
> arch/arm/mach-exynos/Makefile | 1 +
> arch/arm/mach-exynos/mmu-arm64.c | 35 ++++++++++
> arch/arm/mach-exynos/soc.c | 8 +++
> include/configs/espresso7420.h | 35 ++++++++++
> include/configs/exynos7420-common.h | 117 +++++++++++++++++++++++++++++++++++
> 7 files changed, 289 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/dts/exynos7420.dtsi
> create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
> create mode 100644 include/configs/espresso7420.h
> create mode 100644 include/configs/exynos7420-common.h
>
Please see below:
Reviewed-by: Simon Glass <sjg@chromium.org>
> diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
> new file mode 100644
> index 0000000..990f8a1
> --- /dev/null
> +++ b/arch/arm/dts/exynos7420.dtsi
> @@ -0,0 +1,82 @@
> +/*
> + * Samsung Exynos7420 SoC device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "skeleton.dtsi"
> +#include <dt-bindings/clock/exynos7420-clk.h>
> +/ {
> + compatible = "samsung,exynos7420";
> +
> + fin_pll: xxti {
> + compatible = "fixed-clock";
> + clock-output-names = "fin_pll";
> + u-boot,dm-pre-reloc;
> + #clock-cells = <0>;
> + };
> +
> + clock_topc: clock-controller at 10570000 {
> + compatible = "samsung,exynos7-clock-topc";
> + reg = <0x10570000 0x10000>;
> + u-boot,dm-pre-reloc;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>;
> + clock-names = "fin_pll";
> + };
> +
> + clock_top0: clock-controller at 105d0000 {
> + compatible = "samsung,exynos7-clock-top0";
> + reg = <0x105d0000 0xb000>;
> + u-boot,dm-pre-reloc;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
> + <&clock_topc DOUT_SCLK_BUS1_PLL>,
> + <&clock_topc DOUT_SCLK_CC_PLL>,
> + <&clock_topc DOUT_SCLK_MFC_PLL>;
> + clock-names = "fin_pll", "dout_sclk_bus0_pll",
> + "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
> + "dout_sclk_mfc_pll";
> + };
> +
> + clock_peric1: clock-controller at 14c80000 {
> + compatible = "samsung,exynos7-clock-peric1";
> + reg = <0x14c80000 0xd00>;
> + u-boot,dm-pre-reloc;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
> + <&clock_top0 CLK_SCLK_UART1>,
> + <&clock_top0 CLK_SCLK_UART2>,
> + <&clock_top0 CLK_SCLK_UART3>;
> + clock-names = "fin_pll", "dout_aclk_peric1_66",
> + "sclk_uart1", "sclk_uart2", "sclk_uart3";
> + };
> +
> + pinctrl at 13470000 {
> + compatible = "samsung,exynos7420-pinctrl";
> + reg = <0x13470000 0x1000>;
> + u-boot,dm-pre-reloc;
> +
> + serial2_bus: serial2-bus {
> + samsung,pins = "gpd1-4", "gpd1-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> + };
> +
> + serial at 14C30000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x14C30000 0x100>;
> + u-boot,dm-pre-reloc;
> + clocks = <&clock_peric1 PCLK_UART2>,
> + <&clock_peric1 SCLK_UART2>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&serial2_bus>;
> + };
> +};
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index acab947..52a5a30 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
> select SUPPORT_SPL
> select OF_CONTROL
>
> +config TARGET_ESPRESSO7420
> + bool "ESPRESSO7420 board"
> + select ARM64
> + select SUPPORT_SPL
> + select OF_CONTROL
> + select SPL_DISABLE_OF_CONTROL
> + select PINCTRL
> + select PINCTRL_EXYNOS7420
> + select CLK_EXYNOS
> +
> endchoice
>
> config SYS_SOC
> @@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
> source "board/samsung/arndale/Kconfig"
> source "board/samsung/smdk5250/Kconfig"
> source "board/samsung/smdk5420/Kconfig"
> +source "board/samsung/espresso7420/Kconfig"
>
> endif
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index be5912e..a238a98 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -7,6 +7,7 @@
>
> obj-y += soc.o
> obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
> +obj-$(CONFIG_ARM64) += mmu-arm64.o
>
> obj-$(CONFIG_EXYNOS5420) += sec_boot.o
>
> diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
> new file mode 100644
> index 0000000..ba6d99d
> --- /dev/null
> +++ b/arch/arm/mach-exynos/mmu-arm64.c
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/armv8/mmu.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_EXYNOS7420
> +static struct mm_region exynos7420_mem_map[] = {
> + {
> + .base = 0x10000000UL,
> + .size = 0x10000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN,
> + }, {
> + .base = 0x40000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE,
> + }, {
> + /* List terminator */
> + .base = 0,
> + .size = 0,
> + .attrs = 0,
> + },
> +};
> +
> +struct mm_region *mem_map = exynos7420_mem_map;
> +#endif
> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
> index 5cea5ed..0706f5d 100644
> --- a/arch/arm/mach-exynos/soc.c
> +++ b/arch/arm/mach-exynos/soc.c
> @@ -23,3 +23,11 @@ void enable_caches(void)
> dcache_enable();
> }
> #endif
> +
> +#ifdef CONFIG_ARM64
> +void lowlevel_init(void)
> +{
> + armv8_switch_to_el2();
> + armv8_switch_to_el1();
> +}
> +#endif
> diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
> new file mode 100644
> index 0000000..2af33e7
> --- /dev/null
> +++ b/include/configs/espresso7420.h
> @@ -0,0 +1,35 @@
> +/*
> + * Configuration settings for the SAMSUNG ESPRESSO7420 board.
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_ESPRESSO7420_H
> +#define __CONFIG_ESPRESSO7420_H
> +
> +#include <configs/exynos7420-common.h>
> +
> +#define CONFIG_BOARD_COMMON
> +
> +#define CONFIG_ESPRESSO7420
> +#define CONFIG_ENV_IS_NOWHERE
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
> +#define CONFIG_SYS_TEXT_BASE 0x43E00000
> +#define CONFIG_SPL_STACK CONFIG_IRAM_END
> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END
> +
> +/* select serial console configuration */
> +#define CONFIG_SERIAL2 /* use SERIAL 2 */
Is that needed?
> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
> +
> +#define CONFIG_IDENT_STRING " for ESPRESSO7420"
> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
> +
> +/* DRAM Memory Banks */
> +#define CONFIG_NR_DRAM_BANKS 8
> +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
> +
> +#endif /* __CONFIG_ESPRESSO7420_H */
> diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
> new file mode 100644
> index 0000000..9a7e193
> --- /dev/null
> +++ b/include/configs/exynos7420-common.h
> @@ -0,0 +1,117 @@
> +/*
> + * Configuration settings for the Espresso7420 board.
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_EXYNOS7420_COMMON_H
> +#define __CONFIG_EXYNOS7420_COMMON_H
> +
> +/* High Level Configuration Options */
> +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
> +#define CONFIG_EXYNOS7420 /* Exynos7 Family */
> +#define CONFIG_S5P
> +
> +#include <asm/arch/cpu.h> /* get chip and board defs */
> +#include <linux/sizes.h>
> +
> +#define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +/* Size of malloc() pool before and after relocation */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +/* select serial console configuration */
> +#define CONFIG_BAUDRATE 115200
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +/* Timer input clock frequency */
> +#define COUNTER_FREQUENCY 24000000
> +
> +/* Generic Interrupt Controller Definitions */
> +#define CONFIG_GICV2
> +#define GICD_BASE 0x11001000
> +#define GICC_BASE 0x11002000
Can these be in device tree? Or in arch/asm/include/... ?
> +
> +#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
> +
> +/* IRAM Layout */
> +#define CONFIG_IRAM_BASE 0x02100000
> +#define CONFIG_IRAM_SIZE 0x58000
> +#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
> +
> +/* Number of CPUs available */
> +#define CONFIG_CORE_COUNT 0x8
> +
> +/* select serial console configuration */
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SILENT_CONSOLE
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> +#define CONFIG_CONSOLE_MUX
> +
> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
> +
> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
> +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
> +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
> +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
> +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
I wish we could use device tree for this cruft. Any way?
> +
> +/* Configuration of ENV Blocks */
> +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 1) \
> + func(MMC, mmc, 0) \
> +
> +#ifndef MEM_LAYOUT_ENV_SETTINGS
> +#define MEM_LAYOUT_ENV_SETTINGS \
> + "bootm_size=0x10000000\0" \
> + "kernel_addr_r=0x42000000\0" \
> + "fdt_addr_r=0x43000000\0" \
> + "ramdisk_addr_r=0x43300000\0" \
> + "scriptaddr=0x50000000\0" \
> + "pxefile_addr_r=0x51000000\0"
> +#endif
> +
> +#ifndef EXYNOS_DEVICE_SETTINGS
> +#define EXYNOS_DEVICE_SETTINGS \
> + "stdin=serial\0" \
> + "stdout=serial\0" \
> + "stderr=serial\0"
> +#endif
> +
> +#ifndef EXYNOS_FDTFILE_SETTING
> +#define EXYNOS_FDTFILE_SETTING
> +#endif
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + EXYNOS_DEVICE_SETTINGS \
> + EXYNOS_FDTFILE_SETTING \
> + MEM_LAYOUT_ENV_SETTINGS
> +
> +#endif /* __CONFIG_EXYNOS7420_COMMON_H */
> --
> 1.6.6.rc2
>
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC
2016-04-20 14:41 ` [U-Boot] [PATCH " Simon Glass
@ 2016-04-23 15:31 ` Thomas Abraham
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-23 15:31 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, Apr 20, 2016 at 8:11 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Thomas,
>
> On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
>> and four Cortex-A53 CPUs and includes various peripheral controllers.
>>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> arch/arm/dts/exynos7420.dtsi | 82 ++++++++++++++++++++++++
>> arch/arm/mach-exynos/Kconfig | 11 +++
>> arch/arm/mach-exynos/Makefile | 1 +
>> arch/arm/mach-exynos/mmu-arm64.c | 35 ++++++++++
>> arch/arm/mach-exynos/soc.c | 8 +++
>> include/configs/espresso7420.h | 35 ++++++++++
>> include/configs/exynos7420-common.h | 117 +++++++++++++++++++++++++++++++++++
>> 7 files changed, 289 insertions(+), 0 deletions(-)
>> create mode 100644 arch/arm/dts/exynos7420.dtsi
>> create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
>> create mode 100644 include/configs/espresso7420.h
>> create mode 100644 include/configs/exynos7420-common.h
>>
>
> Please see below:
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Thanks.
>
>> diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
>> new file mode 100644
>> index 0000000..990f8a1
>> --- /dev/null
>> +++ b/arch/arm/dts/exynos7420.dtsi
>> @@ -0,0 +1,82 @@
>> +/*
>> + * Samsung Exynos7420 SoC device tree source
>> + *
>> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +/dts-v1/;
>> +#include "skeleton.dtsi"
>> +#include <dt-bindings/clock/exynos7420-clk.h>
>> +/ {
>> + compatible = "samsung,exynos7420";
>> +
>> + fin_pll: xxti {
>> + compatible = "fixed-clock";
>> + clock-output-names = "fin_pll";
>> + u-boot,dm-pre-reloc;
>> + #clock-cells = <0>;
>> + };
>> +
>> + clock_topc: clock-controller at 10570000 {
>> + compatible = "samsung,exynos7-clock-topc";
>> + reg = <0x10570000 0x10000>;
>> + u-boot,dm-pre-reloc;
>> + #clock-cells = <1>;
>> + clocks = <&fin_pll>;
>> + clock-names = "fin_pll";
>> + };
>> +
>> + clock_top0: clock-controller at 105d0000 {
>> + compatible = "samsung,exynos7-clock-top0";
>> + reg = <0x105d0000 0xb000>;
>> + u-boot,dm-pre-reloc;
>> + #clock-cells = <1>;
>> + clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
>> + <&clock_topc DOUT_SCLK_BUS1_PLL>,
>> + <&clock_topc DOUT_SCLK_CC_PLL>,
>> + <&clock_topc DOUT_SCLK_MFC_PLL>;
>> + clock-names = "fin_pll", "dout_sclk_bus0_pll",
>> + "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
>> + "dout_sclk_mfc_pll";
>> + };
>> +
>> + clock_peric1: clock-controller at 14c80000 {
>> + compatible = "samsung,exynos7-clock-peric1";
>> + reg = <0x14c80000 0xd00>;
>> + u-boot,dm-pre-reloc;
>> + #clock-cells = <1>;
>> + clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
>> + <&clock_top0 CLK_SCLK_UART1>,
>> + <&clock_top0 CLK_SCLK_UART2>,
>> + <&clock_top0 CLK_SCLK_UART3>;
>> + clock-names = "fin_pll", "dout_aclk_peric1_66",
>> + "sclk_uart1", "sclk_uart2", "sclk_uart3";
>> + };
>> +
>> + pinctrl at 13470000 {
>> + compatible = "samsung,exynos7420-pinctrl";
>> + reg = <0x13470000 0x1000>;
>> + u-boot,dm-pre-reloc;
>> +
>> + serial2_bus: serial2-bus {
>> + samsung,pins = "gpd1-4", "gpd1-5";
>> + samsung,pin-function = <2>;
>> + samsung,pin-pud = <3>;
>> + samsung,pin-drv = <0>;
>> + };
>> + };
>> +
>> + serial at 14C30000 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x14C30000 0x100>;
>> + u-boot,dm-pre-reloc;
>> + clocks = <&clock_peric1 PCLK_UART2>,
>> + <&clock_peric1 SCLK_UART2>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&serial2_bus>;
>> + };
>> +};
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index acab947..52a5a30 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -81,6 +81,16 @@ config TARGET_PEACH_PIT
>> select SUPPORT_SPL
>> select OF_CONTROL
>>
>> +config TARGET_ESPRESSO7420
>> + bool "ESPRESSO7420 board"
>> + select ARM64
>> + select SUPPORT_SPL
>> + select OF_CONTROL
>> + select SPL_DISABLE_OF_CONTROL
>> + select PINCTRL
>> + select PINCTRL_EXYNOS7420
>> + select CLK_EXYNOS
>> +
>> endchoice
>>
>> config SYS_SOC
>> @@ -95,5 +105,6 @@ source "board/samsung/odroid/Kconfig"
>> source "board/samsung/arndale/Kconfig"
>> source "board/samsung/smdk5250/Kconfig"
>> source "board/samsung/smdk5420/Kconfig"
>> +source "board/samsung/espresso7420/Kconfig"
>>
>> endif
>> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
>> index be5912e..a238a98 100644
>> --- a/arch/arm/mach-exynos/Makefile
>> +++ b/arch/arm/mach-exynos/Makefile
>> @@ -7,6 +7,7 @@
>>
>> obj-y += soc.o
>> obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o soc.o system.o
>> +obj-$(CONFIG_ARM64) += mmu-arm64.o
>>
>> obj-$(CONFIG_EXYNOS5420) += sec_boot.o
>>
>> diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
>> new file mode 100644
>> index 0000000..ba6d99d
>> --- /dev/null
>> +++ b/arch/arm/mach-exynos/mmu-arm64.c
>> @@ -0,0 +1,35 @@
>> +/*
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/armv8/mmu.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#ifdef CONFIG_EXYNOS7420
>> +static struct mm_region exynos7420_mem_map[] = {
>> + {
>> + .base = 0x10000000UL,
>> + .size = 0x10000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>> + PTE_BLOCK_NON_SHARE |
>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN,
>> + }, {
>> + .base = 0x40000000UL,
>> + .size = 0x80000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> + PTE_BLOCK_INNER_SHARE,
>> + }, {
>> + /* List terminator */
>> + .base = 0,
>> + .size = 0,
>> + .attrs = 0,
>> + },
>> +};
>> +
>> +struct mm_region *mem_map = exynos7420_mem_map;
>> +#endif
>> diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
>> index 5cea5ed..0706f5d 100644
>> --- a/arch/arm/mach-exynos/soc.c
>> +++ b/arch/arm/mach-exynos/soc.c
>> @@ -23,3 +23,11 @@ void enable_caches(void)
>> dcache_enable();
>> }
>> #endif
>> +
>> +#ifdef CONFIG_ARM64
>> +void lowlevel_init(void)
>> +{
>> + armv8_switch_to_el2();
>> + armv8_switch_to_el1();
>> +}
>> +#endif
>> diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
>> new file mode 100644
>> index 0000000..2af33e7
>> --- /dev/null
>> +++ b/include/configs/espresso7420.h
>> @@ -0,0 +1,35 @@
>> +/*
>> + * Configuration settings for the SAMSUNG ESPRESSO7420 board.
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_ESPRESSO7420_H
>> +#define __CONFIG_ESPRESSO7420_H
>> +
>> +#include <configs/exynos7420-common.h>
>> +
>> +#define CONFIG_BOARD_COMMON
>> +
>> +#define CONFIG_ESPRESSO7420
>> +#define CONFIG_ENV_IS_NOWHERE
>> +
>> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
>> +#define CONFIG_SYS_TEXT_BASE 0x43E00000
>> +#define CONFIG_SPL_STACK CONFIG_IRAM_END
>> +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END
>> +
>> +/* select serial console configuration */
>> +#define CONFIG_SERIAL2 /* use SERIAL 2 */
>
> Is that needed?
No, that was not needed. This will be removed in the next version.
>
>> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
>> +
>> +#define CONFIG_IDENT_STRING " for ESPRESSO7420"
>> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
>> +
>> +/* DRAM Memory Banks */
>> +#define CONFIG_NR_DRAM_BANKS 8
>> +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
>> +
>> +#endif /* __CONFIG_ESPRESSO7420_H */
>> diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
>> new file mode 100644
>> index 0000000..9a7e193
>> --- /dev/null
>> +++ b/include/configs/exynos7420-common.h
>> @@ -0,0 +1,117 @@
>> +/*
>> + * Configuration settings for the Espresso7420 board.
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_EXYNOS7420_COMMON_H
>> +#define __CONFIG_EXYNOS7420_COMMON_H
>> +
>> +/* High Level Configuration Options */
>> +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
>> +#define CONFIG_EXYNOS7420 /* Exynos7 Family */
>> +#define CONFIG_S5P
>> +
>> +#include <asm/arch/cpu.h> /* get chip and board defs */
>> +#include <linux/sizes.h>
>> +
>> +#define CONFIG_ARCH_CPU_INIT
>> +#define CONFIG_DISPLAY_BOARDINFO
>> +#define CONFIG_BOARD_EARLY_INIT_F
>> +
>> +/* Size of malloc() pool before and after relocation */
>> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
>> +#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
>> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
>> +
>> +/* Boot Argument Buffer Size */
>> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>> +
>> +/* select serial console configuration */
>> +#define CONFIG_BAUDRATE 115200
>> +
>> +/* FLASH and environment organization */
>> +#define CONFIG_SYS_NO_FLASH
>> +
>> +/* Timer input clock frequency */
>> +#define COUNTER_FREQUENCY 24000000
>> +
>> +/* Generic Interrupt Controller Definitions */
>> +#define CONFIG_GICV2
>> +#define GICD_BASE 0x11001000
>> +#define GICC_BASE 0x11002000
>
> Can these be in device tree? Or in arch/asm/include/... ?
These are not required for now. So will remove these as well.
Thanks,
Thomas.
>
>> +
>> +#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
>> +
>> +/* IRAM Layout */
>> +#define CONFIG_IRAM_BASE 0x02100000
>> +#define CONFIG_IRAM_SIZE 0x58000
>> +#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
>> +
>> +/* Number of CPUs available */
>> +#define CONFIG_CORE_COUNT 0x8
>> +
>> +/* select serial console configuration */
>> +#define CONFIG_BAUDRATE 115200
>> +#define CONFIG_SILENT_CONSOLE
>> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
>> +#define CONFIG_CONSOLE_MUX
>> +
>> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
>> +
>> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
>> +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
>> +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
>
> I wish we could use device tree for this cruft. Any way?
>
>> +
>> +/* Configuration of ENV Blocks */
>> +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
>> +
>> +#define BOOT_TARGET_DEVICES(func) \
>> + func(MMC, mmc, 1) \
>> + func(MMC, mmc, 0) \
>> +
>> +#ifndef MEM_LAYOUT_ENV_SETTINGS
>> +#define MEM_LAYOUT_ENV_SETTINGS \
>> + "bootm_size=0x10000000\0" \
>> + "kernel_addr_r=0x42000000\0" \
>> + "fdt_addr_r=0x43000000\0" \
>> + "ramdisk_addr_r=0x43300000\0" \
>> + "scriptaddr=0x50000000\0" \
>> + "pxefile_addr_r=0x51000000\0"
>> +#endif
>> +
>> +#ifndef EXYNOS_DEVICE_SETTINGS
>> +#define EXYNOS_DEVICE_SETTINGS \
>> + "stdin=serial\0" \
>> + "stdout=serial\0" \
>> + "stderr=serial\0"
>> +#endif
>> +
>> +#ifndef EXYNOS_FDTFILE_SETTING
>> +#define EXYNOS_FDTFILE_SETTING
>> +#endif
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS \
>> + EXYNOS_DEVICE_SETTINGS \
>> + EXYNOS_FDTFILE_SETTING \
>> + MEM_LAYOUT_ENV_SETTINGS
>> +
>> +#endif /* __CONFIG_EXYNOS7420_COMMON_H */
>> --
>> 1.6.6.rc2
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (7 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 8/9] arm: exynos: add support for Exynos7420 SoC Thomas Abraham
@ 2016-04-13 10:43 ` Thomas Abraham
2016-04-20 14:41 ` Simon Glass
2016-04-20 9:17 ` [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Alim Akhtar
9 siblings, 1 reply; 28+ messages in thread
From: Thomas Abraham @ 2016-04-13 10:43 UTC (permalink / raw)
To: u-boot
From: Thomas Abraham <thomas.ab@samsung.com>
Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
includes multiple onboard compoments (EMMC/Codec) and various
interconnects (USB/HDMI).
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/exynos7420-espresso7420.dts | 24 ++++++++++++++++++++++++
board/samsung/common/board.c | 18 ++++++++++++++++--
board/samsung/espresso7420/Kconfig | 12 ++++++++++++
board/samsung/espresso7420/MAINTAINERS | 5 +++++
board/samsung/espresso7420/Makefile | 16 ++++++++++++++++
board/samsung/espresso7420/espresso7420.c | 16 ++++++++++++++++
configs/espresso7420_defconfig | 8 ++++++++
8 files changed, 98 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts
create mode 100644 board/samsung/espresso7420/Kconfig
create mode 100644 board/samsung/espresso7420/MAINTAINERS
create mode 100644 board/samsung/espresso7420/Makefile
create mode 100644 board/samsung/espresso7420/espresso7420.c
create mode 100644 configs/espresso7420_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ea635e4..a61bbff 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -19,6 +19,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb \
exynos5422-odroidxu3.dtb
+dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
rk3288-jerry.dtb \
diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts
new file mode 100644
index 0000000..f17a848
--- /dev/null
+++ b/arch/arm/dts/exynos7420-espresso7420.dts
@@ -0,0 +1,24 @@
+/*
+ * Samsung Espresso7420 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "exynos7420.dtsi"
+/ {
+ model = "Samsung Espresso7420 board based on Exynos7420";
+ compatible = "samsung,espresso7420", "samsung,exynos7420";
+
+ aliases {
+ serial2 = "/serial at 14C30000";
+ console = "/serial at 14C30000";
+ pinctrl0 = "/pinctrl at 13470000";
+ };
+};
+
+&fin_pll {
+ clock-frequency = <24000000>;
+};
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 1334c22..e4f189c 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -27,6 +27,8 @@
#include <usb.h>
#include <dwc3-uboot.h>
#include <samsung/misc.h>
+#include <dm/pinctrl.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -97,7 +99,7 @@ int board_init(void)
int dram_init(void)
{
unsigned int i;
- u32 addr;
+ unsigned long addr;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -109,7 +111,7 @@ int dram_init(void)
void dram_init_banksize(void)
{
unsigned int i;
- u32 addr, size;
+ unsigned long addr, size;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -122,6 +124,17 @@ void dram_init_banksize(void)
static int board_uart_init(void)
{
+#if CONFIG_PINCTRL_EXYNOS
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret)
+ return ret;
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART2);
+ return ret;
+#else
int err, uart_id, ret = 0;
for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
@@ -133,6 +146,7 @@ static int board_uart_init(void)
}
}
return ret;
+#endif
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
new file mode 100644
index 0000000..6cfead0
--- /dev/null
+++ b/board/samsung/espresso7420/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ESPRESSO7420
+
+config SYS_BOARD
+ default "espresso7420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "espresso7420"
+
+endif
diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
new file mode 100644
index 0000000..aaebc4c
--- /dev/null
+++ b/board/samsung/espresso7420/MAINTAINERS
@@ -0,0 +1,5 @@
+ESPRESSO7420 Board
+M: Thomas Abraham <thomas.ab@samsung.com>
+S: Maintained
+F: board/samsung/espresso7420/
+F: include/configs/espresso7420.h
diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
new file mode 100644
index 0000000..53d90fd
--- /dev/null
+++ b/board/samsung/espresso7420/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2015 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#obj-y += espresso7420_spl.o
+#obj-y += clk-boot_evt1.o
+#obj-y += lpddr4_evt1.o
+#obj-y += dmc_init_lpddr4.o
+#obj-y += dmc.o
+#obj-y += clock.o clock_init.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += espresso7420.o
+endif
diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
new file mode 100644
index 0000000..04a83bc
--- /dev/null
+++ b/board/samsung/espresso7420/espresso7420.c
@@ -0,0 +1,16 @@
+/*
+ * Espresso7420 board file
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int exynos_init(void)
+{
+ return 0;
+}
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
new file mode 100644
index 0000000..604921f
--- /dev/null
+++ b/configs/espresso7420_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ESPRESSO7420=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_PROMPT="ESPRESSO7420 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
--
1.6.6.rc2
^ permalink raw reply related [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support
2016-04-13 10:43 ` [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support Thomas Abraham
@ 2016-04-20 14:41 ` Simon Glass
2016-04-23 15:35 ` Thomas Abraham
0 siblings, 1 reply; 28+ messages in thread
From: Simon Glass @ 2016-04-20 14:41 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
> includes multiple onboard compoments (EMMC/Codec) and various
> interconnects (USB/HDMI).
>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/exynos7420-espresso7420.dts | 24 ++++++++++++++++++++++++
> board/samsung/common/board.c | 18 ++++++++++++++++--
> board/samsung/espresso7420/Kconfig | 12 ++++++++++++
> board/samsung/espresso7420/MAINTAINERS | 5 +++++
> board/samsung/espresso7420/Makefile | 16 ++++++++++++++++
> board/samsung/espresso7420/espresso7420.c | 16 ++++++++++++++++
> configs/espresso7420_defconfig | 8 ++++++++
> 8 files changed, 98 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts
> create mode 100644 board/samsung/espresso7420/Kconfig
> create mode 100644 board/samsung/espresso7420/MAINTAINERS
> create mode 100644 board/samsung/espresso7420/Makefile
> create mode 100644 board/samsung/espresso7420/espresso7420.c
> create mode 100644 configs/espresso7420_defconfig
>
Reviewed-by: Simon Glass <sjg@chromium.org>
See below.
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ea635e4..a61bbff 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -19,6 +19,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
> exynos5420-peach-pit.dtb \
> exynos5800-peach-pi.dtb \
> exynos5422-odroidxu3.dtb
> +dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> rk3288-firefly.dtb \
> rk3288-jerry.dtb \
> diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts
> new file mode 100644
> index 0000000..f17a848
> --- /dev/null
> +++ b/arch/arm/dts/exynos7420-espresso7420.dts
> @@ -0,0 +1,24 @@
> +/*
> + * Samsung Espresso7420 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include "exynos7420.dtsi"
> +/ {
> + model = "Samsung Espresso7420 board based on Exynos7420";
> + compatible = "samsung,espresso7420", "samsung,exynos7420";
> +
> + aliases {
> + serial2 = "/serial at 14C30000";
> + console = "/serial at 14C30000";
> + pinctrl0 = "/pinctrl at 13470000";
> + };
> +};
> +
> +&fin_pll {
> + clock-frequency = <24000000>;
> +};
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> index 1334c22..e4f189c 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -27,6 +27,8 @@
> #include <usb.h>
> #include <dwc3-uboot.h>
> #include <samsung/misc.h>
> +#include <dm/pinctrl.h>
> +#include <dm.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -97,7 +99,7 @@ int board_init(void)
> int dram_init(void)
> {
> unsigned int i;
> - u32 addr;
> + unsigned long addr;
>
> for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
> @@ -109,7 +111,7 @@ int dram_init(void)
> void dram_init_banksize(void)
> {
> unsigned int i;
> - u32 addr, size;
> + unsigned long addr, size;
>
> for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
> @@ -122,6 +124,17 @@ void dram_init_banksize(void)
>
> static int board_uart_init(void)
> {
> +#if CONFIG_PINCTRL_EXYNOS
> + struct udevice *pinctrl;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> + if (ret)
> + return ret;
> +
> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART2);
Does this not happen automatically when the UART is probed? It should
call pinctrl_select_state(dev, "default");
> + return ret;
> +#else
> int err, uart_id, ret = 0;
>
> for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
> @@ -133,6 +146,7 @@ static int board_uart_init(void)
> }
> }
> return ret;
> +#endif
> }
>
> #ifdef CONFIG_BOARD_EARLY_INIT_F
> diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
> new file mode 100644
> index 0000000..6cfead0
> --- /dev/null
> +++ b/board/samsung/espresso7420/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_ESPRESSO7420
> +
> +config SYS_BOARD
> + default "espresso7420"
Please add a description of the board in help.
> +
> +config SYS_VENDOR
> + default "samsung"
> +
> +config SYS_CONFIG_NAME
> + default "espresso7420"
> +
> +endif
> diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
> new file mode 100644
> index 0000000..aaebc4c
> --- /dev/null
> +++ b/board/samsung/espresso7420/MAINTAINERS
> @@ -0,0 +1,5 @@
> +ESPRESSO7420 Board
> +M: Thomas Abraham <thomas.ab@samsung.com>
> +S: Maintained
> +F: board/samsung/espresso7420/
> +F: include/configs/espresso7420.h
> diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
> new file mode 100644
> index 0000000..53d90fd
> --- /dev/null
> +++ b/board/samsung/espresso7420/Makefile
> @@ -0,0 +1,16 @@
> +#
> +# Copyright (C) 2015 Samsung Electronics
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +#obj-y += espresso7420_spl.o
> +#obj-y += clk-boot_evt1.o
> +#obj-y += lpddr4_evt1.o
> +#obj-y += dmc_init_lpddr4.o
> +#obj-y += dmc.o
> +#obj-y += clock.o clock_init.o
Why the commented-out files?
> +
> +ifndef CONFIG_SPL_BUILD
> +obj-y += espresso7420.o
> +endif
> diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
> new file mode 100644
> index 0000000..04a83bc
> --- /dev/null
> +++ b/board/samsung/espresso7420/espresso7420.c
> @@ -0,0 +1,16 @@
> +/*
> + * Espresso7420 board file
> + * Copyright (C) 2016 Samsung Electronics
> + * Thomas Abraham <thomas.ab@samsung.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int exynos_init(void)
> +{
> + return 0;
> +}
> diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
> new file mode 100644
> index 0000000..604921f
> --- /dev/null
> +++ b/configs/espresso7420_defconfig
> @@ -0,0 +1,8 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_EXYNOS=y
> +CONFIG_TARGET_ESPRESSO7420=y
> +CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SYS_PROMPT="ESPRESSO7420 # "
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_SETEXPR is not set
> --
> 1.6.6.rc2
>
Regards,
Simon
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support
2016-04-20 14:41 ` Simon Glass
@ 2016-04-23 15:35 ` Thomas Abraham
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-23 15:35 UTC (permalink / raw)
To: u-boot
Hi Simon,
On Wed, Apr 20, 2016 at 8:11 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Thomas,
>
> On 13 April 2016 at 04:43, Thomas Abraham <ta.omasab@gmail.com> wrote:
>> From: Thomas Abraham <thomas.ab@samsung.com>
>>
>> Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
>> includes multiple onboard compoments (EMMC/Codec) and various
>> interconnects (USB/HDMI).
>>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/exynos7420-espresso7420.dts | 24 ++++++++++++++++++++++++
>> board/samsung/common/board.c | 18 ++++++++++++++++--
>> board/samsung/espresso7420/Kconfig | 12 ++++++++++++
>> board/samsung/espresso7420/MAINTAINERS | 5 +++++
>> board/samsung/espresso7420/Makefile | 16 ++++++++++++++++
>> board/samsung/espresso7420/espresso7420.c | 16 ++++++++++++++++
>> configs/espresso7420_defconfig | 8 ++++++++
>> 8 files changed, 98 insertions(+), 2 deletions(-)
>> create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts
>> create mode 100644 board/samsung/espresso7420/Kconfig
>> create mode 100644 board/samsung/espresso7420/MAINTAINERS
>> create mode 100644 board/samsung/espresso7420/Makefile
>> create mode 100644 board/samsung/espresso7420/espresso7420.c
>> create mode 100644 configs/espresso7420_defconfig
>>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> See below.
>
>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>> index ea635e4..a61bbff 100644
>> --- a/arch/arm/dts/Makefile
>> +++ b/arch/arm/dts/Makefile
>> @@ -19,6 +19,7 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
>> exynos5420-peach-pit.dtb \
>> exynos5800-peach-pi.dtb \
>> exynos5422-odroidxu3.dtb
>> +dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
>> dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-firefly.dtb \
>> rk3288-jerry.dtb \
>> diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts
>> new file mode 100644
>> index 0000000..f17a848
>> --- /dev/null
>> +++ b/arch/arm/dts/exynos7420-espresso7420.dts
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Samsung Espresso7420 board device tree source
>> + *
>> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include "exynos7420.dtsi"
>> +/ {
>> + model = "Samsung Espresso7420 board based on Exynos7420";
>> + compatible = "samsung,espresso7420", "samsung,exynos7420";
>> +
>> + aliases {
>> + serial2 = "/serial at 14C30000";
>> + console = "/serial at 14C30000";
>> + pinctrl0 = "/pinctrl at 13470000";
>> + };
>> +};
>> +
>> +&fin_pll {
>> + clock-frequency = <24000000>;
>> +};
>> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
>> index 1334c22..e4f189c 100644
>> --- a/board/samsung/common/board.c
>> +++ b/board/samsung/common/board.c
>> @@ -27,6 +27,8 @@
>> #include <usb.h>
>> #include <dwc3-uboot.h>
>> #include <samsung/misc.h>
>> +#include <dm/pinctrl.h>
>> +#include <dm.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -97,7 +99,7 @@ int board_init(void)
>> int dram_init(void)
>> {
>> unsigned int i;
>> - u32 addr;
>> + unsigned long addr;
>>
>> for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
>> addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
>> @@ -109,7 +111,7 @@ int dram_init(void)
>> void dram_init_banksize(void)
>> {
>> unsigned int i;
>> - u32 addr, size;
>> + unsigned long addr, size;
>>
>> for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
>> addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
>> @@ -122,6 +124,17 @@ void dram_init_banksize(void)
>>
>> static int board_uart_init(void)
>> {
>> +#if CONFIG_PINCTRL_EXYNOS
>> + struct udevice *pinctrl;
>> + int ret;
>> +
>> + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> + if (ret)
>> + return ret;
>> +
>> + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART2);
>
> Does this not happen automatically when the UART is probed? It should
> call pinctrl_select_state(dev, "default");
Right, this was not required. With the "u-boot,dm-pre-reloc" property
added to the pin configuration node, this change is not required. This
change will be remove in the next version.
Thanks,
Thomas.
>
>> + return ret;
>> +#else
>> int err, uart_id, ret = 0;
>>
>> for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
>> @@ -133,6 +146,7 @@ static int board_uart_init(void)
>> }
>> }
>> return ret;
>> +#endif
>> }
>>
>> #ifdef CONFIG_BOARD_EARLY_INIT_F
>> diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
>> new file mode 100644
>> index 0000000..6cfead0
>> --- /dev/null
>> +++ b/board/samsung/espresso7420/Kconfig
>> @@ -0,0 +1,12 @@
>> +if TARGET_ESPRESSO7420
>> +
>> +config SYS_BOARD
>> + default "espresso7420"
>
> Please add a description of the board in help.
>
>> +
>> +config SYS_VENDOR
>> + default "samsung"
>> +
>> +config SYS_CONFIG_NAME
>> + default "espresso7420"
>> +
>> +endif
>> diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
>> new file mode 100644
>> index 0000000..aaebc4c
>> --- /dev/null
>> +++ b/board/samsung/espresso7420/MAINTAINERS
>> @@ -0,0 +1,5 @@
>> +ESPRESSO7420 Board
>> +M: Thomas Abraham <thomas.ab@samsung.com>
>> +S: Maintained
>> +F: board/samsung/espresso7420/
>> +F: include/configs/espresso7420.h
>> diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
>> new file mode 100644
>> index 0000000..53d90fd
>> --- /dev/null
>> +++ b/board/samsung/espresso7420/Makefile
>> @@ -0,0 +1,16 @@
>> +#
>> +# Copyright (C) 2015 Samsung Electronics
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +#obj-y += espresso7420_spl.o
>> +#obj-y += clk-boot_evt1.o
>> +#obj-y += lpddr4_evt1.o
>> +#obj-y += dmc_init_lpddr4.o
>> +#obj-y += dmc.o
>> +#obj-y += clock.o clock_init.o
>
> Why the commented-out files?
>
>> +
>> +ifndef CONFIG_SPL_BUILD
>> +obj-y += espresso7420.o
>> +endif
>> diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
>> new file mode 100644
>> index 0000000..04a83bc
>> --- /dev/null
>> +++ b/board/samsung/espresso7420/espresso7420.c
>> @@ -0,0 +1,16 @@
>> +/*
>> + * Espresso7420 board file
>> + * Copyright (C) 2016 Samsung Electronics
>> + * Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int exynos_init(void)
>> +{
>> + return 0;
>> +}
>> diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
>> new file mode 100644
>> index 0000000..604921f
>> --- /dev/null
>> +++ b/configs/espresso7420_defconfig
>> @@ -0,0 +1,8 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_EXYNOS=y
>> +CONFIG_TARGET_ESPRESSO7420=y
>> +CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>> +CONFIG_SYS_PROMPT="ESPRESSO7420 # "
>> +# CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_SETEXPR is not set
>> --
>> 1.6.6.rc2
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 28+ messages in thread
* [U-Boot] [PATCH 0/9] Add support for Espresso7420 board
2016-04-13 10:43 [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Thomas Abraham
` (8 preceding siblings ...)
2016-04-13 10:43 ` [U-Boot] [PATCH 9/9] board: samsung: add initial Espresso7420 board support Thomas Abraham
@ 2016-04-20 9:17 ` Alim Akhtar
2016-04-23 16:06 ` Thomas Abraham
9 siblings, 1 reply; 28+ messages in thread
From: Alim Akhtar @ 2016-04-20 9:17 UTC (permalink / raw)
To: u-boot
Hi Thomas,
On 04/13/2016 04:13 PM, Thomas Abraham wrote:
> This patch series add support for Espresso7420 board. This board is
> the development/evaluation platform for Exynos7420 SoC. The SoC is
> composed of quad Cortex-A57 block, a quad Cortex-A53 block and
> various other peripherals. The board includes multiple components
> such as the EMMC/Codec and support multiple interconnect interfaces
> including HDMI and USB.
>
> The first two patches add Exynos7420 pinctrl driver support which
> was initially posted seperatly but now included in this series.
> Thanks to Simon Glass and Minkyu Kang for their review. The rest
> of the patches add Exynos7420 clock driver support, minor changes
> in the S5P serial driver, Exynos7420 SoC support and Espresso7420
> board support.
>
> Thomas Abraham (9):
> pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices
> pinctrl: Add pinctrl driver support for Exynos7420 SoC
> clk: fixed_rate: allow driver usage prior to relocation
> clk: exynos: add clock driver for Exynos7420 Soc
> serial: s5p: get the port id number from the alias of the device node
> serial: s5p: use clock api to get clock rate
> arm: exynos: realign the code to allow support for newer 64-bit platforms
> arm: exynos: add support for Exynos7420 SoC
> board: samsung: add initial Espresso7420 board support
>
Thanks for posting this series.
Have tested this series on espresso7420 board.
Feel free to add
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
> arch/arm/Kconfig | 1 -
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/exynos7420-espresso7420.dts | 24 +++
> arch/arm/dts/exynos7420.dtsi | 82 ++++++++++
> arch/arm/mach-exynos/Kconfig | 25 +++
> arch/arm/mach-exynos/Makefile | 8 +-
> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
> arch/arm/mach-exynos/mmu-arm64.c | 35 ++++
> arch/arm/mach-exynos/soc.c | 10 ++
> board/samsung/common/board.c | 18 ++-
> board/samsung/espresso7420/Kconfig | 12 ++
> board/samsung/espresso7420/MAINTAINERS | 5 +
> board/samsung/espresso7420/Makefile | 16 ++
> board/samsung/espresso7420/espresso7420.c | 16 ++
> configs/espresso7420_defconfig | 8 +
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk_fixed_rate.c | 1 +
> drivers/clk/exynos/Kconfig | 18 ++
> drivers/clk/exynos/Makefile | 9 +
> drivers/clk/exynos/clk-exynos7420.c | 227 +++++++++++++++++++++++++++
> drivers/clk/exynos/clk-pll.c | 35 ++++
> drivers/clk/exynos/clk-pll.h | 9 +
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/exynos/Kconfig | 10 ++
> drivers/pinctrl/exynos/Makefile | 9 +
> drivers/pinctrl/exynos/pinctrl-exynos.c | 141 +++++++++++++++++
> drivers/pinctrl/exynos/pinctrl-exynos.h | 77 +++++++++
> drivers/pinctrl/exynos/pinctrl-exynos7420.c | 121 ++++++++++++++
> drivers/pinctrl/pinctrl-uclass.c | 1 +
> drivers/serial/serial_s5p.c | 17 ++-
> include/configs/espresso7420.h | 35 ++++
> include/configs/exynos7420-common.h | 117 ++++++++++++++
> include/dt-bindings/clock/exynos7420-clk.h | 207 ++++++++++++++++++++++++
> 36 files changed, 1295 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts
> create mode 100644 arch/arm/dts/exynos7420.dtsi
> create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
> create mode 100644 board/samsung/espresso7420/Kconfig
> create mode 100644 board/samsung/espresso7420/MAINTAINERS
> create mode 100644 board/samsung/espresso7420/Makefile
> create mode 100644 board/samsung/espresso7420/espresso7420.c
> create mode 100644 configs/espresso7420_defconfig
> create mode 100644 drivers/clk/exynos/Kconfig
> create mode 100644 drivers/clk/exynos/Makefile
> create mode 100644 drivers/clk/exynos/clk-exynos7420.c
> create mode 100644 drivers/clk/exynos/clk-pll.c
> create mode 100644 drivers/clk/exynos/clk-pll.h
> create mode 100644 drivers/pinctrl/exynos/Kconfig
> create mode 100644 drivers/pinctrl/exynos/Makefile
> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.c
> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.h
> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos7420.c
> create mode 100644 include/configs/espresso7420.h
> create mode 100644 include/configs/exynos7420-common.h
> create mode 100644 include/dt-bindings/clock/exynos7420-clk.h
>
>
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [U-Boot] [PATCH 0/9] Add support for Espresso7420 board
2016-04-20 9:17 ` [U-Boot] [PATCH 0/9] Add support for Espresso7420 board Alim Akhtar
@ 2016-04-23 16:06 ` Thomas Abraham
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Abraham @ 2016-04-23 16:06 UTC (permalink / raw)
To: u-boot
Hi Alim,
On Wed, Apr 20, 2016 at 2:47 PM, Alim Akhtar <alim.akhtar@samsung.com> wrote:
> Hi Thomas,
>
> On 04/13/2016 04:13 PM, Thomas Abraham wrote:
>>
>> This patch series add support for Espresso7420 board. This board is
>> the development/evaluation platform for Exynos7420 SoC. The SoC is
>> composed of quad Cortex-A57 block, a quad Cortex-A53 block and
>> various other peripherals. The board includes multiple components
>> such as the EMMC/Codec and support multiple interconnect interfaces
>> including HDMI and USB.
>>
>> The first two patches add Exynos7420 pinctrl driver support which
>> was initially posted seperatly but now included in this series.
>> Thanks to Simon Glass and Minkyu Kang for their review. The rest
>> of the patches add Exynos7420 clock driver support, minor changes
>> in the S5P serial driver, Exynos7420 SoC support and Espresso7420
>> board support.
>>
>> Thomas Abraham (9):
>> pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devices
>> pinctrl: Add pinctrl driver support for Exynos7420 SoC
>> clk: fixed_rate: allow driver usage prior to relocation
>> clk: exynos: add clock driver for Exynos7420 Soc
>> serial: s5p: get the port id number from the alias of the device node
>> serial: s5p: use clock api to get clock rate
>> arm: exynos: realign the code to allow support for newer 64-bit
>> platforms
>> arm: exynos: add support for Exynos7420 SoC
>> board: samsung: add initial Espresso7420 board support
>>
> Thanks for posting this series.
> Have tested this series on espresso7420 board.
> Feel free to add
> Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Thanks. There were few more changes in the v3 version and so your
tested-by tag was dropped for the v3 version. Request your review
again.
Regards,
Thomas.
>
>
>> arch/arm/Kconfig | 1 -
>> arch/arm/dts/Makefile | 1 +
>> arch/arm/dts/exynos7420-espresso7420.dts | 24 +++
>> arch/arm/dts/exynos7420.dtsi | 82 ++++++++++
>> arch/arm/mach-exynos/Kconfig | 25 +++
>> arch/arm/mach-exynos/Makefile | 8 +-
>> arch/arm/mach-exynos/include/mach/cpu.h | 2 +-
>> arch/arm/mach-exynos/include/mach/gpio.h | 2 +-
>> arch/arm/mach-exynos/mmu-arm64.c | 35 ++++
>> arch/arm/mach-exynos/soc.c | 10 ++
>> board/samsung/common/board.c | 18 ++-
>> board/samsung/espresso7420/Kconfig | 12 ++
>> board/samsung/espresso7420/MAINTAINERS | 5 +
>> board/samsung/espresso7420/Makefile | 16 ++
>> board/samsung/espresso7420/espresso7420.c | 16 ++
>> configs/espresso7420_defconfig | 8 +
>> drivers/clk/Kconfig | 1 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk_fixed_rate.c | 1 +
>> drivers/clk/exynos/Kconfig | 18 ++
>> drivers/clk/exynos/Makefile | 9 +
>> drivers/clk/exynos/clk-exynos7420.c | 227
>> +++++++++++++++++++++++++++
>> drivers/clk/exynos/clk-pll.c | 35 ++++
>> drivers/clk/exynos/clk-pll.h | 9 +
>> drivers/pinctrl/Kconfig | 1 +
>> drivers/pinctrl/Makefile | 1 +
>> drivers/pinctrl/exynos/Kconfig | 10 ++
>> drivers/pinctrl/exynos/Makefile | 9 +
>> drivers/pinctrl/exynos/pinctrl-exynos.c | 141 +++++++++++++++++
>> drivers/pinctrl/exynos/pinctrl-exynos.h | 77 +++++++++
>> drivers/pinctrl/exynos/pinctrl-exynos7420.c | 121 ++++++++++++++
>> drivers/pinctrl/pinctrl-uclass.c | 1 +
>> drivers/serial/serial_s5p.c | 17 ++-
>> include/configs/espresso7420.h | 35 ++++
>> include/configs/exynos7420-common.h | 117 ++++++++++++++
>> include/dt-bindings/clock/exynos7420-clk.h | 207
>> ++++++++++++++++++++++++
>> 36 files changed, 1295 insertions(+), 8 deletions(-)
>> create mode 100644 arch/arm/dts/exynos7420-espresso7420.dts
>> create mode 100644 arch/arm/dts/exynos7420.dtsi
>> create mode 100644 arch/arm/mach-exynos/mmu-arm64.c
>> create mode 100644 board/samsung/espresso7420/Kconfig
>> create mode 100644 board/samsung/espresso7420/MAINTAINERS
>> create mode 100644 board/samsung/espresso7420/Makefile
>> create mode 100644 board/samsung/espresso7420/espresso7420.c
>> create mode 100644 configs/espresso7420_defconfig
>> create mode 100644 drivers/clk/exynos/Kconfig
>> create mode 100644 drivers/clk/exynos/Makefile
>> create mode 100644 drivers/clk/exynos/clk-exynos7420.c
>> create mode 100644 drivers/clk/exynos/clk-pll.c
>> create mode 100644 drivers/clk/exynos/clk-pll.h
>> create mode 100644 drivers/pinctrl/exynos/Kconfig
>> create mode 100644 drivers/pinctrl/exynos/Makefile
>> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.c
>> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos.h
>> create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos7420.c
>> create mode 100644 include/configs/espresso7420.h
>> create mode 100644 include/configs/exynos7420-common.h
>> create mode 100644 include/dt-bindings/clock/exynos7420-clk.h
>>
>>
>>
>>
>
^ permalink raw reply [flat|nested] 28+ messages in thread