GFX/UVD/VCE PG (v3)

GFX/UVD/VCE PG (v3)

[Tom St Denis]

In this respin I've factored out the changes into multiple patches
followed by adding fixes for powerplay (don't gate on init/resume)
as well as reverse the order of the operations when powering up 
(set the clock last).

Finally, this series adds VCE PG tested on both the Carrizo and Stoney
systems I have.


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[PATCH 01/14] drm/amd/amdgpu: add mutex locking for both DPM and PP based powergating for UVD/VCE

[Tom St Denis]

This adds a mutex lock for both DPM/PP around the changes in
power gating state so that userspace can poll registers without
a race condition on power state.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 58 +++++++++++++++-------------------
 1 file changed, 25 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 12ab58eca581..c4bb4ef8f2c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1105,54 +1105,46 @@ force:
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-	if (adev->pp_enabled)
+	if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
+		/* enable/disable UVD */
+		mutex_lock(&adev->pm.mutex);
 		amdgpu_dpm_powergate_uvd(adev, !enable);
-	else {
-		if (adev->pm.funcs->powergate_uvd) {
+		mutex_unlock(&adev->pm.mutex);
+	} else {
+		if (enable) {
 			mutex_lock(&adev->pm.mutex);
-			/* enable/disable UVD */
-			amdgpu_dpm_powergate_uvd(adev, !enable);
+			adev->pm.dpm.uvd_active = true;
+			adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
 			mutex_unlock(&adev->pm.mutex);
 		} else {
-			if (enable) {
-				mutex_lock(&adev->pm.mutex);
-				adev->pm.dpm.uvd_active = true;
-				adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
-				mutex_unlock(&adev->pm.mutex);
-			} else {
-				mutex_lock(&adev->pm.mutex);
-				adev->pm.dpm.uvd_active = false;
-				mutex_unlock(&adev->pm.mutex);
-			}
-			amdgpu_pm_compute_clocks(adev);
+			mutex_lock(&adev->pm.mutex);
+			adev->pm.dpm.uvd_active = false;
+			mutex_unlock(&adev->pm.mutex);
 		}
-
+		amdgpu_pm_compute_clocks(adev);
 	}
 }
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-	if (adev->pp_enabled)
+	if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
+		/* enable/disable VCE */
+		mutex_lock(&adev->pm.mutex);
 		amdgpu_dpm_powergate_vce(adev, !enable);
-	else {
-		if (adev->pm.funcs->powergate_vce) {
+		mutex_unlock(&adev->pm.mutex);
+	} else {
+		if (enable) {
 			mutex_lock(&adev->pm.mutex);
-			amdgpu_dpm_powergate_vce(adev, !enable);
+			adev->pm.dpm.vce_active = true;
+			/* XXX select vce level based on ring/task */
+			adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
 			mutex_unlock(&adev->pm.mutex);
 		} else {
-			if (enable) {
-				mutex_lock(&adev->pm.mutex);
-				adev->pm.dpm.vce_active = true;
-				/* XXX select vce level based on ring/task */
-				adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
-				mutex_unlock(&adev->pm.mutex);
-			} else {
-				mutex_lock(&adev->pm.mutex);
-				adev->pm.dpm.vce_active = false;
-				mutex_unlock(&adev->pm.mutex);
-			}
-			amdgpu_pm_compute_clocks(adev);
+			mutex_lock(&adev->pm.mutex);
+			adev->pm.dpm.vce_active = false;
+			mutex_unlock(&adev->pm.mutex);
 		}
+		amdgpu_pm_compute_clocks(adev);
 	}
 }
 
-- 
2.9.2

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[PATCH 02/14] drm/amd/amdgpu: add pm lock to debugfs mmio entry

[Tom St Denis]

Adds support for PM locks around access to registers that might
have race conditions on PG transistions.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index eab931a58d06..1fe8ef626407 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2335,22 +2335,26 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 	struct amdgpu_device *adev = f->f_inode->i_private;
 	ssize_t result = 0;
 	int r;
-	bool use_bank;
+	bool pm_pg_lock, use_bank;
 	unsigned instance_bank, sh_bank, se_bank;
 
 	if (size & 0x3 || *pos & 0x3)
 		return -EINVAL;
 
+	/* are we reading registers for which a PG lock is necessary? */
+	pm_pg_lock = (*pos >> 23) & 1;
+
 	if (*pos & (1ULL << 62)) {
 		se_bank = (*pos >> 24) & 0x3FF;
 		sh_bank = (*pos >> 34) & 0x3FF;
 		instance_bank = (*pos >> 44) & 0x3FF;
 		use_bank = 1;
-		*pos &= 0xFFFFFF;
 	} else {
 		use_bank = 0;
 	}
 
+	*pos &= 0x3FFFF;
+
 	if (use_bank) {
 		if (sh_bank >= adev->gfx.config.max_sh_per_se ||
 		    se_bank >= adev->gfx.config.max_shader_engines)
@@ -2360,6 +2364,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 					sh_bank, instance_bank);
 	}
 
+	if (pm_pg_lock)
+		mutex_lock(&adev->pm.mutex);
+
 	while (size) {
 		uint32_t value;
 
@@ -2385,6 +2392,9 @@ end:
 		mutex_unlock(&adev->grbm_idx_mutex);
 	}
 
+	if (pm_pg_lock)
+		mutex_unlock(&adev->pm.mutex);
+
 	return result;
 }
 
-- 
2.9.2

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[PATCH 03/14] drm/amd/amdgpu: don't set clockgating in uvd_v6_0_start()

[Tom St Denis]

This is handled properly by both DPM and PP externally.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 4fa50918e886..4dbd5ab29bba 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -396,15 +396,10 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
 
 	uvd_v6_0_mc_resume(adev);
 
-	/* Set dynamic clock gating in S/W control mode */
-	if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
-		uvd_v6_0_set_sw_clock_gating(adev);
-	} else {
-		/* disable clock gating */
-		uint32_t data = RREG32(mmUVD_CGC_CTRL);
-		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
-		WREG32(mmUVD_CGC_CTRL, data);
-	}
+	/* disable clock gating */
+	tmp = RREG32(mmUVD_CGC_CTRL);
+	tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+	WREG32(mmUVD_CGC_CTRL, tmp);
 
 	/* disable interupt */
 	WREG32_P(mmUVD_MASTINT_EN, 0, ~UVD_MASTINT_EN__VCPU_EN_MASK);
-- 
2.9.2

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[PATCH 04/14] drm/amd/amdgpu: don't track state in UVD clockgating

[Tom St Denis]

There's no need to track CG state anymore.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 4dbd5ab29bba..7f2b5de29f67 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -959,21 +959,15 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
 					  enum amd_clockgating_state state)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
-	static int curstate = -1;
-
-	if (adev->asic_type == CHIP_FIJI ||
-			adev->asic_type == CHIP_POLARIS10)
-		uvd_v6_set_bypass_mode(adev, enable);
 
 	if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 		return 0;
 
-	if (curstate == state)
-		return 0;
+	if (adev->asic_type == CHIP_FIJI ||
+	    adev->asic_type == CHIP_POLARIS10)
+		uvd_v6_set_bypass_mode(adev, state == AMD_CG_STATE_GATE ? true : false);
 
-	curstate = state;
-	if (enable) {
+	if (state == AMD_CG_STATE_GATE) {
 		/* disable HW gating and enable Sw gating */
 		uvd_v6_0_set_sw_clock_gating(adev);
 	} else {
-- 
2.9.2

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[PATCH 05/14] drm/amd/amdgpu: enable PG_EN bit in powergating UVD

[Tom St Denis]

Enable the PG_EN bit just before the SMU would be tasked
with the PG transition.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7f2b5de29f67..391457f1eafd 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -997,6 +997,8 @@ static int uvd_v6_0_set_powergating_state(void *handle,
 	if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
 		return 0;
 
+	WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
+
 	if (state == AMD_PG_STATE_GATE) {
 		uvd_v6_0_stop(adev);
 		return 0;
-- 
2.9.2

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[PATCH 06/14] drm/amd/amdgpu: Add error messages to UVD PG in DPM

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 41 +++++++++++++++++++++++++++++++------
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 8ba07e79d4cb..301d0b98e607 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -2108,29 +2108,58 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
 			/* disable clockgating so we can properly shut down the block */
 			ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 							    AMD_CG_STATE_UNGATE);
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
+				return;
+			}
+
 			/* shutdown the UVD block */
 			ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 							    AMD_PG_STATE_GATE);
-			/* XXX: check for errors */
+
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating failed to set powergating state\n");
+				return;
+			}
 		}
 		cz_update_uvd_dpm(adev, gate);
-		if (pi->caps_uvd_pg)
+		if (pi->caps_uvd_pg) {
 			/* power off the UVD block */
-			cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
+			ret = cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating failed to send SMU PowerOFF message\n");
+				return;
+			}
+		}
 	} else {
 		if (pi->caps_uvd_pg) {
 			/* power on the UVD block */
 			if (pi->uvd_dynamic_pg)
-				cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
+				ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
 			else
-				cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
+				ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
+
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating Failed to send SMU PowerON message\n");
+				return;
+			}
+
 			/* re-init the UVD block */
 			ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 							    AMD_PG_STATE_UNGATE);
+
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating Failed to set powergating state\n");
+				return;
+			}
+
 			/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
 			ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
 							    AMD_CG_STATE_GATE);
-			/* XXX: check for errors */
+			if (ret) {
+				DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
+				return;
+			}
 		}
 		cz_update_uvd_dpm(adev, gate);
 	}
-- 
2.9.2

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[PATCH 07/14] drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events

[Tom St Denis]

Setting PG state this early would cause lock ups in the IP block
initialized functions.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index d6635cc4b0fc..635fc4b48184 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -30,7 +30,6 @@ static const pem_event_action * const initialize_event[] = {
 	system_config_tasks,
 	setup_asic_tasks,
 	enable_dynamic_state_management_tasks,
-	enable_clock_power_gatings_tasks,
 	get_2d_performance_state_tasks,
 	set_performance_state_tasks,
 	initialize_thermal_controller_tasks,
@@ -140,7 +139,6 @@ static const pem_event_action * const resume_event[] = {
 	setup_asic_tasks,
 	enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
 	enable_dynamic_state_management_tasks,
-	enable_clock_power_gatings_tasks,
 	enable_disable_bapm_tasks,
 	initialize_thermal_controller_tasks,
 	get_2d_performance_state_tasks,
-- 
2.9.2

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[PATCH 08/14] drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce

[Tom St Denis]

Cannot set clockgating state before ungating power.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
index 2da548f6337e..2028980f1ed4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
@@ -177,12 +177,12 @@ int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 		cz_dpm_powerdown_uvd(hwmgr);
 	} else {
 		cz_dpm_powerup_uvd(hwmgr);
-		cgs_set_clockgating_state(hwmgr->device,
-						AMD_IP_BLOCK_TYPE_UVD,
-						AMD_PG_STATE_GATE);
 		cgs_set_powergating_state(hwmgr->device,
 						AMD_IP_BLOCK_TYPE_UVD,
 						AMD_CG_STATE_UNGATE);
+		cgs_set_clockgating_state(hwmgr->device,
+						AMD_IP_BLOCK_TYPE_UVD,
+						AMD_PG_STATE_GATE);
 		cz_dpm_update_uvd_dpm(hwmgr, false);
 	}
 
@@ -211,14 +211,14 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 			} else {
 				cz_dpm_powerup_vce(hwmgr);
 				cz_hwmgr->vce_power_gated = false;
-				cgs_set_clockgating_state(
-							hwmgr->device,
-							AMD_IP_BLOCK_TYPE_VCE,
-							AMD_PG_STATE_GATE);
 				cgs_set_powergating_state(
 							hwmgr->device,
 							AMD_IP_BLOCK_TYPE_VCE,
 							AMD_CG_STATE_UNGATE);
+				cgs_set_clockgating_state(
+							hwmgr->device,
+							AMD_IP_BLOCK_TYPE_VCE,
+							AMD_PG_STATE_GATE);
 				cz_dpm_update_vce_dpm(hwmgr);
 				cz_enable_disable_vce_dpm(hwmgr, true);
 				return 0;
-- 
2.9.2

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[PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9ba64989f092..4fa9fea541a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
 			AMD_CG_SUPPORT_SDMA_LS;
+		/* rev0 hardware requires workarounds to support PG */
 		adev->pg_flags = 0;
+		if (adev->rev_id != 0x00) {
+			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+				AMD_PG_SUPPORT_GFX_SMG |
+				AMD_PG_SUPPORT_GFX_PIPELINE;
+		}
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
 	case CHIP_STONEY:
-- 
2.9.2

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[PATCH 10/14] drm/amd/amdgpu: Enable carrizo UVD PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 4fa9fea541a5..f271ee0cc033 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1583,7 +1583,8 @@ static int vi_common_early_init(void *handle)
 		if (adev->rev_id != 0x00) {
 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 				AMD_PG_SUPPORT_GFX_SMG |
-				AMD_PG_SUPPORT_GFX_PIPELINE;
+				AMD_PG_SUPPORT_GFX_PIPELINE |
+				AMD_PG_SUPPORT_UVD;
 		}
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
-- 
2.9.2

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[PATCH 11/14] drm/amd/amdgpu: Enable carrizo VCE PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index f271ee0cc033..550fafb01aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1584,7 +1584,8 @@ static int vi_common_early_init(void *handle)
 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 				AMD_PG_SUPPORT_GFX_SMG |
 				AMD_PG_SUPPORT_GFX_PIPELINE |
-				AMD_PG_SUPPORT_UVD;
+				AMD_PG_SUPPORT_UVD |
+				AMD_PG_SUPPORT_VCE;
 		}
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
-- 
2.9.2

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[PATCH 12/14] drm/amd/amdgpu: Enable stoney GFX PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 550fafb01aba..1f4cf6d3808e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1605,6 +1605,9 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
 			AMD_CG_SUPPORT_SDMA_LS;
+		adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
+			AMD_PG_SUPPORT_GFX_SMG |
+			AMD_PG_SUPPORT_GFX_PIPELINE;
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
 	default:
-- 
2.9.2

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[PATCH 13/14] drm/amd/amdgpu: Enable stoney UVD PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 1f4cf6d3808e..26d15a446ad0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1607,7 +1607,8 @@ static int vi_common_early_init(void *handle)
 			AMD_CG_SUPPORT_SDMA_LS;
 		adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 			AMD_PG_SUPPORT_GFX_SMG |
-			AMD_PG_SUPPORT_GFX_PIPELINE;
+			AMD_PG_SUPPORT_GFX_PIPELINE |
+			AMD_PG_SUPPORT_UVD;
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
 	default:
-- 
2.9.2

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[PATCH 14/14] drm/amd/amdgpu: Enable stoney VCE PG

[Tom St Denis]

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 26d15a446ad0..33bad99176fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1608,7 +1608,8 @@ static int vi_common_early_init(void *handle)
 		adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
 			AMD_PG_SUPPORT_GFX_SMG |
 			AMD_PG_SUPPORT_GFX_PIPELINE |
-			AMD_PG_SUPPORT_UVD;
+			AMD_PG_SUPPORT_UVD |
+			AMD_PG_SUPPORT_VCE;
 		adev->external_rev_id = adev->rev_id + 0x1;
 		break;
 	default:
-- 
2.9.2

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Re: [PATCH 07/14] drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 2383 bytes --]


For the series:
Reviewed-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>


Best Regards

Rex

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Tom St Denis <tstdenis82-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, July 28, 2016 10:19:05 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: [PATCH 07/14] drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events

Setting PG state this early would cause lock ups in the IP block
initialized functions.

Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index d6635cc4b0fc..635fc4b48184 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -30,7 +30,6 @@ static const pem_event_action * const initialize_event[] = {
         system_config_tasks,
         setup_asic_tasks,
         enable_dynamic_state_management_tasks,
-       enable_clock_power_gatings_tasks,
         get_2d_performance_state_tasks,
         set_performance_state_tasks,
         initialize_thermal_controller_tasks,
@@ -140,7 +139,6 @@ static const pem_event_action * const resume_event[] = {
         setup_asic_tasks,
         enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
         enable_dynamic_state_management_tasks,
-       enable_clock_power_gatings_tasks,
         enable_disable_bapm_tasks,
         initialize_thermal_controller_tasks,
         get_2d_performance_state_tasks,
--
2.9.2

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Re: GFX/UVD/VCE PG (v3)

[Alex Deucher]

On Thu, Jul 28, 2016 at 10:18 AM, Tom St Denis <tstdenis82@gmail.com> wrote:
> In this respin I've factored out the changes into multiple patches
> followed by adding fixes for powerplay (don't gate on init/resume)
> as well as reverse the order of the operations when powering up
> (set the clock last).
>
> Finally, this series adds VCE PG tested on both the Carrizo and Stoney
> systems I have.

For the series:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

[Felix Kuehling]

We're reverting this commit on the KFD branch because it's causing hangs
on a bunch of HSA compute tests on CZ.

Regards,
  Felix


On 16-07-28 10:19 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 9ba64989f092..4fa9fea541a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle)
>  			AMD_CG_SUPPORT_HDP_LS |
>  			AMD_CG_SUPPORT_SDMA_MGCG |
>  			AMD_CG_SUPPORT_SDMA_LS;
> +		/* rev0 hardware requires workarounds to support PG */
>  		adev->pg_flags = 0;
> +		if (adev->rev_id != 0x00) {
> +			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> +				AMD_PG_SUPPORT_GFX_SMG |
> +				AMD_PG_SUPPORT_GFX_PIPELINE;
> +		}
>  		adev->external_rev_id = adev->rev_id + 0x1;
>  		break;
>  	case CHIP_STONEY:

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Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

[StDenis, Tom]

[-- Attachment #1.1: Type: text/plain, Size: 1687 bytes --]

Hi Felix,


Hmm, it's unfortunate because I haven't been able to reproduce any hangs on my AM4 based Carrizo.  What specific tests are you running when it hangs?


Cheers,

Tom


________________________________
From: Kuehling, Felix
Sent: Monday, August 8, 2016 13:57
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; StDenis, Tom
Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

We're reverting this commit on the KFD branch because it's causing hangs
on a bunch of HSA compute tests on CZ.

Regards,
  Felix


On 16-07-28 10:19 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 9ba64989f092..4fa9fea541a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle)
>                        AMD_CG_SUPPORT_HDP_LS |
>                        AMD_CG_SUPPORT_SDMA_MGCG |
>                        AMD_CG_SUPPORT_SDMA_LS;
> +             /* rev0 hardware requires workarounds to support PG */
>                adev->pg_flags = 0;
> +             if (adev->rev_id != 0x00) {
> +                     adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> +                             AMD_PG_SUPPORT_GFX_SMG |
> +                             AMD_PG_SUPPORT_GFX_PIPELINE;
> +             }
>                adev->external_rev_id = adev->rev_id + 0x1;
>                break;
>        case CHIP_STONEY:


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RE: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

[Deucher, Alexander]

[-- Attachment #1.1: Type: text/plain, Size: 2324 bytes --]

I'm not sure gfx PG works properly with some of the kfd features.  I know there were problems in the past.  We probably need to add some sort of handshake for when we have kfd running in order to disable gfx PG when necessary.

Alex

From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom
Sent: Monday, August 08, 2016 1:59 PM
To: Kuehling, Felix; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG


Hi Felix,



Hmm, it's unfortunate because I haven't been able to reproduce any hangs on my AM4 based Carrizo.  What specific tests are you running when it hangs?



Cheers,

Tom

________________________________
From: Kuehling, Felix
Sent: Monday, August 8, 2016 13:57
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; StDenis, Tom
Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

We're reverting this commit on the KFD branch because it's causing hangs
on a bunch of HSA compute tests on CZ.

Regards,
  Felix


On 16-07-28 10:19 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 9ba64989f092..4fa9fea541a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle)
>                        AMD_CG_SUPPORT_HDP_LS |
>                        AMD_CG_SUPPORT_SDMA_MGCG |
>                        AMD_CG_SUPPORT_SDMA_LS;
> +             /* rev0 hardware requires workarounds to support PG */
>                adev->pg_flags = 0;
> +             if (adev->rev_id != 0x00) {
> +                     adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> +                             AMD_PG_SUPPORT_GFX_SMG |
> +                             AMD_PG_SUPPORT_GFX_PIPELINE;
> +             }
>                adev->external_rev_id = adev->rev_id + 0x1;
>                break;
>        case CHIP_STONEY:

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RE: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

[Kuehling, Felix]

[-- Attachment #1.1: Type: text/plain, Size: 2896 bytes --]

I'm not sure what the specific features are that are causing issues. FWIW, the first KFDTest unit test that fails has the CPU wait for the GPU to signal 256 events using PM4ReleaseMemory packets. It uses IOMMUv2 for coherent memory access from the GPU.

Regards,
  Felix

From: Deucher, Alexander
Sent: Monday, August 08, 2016 2:04 PM
To: StDenis, Tom; Kuehling, Felix; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

I'm not sure gfx PG works properly with some of the kfd features.  I know there were problems in the past.  We probably need to add some sort of handshake for when we have kfd running in order to disable gfx PG when necessary.

Alex

From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom
Sent: Monday, August 08, 2016 1:59 PM
To: Kuehling, Felix; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32mzQB+pC5nmwQ@public.gmane.orgedesktop.org>
Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG


Hi Felix,



Hmm, it's unfortunate because I haven't been able to reproduce any hangs on my AM4 based Carrizo.  What specific tests are you running when it hangs?



Cheers,

Tom

________________________________
From: Kuehling, Felix
Sent: Monday, August 8, 2016 13:57
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; StDenis, Tom
Subject: Re: [PATCH 09/14] drm/amd/amdgpu: Enable carrizo GFX PG

We're reverting this commit on the KFD branch because it's causing hangs
on a bunch of HSA compute tests on CZ.

Regards,
  Felix


On 16-07-28 10:19 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org<mailto:tom.stdenis@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/vi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 9ba64989f092..4fa9fea541a5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1578,7 +1578,13 @@ static int vi_common_early_init(void *handle)
>                        AMD_CG_SUPPORT_HDP_LS |
>                        AMD_CG_SUPPORT_SDMA_MGCG |
>                        AMD_CG_SUPPORT_SDMA_LS;
> +             /* rev0 hardware requires workarounds to support PG */
>                adev->pg_flags = 0;
> +             if (adev->rev_id != 0x00) {
> +                     adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> +                             AMD_PG_SUPPORT_GFX_SMG |
> +                             AMD_PG_SUPPORT_GFX_PIPELINE;
> +             }
>                adev->external_rev_id = adev->rev_id + 0x1;
>                break;
>        case CHIP_STONEY:

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Re: [PATCH 07/14] drm/amd/powerplay: remove enable_clock_power_gatings_tasks from initialize and resume events

[Eric Huang]

Hi Tom,

I am concerned with the Sclk Deep Sleep feature. If removing this task, 
UVD/VCE will always power on and Sclk deep sleep will not work. And the 
power consumption will block our client's Energy start test. So where 
are you going to re-add this task ?

Thanks,

Eric

On 16-07-28 10:19 AM, Tom St Denis wrote:
> Setting PG state this early would cause lock ups in the IP block
> initialized functions.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>   drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c | 2 --
>   1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
> index d6635cc4b0fc..635fc4b48184 100644
> --- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
> +++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
> @@ -30,7 +30,6 @@ static const pem_event_action * const initialize_event[] = {
>   	system_config_tasks,
>   	setup_asic_tasks,
>   	enable_dynamic_state_management_tasks,
> -	enable_clock_power_gatings_tasks,
>   	get_2d_performance_state_tasks,
>   	set_performance_state_tasks,
>   	initialize_thermal_controller_tasks,
> @@ -140,7 +139,6 @@ static const pem_event_action * const resume_event[] = {
>   	setup_asic_tasks,
>   	enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
>   	enable_dynamic_state_management_tasks,
> -	enable_clock_power_gatings_tasks,
>   	enable_disable_bapm_tasks,
>   	initialize_thermal_controller_tasks,
>   	get_2d_performance_state_tasks,

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