[U-Boot] [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option

[U-Boot] [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option

[Yogesh Gaur]

On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron family
which supports EAR Read/Write cmds, thus enable CONFIG_SPI_FLASH_BAR config.
Else only lower 16MiB accessible for these flashes.

Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
---
 Depends on : 
 https://patchwork.ozlabs.org/patch/755920/

 include/configs/ls2080ardb.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 6abf54b..08ac9a9 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -299,6 +299,11 @@ unsigned long get_board_sys_clk(void);
 #ifdef CONFIG_FSL_QSPI
 #ifdef CONFIG_TARGET_LS2081ARDB
 #define CONFIG_SPI_FLASH_STMICRO
+/*
+ * On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron
+ * family which supports EAR Read/Write cmds, thus enable below config
+ */
+#define CONFIG_SPI_FLASH_BAR
 #else
 #define CONFIG_SPI_FLASH_SPANSION
 #endif
-- 
1.9.1

[U-Boot] [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option

[York Sun]

On 05/11/2017 01:36 AM, Yogesh Gaur wrote:
> On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron family
> which supports EAR Read/Write cmds, thus enable CONFIG_SPI_FLASH_BAR config.
> Else only lower 16MiB accessible for these flashes.
>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> ---
>  Depends on :
>  https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F755920%2F&data=01%7C01%7Cyork.sun%40nxp.com%7C6990807b3cc340bcf5d208d49848c6ee%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=EIlAri7rShB22Yggt2juWDkBGK5PnxyO3RE9rfDEQlc%3D&reserved=0
>
>  include/configs/ls2080ardb.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
> index 6abf54b..08ac9a9 100644
> --- a/include/configs/ls2080ardb.h
> +++ b/include/configs/ls2080ardb.h
> @@ -299,6 +299,11 @@ unsigned long get_board_sys_clk(void);
>  #ifdef CONFIG_FSL_QSPI
>  #ifdef CONFIG_TARGET_LS2081ARDB
>  #define CONFIG_SPI_FLASH_STMICRO
> +/*
> + * On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron
> + * family which supports EAR Read/Write cmds, thus enable below config
> + */
> +#define CONFIG_SPI_FLASH_BAR
>  #else
>  #define CONFIG_SPI_FLASH_SPANSION
>  #endif
>

Suresh,

Is this impacted by the same QSPI driver you are working on?

York

[U-Boot] [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option

[Suresh Gupta]

> -----Original Message-----
> From: York Sun [mailto:york.sun at nxp.com]
> Sent: Friday, May 12, 2017 11:51 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Suresh Gupta
> <suresh.gupta@nxp.com>
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option
> 
> On 05/11/2017 01:36 AM, Yogesh Gaur wrote:
> > On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron
> > family which supports EAR Read/Write cmds, thus enable
> CONFIG_SPI_FLASH_BAR config.
> > Else only lower 16MiB accessible for these flashes.
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > ---
> >  Depends on :
> >
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> >
> chwork.ozlabs.org%2Fpatch%2F755920%2F&data=01%7C01%7Cyork.sun%40nx
> p.co
> >
> m%7C6990807b3cc340bcf5d208d49848c6ee%7C686ea1d3bc2b4c6fa92cd99c5c
> 30163
> >
> 5%7C0&sdata=EIlAri7rShB22Yggt2juWDkBGK5PnxyO3RE9rfDEQlc%3D&reserved
> =0
> >
> >  include/configs/ls2080ardb.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/include/configs/ls2080ardb.h
> > b/include/configs/ls2080ardb.h index 6abf54b..08ac9a9 100644
> > --- a/include/configs/ls2080ardb.h
> > +++ b/include/configs/ls2080ardb.h
> > @@ -299,6 +299,11 @@ unsigned long get_board_sys_clk(void);  #ifdef
> > CONFIG_FSL_QSPI  #ifdef CONFIG_TARGET_LS2081ARDB  #define
> > CONFIG_SPI_FLASH_STMICRO
> > +/*
> > + * On LS2081ARDB both QSPI and DSPI are having flash n25q512a of
> > +micron
> > + * family which supports EAR Read/Write cmds, thus enable below
> > +config  */ #define CONFIG_SPI_FLASH_BAR
> >  #else
> >  #define CONFIG_SPI_FLASH_SPANSION
> >  #endif
> >
> 
> Suresh,
> 
> Is this impacted by the same QSPI driver you are working on?
> 
> York

York,
You are right, LS2081ARDB have similar type of flashes which require 4byte address to access higher address. 
So required to disable CONFIG_SPI_FLASH_BAR config and add new set of commands and code changes. 

Thanks 
SuresH