* [U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum A-009008
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 2/8] armv8: Add workaround for USB erratum A-009798 Suresh Gupta
` (6 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 38 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 47897f4..cceecf0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -22,6 +22,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -40,6 +41,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -68,6 +70,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009008
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -149,6 +152,9 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..1f460d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,29 @@ bool soc_has_aiop(void)
return false;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ val &= ~(0xF << 6);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -194,6 +217,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+ erratum_a009008();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -461,6 +485,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+ erratum_a009008();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8ad199f..62d7046 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,6 +337,12 @@ struct ccsr_gur {
#define SCFG_USBPWRFAULT_USB2_SHIFT 2
#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM1CR_USB3 0x088
+#define USB_TXVREFTUNE 0x9
+
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 43ae686..c23c317 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -129,6 +129,7 @@
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
+#define USB_TXVREFTUNE 0x9
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 2/8] armv8: Add workaround for USB erratum A-009798
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum A-008997 Suresh Gupta
` (5 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
4 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cceecf0..28a0015 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -23,6 +23,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -42,6 +43,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -71,6 +73,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -155,6 +158,9 @@ config SYS_FSL_ERRATUM_A010539
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1f460d7..8d86985 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -486,6 +506,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 62d7046..8bd40e8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -342,6 +342,7 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c23c317..3537ecb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,7 @@
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum A-008997
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum A-009008 Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 2/8] armv8: Add workaround for USB erratum A-009798 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
` (4 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 29 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 +++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
4 files changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 28a0015..d5d6040 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -44,6 +45,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -74,6 +76,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -161,6 +164,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d86985..c56cb72 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -94,6 +94,33 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -238,6 +265,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -507,6 +535,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8bd40e8..2e52078 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -339,10 +339,14 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
+#define SCFG_USB3PRM2CR_USB2 0x080
#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3537ecb..3106ed3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -128,9 +128,11 @@
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_USB3PRM2CR 0x004
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
` (2 preceding siblings ...)
2017-02-03 14:09 ` [U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum A-008997 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-16 21:12 ` york sun
[not found] ` <e8695096-7813-4908-f3c5-221f4d70de0f@nxp.com>
2017-02-03 14:09 ` [U-Boot] [PATCH v3 5/8] armv7: Add workaround for USB erratum A-009008 Suresh Gupta
` (3 subsequent siblings)
7 siblings, 2 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments,
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.
Changes in v3:
Change CONFIG_XXX to CONFIG_ARCH_XXX
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 42 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 9 +++++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++
4 files changed, 66 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index d5d6040..a27e310 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -25,6 +25,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -46,6 +47,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -77,6 +79,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
@@ -167,6 +170,9 @@ config SYS_FSL_ERRATUM_A009798
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
+config SYS_FSL_ERRATUM_A009007
+ bool "Workaround for USB PHY erratum A009007"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c56cb72..9aab8a7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -120,6 +120,46 @@ static void erratum_a008997(void)
#endif
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ void __iomem *usb_phy = (void __iomem *)USB_PHY1;
+ writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ usb_phy = (void __iomem *)USB_PHY2;
+ writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ usb_phy = (void __iomem *)USB_PHY3;
+ writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+ void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+ writew(USB_PHY_RX_EQ_VAL_1,
+ dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2,
+ dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3,
+ dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4,
+ dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_1,
+ dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2,
+ dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3,
+ dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4,
+ dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
#if defined(CONFIG_FSL_LSCH3)
/*
@@ -266,6 +306,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -536,6 +577,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2e52078..2dacdb4 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -347,6 +347,15 @@ struct ccsr_gur {
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY1 0x084F0000
+#define USB_PHY2 0x08500000
+#define USB_PHY3 0x08510000
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+/* TODO : make it generic */
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3106ed3..819172e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -133,6 +133,15 @@
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
#define USB_PCSTXSWINGFULL 0x47
+#define DCSR_BASE 0x700000000ULL
+#define DCSR_USB_PHY1 0x4600000
+#define DCSR_USB_PHY2 0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x1006
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x0080
+#define USB_PHY_RX_EQ_VAL_3 0x0380
+#define USB_PHY_RX_EQ_VAL_4 0x0b80
+
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-03 14:09 ` [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
@ 2017-02-16 21:12 ` york sun
[not found] ` <e8695096-7813-4908-f3c5-221f4d70de0f@nxp.com>
1 sibling, 0 replies; 19+ messages in thread
From: york sun @ 2017-02-16 21:12 UTC (permalink / raw)
To: u-boot
On 02/03/2017 06:08 AM, Suresh Gupta wrote:
> Rx Compliance tests may fail intermittently at high
> jitter frequencies using default register values
>
> Changes identified in test setup makes the Rx compliance test pass
>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
> ---
> Changes in v2:
> Clean up the code after Scott comments,
> Previously in v1, we was defining the pointer as u32,
> then casting it to u8, and then passing it to
> a 16-bit accessor.
> Changes in v3:
> Change CONFIG_XXX to CONFIG_ARCH_XXX
>
>
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++
> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 42 ++++++++++++++++++++++
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 9 +++++
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++
> 4 files changed, 66 insertions(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index d5d6040..a27e310 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -25,6 +25,7 @@ config ARCH_LS1043A
> select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_ERRATUM_A009798
> select SYS_FSL_ERRATUM_A008997
> + select SYS_FSL_ERRATUM_A009007
> select SYS_FSL_HAS_DDR3
> select SYS_FSL_HAS_DDR4
> select ARCH_EARLY_INIT_R
> @@ -46,6 +47,7 @@ config ARCH_LS1046A
> select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_ERRATUM_A009798
> select SYS_FSL_ERRATUM_A008997
> + select SYS_FSL_ERRATUM_A009007
> select SYS_FSL_HAS_DDR4
> select SYS_FSL_SRDS_2
> select ARCH_EARLY_INIT_R
> @@ -77,6 +79,7 @@ config ARCH_LS2080A
> select SYS_FSL_ERRATUM_A009008
> select SYS_FSL_ERRATUM_A009798
> select SYS_FSL_ERRATUM_A008997
> + select SYS_FSL_ERRATUM_A009007
> select ARCH_EARLY_INIT_R
> select BOARD_EARLY_INIT_F
>
> @@ -167,6 +170,9 @@ config SYS_FSL_ERRATUM_A009798
> config SYS_FSL_ERRATUM_A008997
> bool "Workaround for USB PHY erratum A008997"
>
> +config SYS_FSL_ERRATUM_A009007
> + bool "Workaround for USB PHY erratum A009007"
> +
> config MAX_CPUS
> int "Maximum number of CPUs permitted for Layerscape"
> default 4 if ARCH_LS1043A
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index c56cb72..9aab8a7 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -120,6 +120,46 @@ static void erratum_a008997(void)
> #endif
> #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
> }
> +static void erratum_a009007(void)
> +{
> +/* TODO:implement the out_be16 instead of writew which is taking
> +little endian style */
Did you mean to remind yourself to finish this before sending this
patch? You know we already have out_be16(), don't you?
York
^ permalink raw reply [flat|nested] 19+ messages in thread[parent not found: <e8695096-7813-4908-f3c5-221f4d70de0f@nxp.com>]
* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
[not found] ` <e8695096-7813-4908-f3c5-221f4d70de0f@nxp.com>
@ 2017-02-23 17:48 ` york sun
2017-02-24 7:19 ` Suresh Gupta
0 siblings, 1 reply; 19+ messages in thread
From: york sun @ 2017-02-23 17:48 UTC (permalink / raw)
To: u-boot
On 02/16/2017 01:12 PM, york.sun at nxp.com wrote:
> On 02/03/2017 06:08 AM, Suresh Gupta wrote:
<snip>
>> +static void erratum_a009007(void)
>> +{
>> +/* TODO:implement the out_be16 instead of writew which is taking
>> +little endian style */
>
> Did you mean to remind yourself to finish this before sending this
> patch? You know we already have out_be16(), don't you?
>
Suresh,
Are you going to send an update?
York
^ permalink raw reply [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-23 17:48 ` york sun
@ 2017-02-24 7:19 ` Suresh Gupta
2017-02-24 17:00 ` york sun
0 siblings, 1 reply; 19+ messages in thread
From: Suresh Gupta @ 2017-02-24 7:19 UTC (permalink / raw)
To: u-boot
Hi York,
It is not good idea to change the values of all macro at this time as the code tested on different platforms.
If required, I will remove the TODO statement.
What you say.
Thanks
SuresH
> -----Original Message-----
> From: york sun
> Sent: Thursday, February 23, 2017 11:18 PM
> To: Suresh Gupta <suresh.gupta@nxp.com>
> Cc: u-boot at lists.denx.de; Scott Wood <scott.wood@nxp.com>; Leo Li
> <leoyang.li@nxp.com>; Sriram Dash <sriram.dash@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
> On 02/16/2017 01:12 PM, mailto:york.sun at nxp.com wrote:
> > On 02/03/2017 06:08 AM, Suresh Gupta wrote:
>
> <snip>
>
> >> +static void erratum_a009007(void)
> >> +{
> >> +/* TODO:implement the out_be16 instead of writew which is taking
> >> +little endian style */
> >
> > Did you mean to remind yourself to finish this before sending this
> > patch? You know we already have out_be16(), don't you?
> >
>
> Suresh,
>
> Are you going to send an update?
>
> York
^ permalink raw reply [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-24 7:19 ` Suresh Gupta
@ 2017-02-24 17:00 ` york sun
2017-02-28 10:52 ` Suresh Gupta
0 siblings, 1 reply; 19+ messages in thread
From: york sun @ 2017-02-24 17:00 UTC (permalink / raw)
To: u-boot
On 02/23/2017 11:19 PM, Suresh Gupta wrote:
> Hi York,
>
> It is not good idea to change the values of all macro at this time as the code tested on different platforms.
I am not talking about any value change. You are using writew. Why not
using out_be16 as you thought?
York
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-24 17:00 ` york sun
@ 2017-02-28 10:52 ` Suresh Gupta
2017-02-28 16:25 ` york sun
0 siblings, 1 reply; 19+ messages in thread
From: Suresh Gupta @ 2017-02-28 10:52 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: york sun
> Sent: Friday, February 24, 2017 10:31 PM
> To: Suresh Gupta <suresh.gupta@nxp.com>
> Cc: u-boot at lists.denx.de; Scott Wood <scott.wood@nxp.com>; Leo Li
> <leoyang.li@nxp.com>; Sriram Dash <sriram.dash@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
> On 02/23/2017 11:19 PM, Suresh Gupta wrote:
> > Hi York,
> >
> > It is not good idea to change the values of all macro at this time as the code
> tested on different platforms.
>
> I am not talking about any value change. You are using writew. Why not using
> out_be16 as you thought?
For now all values in macro (like USB_PHY_RX_EQ_VAL_2) are swapped and
if I want to use out_be16, then I need to change values of all macros,
which intern require testing on all platform.
That's the reason, I don't want to make such changes and break the working USB
>
> York
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-28 10:52 ` Suresh Gupta
@ 2017-02-28 16:25 ` york sun
2017-03-01 4:06 ` Suresh Gupta
0 siblings, 1 reply; 19+ messages in thread
From: york sun @ 2017-02-28 16:25 UTC (permalink / raw)
To: u-boot
On 02/28/2017 02:52 AM, Suresh Gupta wrote:
>
>
>> -----Original Message-----
>> From: york sun
>> Sent: Friday, February 24, 2017 10:31 PM
>> To: Suresh Gupta <suresh.gupta@nxp.com>
>> Cc: u-boot at lists.denx.de; Scott Wood <scott.wood@nxp.com>; Leo Li
>> <leoyang.li@nxp.com>; Sriram Dash <sriram.dash@nxp.com>; Rajesh Bhagat
>> <rajesh.bhagat@nxp.com>
>> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>>
>> On 02/23/2017 11:19 PM, Suresh Gupta wrote:
>>> Hi York,
>>>
>>> It is not good idea to change the values of all macro at this time as the code
>> tested on different platforms.
>>
>> I am not talking about any value change. You are using writew. Why not using
>> out_be16 as you thought?
>
> For now all values in macro (like USB_PHY_RX_EQ_VAL_2) are swapped and
> if I want to use out_be16, then I need to change values of all macros,
> which intern require testing on all platform.
> That’s the reason, I don’t want to make such changes and break the working USB
>
Suresh,
This erratum only applies to LS1043A, LS1046A, LS2080A. It wouldn't be
too much trouble to verify all of them. I'd rather we do it right at the
first place than coming back to fix it. Are you in a rush to get this
patch out?
Another thing, please drop defined(CONFIG_ARCH_LS2085A) for all the
patches. We only use CONFIG_ARCH_LS2080A.
York
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
2017-02-28 16:25 ` york sun
@ 2017-03-01 4:06 ` Suresh Gupta
2017-03-22 16:42 ` york sun
2017-04-18 15:57 ` York Sun
0 siblings, 2 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-03-01 4:06 UTC (permalink / raw)
To: u-boot
OK York, will send new patch..
> -----Original Message-----
> From: york sun
> Sent: Tuesday, February 28, 2017 9:56 PM
> To: Suresh Gupta <suresh.gupta@nxp.com>
> Cc: u-boot at lists.denx.de; Scott Wood <scott.wood@nxp.com>; Leo Li
> <leoyang.li@nxp.com>; Sriram Dash <sriram.dash@nxp.com>; Rajesh Bhagat
> <rajesh.bhagat@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
> On 02/28/2017 02:52 AM, Suresh Gupta wrote:
> >
> >
> >> -----Original Message-----
> >> From: york sun
> >> Sent: Friday, February 24, 2017 10:31 PM
> >> To: Suresh Gupta <suresh.gupta@nxp.com>
> >> Cc: u-boot at lists.denx.de; Scott Wood <scott.wood@nxp.com>; Leo Li
> >> <leoyang.li@nxp.com>; Sriram Dash <sriram.dash@nxp.com>; Rajesh
> >> Bhagat <rajesh.bhagat@nxp.com>
> >> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum
> >> A-009007
> >>
> >> On 02/23/2017 11:19 PM, Suresh Gupta wrote:
> >>> Hi York,
> >>>
> >>> It is not good idea to change the values of all macro at this time
> >>> as the code
> >> tested on different platforms.
> >>
> >> I am not talking about any value change. You are using writew. Why
> >> not using
> >> out_be16 as you thought?
> >
> > For now all values in macro (like USB_PHY_RX_EQ_VAL_2) are swapped and
> > if I want to use out_be16, then I need to change values of all macros,
> > which intern require testing on all platform.
> > That's the reason, I don't want to make such changes and break the
> > working USB
> >
>
> Suresh,
>
> This erratum only applies to LS1043A, LS1046A, LS2080A. It wouldn't be too
> much trouble to verify all of them. I'd rather we do it right at the first place than
> coming back to fix it. Are you in a rush to get this patch out?
>
> Another thing, please drop defined(CONFIG_ARCH_LS2085A) for all the patches.
> We only use CONFIG_ARCH_LS2080A.
>
> York
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v3 5/8] armv7: Add workaround for USB erratum A-009008
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
` (3 preceding siblings ...)
2017-02-03 14:09 ` [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 6/8] armv7: Add workaround for USB erratum A-009798 Suresh Gupta
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
From: Suresh Gupta <suresh.gupta@freescale.com>
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2: None
Changes in v3: None
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 13 +++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index b61f3cd..9578e85 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,9 @@ config SECURE_BOOT
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_ERRATUM_A009008
+ bool "Workaround for USB PHY erratum A009008"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..ee27b0c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
}
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+ val &= ~(0xF << 6);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
void s_init(void)
{
}
@@ -146,6 +156,9 @@ int arch_soc_init(void)
*/
out_be32(&scfg->eddrtqcfg, 0x63b20042);
+ /* Erratum */
+ erratum_a009008();
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
#define SCFG_PMCINTECR_ETSECERRG1 0x00040000
#define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR 0x070
+#define USB_TXVREFTUNE 0x9
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u32 dpslpcr;
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 6/8] armv7: Add workaround for USB erratum A-009798
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
` (4 preceding siblings ...)
2017-02-03 14:09 ` [U-Boot] [PATCH v3 5/8] armv7: Add workaround for USB erratum A-009008 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 7/8] armv7: Add workaround for USB erratum A-008997 Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 8/8] armv7: Add workaround for USB erratum A-009007 Suresh Gupta
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
From: Suresh Gupta <suresh.gupta@freescale.com>
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.
The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2: None
Changes in v3: None
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9578e85..7e12565 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ee27b0c..7ae5b29 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+ out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
void s_init(void)
{
}
@@ -158,6 +167,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
+ erratum_a009798();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
#define SCFG_BASE 0x01570000
#define SCFG_USB3PRM1CR 0x070
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 7/8] armv7: Add workaround for USB erratum A-008997
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
` (5 preceding siblings ...)
2017-02-03 14:09 ` [U-Boot] [PATCH v3 6/8] armv7: Add workaround for USB erratum A-009798 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
2017-02-03 14:09 ` [U-Boot] [PATCH v3 8/8] armv7: Add workaround for USB erratum A-009007 Suresh Gupta
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
From: Suresh Gupta <suresh.gupta@freescale.com>
Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings
Change settings required for transmitter signal swings to pass
compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments,
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.
Changes in v3: None
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 16 ++++++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 9 +++++++++
3 files changed, 29 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 7e12565..cbd4ab6 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -58,6 +59,9 @@ config SYS_FSL_ERRATUM_A009008
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
+config SYS_FSL_ERRATUM_A008997
+ bool "Workaround for USB PHY erratum A008997"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 7ae5b29..3d6cc5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+ void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+ writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+ usb_phy + USB_PHY_TX_OVRD_DRV_LO);
+ writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+ usb_phy + USB_PHY_MPLL_OVRD_IN_HI);
+ writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+ usb_phy + USB_PHY_LEVEL_OVRD_IN);
+ writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+ usb_phy + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
void s_init(void)
{
}
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR 0x070
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PHY_BASE 0x08510000
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI 0x0024
+#define USB_PHY_LEVEL_OVRD_IN 0x002a
+#define USB_PHY_TX_OVRD_IN_HI 0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL 0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL 0x0003
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [U-Boot] [PATCH v3 8/8] armv7: Add workaround for USB erratum A-009007
2017-02-03 14:09 [U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata Suresh Gupta
` (6 preceding siblings ...)
2017-02-03 14:09 ` [U-Boot] [PATCH v3 7/8] armv7: Add workaround for USB erratum A-008997 Suresh Gupta
@ 2017-02-03 14:09 ` Suresh Gupta
7 siblings, 0 replies; 19+ messages in thread
From: Suresh Gupta @ 2017-02-03 14:09 UTC (permalink / raw)
To: u-boot
From: Suresh Gupta <suresh.gupta@freescale.com>
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values
Changes identified in test setup makes the Rx compliance test pass
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments,
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.
Changes in v3: None
arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++
arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index cbd4ab6..554b57b 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+ select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -62,6 +63,9 @@ config SYS_FSL_ERRATUM_A009798
config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
+config SYS_FSL_ERRATUM_A009007
+ bool "Workaround for USB PHY erratum A009007"
+
config SYS_FSL_SRDS_1
bool
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
}
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+ void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+ writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+ writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
void s_init(void)
{
}
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+ erratum_a009007();
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
#define USB_PHY_MPLL_OVRD_IN_HI 0x0024
#define USB_PHY_LEVEL_OVRD_IN 0x002a
#define USB_PHY_TX_OVRD_IN_HI 0x2002
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
#define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080
#define USB_PHY_LEVEL_OVRD_IN_VAL 0xA9A5
#define USB_PHY_TX_OVRD_IN_HI_VAL 0x0003
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8004
+#define USB_PHY_RX_EQ_VAL_4 0x800C
/* Supplemental Configuration Unit */
struct ccsr_scfg {
--
1.9.3
^ permalink raw reply related [flat|nested] 19+ messages in thread