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* [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
@ 2016-09-12  4:08 Zhiqiang Hou
  2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Zhiqiang Hou @ 2016-09-12  4:08 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Up to now, there are 3 kinds of SoC under Layerscape Chassis 2,
such as LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of difference, for instance the IP modules have different
divisors to get clock from Platform PLL. And the core cluster
and platform PLL maybe have different reference clock, such as
LS1012A. Another problem is which clock/PLL should be described
by sys_info->freq_systembus, it is confused in Chissis 2.

This patch is to map the sys_info->freq_systembus to the Platform
PLL, and handle the different divisor of IP modules separately
between different SoCs. And separate cluster and platform PLL
reference clock.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96 ++++++++++++++++++----
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
 include/configs/ls1012a_common.h                   |  6 +-
 include/configs/ls1043a_common.h                   |  2 +-
 4 files changed, 86 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 8922197..4fb736d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_CLUSTER_CLK_FREQ
+	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
+#else
+	cluster_clk = sysclk;
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
 	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
-#ifdef CONFIG_LS1012A
-	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
-			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-#else
+	/* The freq_systembus is used to record frequency of platform PLL */
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
+#else
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
@@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
 		if (ratio[i] > 4)
-			freq_c_pll[i] = sysclk * ratio[i];
+			freq_c_pll[i] = cluster_clk * ratio[i];
 		else
 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
@@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
-#ifdef CONFIG_LS1012A
-	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
-	sys_info->freq_ddrbus *= 2;
-#endif
-
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -148,7 +149,11 @@ void get_sys_info(struct sys_info *sys_info)
 		break;
 	}
 #else
+#ifdef CONFIG_LS1043A
 	sys_info->freq_sdhc = sys_info->freq_systembus;
+#elif defined(CONFIG_LS1046A) || defined(CONFIG_LS1012A)
+	sys_info->freq_sdhc = sys_info->freq_systembus / 2;
+#endif
 #endif
 #endif
 
@@ -156,7 +161,11 @@ void get_sys_info(struct sys_info *sys_info)
 	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
+#ifdef CONFIG_LS1043A
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#elif defined(CONFIG_LS1046A)
+	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
+#endif
 #endif
 }
 
@@ -179,41 +188,98 @@ int get_clocks(void)
 		return 1;
 }
 
+/********************************************
+ * get_bus_freq
+ * return platform PLL freq in Hz
+ *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
+	if (!gd->bus_clk)
+		get_clocks();
+
 	return gd->bus_clk;
 }
 
 ulong get_ddr_freq(ulong dummy)
 {
+	if (!gd->mem_clk)
+		get_clocks();
+
 	return gd->mem_clk;
 }
 
 #ifdef CONFIG_FSL_ESDHC
 int get_sdhc_freq(ulong dummy)
 {
+	if (!gd->arch.sdhc_clk)
+		get_clocks();
+
 	return gd->arch.sdhc_clk;
 }
 #endif
 
 int get_serial_clock(void)
 {
-	return gd->bus_clk;
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
+}
+
+int get_i2c_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
 }
 
+int get_dspi_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#elif defined(CONFIG_LS1012A)
+	return get_bus_freq(0) / 4;
+#else
+	return 0;
+#endif
+}
+
+int get_uart_freq(ulong dummy)
+{
+#ifdef CONFIG_LS1043A
+	return get_bus_freq(0);
+#elif defined(CONFIG_LS1046A)
+	return get_bus_freq(0) / 2;
+#else
+	return 0;
+#endif
+}
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_I2C_CLK:
-		return get_bus_freq(0);
+		return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
 	case MXC_ESDHC_CLK:
 		return get_sdhc_freq(0);
 #endif
 	case MXC_DSPI_CLK:
-		return get_bus_freq(0);
+		return get_dspi_freq(0);
 	case MXC_UART_CLK:
-		return get_bus_freq(0);
+		return get_uart_freq(0);
 	default:
 		printf("Unsupported clock\n");
 	}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a4293..ee10765 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -136,6 +136,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 	unsigned long freq_localbus;
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index fba2fac..928fd76 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -24,8 +24,8 @@
 #define CONFIG_SYS_TEXT_BASE		0x40100000
 
 #define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_CLK_FREQ		100000000
-#define CONFIG_DDR_CLK_FREQ		125000000
+#define CONFIG_SYS_CLK_FREQ		125000000
+#define CONFIG_CLUSTER_CLK_FREQ		100000000
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F	1
@@ -86,7 +86,7 @@
 #define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index e55fcb2..3b55699 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -50,7 +50,7 @@
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-- 
2.1.0.27.g96db324

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-12  4:08 [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization Zhiqiang Hou
@ 2016-09-12  4:08 ` Zhiqiang Hou
  2016-09-13  7:22   ` Prabhakar Kushwaha
  2016-09-12 16:37 ` [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor " york sun
  2016-09-13  7:17 ` Prabhakar Kushwaha
  2 siblings, 1 reply; 11+ messages in thread
From: Zhiqiang Hou @ 2016-09-12  4:08 UTC (permalink / raw)
  To: u-boot

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

This patch map the sys_info->freq_systembus to Platform PLL, and
implement the IPs' clock function individually.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 +++++++++++++++++-----
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 include/configs/ls2080a_common.h                   |  2 +-
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index a9b12a4..daad80a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 #endif
 
+	/* The freq_systembus is used to record frequency of platform PLL */
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
-	/* Platform clock is half of platform PLL */
-	sys_info->freq_systembus /= 2;
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
 	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
 #endif
 }
 
@@ -159,7 +158,7 @@ int get_clocks(void)
 
 /********************************************
  * get_bus_freq
- * return system bus freq in Hz
+ * return platform PLL freq in Hz
  *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
@@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
 	return gd->mem_clk;
 }
 
+int get_i2c_freq(ulong dummy)
+{
+	return  get_bus_freq(0) / 4;
+}
+
+int get_dspi_freq(ulong dummy)
+{
+	return  get_bus_freq(0) / 4;
+}
+
+int get_serial_clock(void)
+{
+	return get_bus_freq(0) / 4;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_I2C_CLK:
-		return get_bus_freq(0) / 2;
+		return get_i2c_freq(0);
 	case MXC_DSPI_CLK:
-		return get_bus_freq(0) / 2;
+		return get_dspi_freq(0);
 	default:
 		printf("Unsupported clock\n");
 	}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 93e26c1..5415165 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -165,6 +165,7 @@
 
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index ebe1415..8cfb7fb 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -102,7 +102,7 @@
 #define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-- 
2.1.0.27.g96db324

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
  2016-09-12  4:08 [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization Zhiqiang Hou
  2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
@ 2016-09-12 16:37 ` york sun
  2016-09-13  7:17 ` Prabhakar Kushwaha
  2 siblings, 0 replies; 11+ messages in thread
From: york sun @ 2016-09-12 16:37 UTC (permalink / raw)
  To: u-boot

Prabhakar,

On 09/11/2016 09:20 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Up to now, there are 3 kinds of SoC under Layerscape Chassis 2,
> such as LS1043A, LS1046A and LS1012A. But the clocks tree has a
> lot of difference, for instance the IP modules have different
> divisors to get clock from Platform PLL. And the core cluster
> and platform PLL maybe have different reference clock, such as
> LS1012A. Another problem is which clock/PLL should be described
> by sys_info->freq_systembus, it is confused in Chissis 2.
>
> This patch is to map the sys_info->freq_systembus to the Platform
> PLL, and handle the different divisor of IP modules separately
> between different SoCs. And separate cluster and platform PLL
> reference clock.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96 ++++++++++++++++++----
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
>  include/configs/ls1012a_common.h                   |  6 +-
>  include/configs/ls1043a_common.h                   |  2 +-
>  4 files changed, 86 insertions(+), 19 deletions(-)

Please review this set. It collides with your patch set. I like 
Zhiqiang's idea to use platform PLL instead of platform clock.

York

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
  2016-09-12  4:08 [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization Zhiqiang Hou
  2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
  2016-09-12 16:37 ` [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor " york sun
@ 2016-09-13  7:17 ` Prabhakar Kushwaha
  2016-09-13  8:52   ` Z.Q. Hou
  2 siblings, 1 reply; 11+ messages in thread
From: Prabhakar Kushwaha @ 2016-09-13  7:17 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> Sent: Monday, September 12, 2016 9:39 AM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> <calvin.johnson@nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> Up to now, there are 3 kinds of SoC under Layerscape Chassis 2,
> such as LS1043A, LS1046A and LS1012A. But the clocks tree has a
> lot of difference, for instance the IP modules have different
> divisors to get clock from Platform PLL. And the core cluster
> and platform PLL maybe have different reference clock, such as
> LS1012A. Another problem is which clock/PLL should be described
> by sys_info->freq_systembus, it is confused in Chissis 2.
> 
> This patch is to map the sys_info->freq_systembus to the Platform
> PLL, and handle the different divisor of IP modules separately
> between different SoCs. And separate cluster and platform PLL
> reference clock.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96
> ++++++++++++++++++----
>  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
>  include/configs/ls1012a_common.h                   |  6 +-
>  include/configs/ls1043a_common.h                   |  2 +-
>  4 files changed, 86 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> index 8922197..4fb736d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
>  	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
>  	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
>  	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
> +	unsigned long cluster_clk;
> 
>  	sys_info->freq_systembus = sysclk;
> +#ifdef CONFIG_CLUSTER_CLK_FREQ
> +	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;

Just thinking, why to have CONFIG_CLUSTER_CLK_FREQ specially for LS1012A.

Why cannot below be defined for all SoCs 
#ifndef CONFIG_CLUSTER_CLK_FREQ  
#define CONFIG_CLUSTER_CLK_FREQ  CONFIG_SYS_CLK_FREQ 
#endif

This will avoid special #else part mentioned just below. 

> +#else
> +	cluster_clk = sysclk;
> +#endif
>  #ifdef CONFIG_DDR_CLK_FREQ
>  	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
>  #else
>  	sys_info->freq_ddrbus = sysclk;

Is this case is only for LS1012A. then it is not required as below code under CONFIG_LS1012A doing same. 

>  #endif
> 
> -#ifdef CONFIG_LS1012A
> -	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> -			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> -			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> -#else
> +	/* The freq_systembus is used to record frequency of platform PLL */
>  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> +
> +#ifdef CONFIG_LS1012A
> +	sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
> +#else
>  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
>  	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
>  		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
>  		if (ratio[i] > 4)
> -			freq_c_pll[i] = sysclk * ratio[i];
> +			freq_c_pll[i] = cluster_clk * ratio[i];
>  		else
>  			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
>  	}
> @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
>  			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
>  	}
> 
> -#ifdef CONFIG_LS1012A
> -	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
> -	sys_info->freq_ddrbus *= 2;
> -#endif
> -
>  #define HWA_CGA_M1_CLK_SEL	0xe0000000
>  #define HWA_CGA_M1_CLK_SHIFT	29
>  #ifdef CONFIG_SYS_DPAA_FMAN
> @@ -148,7 +149,11 @@ void get_sys_info(struct sys_info *sys_info)
>  		break;
>  	}
>  #else
> +#ifdef CONFIG_LS1043A
>  	sys_info->freq_sdhc = sys_info->freq_systembus;
> +#elif defined(CONFIG_LS1046A) || defined(CONFIG_LS1012A)
> +	sys_info->freq_sdhc = sys_info->freq_systembus / 2;
> +#endif
>  #endif
>  #endif
> 
> @@ -156,7 +161,11 @@ void get_sys_info(struct sys_info *sys_info)
>  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
>  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> 
> +#ifdef CONFIG_LS1043A
>  	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> +#elif defined(CONFIG_LS1046A)
> +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> +#endif
>  #endif
>  }
> 
> @@ -179,41 +188,98 @@ int get_clocks(void)
>  		return 1;
>  }
> 
> +/********************************************
> + * get_bus_freq
> + * return platform PLL freq in Hz
> + *********************************************/
>  ulong get_bus_freq(ulong dummy)
>  {
> +	if (!gd->bus_clk)
> +		get_clocks();
> +
>  	return gd->bus_clk;
>  }
> 
>  ulong get_ddr_freq(ulong dummy)
>  {
> +	if (!gd->mem_clk)
> +		get_clocks();
> +
>  	return gd->mem_clk;
>  }
> 
>  #ifdef CONFIG_FSL_ESDHC
>  int get_sdhc_freq(ulong dummy)
>  {
> +	if (!gd->arch.sdhc_clk)
> +		get_clocks();
> +
>  	return gd->arch.sdhc_clk;
>  }
>  #endif
> 
>  int get_serial_clock(void)
>  {
> -	return gd->bus_clk;
> +#ifdef CONFIG_LS1043A
> +	return get_bus_freq(0);
> +#elif defined(CONFIG_LS1046A)
> +	return get_bus_freq(0) / 2;
> +#elif defined(CONFIG_LS1012A)
> +	return get_bus_freq(0) / 4;
> +#else
> +	return 0;
> +#endif
> +}
> +
> +int get_i2c_freq(ulong dummy)
> +{
> +#ifdef CONFIG_LS1043A
> +	return get_bus_freq(0);

I will suggest to avoid SoC specific define from this file.
Define CONFIG_SYS_FSL_I2C_CLK_DIV. 
#ifndef CONFIG_SYS_FSL_I2C_CLK_DIV
#define CONFIG_SYS_FSL_I2C_CLK_DIV 2
#endif

Its value will be 1 and 4 only for LS1042 and LS1012A. 
Similarly you can do for other clocks like serial, dspi etc.

-prabhakar

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
@ 2016-09-13  7:22   ` Prabhakar Kushwaha
  2016-09-13  9:09     ` Z.Q. Hou
  0 siblings, 1 reply; 11+ messages in thread
From: Prabhakar Kushwaha @ 2016-09-13  7:22 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> Sent: Monday, September 12, 2016 9:39 AM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> <calvin.johnson@nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
> 
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This patch map the sys_info->freq_systembus to Platform PLL, and
> implement the IPs' clock function individually.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
>  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26 +++++++++++++++++--
> ---
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
>  include/configs/ls2080a_common.h                   |  2 +-
>  3 files changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> index a9b12a4..daad80a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
>  #endif
>  #endif
> 
> +	/* The freq_systembus is used to record frequency of platform PLL */
>  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> -	/* Platform clock is half of platform PLL */
> -	sys_info->freq_systembus /= 2;

This is required only for ls2080A and ls2088A otherwise u-boot will be printing dicken speed in boot log.

>  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
>  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
>  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
>  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
>  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> 
> -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
>  #endif
>  }
> 
> @@ -159,7 +158,7 @@ int get_clocks(void)
> 
>  /********************************************
>   * get_bus_freq
> - * return system bus freq in Hz
> + * return platform PLL freq in Hz
>   *********************************************/
>  ulong get_bus_freq(ulong dummy)
>  {
> @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
>  	return gd->mem_clk;
>  }
> 
> +int get_i2c_freq(ulong dummy)
> +{
> +	return  get_bus_freq(0) / 4;
> +}
> +
> +int get_dspi_freq(ulong dummy)
> +{
> +	return  get_bus_freq(0) / 4;
> +}
> +
> +int get_serial_clock(void)
> +{
> +	return get_bus_freq(0) / 4;
> +}
> +

get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this for above code. 

--prabhakar

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
  2016-09-13  7:17 ` Prabhakar Kushwaha
@ 2016-09-13  8:52   ` Z.Q. Hou
  0 siblings, 0 replies; 11+ messages in thread
From: Z.Q. Hou @ 2016-09-13  8:52 UTC (permalink / raw)
  To: u-boot

Hi Prabhakar,

Thanks for your comments.

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?9?13? 15:18
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: RE: [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system
> initialization
> 
> 
> > -----Original Message-----
> > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > Sent: Monday, September 12, 2016 9:39 AM
> > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > <calvin.johnson@nxp.com>
> > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > Subject: [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system
> > initialization
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Up to now, there are 3 kinds of SoC under Layerscape Chassis 2, such
> > as LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of
> > difference, for instance the IP modules have different divisors to get
> > clock from Platform PLL. And the core cluster and platform PLL maybe
> > have different reference clock, such as LS1012A. Another problem is
> > which clock/PLL should be described by sys_info->freq_systembus, it is
> > confused in Chissis 2.
> >
> > This patch is to map the sys_info->freq_systembus to the Platform PLL,
> > and handle the different divisor of IP modules separately between
> > different SoCs. And separate cluster and platform PLL reference clock.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96
> > ++++++++++++++++++----
> >  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  1 +
> >  include/configs/ls1012a_common.h                   |  6 +-
> >  include/configs/ls1043a_common.h                   |  2 +-
> >  4 files changed, 86 insertions(+), 19 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > index 8922197..4fb736d 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> > @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info)
> >  	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
> >  	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
> >  	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
> > +	unsigned long cluster_clk;
> >
> >  	sys_info->freq_systembus = sysclk;
> > +#ifdef CONFIG_CLUSTER_CLK_FREQ
> > +	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
> 
> Just thinking, why to have CONFIG_CLUSTER_CLK_FREQ specially for LS1012A.
>

The CONFIG_CLUSTER_CLK_FREQ is not special for LS1012A, actually all SoCs should define it. As the other SoCs have the same core cluster PLL and platform PLL reference clock, doesn't like LS1012A have 100MHz for core cluster PLL and 125MHz for platform PLL, so add this macro only in LS1012A and others reuse CONFIG_SYS_CLK_FREQ.
 
> Why cannot below be defined for all SoCs #ifndef
> CONFIG_CLUSTER_CLK_FREQ #define CONFIG_CLUSTER_CLK_FREQ
> CONFIG_SYS_CLK_FREQ #endif
> 
> This will avoid special #else part mentioned just below.
> 

Yes, it could be arranged, although have no functional change, seems more brief.

> > +#else
> > +	cluster_clk = sysclk;
> > +#endif
> >  #ifdef CONFIG_DDR_CLK_FREQ
> >  	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;  #else
> >  	sys_info->freq_ddrbus = sysclk;
> 
> Is this case is only for LS1012A. then it is not required as below code under
> CONFIG_LS1012A doing same.
> 

No, it works for all SoCs that have DDR PLL and DDR reference clock. Actually the reason to introduce the macro CONFIG_CLUSTER_CLK_FREQ is to avoid using CONFIG_DDR_CLK_FREQ on LS1012A.
The LS1012A has no DDR PLL and DDR clock is provided by platform PLL, so it isn't reasonable to use CONFIG_DDR_CLK_FREQ on LS1012A.

> >  #endif
> >
> > -#ifdef CONFIG_LS1012A
> > -	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > -			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > -			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > -#else
> > +	/* The freq_systembus is used to record frequency of platform PLL */
> >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> >  			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> >  			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > +
> > +#ifdef CONFIG_LS1012A
> > +	sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; #else
> >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> >  			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> >  			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> > @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info)
> >  	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
> >  		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
> >  		if (ratio[i] > 4)
> > -			freq_c_pll[i] = sysclk * ratio[i];
> > +			freq_c_pll[i] = cluster_clk * ratio[i];
> >  		else
> >  			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
> >  	}
> > @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info)
> >  			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
> >  	}
> >
> > -#ifdef CONFIG_LS1012A
> > -	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
> > -	sys_info->freq_ddrbus *= 2;
> > -#endif
> > -
> >  #define HWA_CGA_M1_CLK_SEL	0xe0000000
> >  #define HWA_CGA_M1_CLK_SHIFT	29
> >  #ifdef CONFIG_SYS_DPAA_FMAN
> > @@ -148,7 +149,11 @@ void get_sys_info(struct sys_info *sys_info)
> >  		break;
> >  	}
> >  #else
> > +#ifdef CONFIG_LS1043A
> >  	sys_info->freq_sdhc = sys_info->freq_systembus;
> > +#elif defined(CONFIG_LS1046A) || defined(CONFIG_LS1012A)
> > +	sys_info->freq_sdhc = sys_info->freq_systembus / 2; #endif
> >  #endif
> >  #endif
> >
> > @@ -156,7 +161,11 @@ void get_sys_info(struct sys_info *sys_info)
> >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> >
> > +#ifdef CONFIG_LS1043A
> >  	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > +#elif defined(CONFIG_LS1046A)
> > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; #endif
> >  #endif
> >  }
> >
> > @@ -179,41 +188,98 @@ int get_clocks(void)
> >  		return 1;
> >  }
> >
> > +/********************************************
> > + * get_bus_freq
> > + * return platform PLL freq in Hz
> > + *********************************************/
> >  ulong get_bus_freq(ulong dummy)
> >  {
> > +	if (!gd->bus_clk)
> > +		get_clocks();
> > +
> >  	return gd->bus_clk;
> >  }
> >
> >  ulong get_ddr_freq(ulong dummy)
> >  {
> > +	if (!gd->mem_clk)
> > +		get_clocks();
> > +
> >  	return gd->mem_clk;
> >  }
> >
> >  #ifdef CONFIG_FSL_ESDHC
> >  int get_sdhc_freq(ulong dummy)
> >  {
> > +	if (!gd->arch.sdhc_clk)
> > +		get_clocks();
> > +
> >  	return gd->arch.sdhc_clk;
> >  }
> >  #endif
> >
> >  int get_serial_clock(void)
> >  {
> > -	return gd->bus_clk;
> > +#ifdef CONFIG_LS1043A
> > +	return get_bus_freq(0);
> > +#elif defined(CONFIG_LS1046A)
> > +	return get_bus_freq(0) / 2;
> > +#elif defined(CONFIG_LS1012A)
> > +	return get_bus_freq(0) / 4;
> > +#else
> > +	return 0;
> > +#endif
> > +}
> > +
> > +int get_i2c_freq(ulong dummy)
> > +{
> > +#ifdef CONFIG_LS1043A
> > +	return get_bus_freq(0);
> 
> I will suggest to avoid SoC specific define from this file.
> Define CONFIG_SYS_FSL_I2C_CLK_DIV.
> #ifndef CONFIG_SYS_FSL_I2C_CLK_DIV
> #define CONFIG_SYS_FSL_I2C_CLK_DIV 2
> #endif
> 
> Its value will be 1 and 4 only for LS1042 and LS1012A.
> Similarly you can do for other clocks like serial, dspi etc.
>

Yes, this is a good idea, will add in next version.
 
Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-13  7:22   ` Prabhakar Kushwaha
@ 2016-09-13  9:09     ` Z.Q. Hou
  2016-09-13 10:03       ` Prabhakar Kushwaha
  0 siblings, 1 reply; 11+ messages in thread
From: Z.Q. Hou @ 2016-09-13  9:09 UTC (permalink / raw)
  To: u-boot

Hi Prabhakar,

Thanks for your feedback.

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?9?13? 15:22
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> 
> > -----Original Message-----
> > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > Sent: Monday, September 12, 2016 9:39 AM
> > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > <calvin.johnson@nxp.com>
> > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > This patch map the sys_info->freq_systembus to Platform PLL, and
> > implement the IPs' clock function individually.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > +++++++++++++++++--
> > ---
> >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> >  include/configs/ls2080a_common.h                   |  2 +-
> >  3 files changed, 22 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > index a9b12a4..daad80a 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
> > #endif  #endif
> >
> > +	/* The freq_systembus is used to record frequency of platform PLL */
> >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > -	/* Platform clock is half of platform PLL */
> > -	sys_info->freq_systembus /= 2;
> 
> This is required only for ls2080A and ls2088A otherwise u-boot will be printing
> dicken speed in boot log.

Why it is required by ls2080A and ls2088A? and I don't know what's 'dicken speed'?

> 
> >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> >
> > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> >  #endif
> >  }
> >
> > @@ -159,7 +158,7 @@ int get_clocks(void)
> >
> >  /********************************************
> >   * get_bus_freq
> > - * return system bus freq in Hz
> > + * return platform PLL freq in Hz
> >   *********************************************/
> >  ulong get_bus_freq(ulong dummy)
> >  {
> > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
> >  	return gd->mem_clk;
> >  }
> >
> > +int get_i2c_freq(ulong dummy)
> > +{
> > +	return  get_bus_freq(0) / 4;
> > +}
> > +
> > +int get_dspi_freq(ulong dummy)
> > +{
> > +	return  get_bus_freq(0) / 4;
> > +}
> > +
> > +int get_serial_clock(void)
> > +{
> > +	return get_bus_freq(0) / 4;
> > +}
> > +
> 
> get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this for above
> code.

Will take LS1088A into account.

Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-13  9:09     ` Z.Q. Hou
@ 2016-09-13 10:03       ` Prabhakar Kushwaha
  2016-09-14  2:45         ` Z.Q. Hou
  0 siblings, 1 reply; 11+ messages in thread
From: Prabhakar Kushwaha @ 2016-09-13 10:03 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Z.Q. Hou
> Sent: Tuesday, September 13, 2016 2:39 PM
> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> boot at lists.denx.de; albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>;
> Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> Hi Prabhakar,
> 
> Thanks for your feedback.
> 
> > -----Original Message-----
> > From: Prabhakar Kushwaha
> > Sent: 2016?9?13? 15:22
> > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> >
> > > -----Original Message-----
> > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > > Sent: Monday, September 12, 2016 9:39 AM
> > > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > > <calvin.johnson@nxp.com>
> > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > > initialization
> > >
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > This patch map the sys_info->freq_systembus to Platform PLL, and
> > > implement the IPs' clock function individually.
> > >
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > ---
> > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > > +++++++++++++++++--
> > > ---
> > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> > >  include/configs/ls2080a_common.h                   |  2 +-
> > >  3 files changed, 22 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > index a9b12a4..daad80a 100644
> > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
> > > #endif  #endif
> > >
> > > +	/* The freq_systembus is used to record frequency of platform PLL */
> > >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > > -	/* Platform clock is half of platform PLL */
> > > -	sys_info->freq_systembus /= 2;
> >
> > This is required only for ls2080A and ls2088A otherwise u-boot will be printing
> > dicken speed in boot log.
> 
> Why it is required by ls2080A and ls2088A? and I don't know what's 'dicken
> speed'?
> 

Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080 and LS2088A.
Platform clock or CCB = dicken speed/2


> >
> > >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> > >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> > >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
> > >
> > > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> > >  #endif
> > >  }
> > >
> > > @@ -159,7 +158,7 @@ int get_clocks(void)
> > >
> > >  /********************************************
> > >   * get_bus_freq
> > > - * return system bus freq in Hz
> > > + * return platform PLL freq in Hz
> > >   *********************************************/
> > >  ulong get_bus_freq(ulong dummy)
> > >  {
> > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
> > >  	return gd->mem_clk;
> > >  }
> > >
> > > +int get_i2c_freq(ulong dummy)
> > > +{
> > > +	return  get_bus_freq(0) / 4;
> > > +}
> > > +
> > > +int get_dspi_freq(ulong dummy)
> > > +{
> > > +	return  get_bus_freq(0) / 4;
> > > +}
> > > +
> > > +int get_serial_clock(void)
> > > +{
> > > +	return get_bus_freq(0) / 4;
> > > +}
> > > +
> >
> > get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this for above
> > code.
> 
> Will take LS1088A into account.
> 
Thanks

--prabhakar

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-13 10:03       ` Prabhakar Kushwaha
@ 2016-09-14  2:45         ` Z.Q. Hou
  2016-09-14  8:18           ` Prabhakar Kushwaha
  0 siblings, 1 reply; 11+ messages in thread
From: Z.Q. Hou @ 2016-09-14  2:45 UTC (permalink / raw)
  To: u-boot

Hi Prabhakar,

Thanks for your feedback!

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?9?13? 18:04
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> 
> > -----Original Message-----
> > From: Z.Q. Hou
> > Sent: Tuesday, September 13, 2016 2:39 PM
> > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> > boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson
> > <calvin.johnson@nxp.com>
> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> > Hi Prabhakar,
> >
> > Thanks for your feedback.
> >
> > > -----Original Message-----
> > > From: Prabhakar Kushwaha
> > > Sent: 2016?9?13? 15:22
> > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > system initialization
> > >
> > >
> > > > -----Original Message-----
> > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > > > Sent: Monday, September 12, 2016 9:39 AM
> > > > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > > > <calvin.johnson@nxp.com>
> > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > > > initialization
> > > >
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > >
> > > > This patch map the sys_info->freq_systembus to Platform PLL, and
> > > > implement the IPs' clock function individually.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > ---
> > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > > > +++++++++++++++++--
> > > > ---
> > > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> > > >  include/configs/ls2080a_common.h                   |  2 +-
> > > >  3 files changed, 22 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > index a9b12a4..daad80a 100644
> > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
> > > > #endif  #endif
> > > >
> > > > +	/* The freq_systembus is used to record frequency of platform
> > > > +PLL */
> > > >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > > > -	/* Platform clock is half of platform PLL */
> > > > -	sys_info->freq_systembus /= 2;
> > >
> > > This is required only for ls2080A and ls2088A otherwise u-boot will
> > > be printing dicken speed in boot log.
> >
> > Why it is required by ls2080A and ls2088A? and I don't know what's
> > 'dicken speed'?
> >
> 
> Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080
> and LS2088A.
> Platform clock or CCB = dicken speed/2

Why it is required by ls2080A and ls2088A but without #ifdef LS2080||LS2088?
Is there any document upon the concept 'dicken speed'? As you said the dicken speed == platform PLL frequency on LS2080A and LS2088A, what about other SoCs?
if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3?

> 
> > >
> > > >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> > > >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> > > >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT)
> +
> > > > 1;
> > > >
> > > > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > > > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> > > >  #endif
> > > >  }
> > > >
> > > > @@ -159,7 +158,7 @@ int get_clocks(void)
> > > >
> > > >  /********************************************
> > > >   * get_bus_freq
> > > > - * return system bus freq in Hz
> > > > + * return platform PLL freq in Hz
> > > >   *********************************************/
> > > >  ulong get_bus_freq(ulong dummy)
> > > >  {
> > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
> > > >  	return gd->mem_clk;
> > > >  }
> > > >
> > > > +int get_i2c_freq(ulong dummy)
> > > > +{
> > > > +	return  get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > > > +int get_dspi_freq(ulong dummy)
> > > > +{
> > > > +	return  get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > > > +int get_serial_clock(void)
> > > > +{
> > > > +	return get_bus_freq(0) / 4;
> > > > +}
> > > > +
> > >
> > > get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this
> > > for above code.
> >
> > Will take LS1088A into account.
> >
> Thanks
> 

Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-14  2:45         ` Z.Q. Hou
@ 2016-09-14  8:18           ` Prabhakar Kushwaha
  2016-09-14  9:56             ` Z.Q. Hou
  0 siblings, 1 reply; 11+ messages in thread
From: Prabhakar Kushwaha @ 2016-09-14  8:18 UTC (permalink / raw)
  To: u-boot


> -----Original Message-----
> From: Z.Q. Hou
> Sent: Wednesday, September 14, 2016 8:16 AM
> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> boot at lists.denx.de; albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>;
> Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> Hi Prabhakar,
> 
> Thanks for your feedback!
> 
> > -----Original Message-----
> > From: Prabhakar Kushwaha
> > Sent: 2016?9?13? 18:04
> > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> >
> > > -----Original Message-----
> > > From: Z.Q. Hou
> > > Sent: Tuesday, September 13, 2016 2:39 PM
> > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> > > boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson
> > > <calvin.johnson@nxp.com>
> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > > initialization
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for your feedback.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar Kushwaha
> > > > Sent: 2016?9?13? 15:22
> > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > > > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> > > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > > system initialization
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > > > > Sent: Monday, September 12, 2016 9:39 AM
> > > > > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > > > > <calvin.johnson@nxp.com>
> > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > > > > initialization
> > > > >
> > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > >
> > > > > This patch map the sys_info->freq_systembus to Platform PLL, and
> > > > > implement the IPs' clock function individually.
> > > > >
> > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > ---
> > > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > > > > +++++++++++++++++--
> > > > > ---
> > > > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> > > > >  include/configs/ls2080a_common.h                   |  2 +-
> > > > >  3 files changed, 22 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > index a9b12a4..daad80a 100644
> > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info)
> > > > > #endif  #endif
> > > > >
> > > > > +	/* The freq_systembus is used to record frequency of platform
> > > > > +PLL */
> > > > >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> > > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > > > > -	/* Platform clock is half of platform PLL */
> > > > > -	sys_info->freq_systembus /= 2;
> > > >
> > > > This is required only for ls2080A and ls2088A otherwise u-boot will
> > > > be printing dicken speed in boot log.
> > >
> > > Why it is required by ls2080A and ls2088A? and I don't know what's
> > > 'dicken speed'?
> > >
> >
> > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for LS2080
> > and LS2088A.
> > Platform clock or CCB = dicken speed/2
> 
> Why it is required by ls2080A and ls2088A but without #ifdef LS2080||LS2088?
> Is there any document upon the concept 'dicken speed'? As you said the dicken
> speed == platform PLL frequency on LS2080A and LS2088A, what about other
> SoCs?
> if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3?
> 

Platform clock == dicken speed/2. It is only for LS2080A and LS2088A. 
For ls1088a and other SoCs platform clock  = SYSCLK * RCW[SYS_PLL_RAT]

> >
> > > >
> > > > >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> > > > >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> > > > >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT)
> > +
> > > > > 1;
> > > > >
> > > > > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > > > > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr;
> > > > >  #endif
> > > > >  }
> > > > >
> > > > > @@ -159,7 +158,7 @@ int get_clocks(void)
> > > > >
> > > > >  /********************************************
> > > > >   * get_bus_freq
> > > > > - * return system bus freq in Hz
> > > > > + * return platform PLL freq in Hz
> > > > >   *********************************************/
> > > > >  ulong get_bus_freq(ulong dummy)
> > > > >  {
> > > > > @@ -190,13 +189,28 @@ ulong get_ddr_freq(ulong ctrl_num)
> > > > >  	return gd->mem_clk;
> > > > >  }
> > > > >
> > > > > +int get_i2c_freq(ulong dummy)
> > > > > +{
> > > > > +	return  get_bus_freq(0) / 4;
> > > > > +}
> > > > > +
> > > > > +int get_dspi_freq(ulong dummy)
> > > > > +{
> > > > > +	return  get_bus_freq(0) / 4;
> > > > > +}
> > > > > +
> > > > > +int get_serial_clock(void)
> > > > > +{
> > > > > +	return get_bus_freq(0) / 4;
> > > > > +}
> > > > > +
> > > >
> > > > get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid this
> > > > for above code.
> > >
> > > Will take LS1088A into account.
> > >
> > Thanks
> >
> 
> Thanks,
> Zhiqiang

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system initialization
  2016-09-14  8:18           ` Prabhakar Kushwaha
@ 2016-09-14  9:56             ` Z.Q. Hou
  0 siblings, 0 replies; 11+ messages in thread
From: Z.Q. Hou @ 2016-09-14  9:56 UTC (permalink / raw)
  To: u-boot

Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?9?14? 16:18
> To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> initialization
> 
> 
> > -----Original Message-----
> > From: Z.Q. Hou
> > Sent: Wednesday, September 14, 2016 8:16 AM
> > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> > boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin Johnson
> > <calvin.johnson@nxp.com>
> > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock system
> > initialization
> >
> > Hi Prabhakar,
> >
> > Thanks for your feedback!
> >
> > > -----Original Message-----
> > > From: Prabhakar Kushwaha
> > > Sent: 2016?9?13? 18:04
> > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent Hu
> > > <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > system initialization
> > >
> > >
> > > > -----Original Message-----
> > > > From: Z.Q. Hou
> > > > Sent: Tuesday, September 13, 2016 2:39 PM
> > > > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; u-
> > > > boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Calvin
> > > > Johnson <calvin.johnson@nxp.com>
> > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > > system initialization
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Thanks for your feedback.
> > > >
> > > > > -----Original Message-----
> > > > > From: Prabhakar Kushwaha
> > > > > Sent: 2016?9?13? 15:22
> > > > > To: Z.Q. Hou <zhiqiang.hou@nxp.com>; u-boot at lists.denx.de;
> > > > > albert.u.boot at aribaud.net; york sun <york.sun@nxp.com>; Vincent
> > > > > Hu <mingkai.hu@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > > > Subject: RE: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > > > system initialization
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at nxp.com]
> > > > > > Sent: Monday, September 12, 2016 9:39 AM
> > > > > > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net; york sun
> > > > > > <york.sun@nxp.com>; Vincent Hu <mingkai.hu@nxp.com>; Prabhakar
> > > > > > Kushwaha <prabhakar.kushwaha@nxp.com>; Calvin Johnson
> > > > > > <calvin.johnson@nxp.com>
> > > > > > Cc: Z.Q. Hou <zhiqiang.hou@nxp.com>
> > > > > > Subject: [PATCH 2/2] armv8/fsl-lsch3: consolidate the clock
> > > > > > system initialization
> > > > > >
> > > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > >
> > > > > > This patch map the sys_info->freq_systembus to Platform PLL,
> > > > > > and implement the IPs' clock function individually.
> > > > > >
> > > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > > > > ---
> > > > > >  .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 26
> > > > > > +++++++++++++++++--
> > > > > > ---
> > > > > >  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
> > > > > >  include/configs/ls2080a_common.h                   |  2 +-
> > > > > >  3 files changed, 22 insertions(+), 7 deletions(-)
> > > > > >
> > > > > > diff --git
> > > > > > a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > > b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > > index a9b12a4..daad80a 100644
> > > > > > --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
> > > > > > @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info
> > > > > > *sys_info) #endif  #endif
> > > > > >
> > > > > > +	/* The freq_systembus is used to record frequency of
> > > > > > +platform PLL */
> > > > > >  	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> > > > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > > > >  			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
> > > > > > -	/* Platform clock is half of platform PLL */
> > > > > > -	sys_info->freq_systembus /= 2;
> > > > >
> > > > > This is required only for ls2080A and ls2088A otherwise u-boot
> > > > > will be printing dicken speed in boot log.
> > > >
> > > > Why it is required by ls2080A and ls2088A? and I don't know what's
> > > > 'dicken speed'?
> > > >
> > >
> > > Clock generated by SYSCLK * RCW[SYS_PLL_RAT] == dicken speed for
> > > LS2080 and LS2088A.
> > > Platform clock or CCB = dicken speed/2
> >
> > Why it is required by ls2080A and ls2088A but without #ifdef
> LS2080||LS2088?
> > Is there any document upon the concept 'dicken speed'? As you said the
> > dicken speed == platform PLL frequency on LS2080A and LS2088A, what
> > about other SoCs?
> > if the platform clock == dicken speed/2 on all Layerscape chassis2 and 3?
> >
> 
> Platform clock == dicken speed/2. It is only for LS2080A and LS2088A.
> For ls1088a and other SoCs platform clock  = SYSCLK * RCW[SYS_PLL_RAT]
>

Refer to LS1012A RM revC, the ls1012a platform clock = SYSCLK * RCW[SYS_PLL_RAT] / 2.

For this patch, what do you think about matching sys_info->freq_systembus with platform PLL frequency?
Do you have any suggestion on either the platform PLL or platform clock should be printed as bus clock in u-boot?
 
> > >
> > > > >
> > > > > >  	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> > > > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > > > > >  			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
> > > > > > @@ -132,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
> > > > > >  	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
> > > > > >  	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >>
> > > > > > IFC_CCR_CLK_DIV_SHIFT)
> > > +
> > > > > > 1;
> > > > > >
> > > > > > -	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
> > > > > > +	sys_info->freq_localbus = sys_info->freq_systembus / 2 /
> > > > > > +ccr;
> > > > > >  #endif
> > > > > >  }
> > > > > >
> > > > > > @@ -159,7 +158,7 @@ int get_clocks(void)
> > > > > >
> > > > > >  /********************************************
> > > > > >   * get_bus_freq
> > > > > > - * return system bus freq in Hz
> > > > > > + * return platform PLL freq in Hz
> > > > > >   *********************************************/
> > > > > >  ulong get_bus_freq(ulong dummy)  { @@ -190,13 +189,28 @@
> > > > > > ulong get_ddr_freq(ulong ctrl_num)
> > > > > >  	return gd->mem_clk;
> > > > > >  }
> > > > > >
> > > > > > +int get_i2c_freq(ulong dummy) {
> > > > > > +	return  get_bus_freq(0) / 4; }
> > > > > > +
> > > > > > +int get_dspi_freq(ulong dummy) {
> > > > > > +	return  get_bus_freq(0) / 4; }
> > > > > > +
> > > > > > +int get_serial_clock(void)
> > > > > > +{
> > > > > > +	return get_bus_freq(0) / 4;
> > > > > > +}
> > > > > > +
> > > > >
> > > > > get_bus_freq(0) / 4  --> May not be true for LS1088A. So Avoid
> > > > > this for above code.
> > > >
> > > > Will take LS1088A into account.
> > > >
> > > Thanks
> > >

Thanks,
Zhiqiang

^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2016-09-14  9:56 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-12  4:08 [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization Zhiqiang Hou
2016-09-12  4:08 ` [U-Boot] [PATCH 2/2] armv8/fsl-lsch3: consolidate " Zhiqiang Hou
2016-09-13  7:22   ` Prabhakar Kushwaha
2016-09-13  9:09     ` Z.Q. Hou
2016-09-13 10:03       ` Prabhakar Kushwaha
2016-09-14  2:45         ` Z.Q. Hou
2016-09-14  8:18           ` Prabhakar Kushwaha
2016-09-14  9:56             ` Z.Q. Hou
2016-09-12 16:37 ` [U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor " york sun
2016-09-13  7:17 ` Prabhakar Kushwaha
2016-09-13  8:52   ` Z.Q. Hou

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