* [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file
@ 2017-11-27 18:30 Shaoyun Liu
[not found] ` <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Shaoyun Liu @ 2017-11-27 18:30 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Shaoyun Liu
Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
---
.../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++
1 file changed, 1248 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
new file mode 100644
index 0000000..76cb748
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
@@ -0,0 +1,1248 @@
+#ifndef _ip_offset_1_HEADER
+#define _ip_offset_1_HEADER
+
+#define MAX_INSTANCE 5
+#define MAX_SEGMENT 5
+
+
+struct IP_BASE_INSTANCE
+{
+ unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+ struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
+static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } }; // not exist
+static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
+ { { 0x00016E00, 0, 0, 0, 0 } },
+ { { 0x00017000, 0, 0, 0, 0 } },
+ { { 0x00017200, 0, 0, 0, 0 } },
+ { { 0x00017E00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0 } } } };
+
+
+#define NBIF_BASE__INST0_SEG0 0x00000000
+#define NBIF_BASE__INST0_SEG1 0x00000014
+#define NBIF_BASE__INST0_SEG2 0x00000D20
+#define NBIF_BASE__INST0_SEG3 0x00010400
+#define NBIF_BASE__INST0_SEG4 0
+
+#define NBIF_BASE__INST1_SEG0 0
+#define NBIF_BASE__INST1_SEG1 0
+#define NBIF_BASE__INST1_SEG2 0
+#define NBIF_BASE__INST1_SEG3 0
+#define NBIF_BASE__INST1_SEG4 0
+
+#define NBIF_BASE__INST2_SEG0 0
+#define NBIF_BASE__INST2_SEG1 0
+#define NBIF_BASE__INST2_SEG2 0
+#define NBIF_BASE__INST2_SEG3 0
+#define NBIF_BASE__INST2_SEG4 0
+
+#define NBIF_BASE__INST3_SEG0 0
+#define NBIF_BASE__INST3_SEG1 0
+#define NBIF_BASE__INST3_SEG2 0
+#define NBIF_BASE__INST3_SEG3 0
+#define NBIF_BASE__INST3_SEG4 0
+
+#define NBIF_BASE__INST4_SEG0 0
+#define NBIF_BASE__INST4_SEG1 0
+#define NBIF_BASE__INST4_SEG2 0
+#define NBIF_BASE__INST4_SEG3 0
+#define NBIF_BASE__INST4_SEG4 0
+
+#define NBIO_BASE__INST0_SEG0 0x00000000
+#define NBIO_BASE__INST0_SEG1 0x00000014
+#define NBIO_BASE__INST0_SEG2 0x00000D20
+#define NBIO_BASE__INST0_SEG3 0x00010400
+#define NBIO_BASE__INST0_SEG4 0
+
+#define NBIO_BASE__INST1_SEG0 0
+#define NBIO_BASE__INST1_SEG1 0
+#define NBIO_BASE__INST1_SEG2 0
+#define NBIO_BASE__INST1_SEG3 0
+#define NBIO_BASE__INST1_SEG4 0
+
+#define NBIO_BASE__INST2_SEG0 0
+#define NBIO_BASE__INST2_SEG1 0
+#define NBIO_BASE__INST2_SEG2 0
+#define NBIO_BASE__INST2_SEG3 0
+#define NBIO_BASE__INST2_SEG4 0
+
+#define NBIO_BASE__INST3_SEG0 0
+#define NBIO_BASE__INST3_SEG1 0
+#define NBIO_BASE__INST3_SEG2 0
+#define NBIO_BASE__INST3_SEG3 0
+#define NBIO_BASE__INST3_SEG4 0
+
+#define NBIO_BASE__INST4_SEG0 0
+#define NBIO_BASE__INST4_SEG1 0
+#define NBIO_BASE__INST4_SEG2 0
+#define NBIO_BASE__INST4_SEG3 0
+#define NBIO_BASE__INST4_SEG4 0
+
+#define DCE_BASE__INST0_SEG0 0x00000012
+#define DCE_BASE__INST0_SEG1 0x000000C0
+#define DCE_BASE__INST0_SEG2 0x000034C0
+#define DCE_BASE__INST0_SEG3 0
+#define DCE_BASE__INST0_SEG4 0
+
+#define DCE_BASE__INST1_SEG0 0
+#define DCE_BASE__INST1_SEG1 0
+#define DCE_BASE__INST1_SEG2 0
+#define DCE_BASE__INST1_SEG3 0
+#define DCE_BASE__INST1_SEG4 0
+
+#define DCE_BASE__INST2_SEG0 0
+#define DCE_BASE__INST2_SEG1 0
+#define DCE_BASE__INST2_SEG2 0
+#define DCE_BASE__INST2_SEG3 0
+#define DCE_BASE__INST2_SEG4 0
+
+#define DCE_BASE__INST3_SEG0 0
+#define DCE_BASE__INST3_SEG1 0
+#define DCE_BASE__INST3_SEG2 0
+#define DCE_BASE__INST3_SEG3 0
+#define DCE_BASE__INST3_SEG4 0
+
+#define DCE_BASE__INST4_SEG0 0
+#define DCE_BASE__INST4_SEG1 0
+#define DCE_BASE__INST4_SEG2 0
+#define DCE_BASE__INST4_SEG3 0
+#define DCE_BASE__INST4_SEG4 0
+
+#define DCN_BASE__INST0_SEG0 0x00000012
+#define DCN_BASE__INST0_SEG1 0x000000C0
+#define DCN_BASE__INST0_SEG2 0x000034C0
+#define DCN_BASE__INST0_SEG3 0
+#define DCN_BASE__INST0_SEG4 0
+
+#define DCN_BASE__INST1_SEG0 0
+#define DCN_BASE__INST1_SEG1 0
+#define DCN_BASE__INST1_SEG2 0
+#define DCN_BASE__INST1_SEG3 0
+#define DCN_BASE__INST1_SEG4 0
+
+#define DCN_BASE__INST2_SEG0 0
+#define DCN_BASE__INST2_SEG1 0
+#define DCN_BASE__INST2_SEG2 0
+#define DCN_BASE__INST2_SEG3 0
+#define DCN_BASE__INST2_SEG4 0
+
+#define DCN_BASE__INST3_SEG0 0
+#define DCN_BASE__INST3_SEG1 0
+#define DCN_BASE__INST3_SEG2 0
+#define DCN_BASE__INST3_SEG3 0
+#define DCN_BASE__INST3_SEG4 0
+
+#define DCN_BASE__INST4_SEG0 0
+#define DCN_BASE__INST4_SEG1 0
+#define DCN_BASE__INST4_SEG2 0
+#define DCN_BASE__INST4_SEG3 0
+#define DCN_BASE__INST4_SEG4 0
+
+#define MP0_BASE__INST0_SEG0 0x00016000
+#define MP0_BASE__INST0_SEG1 0
+#define MP0_BASE__INST0_SEG2 0
+#define MP0_BASE__INST0_SEG3 0
+#define MP0_BASE__INST0_SEG4 0
+
+#define MP0_BASE__INST1_SEG0 0
+#define MP0_BASE__INST1_SEG1 0
+#define MP0_BASE__INST1_SEG2 0
+#define MP0_BASE__INST1_SEG3 0
+#define MP0_BASE__INST1_SEG4 0
+
+#define MP0_BASE__INST2_SEG0 0
+#define MP0_BASE__INST2_SEG1 0
+#define MP0_BASE__INST2_SEG2 0
+#define MP0_BASE__INST2_SEG3 0
+#define MP0_BASE__INST2_SEG4 0
+
+#define MP0_BASE__INST3_SEG0 0
+#define MP0_BASE__INST3_SEG1 0
+#define MP0_BASE__INST3_SEG2 0
+#define MP0_BASE__INST3_SEG3 0
+#define MP0_BASE__INST3_SEG4 0
+
+#define MP0_BASE__INST4_SEG0 0
+#define MP0_BASE__INST4_SEG1 0
+#define MP0_BASE__INST4_SEG2 0
+#define MP0_BASE__INST4_SEG3 0
+#define MP0_BASE__INST4_SEG4 0
+
+#define MP1_BASE__INST0_SEG0 0x00016000
+#define MP1_BASE__INST0_SEG1 0
+#define MP1_BASE__INST0_SEG2 0
+#define MP1_BASE__INST0_SEG3 0
+#define MP1_BASE__INST0_SEG4 0
+
+#define MP1_BASE__INST1_SEG0 0
+#define MP1_BASE__INST1_SEG1 0
+#define MP1_BASE__INST1_SEG2 0
+#define MP1_BASE__INST1_SEG3 0
+#define MP1_BASE__INST1_SEG4 0
+
+#define MP1_BASE__INST2_SEG0 0
+#define MP1_BASE__INST2_SEG1 0
+#define MP1_BASE__INST2_SEG2 0
+#define MP1_BASE__INST2_SEG3 0
+#define MP1_BASE__INST2_SEG4 0
+
+#define MP1_BASE__INST3_SEG0 0
+#define MP1_BASE__INST3_SEG1 0
+#define MP1_BASE__INST3_SEG2 0
+#define MP1_BASE__INST3_SEG3 0
+#define MP1_BASE__INST3_SEG4 0
+
+#define MP1_BASE__INST4_SEG0 0
+#define MP1_BASE__INST4_SEG1 0
+#define MP1_BASE__INST4_SEG2 0
+#define MP1_BASE__INST4_SEG3 0
+#define MP1_BASE__INST4_SEG4 0
+
+#define MP2_BASE__INST0_SEG0 0x00016000
+#define MP2_BASE__INST0_SEG1 0
+#define MP2_BASE__INST0_SEG2 0
+#define MP2_BASE__INST0_SEG3 0
+#define MP2_BASE__INST0_SEG4 0
+
+#define MP2_BASE__INST1_SEG0 0
+#define MP2_BASE__INST1_SEG1 0
+#define MP2_BASE__INST1_SEG2 0
+#define MP2_BASE__INST1_SEG3 0
+#define MP2_BASE__INST1_SEG4 0
+
+#define MP2_BASE__INST2_SEG0 0
+#define MP2_BASE__INST2_SEG1 0
+#define MP2_BASE__INST2_SEG2 0
+#define MP2_BASE__INST2_SEG3 0
+#define MP2_BASE__INST2_SEG4 0
+
+#define MP2_BASE__INST3_SEG0 0
+#define MP2_BASE__INST3_SEG1 0
+#define MP2_BASE__INST3_SEG2 0
+#define MP2_BASE__INST3_SEG3 0
+#define MP2_BASE__INST3_SEG4 0
+
+#define MP2_BASE__INST4_SEG0 0
+#define MP2_BASE__INST4_SEG1 0
+#define MP2_BASE__INST4_SEG2 0
+#define MP2_BASE__INST4_SEG3 0
+#define MP2_BASE__INST4_SEG4 0
+
+#define DF_BASE__INST0_SEG0 0x00007000
+#define DF_BASE__INST0_SEG1 0
+#define DF_BASE__INST0_SEG2 0
+#define DF_BASE__INST0_SEG3 0
+#define DF_BASE__INST0_SEG4 0
+
+#define DF_BASE__INST1_SEG0 0
+#define DF_BASE__INST1_SEG1 0
+#define DF_BASE__INST1_SEG2 0
+#define DF_BASE__INST1_SEG3 0
+#define DF_BASE__INST1_SEG4 0
+
+#define DF_BASE__INST2_SEG0 0
+#define DF_BASE__INST2_SEG1 0
+#define DF_BASE__INST2_SEG2 0
+#define DF_BASE__INST2_SEG3 0
+#define DF_BASE__INST2_SEG4 0
+
+#define DF_BASE__INST3_SEG0 0
+#define DF_BASE__INST3_SEG1 0
+#define DF_BASE__INST3_SEG2 0
+#define DF_BASE__INST3_SEG3 0
+#define DF_BASE__INST3_SEG4 0
+
+#define DF_BASE__INST4_SEG0 0
+#define DF_BASE__INST4_SEG1 0
+#define DF_BASE__INST4_SEG2 0
+#define DF_BASE__INST4_SEG3 0
+#define DF_BASE__INST4_SEG4 0
+
+#define UVD_BASE__INST0_SEG0 0x00007800
+#define UVD_BASE__INST0_SEG1 0x00007E00
+#define UVD_BASE__INST0_SEG2 0
+#define UVD_BASE__INST0_SEG3 0
+#define UVD_BASE__INST0_SEG4 0
+
+#define UVD_BASE__INST1_SEG0 0
+#define UVD_BASE__INST1_SEG1 0
+#define UVD_BASE__INST1_SEG2 0
+#define UVD_BASE__INST1_SEG3 0
+#define UVD_BASE__INST1_SEG4 0
+
+#define UVD_BASE__INST2_SEG0 0
+#define UVD_BASE__INST2_SEG1 0
+#define UVD_BASE__INST2_SEG2 0
+#define UVD_BASE__INST2_SEG3 0
+#define UVD_BASE__INST2_SEG4 0
+
+#define UVD_BASE__INST3_SEG0 0
+#define UVD_BASE__INST3_SEG1 0
+#define UVD_BASE__INST3_SEG2 0
+#define UVD_BASE__INST3_SEG3 0
+#define UVD_BASE__INST3_SEG4 0
+
+#define UVD_BASE__INST4_SEG0 0
+#define UVD_BASE__INST4_SEG1 0
+#define UVD_BASE__INST4_SEG2 0
+#define UVD_BASE__INST4_SEG3 0
+#define UVD_BASE__INST4_SEG4 0
+
+#define VCN_BASE__INST0_SEG0 0x00007800
+#define VCN_BASE__INST0_SEG1 0x00007E00
+#define VCN_BASE__INST0_SEG2 0
+#define VCN_BASE__INST0_SEG3 0
+#define VCN_BASE__INST0_SEG4 0
+
+#define VCN_BASE__INST1_SEG0 0
+#define VCN_BASE__INST1_SEG1 0
+#define VCN_BASE__INST1_SEG2 0
+#define VCN_BASE__INST1_SEG3 0
+#define VCN_BASE__INST1_SEG4 0
+
+#define VCN_BASE__INST2_SEG0 0
+#define VCN_BASE__INST2_SEG1 0
+#define VCN_BASE__INST2_SEG2 0
+#define VCN_BASE__INST2_SEG3 0
+#define VCN_BASE__INST2_SEG4 0
+
+#define VCN_BASE__INST3_SEG0 0
+#define VCN_BASE__INST3_SEG1 0
+#define VCN_BASE__INST3_SEG2 0
+#define VCN_BASE__INST3_SEG3 0
+#define VCN_BASE__INST3_SEG4 0
+
+#define VCN_BASE__INST4_SEG0 0
+#define VCN_BASE__INST4_SEG1 0
+#define VCN_BASE__INST4_SEG2 0
+#define VCN_BASE__INST4_SEG3 0
+#define VCN_BASE__INST4_SEG4 0
+
+#define DBGU_BASE__INST0_SEG0 0x00000180
+#define DBGU_BASE__INST0_SEG1 0x000001A0
+#define DBGU_BASE__INST0_SEG2 0
+#define DBGU_BASE__INST0_SEG3 0
+#define DBGU_BASE__INST0_SEG4 0
+
+#define DBGU_BASE__INST1_SEG0 0
+#define DBGU_BASE__INST1_SEG1 0
+#define DBGU_BASE__INST1_SEG2 0
+#define DBGU_BASE__INST1_SEG3 0
+#define DBGU_BASE__INST1_SEG4 0
+
+#define DBGU_BASE__INST2_SEG0 0
+#define DBGU_BASE__INST2_SEG1 0
+#define DBGU_BASE__INST2_SEG2 0
+#define DBGU_BASE__INST2_SEG3 0
+#define DBGU_BASE__INST2_SEG4 0
+
+#define DBGU_BASE__INST3_SEG0 0
+#define DBGU_BASE__INST3_SEG1 0
+#define DBGU_BASE__INST3_SEG2 0
+#define DBGU_BASE__INST3_SEG3 0
+#define DBGU_BASE__INST3_SEG4 0
+
+#define DBGU_BASE__INST4_SEG0 0
+#define DBGU_BASE__INST4_SEG1 0
+#define DBGU_BASE__INST4_SEG2 0
+#define DBGU_BASE__INST4_SEG3 0
+#define DBGU_BASE__INST4_SEG4 0
+
+#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
+#define DBGU_NBIO_BASE__INST0_SEG1 0
+#define DBGU_NBIO_BASE__INST0_SEG2 0
+#define DBGU_NBIO_BASE__INST0_SEG3 0
+#define DBGU_NBIO_BASE__INST0_SEG4 0
+
+#define DBGU_NBIO_BASE__INST1_SEG0 0
+#define DBGU_NBIO_BASE__INST1_SEG1 0
+#define DBGU_NBIO_BASE__INST1_SEG2 0
+#define DBGU_NBIO_BASE__INST1_SEG3 0
+#define DBGU_NBIO_BASE__INST1_SEG4 0
+
+#define DBGU_NBIO_BASE__INST2_SEG0 0
+#define DBGU_NBIO_BASE__INST2_SEG1 0
+#define DBGU_NBIO_BASE__INST2_SEG2 0
+#define DBGU_NBIO_BASE__INST2_SEG3 0
+#define DBGU_NBIO_BASE__INST2_SEG4 0
+
+#define DBGU_NBIO_BASE__INST3_SEG0 0
+#define DBGU_NBIO_BASE__INST3_SEG1 0
+#define DBGU_NBIO_BASE__INST3_SEG2 0
+#define DBGU_NBIO_BASE__INST3_SEG3 0
+#define DBGU_NBIO_BASE__INST3_SEG4 0
+
+#define DBGU_NBIO_BASE__INST4_SEG0 0
+#define DBGU_NBIO_BASE__INST4_SEG1 0
+#define DBGU_NBIO_BASE__INST4_SEG2 0
+#define DBGU_NBIO_BASE__INST4_SEG3 0
+#define DBGU_NBIO_BASE__INST4_SEG4 0
+
+#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
+#define DBGU_IO_BASE__INST0_SEG1 0
+#define DBGU_IO_BASE__INST0_SEG2 0
+#define DBGU_IO_BASE__INST0_SEG3 0
+#define DBGU_IO_BASE__INST0_SEG4 0
+
+#define DBGU_IO_BASE__INST1_SEG0 0
+#define DBGU_IO_BASE__INST1_SEG1 0
+#define DBGU_IO_BASE__INST1_SEG2 0
+#define DBGU_IO_BASE__INST1_SEG3 0
+#define DBGU_IO_BASE__INST1_SEG4 0
+
+#define DBGU_IO_BASE__INST2_SEG0 0
+#define DBGU_IO_BASE__INST2_SEG1 0
+#define DBGU_IO_BASE__INST2_SEG2 0
+#define DBGU_IO_BASE__INST2_SEG3 0
+#define DBGU_IO_BASE__INST2_SEG4 0
+
+#define DBGU_IO_BASE__INST3_SEG0 0
+#define DBGU_IO_BASE__INST3_SEG1 0
+#define DBGU_IO_BASE__INST3_SEG2 0
+#define DBGU_IO_BASE__INST3_SEG3 0
+#define DBGU_IO_BASE__INST3_SEG4 0
+
+#define DBGU_IO_BASE__INST4_SEG0 0
+#define DBGU_IO_BASE__INST4_SEG1 0
+#define DBGU_IO_BASE__INST4_SEG2 0
+#define DBGU_IO_BASE__INST4_SEG3 0
+#define DBGU_IO_BASE__INST4_SEG4 0
+
+#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
+#define DFX_DAP_BASE__INST0_SEG1 0
+#define DFX_DAP_BASE__INST0_SEG2 0
+#define DFX_DAP_BASE__INST0_SEG3 0
+#define DFX_DAP_BASE__INST0_SEG4 0
+
+#define DFX_DAP_BASE__INST1_SEG0 0
+#define DFX_DAP_BASE__INST1_SEG1 0
+#define DFX_DAP_BASE__INST1_SEG2 0
+#define DFX_DAP_BASE__INST1_SEG3 0
+#define DFX_DAP_BASE__INST1_SEG4 0
+
+#define DFX_DAP_BASE__INST2_SEG0 0
+#define DFX_DAP_BASE__INST2_SEG1 0
+#define DFX_DAP_BASE__INST2_SEG2 0
+#define DFX_DAP_BASE__INST2_SEG3 0
+#define DFX_DAP_BASE__INST2_SEG4 0
+
+#define DFX_DAP_BASE__INST3_SEG0 0
+#define DFX_DAP_BASE__INST3_SEG1 0
+#define DFX_DAP_BASE__INST3_SEG2 0
+#define DFX_DAP_BASE__INST3_SEG3 0
+#define DFX_DAP_BASE__INST3_SEG4 0
+
+#define DFX_DAP_BASE__INST4_SEG0 0
+#define DFX_DAP_BASE__INST4_SEG1 0
+#define DFX_DAP_BASE__INST4_SEG2 0
+#define DFX_DAP_BASE__INST4_SEG3 0
+#define DFX_DAP_BASE__INST4_SEG4 0
+
+#define DFX_BASE__INST0_SEG0 0x00000580
+#define DFX_BASE__INST0_SEG1 0
+#define DFX_BASE__INST0_SEG2 0
+#define DFX_BASE__INST0_SEG3 0
+#define DFX_BASE__INST0_SEG4 0
+
+#define DFX_BASE__INST1_SEG0 0
+#define DFX_BASE__INST1_SEG1 0
+#define DFX_BASE__INST1_SEG2 0
+#define DFX_BASE__INST1_SEG3 0
+#define DFX_BASE__INST1_SEG4 0
+
+#define DFX_BASE__INST2_SEG0 0
+#define DFX_BASE__INST2_SEG1 0
+#define DFX_BASE__INST2_SEG2 0
+#define DFX_BASE__INST2_SEG3 0
+#define DFX_BASE__INST2_SEG4 0
+
+#define DFX_BASE__INST3_SEG0 0
+#define DFX_BASE__INST3_SEG1 0
+#define DFX_BASE__INST3_SEG2 0
+#define DFX_BASE__INST3_SEG3 0
+#define DFX_BASE__INST3_SEG4 0
+
+#define DFX_BASE__INST4_SEG0 0
+#define DFX_BASE__INST4_SEG1 0
+#define DFX_BASE__INST4_SEG2 0
+#define DFX_BASE__INST4_SEG3 0
+#define DFX_BASE__INST4_SEG4 0
+
+#define ISP_BASE__INST0_SEG0 0x00018000
+#define ISP_BASE__INST0_SEG1 0
+#define ISP_BASE__INST0_SEG2 0
+#define ISP_BASE__INST0_SEG3 0
+#define ISP_BASE__INST0_SEG4 0
+
+#define ISP_BASE__INST1_SEG0 0
+#define ISP_BASE__INST1_SEG1 0
+#define ISP_BASE__INST1_SEG2 0
+#define ISP_BASE__INST1_SEG3 0
+#define ISP_BASE__INST1_SEG4 0
+
+#define ISP_BASE__INST2_SEG0 0
+#define ISP_BASE__INST2_SEG1 0
+#define ISP_BASE__INST2_SEG2 0
+#define ISP_BASE__INST2_SEG3 0
+#define ISP_BASE__INST2_SEG4 0
+
+#define ISP_BASE__INST3_SEG0 0
+#define ISP_BASE__INST3_SEG1 0
+#define ISP_BASE__INST3_SEG2 0
+#define ISP_BASE__INST3_SEG3 0
+#define ISP_BASE__INST3_SEG4 0
+
+#define ISP_BASE__INST4_SEG0 0
+#define ISP_BASE__INST4_SEG1 0
+#define ISP_BASE__INST4_SEG2 0
+#define ISP_BASE__INST4_SEG3 0
+#define ISP_BASE__INST4_SEG4 0
+
+#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
+#define SYSTEMHUB_BASE__INST0_SEG1 0
+#define SYSTEMHUB_BASE__INST0_SEG2 0
+#define SYSTEMHUB_BASE__INST0_SEG3 0
+#define SYSTEMHUB_BASE__INST0_SEG4 0
+
+#define SYSTEMHUB_BASE__INST1_SEG0 0
+#define SYSTEMHUB_BASE__INST1_SEG1 0
+#define SYSTEMHUB_BASE__INST1_SEG2 0
+#define SYSTEMHUB_BASE__INST1_SEG3 0
+#define SYSTEMHUB_BASE__INST1_SEG4 0
+
+#define SYSTEMHUB_BASE__INST2_SEG0 0
+#define SYSTEMHUB_BASE__INST2_SEG1 0
+#define SYSTEMHUB_BASE__INST2_SEG2 0
+#define SYSTEMHUB_BASE__INST2_SEG3 0
+#define SYSTEMHUB_BASE__INST2_SEG4 0
+
+#define SYSTEMHUB_BASE__INST3_SEG0 0
+#define SYSTEMHUB_BASE__INST3_SEG1 0
+#define SYSTEMHUB_BASE__INST3_SEG2 0
+#define SYSTEMHUB_BASE__INST3_SEG3 0
+#define SYSTEMHUB_BASE__INST3_SEG4 0
+
+#define SYSTEMHUB_BASE__INST4_SEG0 0
+#define SYSTEMHUB_BASE__INST4_SEG1 0
+#define SYSTEMHUB_BASE__INST4_SEG2 0
+#define SYSTEMHUB_BASE__INST4_SEG3 0
+#define SYSTEMHUB_BASE__INST4_SEG4 0
+
+#define L2IMU_BASE__INST0_SEG0 0x00007DC0
+#define L2IMU_BASE__INST0_SEG1 0
+#define L2IMU_BASE__INST0_SEG2 0
+#define L2IMU_BASE__INST0_SEG3 0
+#define L2IMU_BASE__INST0_SEG4 0
+
+#define L2IMU_BASE__INST1_SEG0 0
+#define L2IMU_BASE__INST1_SEG1 0
+#define L2IMU_BASE__INST1_SEG2 0
+#define L2IMU_BASE__INST1_SEG3 0
+#define L2IMU_BASE__INST1_SEG4 0
+
+#define L2IMU_BASE__INST2_SEG0 0
+#define L2IMU_BASE__INST2_SEG1 0
+#define L2IMU_BASE__INST2_SEG2 0
+#define L2IMU_BASE__INST2_SEG3 0
+#define L2IMU_BASE__INST2_SEG4 0
+
+#define L2IMU_BASE__INST3_SEG0 0
+#define L2IMU_BASE__INST3_SEG1 0
+#define L2IMU_BASE__INST3_SEG2 0
+#define L2IMU_BASE__INST3_SEG3 0
+#define L2IMU_BASE__INST3_SEG4 0
+
+#define L2IMU_BASE__INST4_SEG0 0
+#define L2IMU_BASE__INST4_SEG1 0
+#define L2IMU_BASE__INST4_SEG2 0
+#define L2IMU_BASE__INST4_SEG3 0
+#define L2IMU_BASE__INST4_SEG4 0
+
+#define IOHC_BASE__INST0_SEG0 0x00010000
+#define IOHC_BASE__INST0_SEG1 0
+#define IOHC_BASE__INST0_SEG2 0
+#define IOHC_BASE__INST0_SEG3 0
+#define IOHC_BASE__INST0_SEG4 0
+
+#define IOHC_BASE__INST1_SEG0 0
+#define IOHC_BASE__INST1_SEG1 0
+#define IOHC_BASE__INST1_SEG2 0
+#define IOHC_BASE__INST1_SEG3 0
+#define IOHC_BASE__INST1_SEG4 0
+
+#define IOHC_BASE__INST2_SEG0 0
+#define IOHC_BASE__INST2_SEG1 0
+#define IOHC_BASE__INST2_SEG2 0
+#define IOHC_BASE__INST2_SEG3 0
+#define IOHC_BASE__INST2_SEG4 0
+
+#define IOHC_BASE__INST3_SEG0 0
+#define IOHC_BASE__INST3_SEG1 0
+#define IOHC_BASE__INST3_SEG2 0
+#define IOHC_BASE__INST3_SEG3 0
+#define IOHC_BASE__INST3_SEG4 0
+
+#define IOHC_BASE__INST4_SEG0 0
+#define IOHC_BASE__INST4_SEG1 0
+#define IOHC_BASE__INST4_SEG2 0
+#define IOHC_BASE__INST4_SEG3 0
+#define IOHC_BASE__INST4_SEG4 0
+
+#define ATHUB_BASE__INST0_SEG0 0x00000C20
+#define ATHUB_BASE__INST0_SEG1 0
+#define ATHUB_BASE__INST0_SEG2 0
+#define ATHUB_BASE__INST0_SEG3 0
+#define ATHUB_BASE__INST0_SEG4 0
+
+#define ATHUB_BASE__INST1_SEG0 0
+#define ATHUB_BASE__INST1_SEG1 0
+#define ATHUB_BASE__INST1_SEG2 0
+#define ATHUB_BASE__INST1_SEG3 0
+#define ATHUB_BASE__INST1_SEG4 0
+
+#define ATHUB_BASE__INST2_SEG0 0
+#define ATHUB_BASE__INST2_SEG1 0
+#define ATHUB_BASE__INST2_SEG2 0
+#define ATHUB_BASE__INST2_SEG3 0
+#define ATHUB_BASE__INST2_SEG4 0
+
+#define ATHUB_BASE__INST3_SEG0 0
+#define ATHUB_BASE__INST3_SEG1 0
+#define ATHUB_BASE__INST3_SEG2 0
+#define ATHUB_BASE__INST3_SEG3 0
+#define ATHUB_BASE__INST3_SEG4 0
+
+#define ATHUB_BASE__INST4_SEG0 0
+#define ATHUB_BASE__INST4_SEG1 0
+#define ATHUB_BASE__INST4_SEG2 0
+#define ATHUB_BASE__INST4_SEG3 0
+#define ATHUB_BASE__INST4_SEG4 0
+
+#define VCE_BASE__INST0_SEG0 0x00007E00
+#define VCE_BASE__INST0_SEG1 0x00048800
+#define VCE_BASE__INST0_SEG2 0
+#define VCE_BASE__INST0_SEG3 0
+#define VCE_BASE__INST0_SEG4 0
+
+#define VCE_BASE__INST1_SEG0 0
+#define VCE_BASE__INST1_SEG1 0
+#define VCE_BASE__INST1_SEG2 0
+#define VCE_BASE__INST1_SEG3 0
+#define VCE_BASE__INST1_SEG4 0
+
+#define VCE_BASE__INST2_SEG0 0
+#define VCE_BASE__INST2_SEG1 0
+#define VCE_BASE__INST2_SEG2 0
+#define VCE_BASE__INST2_SEG3 0
+#define VCE_BASE__INST2_SEG4 0
+
+#define VCE_BASE__INST3_SEG0 0
+#define VCE_BASE__INST3_SEG1 0
+#define VCE_BASE__INST3_SEG2 0
+#define VCE_BASE__INST3_SEG3 0
+#define VCE_BASE__INST3_SEG4 0
+
+#define VCE_BASE__INST4_SEG0 0
+#define VCE_BASE__INST4_SEG1 0
+#define VCE_BASE__INST4_SEG2 0
+#define VCE_BASE__INST4_SEG3 0
+#define VCE_BASE__INST4_SEG4 0
+
+#define GC_BASE__INST0_SEG0 0x00002000
+#define GC_BASE__INST0_SEG1 0x0000A000
+#define GC_BASE__INST0_SEG2 0
+#define GC_BASE__INST0_SEG3 0
+#define GC_BASE__INST0_SEG4 0
+
+#define GC_BASE__INST1_SEG0 0
+#define GC_BASE__INST1_SEG1 0
+#define GC_BASE__INST1_SEG2 0
+#define GC_BASE__INST1_SEG3 0
+#define GC_BASE__INST1_SEG4 0
+
+#define GC_BASE__INST2_SEG0 0
+#define GC_BASE__INST2_SEG1 0
+#define GC_BASE__INST2_SEG2 0
+#define GC_BASE__INST2_SEG3 0
+#define GC_BASE__INST2_SEG4 0
+
+#define GC_BASE__INST3_SEG0 0
+#define GC_BASE__INST3_SEG1 0
+#define GC_BASE__INST3_SEG2 0
+#define GC_BASE__INST3_SEG3 0
+#define GC_BASE__INST3_SEG4 0
+
+#define GC_BASE__INST4_SEG0 0
+#define GC_BASE__INST4_SEG1 0
+#define GC_BASE__INST4_SEG2 0
+#define GC_BASE__INST4_SEG3 0
+#define GC_BASE__INST4_SEG4 0
+
+#define MMHUB_BASE__INST0_SEG0 0x0001A000
+#define MMHUB_BASE__INST0_SEG1 0
+#define MMHUB_BASE__INST0_SEG2 0
+#define MMHUB_BASE__INST0_SEG3 0
+#define MMHUB_BASE__INST0_SEG4 0
+
+#define MMHUB_BASE__INST1_SEG0 0
+#define MMHUB_BASE__INST1_SEG1 0
+#define MMHUB_BASE__INST1_SEG2 0
+#define MMHUB_BASE__INST1_SEG3 0
+#define MMHUB_BASE__INST1_SEG4 0
+
+#define MMHUB_BASE__INST2_SEG0 0
+#define MMHUB_BASE__INST2_SEG1 0
+#define MMHUB_BASE__INST2_SEG2 0
+#define MMHUB_BASE__INST2_SEG3 0
+#define MMHUB_BASE__INST2_SEG4 0
+
+#define MMHUB_BASE__INST3_SEG0 0
+#define MMHUB_BASE__INST3_SEG1 0
+#define MMHUB_BASE__INST3_SEG2 0
+#define MMHUB_BASE__INST3_SEG3 0
+#define MMHUB_BASE__INST3_SEG4 0
+
+#define MMHUB_BASE__INST4_SEG0 0
+#define MMHUB_BASE__INST4_SEG1 0
+#define MMHUB_BASE__INST4_SEG2 0
+#define MMHUB_BASE__INST4_SEG3 0
+#define MMHUB_BASE__INST4_SEG4 0
+
+#define RSMU_BASE__INST0_SEG0 0x00012000
+#define RSMU_BASE__INST0_SEG1 0
+#define RSMU_BASE__INST0_SEG2 0
+#define RSMU_BASE__INST0_SEG3 0
+#define RSMU_BASE__INST0_SEG4 0
+
+#define RSMU_BASE__INST1_SEG0 0
+#define RSMU_BASE__INST1_SEG1 0
+#define RSMU_BASE__INST1_SEG2 0
+#define RSMU_BASE__INST1_SEG3 0
+#define RSMU_BASE__INST1_SEG4 0
+
+#define RSMU_BASE__INST2_SEG0 0
+#define RSMU_BASE__INST2_SEG1 0
+#define RSMU_BASE__INST2_SEG2 0
+#define RSMU_BASE__INST2_SEG3 0
+#define RSMU_BASE__INST2_SEG4 0
+
+#define RSMU_BASE__INST3_SEG0 0
+#define RSMU_BASE__INST3_SEG1 0
+#define RSMU_BASE__INST3_SEG2 0
+#define RSMU_BASE__INST3_SEG3 0
+#define RSMU_BASE__INST3_SEG4 0
+
+#define RSMU_BASE__INST4_SEG0 0
+#define RSMU_BASE__INST4_SEG1 0
+#define RSMU_BASE__INST4_SEG2 0
+#define RSMU_BASE__INST4_SEG3 0
+#define RSMU_BASE__INST4_SEG4 0
+
+#define HDP_BASE__INST0_SEG0 0x00000F20
+#define HDP_BASE__INST0_SEG1 0
+#define HDP_BASE__INST0_SEG2 0
+#define HDP_BASE__INST0_SEG3 0
+#define HDP_BASE__INST0_SEG4 0
+
+#define HDP_BASE__INST1_SEG0 0
+#define HDP_BASE__INST1_SEG1 0
+#define HDP_BASE__INST1_SEG2 0
+#define HDP_BASE__INST1_SEG3 0
+#define HDP_BASE__INST1_SEG4 0
+
+#define HDP_BASE__INST2_SEG0 0
+#define HDP_BASE__INST2_SEG1 0
+#define HDP_BASE__INST2_SEG2 0
+#define HDP_BASE__INST2_SEG3 0
+#define HDP_BASE__INST2_SEG4 0
+
+#define HDP_BASE__INST3_SEG0 0
+#define HDP_BASE__INST3_SEG1 0
+#define HDP_BASE__INST3_SEG2 0
+#define HDP_BASE__INST3_SEG3 0
+#define HDP_BASE__INST3_SEG4 0
+
+#define HDP_BASE__INST4_SEG0 0
+#define HDP_BASE__INST4_SEG1 0
+#define HDP_BASE__INST4_SEG2 0
+#define HDP_BASE__INST4_SEG3 0
+#define HDP_BASE__INST4_SEG4 0
+
+#define OSSSYS_BASE__INST0_SEG0 0x000010A0
+#define OSSSYS_BASE__INST0_SEG1 0
+#define OSSSYS_BASE__INST0_SEG2 0
+#define OSSSYS_BASE__INST0_SEG3 0
+#define OSSSYS_BASE__INST0_SEG4 0
+
+#define OSSSYS_BASE__INST1_SEG0 0
+#define OSSSYS_BASE__INST1_SEG1 0
+#define OSSSYS_BASE__INST1_SEG2 0
+#define OSSSYS_BASE__INST1_SEG3 0
+#define OSSSYS_BASE__INST1_SEG4 0
+
+#define OSSSYS_BASE__INST2_SEG0 0
+#define OSSSYS_BASE__INST2_SEG1 0
+#define OSSSYS_BASE__INST2_SEG2 0
+#define OSSSYS_BASE__INST2_SEG3 0
+#define OSSSYS_BASE__INST2_SEG4 0
+
+#define OSSSYS_BASE__INST3_SEG0 0
+#define OSSSYS_BASE__INST3_SEG1 0
+#define OSSSYS_BASE__INST3_SEG2 0
+#define OSSSYS_BASE__INST3_SEG3 0
+#define OSSSYS_BASE__INST3_SEG4 0
+
+#define OSSSYS_BASE__INST4_SEG0 0
+#define OSSSYS_BASE__INST4_SEG1 0
+#define OSSSYS_BASE__INST4_SEG2 0
+#define OSSSYS_BASE__INST4_SEG3 0
+#define OSSSYS_BASE__INST4_SEG4 0
+
+#define SDMA0_BASE__INST0_SEG0 0x00001260
+#define SDMA0_BASE__INST0_SEG1 0
+#define SDMA0_BASE__INST0_SEG2 0
+#define SDMA0_BASE__INST0_SEG3 0
+#define SDMA0_BASE__INST0_SEG4 0
+
+#define SDMA0_BASE__INST1_SEG0 0
+#define SDMA0_BASE__INST1_SEG1 0
+#define SDMA0_BASE__INST1_SEG2 0
+#define SDMA0_BASE__INST1_SEG3 0
+#define SDMA0_BASE__INST1_SEG4 0
+
+#define SDMA0_BASE__INST2_SEG0 0
+#define SDMA0_BASE__INST2_SEG1 0
+#define SDMA0_BASE__INST2_SEG2 0
+#define SDMA0_BASE__INST2_SEG3 0
+#define SDMA0_BASE__INST2_SEG4 0
+
+#define SDMA0_BASE__INST3_SEG0 0
+#define SDMA0_BASE__INST3_SEG1 0
+#define SDMA0_BASE__INST3_SEG2 0
+#define SDMA0_BASE__INST3_SEG3 0
+#define SDMA0_BASE__INST3_SEG4 0
+
+#define SDMA0_BASE__INST4_SEG0 0
+#define SDMA0_BASE__INST4_SEG1 0
+#define SDMA0_BASE__INST4_SEG2 0
+#define SDMA0_BASE__INST4_SEG3 0
+#define SDMA0_BASE__INST4_SEG4 0
+
+#define SDMA1_BASE__INST0_SEG0 0x00001460
+#define SDMA1_BASE__INST0_SEG1 0
+#define SDMA1_BASE__INST0_SEG2 0
+#define SDMA1_BASE__INST0_SEG3 0
+#define SDMA1_BASE__INST0_SEG4 0
+
+#define SDMA1_BASE__INST1_SEG0 0
+#define SDMA1_BASE__INST1_SEG1 0
+#define SDMA1_BASE__INST1_SEG2 0
+#define SDMA1_BASE__INST1_SEG3 0
+#define SDMA1_BASE__INST1_SEG4 0
+
+#define SDMA1_BASE__INST2_SEG0 0
+#define SDMA1_BASE__INST2_SEG1 0
+#define SDMA1_BASE__INST2_SEG2 0
+#define SDMA1_BASE__INST2_SEG3 0
+#define SDMA1_BASE__INST2_SEG4 0
+
+#define SDMA1_BASE__INST3_SEG0 0
+#define SDMA1_BASE__INST3_SEG1 0
+#define SDMA1_BASE__INST3_SEG2 0
+#define SDMA1_BASE__INST3_SEG3 0
+#define SDMA1_BASE__INST3_SEG4 0
+
+#define SDMA1_BASE__INST4_SEG0 0
+#define SDMA1_BASE__INST4_SEG1 0
+#define SDMA1_BASE__INST4_SEG2 0
+#define SDMA1_BASE__INST4_SEG3 0
+#define SDMA1_BASE__INST4_SEG4 0
+
+#define XDMA_BASE__INST0_SEG0 0x00003400
+#define XDMA_BASE__INST0_SEG1 0
+#define XDMA_BASE__INST0_SEG2 0
+#define XDMA_BASE__INST0_SEG3 0
+#define XDMA_BASE__INST0_SEG4 0
+
+#define XDMA_BASE__INST1_SEG0 0
+#define XDMA_BASE__INST1_SEG1 0
+#define XDMA_BASE__INST1_SEG2 0
+#define XDMA_BASE__INST1_SEG3 0
+#define XDMA_BASE__INST1_SEG4 0
+
+#define XDMA_BASE__INST2_SEG0 0
+#define XDMA_BASE__INST2_SEG1 0
+#define XDMA_BASE__INST2_SEG2 0
+#define XDMA_BASE__INST2_SEG3 0
+#define XDMA_BASE__INST2_SEG4 0
+
+#define XDMA_BASE__INST3_SEG0 0
+#define XDMA_BASE__INST3_SEG1 0
+#define XDMA_BASE__INST3_SEG2 0
+#define XDMA_BASE__INST3_SEG3 0
+#define XDMA_BASE__INST3_SEG4 0
+
+#define XDMA_BASE__INST4_SEG0 0
+#define XDMA_BASE__INST4_SEG1 0
+#define XDMA_BASE__INST4_SEG2 0
+#define XDMA_BASE__INST4_SEG3 0
+#define XDMA_BASE__INST4_SEG4 0
+
+#define UMC_BASE__INST0_SEG0 0x00014000
+#define UMC_BASE__INST0_SEG1 0
+#define UMC_BASE__INST0_SEG2 0
+#define UMC_BASE__INST0_SEG3 0
+#define UMC_BASE__INST0_SEG4 0
+
+#define UMC_BASE__INST1_SEG0 0
+#define UMC_BASE__INST1_SEG1 0
+#define UMC_BASE__INST1_SEG2 0
+#define UMC_BASE__INST1_SEG3 0
+#define UMC_BASE__INST1_SEG4 0
+
+#define UMC_BASE__INST2_SEG0 0
+#define UMC_BASE__INST2_SEG1 0
+#define UMC_BASE__INST2_SEG2 0
+#define UMC_BASE__INST2_SEG3 0
+#define UMC_BASE__INST2_SEG4 0
+
+#define UMC_BASE__INST3_SEG0 0
+#define UMC_BASE__INST3_SEG1 0
+#define UMC_BASE__INST3_SEG2 0
+#define UMC_BASE__INST3_SEG3 0
+#define UMC_BASE__INST3_SEG4 0
+
+#define UMC_BASE__INST4_SEG0 0
+#define UMC_BASE__INST4_SEG1 0
+#define UMC_BASE__INST4_SEG2 0
+#define UMC_BASE__INST4_SEG3 0
+#define UMC_BASE__INST4_SEG4 0
+
+#define THM_BASE__INST0_SEG0 0x00016600
+#define THM_BASE__INST0_SEG1 0
+#define THM_BASE__INST0_SEG2 0
+#define THM_BASE__INST0_SEG3 0
+#define THM_BASE__INST0_SEG4 0
+
+#define THM_BASE__INST1_SEG0 0
+#define THM_BASE__INST1_SEG1 0
+#define THM_BASE__INST1_SEG2 0
+#define THM_BASE__INST1_SEG3 0
+#define THM_BASE__INST1_SEG4 0
+
+#define THM_BASE__INST2_SEG0 0
+#define THM_BASE__INST2_SEG1 0
+#define THM_BASE__INST2_SEG2 0
+#define THM_BASE__INST2_SEG3 0
+#define THM_BASE__INST2_SEG4 0
+
+#define THM_BASE__INST3_SEG0 0
+#define THM_BASE__INST3_SEG1 0
+#define THM_BASE__INST3_SEG2 0
+#define THM_BASE__INST3_SEG3 0
+#define THM_BASE__INST3_SEG4 0
+
+#define THM_BASE__INST4_SEG0 0
+#define THM_BASE__INST4_SEG1 0
+#define THM_BASE__INST4_SEG2 0
+#define THM_BASE__INST4_SEG3 0
+#define THM_BASE__INST4_SEG4 0
+
+#define SMUIO_BASE__INST0_SEG0 0x00016800
+#define SMUIO_BASE__INST0_SEG1 0
+#define SMUIO_BASE__INST0_SEG2 0
+#define SMUIO_BASE__INST0_SEG3 0
+#define SMUIO_BASE__INST0_SEG4 0
+
+#define SMUIO_BASE__INST1_SEG0 0
+#define SMUIO_BASE__INST1_SEG1 0
+#define SMUIO_BASE__INST1_SEG2 0
+#define SMUIO_BASE__INST1_SEG3 0
+#define SMUIO_BASE__INST1_SEG4 0
+
+#define SMUIO_BASE__INST2_SEG0 0
+#define SMUIO_BASE__INST2_SEG1 0
+#define SMUIO_BASE__INST2_SEG2 0
+#define SMUIO_BASE__INST2_SEG3 0
+#define SMUIO_BASE__INST2_SEG4 0
+
+#define SMUIO_BASE__INST3_SEG0 0
+#define SMUIO_BASE__INST3_SEG1 0
+#define SMUIO_BASE__INST3_SEG2 0
+#define SMUIO_BASE__INST3_SEG3 0
+#define SMUIO_BASE__INST3_SEG4 0
+
+#define SMUIO_BASE__INST4_SEG0 0
+#define SMUIO_BASE__INST4_SEG1 0
+#define SMUIO_BASE__INST4_SEG2 0
+#define SMUIO_BASE__INST4_SEG3 0
+#define SMUIO_BASE__INST4_SEG4 0
+
+#define PWR_BASE__INST0_SEG0 0x00016A00
+#define PWR_BASE__INST0_SEG1 0
+#define PWR_BASE__INST0_SEG2 0
+#define PWR_BASE__INST0_SEG3 0
+#define PWR_BASE__INST0_SEG4 0
+
+#define PWR_BASE__INST1_SEG0 0
+#define PWR_BASE__INST1_SEG1 0
+#define PWR_BASE__INST1_SEG2 0
+#define PWR_BASE__INST1_SEG3 0
+#define PWR_BASE__INST1_SEG4 0
+
+#define PWR_BASE__INST2_SEG0 0
+#define PWR_BASE__INST2_SEG1 0
+#define PWR_BASE__INST2_SEG2 0
+#define PWR_BASE__INST2_SEG3 0
+#define PWR_BASE__INST2_SEG4 0
+
+#define PWR_BASE__INST3_SEG0 0
+#define PWR_BASE__INST3_SEG1 0
+#define PWR_BASE__INST3_SEG2 0
+#define PWR_BASE__INST3_SEG3 0
+#define PWR_BASE__INST3_SEG4 0
+
+#define PWR_BASE__INST4_SEG0 0
+#define PWR_BASE__INST4_SEG1 0
+#define PWR_BASE__INST4_SEG2 0
+#define PWR_BASE__INST4_SEG3 0
+#define PWR_BASE__INST4_SEG4 0
+
+#define CLK_BASE__INST0_SEG0 0x00016C00
+#define CLK_BASE__INST0_SEG1 0
+#define CLK_BASE__INST0_SEG2 0
+#define CLK_BASE__INST0_SEG3 0
+#define CLK_BASE__INST0_SEG4 0
+
+#define CLK_BASE__INST1_SEG0 0x00016E00
+#define CLK_BASE__INST1_SEG1 0
+#define CLK_BASE__INST1_SEG2 0
+#define CLK_BASE__INST1_SEG3 0
+#define CLK_BASE__INST1_SEG4 0
+
+#define CLK_BASE__INST2_SEG0 0x00017000
+#define CLK_BASE__INST2_SEG1 0
+#define CLK_BASE__INST2_SEG2 0
+#define CLK_BASE__INST2_SEG3 0
+#define CLK_BASE__INST2_SEG4 0
+
+#define CLK_BASE__INST3_SEG0 0x00017200
+#define CLK_BASE__INST3_SEG1 0
+#define CLK_BASE__INST3_SEG2 0
+#define CLK_BASE__INST3_SEG3 0
+#define CLK_BASE__INST3_SEG4 0
+
+#define CLK_BASE__INST4_SEG0 0x00017E00
+#define CLK_BASE__INST4_SEG1 0
+#define CLK_BASE__INST4_SEG2 0
+#define CLK_BASE__INST4_SEG3 0
+#define CLK_BASE__INST4_SEG4 0
+
+#define FUSE_BASE__INST0_SEG0 0x00017400
+#define FUSE_BASE__INST0_SEG1 0
+#define FUSE_BASE__INST0_SEG2 0
+#define FUSE_BASE__INST0_SEG3 0
+#define FUSE_BASE__INST0_SEG4 0
+
+#define FUSE_BASE__INST1_SEG0 0
+#define FUSE_BASE__INST1_SEG1 0
+#define FUSE_BASE__INST1_SEG2 0
+#define FUSE_BASE__INST1_SEG3 0
+#define FUSE_BASE__INST1_SEG4 0
+
+#define FUSE_BASE__INST2_SEG0 0
+#define FUSE_BASE__INST2_SEG1 0
+#define FUSE_BASE__INST2_SEG2 0
+#define FUSE_BASE__INST2_SEG3 0
+#define FUSE_BASE__INST2_SEG4 0
+
+#define FUSE_BASE__INST3_SEG0 0
+#define FUSE_BASE__INST3_SEG1 0
+#define FUSE_BASE__INST3_SEG2 0
+#define FUSE_BASE__INST3_SEG3 0
+#define FUSE_BASE__INST3_SEG4 0
+
+#define FUSE_BASE__INST4_SEG0 0
+#define FUSE_BASE__INST4_SEG1 0
+#define FUSE_BASE__INST4_SEG2 0
+#define FUSE_BASE__INST4_SEG3 0
+#define FUSE_BASE__INST4_SEG4 0
+
+
+#endif
+
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread[parent not found: <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org> @ 2017-11-27 18:54 ` Tom St Denis [not found] ` <a831909b-4381-1a63-fba3-0eb816fa5e61-5C7GfCeVMHo@public.gmane.org> 2017-11-27 19:17 ` Christian König 1 sibling, 1 reply; 14+ messages in thread From: Tom St Denis @ 2017-11-27 18:54 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW On 27/11/17 01:30 PM, Shaoyun Liu wrote: > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> > --- > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++ > 1 file changed, 1248 insertions(+) > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > new file mode 100644 > index 0000000..76cb748 > --- /dev/null > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > @@ -0,0 +1,1248 @@ > +#ifndef _ip_offset_1_HEADER > +#define _ip_offset_1_HEADER > + > +#define MAX_INSTANCE 5 > +#define MAX_SEGMENT 5 > + > + > +struct IP_BASE_INSTANCE > +{ > + unsigned int segment[MAX_SEGMENT]; > +}; > + > +struct IP_BASE > +{ > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; > +}; > + > + > +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, > + { { 0x00016E00, 0, 0, 0, 0 } }, > + { { 0x00017000, 0, 0, 0, 0 } }, > + { { 0x00017200, 0, 0, 0, 0 } }, > + { { 0x00017E00, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; Since these are likely to be ASIC specific wouldn't it make more sense to organize these as one global struct/array per asic instead? Variables like FUSE_BASE don't take into account that future ASICs might also have a FUSE IP block but with different offsets. > + > + > +#define NBIF_BASE__INST0_SEG0 0x00000000 > +#define NBIF_BASE__INST0_SEG1 0x00000014 > +#define NBIF_BASE__INST0_SEG2 0x00000D20 > +#define NBIF_BASE__INST0_SEG3 0x00010400 > +#define NBIF_BASE__INST0_SEG4 0 If we have the arrays above why keep these? At the very least the two should be intertwined so changing one changes the other (if we don't drop the define blocks). Tom > + > +#define NBIF_BASE__INST1_SEG0 0 > +#define NBIF_BASE__INST1_SEG1 0 > +#define NBIF_BASE__INST1_SEG2 0 > +#define NBIF_BASE__INST1_SEG3 0 > +#define NBIF_BASE__INST1_SEG4 0 > + > +#define NBIF_BASE__INST2_SEG0 0 > +#define NBIF_BASE__INST2_SEG1 0 > +#define NBIF_BASE__INST2_SEG2 0 > +#define NBIF_BASE__INST2_SEG3 0 > +#define NBIF_BASE__INST2_SEG4 0 > + > +#define NBIF_BASE__INST3_SEG0 0 > +#define NBIF_BASE__INST3_SEG1 0 > +#define NBIF_BASE__INST3_SEG2 0 > +#define NBIF_BASE__INST3_SEG3 0 > +#define NBIF_BASE__INST3_SEG4 0 > + > +#define NBIF_BASE__INST4_SEG0 0 > +#define NBIF_BASE__INST4_SEG1 0 > +#define NBIF_BASE__INST4_SEG2 0 > +#define NBIF_BASE__INST4_SEG3 0 > +#define NBIF_BASE__INST4_SEG4 0 > + > +#define NBIO_BASE__INST0_SEG0 0x00000000 > +#define NBIO_BASE__INST0_SEG1 0x00000014 > +#define NBIO_BASE__INST0_SEG2 0x00000D20 > +#define NBIO_BASE__INST0_SEG3 0x00010400 > +#define NBIO_BASE__INST0_SEG4 0 > + > +#define NBIO_BASE__INST1_SEG0 0 > +#define NBIO_BASE__INST1_SEG1 0 > +#define NBIO_BASE__INST1_SEG2 0 > +#define NBIO_BASE__INST1_SEG3 0 > +#define NBIO_BASE__INST1_SEG4 0 > + > +#define NBIO_BASE__INST2_SEG0 0 > +#define NBIO_BASE__INST2_SEG1 0 > +#define NBIO_BASE__INST2_SEG2 0 > +#define NBIO_BASE__INST2_SEG3 0 > +#define NBIO_BASE__INST2_SEG4 0 > + > +#define NBIO_BASE__INST3_SEG0 0 > +#define NBIO_BASE__INST3_SEG1 0 > +#define NBIO_BASE__INST3_SEG2 0 > +#define NBIO_BASE__INST3_SEG3 0 > +#define NBIO_BASE__INST3_SEG4 0 > + > +#define NBIO_BASE__INST4_SEG0 0 > +#define NBIO_BASE__INST4_SEG1 0 > +#define NBIO_BASE__INST4_SEG2 0 > +#define NBIO_BASE__INST4_SEG3 0 > +#define NBIO_BASE__INST4_SEG4 0 > + > +#define DCE_BASE__INST0_SEG0 0x00000012 > +#define DCE_BASE__INST0_SEG1 0x000000C0 > +#define DCE_BASE__INST0_SEG2 0x000034C0 > +#define DCE_BASE__INST0_SEG3 0 > +#define DCE_BASE__INST0_SEG4 0 > + > +#define DCE_BASE__INST1_SEG0 0 > +#define DCE_BASE__INST1_SEG1 0 > +#define DCE_BASE__INST1_SEG2 0 > +#define DCE_BASE__INST1_SEG3 0 > +#define DCE_BASE__INST1_SEG4 0 > + > +#define DCE_BASE__INST2_SEG0 0 > +#define DCE_BASE__INST2_SEG1 0 > +#define DCE_BASE__INST2_SEG2 0 > +#define DCE_BASE__INST2_SEG3 0 > +#define DCE_BASE__INST2_SEG4 0 > + > +#define DCE_BASE__INST3_SEG0 0 > +#define DCE_BASE__INST3_SEG1 0 > +#define DCE_BASE__INST3_SEG2 0 > +#define DCE_BASE__INST3_SEG3 0 > +#define DCE_BASE__INST3_SEG4 0 > + > +#define DCE_BASE__INST4_SEG0 0 > +#define DCE_BASE__INST4_SEG1 0 > +#define DCE_BASE__INST4_SEG2 0 > +#define DCE_BASE__INST4_SEG3 0 > +#define DCE_BASE__INST4_SEG4 0 > + > +#define DCN_BASE__INST0_SEG0 0x00000012 > +#define DCN_BASE__INST0_SEG1 0x000000C0 > +#define DCN_BASE__INST0_SEG2 0x000034C0 > +#define DCN_BASE__INST0_SEG3 0 > +#define DCN_BASE__INST0_SEG4 0 > + > +#define DCN_BASE__INST1_SEG0 0 > +#define DCN_BASE__INST1_SEG1 0 > +#define DCN_BASE__INST1_SEG2 0 > +#define DCN_BASE__INST1_SEG3 0 > +#define DCN_BASE__INST1_SEG4 0 > + > +#define DCN_BASE__INST2_SEG0 0 > +#define DCN_BASE__INST2_SEG1 0 > +#define DCN_BASE__INST2_SEG2 0 > +#define DCN_BASE__INST2_SEG3 0 > +#define DCN_BASE__INST2_SEG4 0 > + > +#define DCN_BASE__INST3_SEG0 0 > +#define DCN_BASE__INST3_SEG1 0 > +#define DCN_BASE__INST3_SEG2 0 > +#define DCN_BASE__INST3_SEG3 0 > +#define DCN_BASE__INST3_SEG4 0 > + > +#define DCN_BASE__INST4_SEG0 0 > +#define DCN_BASE__INST4_SEG1 0 > +#define DCN_BASE__INST4_SEG2 0 > +#define DCN_BASE__INST4_SEG3 0 > +#define DCN_BASE__INST4_SEG4 0 > + > +#define MP0_BASE__INST0_SEG0 0x00016000 > +#define MP0_BASE__INST0_SEG1 0 > +#define MP0_BASE__INST0_SEG2 0 > +#define MP0_BASE__INST0_SEG3 0 > +#define MP0_BASE__INST0_SEG4 0 > + > +#define MP0_BASE__INST1_SEG0 0 > +#define MP0_BASE__INST1_SEG1 0 > +#define MP0_BASE__INST1_SEG2 0 > +#define MP0_BASE__INST1_SEG3 0 > +#define MP0_BASE__INST1_SEG4 0 > + > +#define MP0_BASE__INST2_SEG0 0 > +#define MP0_BASE__INST2_SEG1 0 > +#define MP0_BASE__INST2_SEG2 0 > +#define MP0_BASE__INST2_SEG3 0 > +#define MP0_BASE__INST2_SEG4 0 > + > +#define MP0_BASE__INST3_SEG0 0 > +#define MP0_BASE__INST3_SEG1 0 > +#define MP0_BASE__INST3_SEG2 0 > +#define MP0_BASE__INST3_SEG3 0 > +#define MP0_BASE__INST3_SEG4 0 > + > +#define MP0_BASE__INST4_SEG0 0 > +#define MP0_BASE__INST4_SEG1 0 > +#define MP0_BASE__INST4_SEG2 0 > +#define MP0_BASE__INST4_SEG3 0 > +#define MP0_BASE__INST4_SEG4 0 > + > +#define MP1_BASE__INST0_SEG0 0x00016000 > +#define MP1_BASE__INST0_SEG1 0 > +#define MP1_BASE__INST0_SEG2 0 > +#define MP1_BASE__INST0_SEG3 0 > +#define MP1_BASE__INST0_SEG4 0 > + > +#define MP1_BASE__INST1_SEG0 0 > +#define MP1_BASE__INST1_SEG1 0 > +#define MP1_BASE__INST1_SEG2 0 > +#define MP1_BASE__INST1_SEG3 0 > +#define MP1_BASE__INST1_SEG4 0 > + > +#define MP1_BASE__INST2_SEG0 0 > +#define MP1_BASE__INST2_SEG1 0 > +#define MP1_BASE__INST2_SEG2 0 > +#define MP1_BASE__INST2_SEG3 0 > +#define MP1_BASE__INST2_SEG4 0 > + > +#define MP1_BASE__INST3_SEG0 0 > +#define MP1_BASE__INST3_SEG1 0 > +#define MP1_BASE__INST3_SEG2 0 > +#define MP1_BASE__INST3_SEG3 0 > +#define MP1_BASE__INST3_SEG4 0 > + > +#define MP1_BASE__INST4_SEG0 0 > +#define MP1_BASE__INST4_SEG1 0 > +#define MP1_BASE__INST4_SEG2 0 > +#define MP1_BASE__INST4_SEG3 0 > +#define MP1_BASE__INST4_SEG4 0 > + > +#define MP2_BASE__INST0_SEG0 0x00016000 > +#define MP2_BASE__INST0_SEG1 0 > +#define MP2_BASE__INST0_SEG2 0 > +#define MP2_BASE__INST0_SEG3 0 > +#define MP2_BASE__INST0_SEG4 0 > + > +#define MP2_BASE__INST1_SEG0 0 > +#define MP2_BASE__INST1_SEG1 0 > +#define MP2_BASE__INST1_SEG2 0 > +#define MP2_BASE__INST1_SEG3 0 > +#define MP2_BASE__INST1_SEG4 0 > + > +#define MP2_BASE__INST2_SEG0 0 > +#define MP2_BASE__INST2_SEG1 0 > +#define MP2_BASE__INST2_SEG2 0 > +#define MP2_BASE__INST2_SEG3 0 > +#define MP2_BASE__INST2_SEG4 0 > + > +#define MP2_BASE__INST3_SEG0 0 > +#define MP2_BASE__INST3_SEG1 0 > +#define MP2_BASE__INST3_SEG2 0 > +#define MP2_BASE__INST3_SEG3 0 > +#define MP2_BASE__INST3_SEG4 0 > + > +#define MP2_BASE__INST4_SEG0 0 > +#define MP2_BASE__INST4_SEG1 0 > +#define MP2_BASE__INST4_SEG2 0 > +#define MP2_BASE__INST4_SEG3 0 > +#define MP2_BASE__INST4_SEG4 0 > + > +#define DF_BASE__INST0_SEG0 0x00007000 > +#define DF_BASE__INST0_SEG1 0 > +#define DF_BASE__INST0_SEG2 0 > +#define DF_BASE__INST0_SEG3 0 > +#define DF_BASE__INST0_SEG4 0 > + > +#define DF_BASE__INST1_SEG0 0 > +#define DF_BASE__INST1_SEG1 0 > +#define DF_BASE__INST1_SEG2 0 > +#define DF_BASE__INST1_SEG3 0 > +#define DF_BASE__INST1_SEG4 0 > + > +#define DF_BASE__INST2_SEG0 0 > +#define DF_BASE__INST2_SEG1 0 > +#define DF_BASE__INST2_SEG2 0 > +#define DF_BASE__INST2_SEG3 0 > +#define DF_BASE__INST2_SEG4 0 > + > +#define DF_BASE__INST3_SEG0 0 > +#define DF_BASE__INST3_SEG1 0 > +#define DF_BASE__INST3_SEG2 0 > +#define DF_BASE__INST3_SEG3 0 > +#define DF_BASE__INST3_SEG4 0 > + > +#define DF_BASE__INST4_SEG0 0 > +#define DF_BASE__INST4_SEG1 0 > +#define DF_BASE__INST4_SEG2 0 > +#define DF_BASE__INST4_SEG3 0 > +#define DF_BASE__INST4_SEG4 0 > + > +#define UVD_BASE__INST0_SEG0 0x00007800 > +#define UVD_BASE__INST0_SEG1 0x00007E00 > +#define UVD_BASE__INST0_SEG2 0 > +#define UVD_BASE__INST0_SEG3 0 > +#define UVD_BASE__INST0_SEG4 0 > + > +#define UVD_BASE__INST1_SEG0 0 > +#define UVD_BASE__INST1_SEG1 0 > +#define UVD_BASE__INST1_SEG2 0 > +#define UVD_BASE__INST1_SEG3 0 > +#define UVD_BASE__INST1_SEG4 0 > + > +#define UVD_BASE__INST2_SEG0 0 > +#define UVD_BASE__INST2_SEG1 0 > +#define UVD_BASE__INST2_SEG2 0 > +#define UVD_BASE__INST2_SEG3 0 > +#define UVD_BASE__INST2_SEG4 0 > + > +#define UVD_BASE__INST3_SEG0 0 > +#define UVD_BASE__INST3_SEG1 0 > +#define UVD_BASE__INST3_SEG2 0 > +#define UVD_BASE__INST3_SEG3 0 > +#define UVD_BASE__INST3_SEG4 0 > + > +#define UVD_BASE__INST4_SEG0 0 > +#define UVD_BASE__INST4_SEG1 0 > +#define UVD_BASE__INST4_SEG2 0 > +#define UVD_BASE__INST4_SEG3 0 > +#define UVD_BASE__INST4_SEG4 0 > + > +#define VCN_BASE__INST0_SEG0 0x00007800 > +#define VCN_BASE__INST0_SEG1 0x00007E00 > +#define VCN_BASE__INST0_SEG2 0 > +#define VCN_BASE__INST0_SEG3 0 > +#define VCN_BASE__INST0_SEG4 0 > + > +#define VCN_BASE__INST1_SEG0 0 > +#define VCN_BASE__INST1_SEG1 0 > +#define VCN_BASE__INST1_SEG2 0 > +#define VCN_BASE__INST1_SEG3 0 > +#define VCN_BASE__INST1_SEG4 0 > + > +#define VCN_BASE__INST2_SEG0 0 > +#define VCN_BASE__INST2_SEG1 0 > +#define VCN_BASE__INST2_SEG2 0 > +#define VCN_BASE__INST2_SEG3 0 > +#define VCN_BASE__INST2_SEG4 0 > + > +#define VCN_BASE__INST3_SEG0 0 > +#define VCN_BASE__INST3_SEG1 0 > +#define VCN_BASE__INST3_SEG2 0 > +#define VCN_BASE__INST3_SEG3 0 > +#define VCN_BASE__INST3_SEG4 0 > + > +#define VCN_BASE__INST4_SEG0 0 > +#define VCN_BASE__INST4_SEG1 0 > +#define VCN_BASE__INST4_SEG2 0 > +#define VCN_BASE__INST4_SEG3 0 > +#define VCN_BASE__INST4_SEG4 0 > + > +#define DBGU_BASE__INST0_SEG0 0x00000180 > +#define DBGU_BASE__INST0_SEG1 0x000001A0 > +#define DBGU_BASE__INST0_SEG2 0 > +#define DBGU_BASE__INST0_SEG3 0 > +#define DBGU_BASE__INST0_SEG4 0 > + > +#define DBGU_BASE__INST1_SEG0 0 > +#define DBGU_BASE__INST1_SEG1 0 > +#define DBGU_BASE__INST1_SEG2 0 > +#define DBGU_BASE__INST1_SEG3 0 > +#define DBGU_BASE__INST1_SEG4 0 > + > +#define DBGU_BASE__INST2_SEG0 0 > +#define DBGU_BASE__INST2_SEG1 0 > +#define DBGU_BASE__INST2_SEG2 0 > +#define DBGU_BASE__INST2_SEG3 0 > +#define DBGU_BASE__INST2_SEG4 0 > + > +#define DBGU_BASE__INST3_SEG0 0 > +#define DBGU_BASE__INST3_SEG1 0 > +#define DBGU_BASE__INST3_SEG2 0 > +#define DBGU_BASE__INST3_SEG3 0 > +#define DBGU_BASE__INST3_SEG4 0 > + > +#define DBGU_BASE__INST4_SEG0 0 > +#define DBGU_BASE__INST4_SEG1 0 > +#define DBGU_BASE__INST4_SEG2 0 > +#define DBGU_BASE__INST4_SEG3 0 > +#define DBGU_BASE__INST4_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 > +#define DBGU_NBIO_BASE__INST0_SEG1 0 > +#define DBGU_NBIO_BASE__INST0_SEG2 0 > +#define DBGU_NBIO_BASE__INST0_SEG3 0 > +#define DBGU_NBIO_BASE__INST0_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST1_SEG0 0 > +#define DBGU_NBIO_BASE__INST1_SEG1 0 > +#define DBGU_NBIO_BASE__INST1_SEG2 0 > +#define DBGU_NBIO_BASE__INST1_SEG3 0 > +#define DBGU_NBIO_BASE__INST1_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST2_SEG0 0 > +#define DBGU_NBIO_BASE__INST2_SEG1 0 > +#define DBGU_NBIO_BASE__INST2_SEG2 0 > +#define DBGU_NBIO_BASE__INST2_SEG3 0 > +#define DBGU_NBIO_BASE__INST2_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST3_SEG0 0 > +#define DBGU_NBIO_BASE__INST3_SEG1 0 > +#define DBGU_NBIO_BASE__INST3_SEG2 0 > +#define DBGU_NBIO_BASE__INST3_SEG3 0 > +#define DBGU_NBIO_BASE__INST3_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST4_SEG0 0 > +#define DBGU_NBIO_BASE__INST4_SEG1 0 > +#define DBGU_NBIO_BASE__INST4_SEG2 0 > +#define DBGU_NBIO_BASE__INST4_SEG3 0 > +#define DBGU_NBIO_BASE__INST4_SEG4 0 > + > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 > +#define DBGU_IO_BASE__INST0_SEG1 0 > +#define DBGU_IO_BASE__INST0_SEG2 0 > +#define DBGU_IO_BASE__INST0_SEG3 0 > +#define DBGU_IO_BASE__INST0_SEG4 0 > + > +#define DBGU_IO_BASE__INST1_SEG0 0 > +#define DBGU_IO_BASE__INST1_SEG1 0 > +#define DBGU_IO_BASE__INST1_SEG2 0 > +#define DBGU_IO_BASE__INST1_SEG3 0 > +#define DBGU_IO_BASE__INST1_SEG4 0 > + > +#define DBGU_IO_BASE__INST2_SEG0 0 > +#define DBGU_IO_BASE__INST2_SEG1 0 > +#define DBGU_IO_BASE__INST2_SEG2 0 > +#define DBGU_IO_BASE__INST2_SEG3 0 > +#define DBGU_IO_BASE__INST2_SEG4 0 > + > +#define DBGU_IO_BASE__INST3_SEG0 0 > +#define DBGU_IO_BASE__INST3_SEG1 0 > +#define DBGU_IO_BASE__INST3_SEG2 0 > +#define DBGU_IO_BASE__INST3_SEG3 0 > +#define DBGU_IO_BASE__INST3_SEG4 0 > + > +#define DBGU_IO_BASE__INST4_SEG0 0 > +#define DBGU_IO_BASE__INST4_SEG1 0 > +#define DBGU_IO_BASE__INST4_SEG2 0 > +#define DBGU_IO_BASE__INST4_SEG3 0 > +#define DBGU_IO_BASE__INST4_SEG4 0 > + > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 > +#define DFX_DAP_BASE__INST0_SEG1 0 > +#define DFX_DAP_BASE__INST0_SEG2 0 > +#define DFX_DAP_BASE__INST0_SEG3 0 > +#define DFX_DAP_BASE__INST0_SEG4 0 > + > +#define DFX_DAP_BASE__INST1_SEG0 0 > +#define DFX_DAP_BASE__INST1_SEG1 0 > +#define DFX_DAP_BASE__INST1_SEG2 0 > +#define DFX_DAP_BASE__INST1_SEG3 0 > +#define DFX_DAP_BASE__INST1_SEG4 0 > + > +#define DFX_DAP_BASE__INST2_SEG0 0 > +#define DFX_DAP_BASE__INST2_SEG1 0 > +#define DFX_DAP_BASE__INST2_SEG2 0 > +#define DFX_DAP_BASE__INST2_SEG3 0 > +#define DFX_DAP_BASE__INST2_SEG4 0 > + > +#define DFX_DAP_BASE__INST3_SEG0 0 > +#define DFX_DAP_BASE__INST3_SEG1 0 > +#define DFX_DAP_BASE__INST3_SEG2 0 > +#define DFX_DAP_BASE__INST3_SEG3 0 > +#define DFX_DAP_BASE__INST3_SEG4 0 > + > +#define DFX_DAP_BASE__INST4_SEG0 0 > +#define DFX_DAP_BASE__INST4_SEG1 0 > +#define DFX_DAP_BASE__INST4_SEG2 0 > +#define DFX_DAP_BASE__INST4_SEG3 0 > +#define DFX_DAP_BASE__INST4_SEG4 0 > + > +#define DFX_BASE__INST0_SEG0 0x00000580 > +#define DFX_BASE__INST0_SEG1 0 > +#define DFX_BASE__INST0_SEG2 0 > +#define DFX_BASE__INST0_SEG3 0 > +#define DFX_BASE__INST0_SEG4 0 > + > +#define DFX_BASE__INST1_SEG0 0 > +#define DFX_BASE__INST1_SEG1 0 > +#define DFX_BASE__INST1_SEG2 0 > +#define DFX_BASE__INST1_SEG3 0 > +#define DFX_BASE__INST1_SEG4 0 > + > +#define DFX_BASE__INST2_SEG0 0 > +#define DFX_BASE__INST2_SEG1 0 > +#define DFX_BASE__INST2_SEG2 0 > +#define DFX_BASE__INST2_SEG3 0 > +#define DFX_BASE__INST2_SEG4 0 > + > +#define DFX_BASE__INST3_SEG0 0 > +#define DFX_BASE__INST3_SEG1 0 > +#define DFX_BASE__INST3_SEG2 0 > +#define DFX_BASE__INST3_SEG3 0 > +#define DFX_BASE__INST3_SEG4 0 > + > +#define DFX_BASE__INST4_SEG0 0 > +#define DFX_BASE__INST4_SEG1 0 > +#define DFX_BASE__INST4_SEG2 0 > +#define DFX_BASE__INST4_SEG3 0 > +#define DFX_BASE__INST4_SEG4 0 > + > +#define ISP_BASE__INST0_SEG0 0x00018000 > +#define ISP_BASE__INST0_SEG1 0 > +#define ISP_BASE__INST0_SEG2 0 > +#define ISP_BASE__INST0_SEG3 0 > +#define ISP_BASE__INST0_SEG4 0 > + > +#define ISP_BASE__INST1_SEG0 0 > +#define ISP_BASE__INST1_SEG1 0 > +#define ISP_BASE__INST1_SEG2 0 > +#define ISP_BASE__INST1_SEG3 0 > +#define ISP_BASE__INST1_SEG4 0 > + > +#define ISP_BASE__INST2_SEG0 0 > +#define ISP_BASE__INST2_SEG1 0 > +#define ISP_BASE__INST2_SEG2 0 > +#define ISP_BASE__INST2_SEG3 0 > +#define ISP_BASE__INST2_SEG4 0 > + > +#define ISP_BASE__INST3_SEG0 0 > +#define ISP_BASE__INST3_SEG1 0 > +#define ISP_BASE__INST3_SEG2 0 > +#define ISP_BASE__INST3_SEG3 0 > +#define ISP_BASE__INST3_SEG4 0 > + > +#define ISP_BASE__INST4_SEG0 0 > +#define ISP_BASE__INST4_SEG1 0 > +#define ISP_BASE__INST4_SEG2 0 > +#define ISP_BASE__INST4_SEG3 0 > +#define ISP_BASE__INST4_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 > +#define SYSTEMHUB_BASE__INST0_SEG1 0 > +#define SYSTEMHUB_BASE__INST0_SEG2 0 > +#define SYSTEMHUB_BASE__INST0_SEG3 0 > +#define SYSTEMHUB_BASE__INST0_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST1_SEG0 0 > +#define SYSTEMHUB_BASE__INST1_SEG1 0 > +#define SYSTEMHUB_BASE__INST1_SEG2 0 > +#define SYSTEMHUB_BASE__INST1_SEG3 0 > +#define SYSTEMHUB_BASE__INST1_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST2_SEG0 0 > +#define SYSTEMHUB_BASE__INST2_SEG1 0 > +#define SYSTEMHUB_BASE__INST2_SEG2 0 > +#define SYSTEMHUB_BASE__INST2_SEG3 0 > +#define SYSTEMHUB_BASE__INST2_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST3_SEG0 0 > +#define SYSTEMHUB_BASE__INST3_SEG1 0 > +#define SYSTEMHUB_BASE__INST3_SEG2 0 > +#define SYSTEMHUB_BASE__INST3_SEG3 0 > +#define SYSTEMHUB_BASE__INST3_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST4_SEG0 0 > +#define SYSTEMHUB_BASE__INST4_SEG1 0 > +#define SYSTEMHUB_BASE__INST4_SEG2 0 > +#define SYSTEMHUB_BASE__INST4_SEG3 0 > +#define SYSTEMHUB_BASE__INST4_SEG4 0 > + > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 > +#define L2IMU_BASE__INST0_SEG1 0 > +#define L2IMU_BASE__INST0_SEG2 0 > +#define L2IMU_BASE__INST0_SEG3 0 > +#define L2IMU_BASE__INST0_SEG4 0 > + > +#define L2IMU_BASE__INST1_SEG0 0 > +#define L2IMU_BASE__INST1_SEG1 0 > +#define L2IMU_BASE__INST1_SEG2 0 > +#define L2IMU_BASE__INST1_SEG3 0 > +#define L2IMU_BASE__INST1_SEG4 0 > + > +#define L2IMU_BASE__INST2_SEG0 0 > +#define L2IMU_BASE__INST2_SEG1 0 > +#define L2IMU_BASE__INST2_SEG2 0 > +#define L2IMU_BASE__INST2_SEG3 0 > +#define L2IMU_BASE__INST2_SEG4 0 > + > +#define L2IMU_BASE__INST3_SEG0 0 > +#define L2IMU_BASE__INST3_SEG1 0 > +#define L2IMU_BASE__INST3_SEG2 0 > +#define L2IMU_BASE__INST3_SEG3 0 > +#define L2IMU_BASE__INST3_SEG4 0 > + > +#define L2IMU_BASE__INST4_SEG0 0 > +#define L2IMU_BASE__INST4_SEG1 0 > +#define L2IMU_BASE__INST4_SEG2 0 > +#define L2IMU_BASE__INST4_SEG3 0 > +#define L2IMU_BASE__INST4_SEG4 0 > + > +#define IOHC_BASE__INST0_SEG0 0x00010000 > +#define IOHC_BASE__INST0_SEG1 0 > +#define IOHC_BASE__INST0_SEG2 0 > +#define IOHC_BASE__INST0_SEG3 0 > +#define IOHC_BASE__INST0_SEG4 0 > + > +#define IOHC_BASE__INST1_SEG0 0 > +#define IOHC_BASE__INST1_SEG1 0 > +#define IOHC_BASE__INST1_SEG2 0 > +#define IOHC_BASE__INST1_SEG3 0 > +#define IOHC_BASE__INST1_SEG4 0 > + > +#define IOHC_BASE__INST2_SEG0 0 > +#define IOHC_BASE__INST2_SEG1 0 > +#define IOHC_BASE__INST2_SEG2 0 > +#define IOHC_BASE__INST2_SEG3 0 > +#define IOHC_BASE__INST2_SEG4 0 > + > +#define IOHC_BASE__INST3_SEG0 0 > +#define IOHC_BASE__INST3_SEG1 0 > +#define IOHC_BASE__INST3_SEG2 0 > +#define IOHC_BASE__INST3_SEG3 0 > +#define IOHC_BASE__INST3_SEG4 0 > + > +#define IOHC_BASE__INST4_SEG0 0 > +#define IOHC_BASE__INST4_SEG1 0 > +#define IOHC_BASE__INST4_SEG2 0 > +#define IOHC_BASE__INST4_SEG3 0 > +#define IOHC_BASE__INST4_SEG4 0 > + > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 > +#define ATHUB_BASE__INST0_SEG1 0 > +#define ATHUB_BASE__INST0_SEG2 0 > +#define ATHUB_BASE__INST0_SEG3 0 > +#define ATHUB_BASE__INST0_SEG4 0 > + > +#define ATHUB_BASE__INST1_SEG0 0 > +#define ATHUB_BASE__INST1_SEG1 0 > +#define ATHUB_BASE__INST1_SEG2 0 > +#define ATHUB_BASE__INST1_SEG3 0 > +#define ATHUB_BASE__INST1_SEG4 0 > + > +#define ATHUB_BASE__INST2_SEG0 0 > +#define ATHUB_BASE__INST2_SEG1 0 > +#define ATHUB_BASE__INST2_SEG2 0 > +#define ATHUB_BASE__INST2_SEG3 0 > +#define ATHUB_BASE__INST2_SEG4 0 > + > +#define ATHUB_BASE__INST3_SEG0 0 > +#define ATHUB_BASE__INST3_SEG1 0 > +#define ATHUB_BASE__INST3_SEG2 0 > +#define ATHUB_BASE__INST3_SEG3 0 > +#define ATHUB_BASE__INST3_SEG4 0 > + > +#define ATHUB_BASE__INST4_SEG0 0 > +#define ATHUB_BASE__INST4_SEG1 0 > +#define ATHUB_BASE__INST4_SEG2 0 > +#define ATHUB_BASE__INST4_SEG3 0 > +#define ATHUB_BASE__INST4_SEG4 0 > + > +#define VCE_BASE__INST0_SEG0 0x00007E00 > +#define VCE_BASE__INST0_SEG1 0x00048800 > +#define VCE_BASE__INST0_SEG2 0 > +#define VCE_BASE__INST0_SEG3 0 > +#define VCE_BASE__INST0_SEG4 0 > + > +#define VCE_BASE__INST1_SEG0 0 > +#define VCE_BASE__INST1_SEG1 0 > +#define VCE_BASE__INST1_SEG2 0 > +#define VCE_BASE__INST1_SEG3 0 > +#define VCE_BASE__INST1_SEG4 0 > + > +#define VCE_BASE__INST2_SEG0 0 > +#define VCE_BASE__INST2_SEG1 0 > +#define VCE_BASE__INST2_SEG2 0 > +#define VCE_BASE__INST2_SEG3 0 > +#define VCE_BASE__INST2_SEG4 0 > + > +#define VCE_BASE__INST3_SEG0 0 > +#define VCE_BASE__INST3_SEG1 0 > +#define VCE_BASE__INST3_SEG2 0 > +#define VCE_BASE__INST3_SEG3 0 > +#define VCE_BASE__INST3_SEG4 0 > + > +#define VCE_BASE__INST4_SEG0 0 > +#define VCE_BASE__INST4_SEG1 0 > +#define VCE_BASE__INST4_SEG2 0 > +#define VCE_BASE__INST4_SEG3 0 > +#define VCE_BASE__INST4_SEG4 0 > + > +#define GC_BASE__INST0_SEG0 0x00002000 > +#define GC_BASE__INST0_SEG1 0x0000A000 > +#define GC_BASE__INST0_SEG2 0 > +#define GC_BASE__INST0_SEG3 0 > +#define GC_BASE__INST0_SEG4 0 > + > +#define GC_BASE__INST1_SEG0 0 > +#define GC_BASE__INST1_SEG1 0 > +#define GC_BASE__INST1_SEG2 0 > +#define GC_BASE__INST1_SEG3 0 > +#define GC_BASE__INST1_SEG4 0 > + > +#define GC_BASE__INST2_SEG0 0 > +#define GC_BASE__INST2_SEG1 0 > +#define GC_BASE__INST2_SEG2 0 > +#define GC_BASE__INST2_SEG3 0 > +#define GC_BASE__INST2_SEG4 0 > + > +#define GC_BASE__INST3_SEG0 0 > +#define GC_BASE__INST3_SEG1 0 > +#define GC_BASE__INST3_SEG2 0 > +#define GC_BASE__INST3_SEG3 0 > +#define GC_BASE__INST3_SEG4 0 > + > +#define GC_BASE__INST4_SEG0 0 > +#define GC_BASE__INST4_SEG1 0 > +#define GC_BASE__INST4_SEG2 0 > +#define GC_BASE__INST4_SEG3 0 > +#define GC_BASE__INST4_SEG4 0 > + > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 > +#define MMHUB_BASE__INST0_SEG1 0 > +#define MMHUB_BASE__INST0_SEG2 0 > +#define MMHUB_BASE__INST0_SEG3 0 > +#define MMHUB_BASE__INST0_SEG4 0 > + > +#define MMHUB_BASE__INST1_SEG0 0 > +#define MMHUB_BASE__INST1_SEG1 0 > +#define MMHUB_BASE__INST1_SEG2 0 > +#define MMHUB_BASE__INST1_SEG3 0 > +#define MMHUB_BASE__INST1_SEG4 0 > + > +#define MMHUB_BASE__INST2_SEG0 0 > +#define MMHUB_BASE__INST2_SEG1 0 > +#define MMHUB_BASE__INST2_SEG2 0 > +#define MMHUB_BASE__INST2_SEG3 0 > +#define MMHUB_BASE__INST2_SEG4 0 > + > +#define MMHUB_BASE__INST3_SEG0 0 > +#define MMHUB_BASE__INST3_SEG1 0 > +#define MMHUB_BASE__INST3_SEG2 0 > +#define MMHUB_BASE__INST3_SEG3 0 > +#define MMHUB_BASE__INST3_SEG4 0 > + > +#define MMHUB_BASE__INST4_SEG0 0 > +#define MMHUB_BASE__INST4_SEG1 0 > +#define MMHUB_BASE__INST4_SEG2 0 > +#define MMHUB_BASE__INST4_SEG3 0 > +#define MMHUB_BASE__INST4_SEG4 0 > + > +#define RSMU_BASE__INST0_SEG0 0x00012000 > +#define RSMU_BASE__INST0_SEG1 0 > +#define RSMU_BASE__INST0_SEG2 0 > +#define RSMU_BASE__INST0_SEG3 0 > +#define RSMU_BASE__INST0_SEG4 0 > + > +#define RSMU_BASE__INST1_SEG0 0 > +#define RSMU_BASE__INST1_SEG1 0 > +#define RSMU_BASE__INST1_SEG2 0 > +#define RSMU_BASE__INST1_SEG3 0 > +#define RSMU_BASE__INST1_SEG4 0 > + > +#define RSMU_BASE__INST2_SEG0 0 > +#define RSMU_BASE__INST2_SEG1 0 > +#define RSMU_BASE__INST2_SEG2 0 > +#define RSMU_BASE__INST2_SEG3 0 > +#define RSMU_BASE__INST2_SEG4 0 > + > +#define RSMU_BASE__INST3_SEG0 0 > +#define RSMU_BASE__INST3_SEG1 0 > +#define RSMU_BASE__INST3_SEG2 0 > +#define RSMU_BASE__INST3_SEG3 0 > +#define RSMU_BASE__INST3_SEG4 0 > + > +#define RSMU_BASE__INST4_SEG0 0 > +#define RSMU_BASE__INST4_SEG1 0 > +#define RSMU_BASE__INST4_SEG2 0 > +#define RSMU_BASE__INST4_SEG3 0 > +#define RSMU_BASE__INST4_SEG4 0 > + > +#define HDP_BASE__INST0_SEG0 0x00000F20 > +#define HDP_BASE__INST0_SEG1 0 > +#define HDP_BASE__INST0_SEG2 0 > +#define HDP_BASE__INST0_SEG3 0 > +#define HDP_BASE__INST0_SEG4 0 > + > +#define HDP_BASE__INST1_SEG0 0 > +#define HDP_BASE__INST1_SEG1 0 > +#define HDP_BASE__INST1_SEG2 0 > +#define HDP_BASE__INST1_SEG3 0 > +#define HDP_BASE__INST1_SEG4 0 > + > +#define HDP_BASE__INST2_SEG0 0 > +#define HDP_BASE__INST2_SEG1 0 > +#define HDP_BASE__INST2_SEG2 0 > +#define HDP_BASE__INST2_SEG3 0 > +#define HDP_BASE__INST2_SEG4 0 > + > +#define HDP_BASE__INST3_SEG0 0 > +#define HDP_BASE__INST3_SEG1 0 > +#define HDP_BASE__INST3_SEG2 0 > +#define HDP_BASE__INST3_SEG3 0 > +#define HDP_BASE__INST3_SEG4 0 > + > +#define HDP_BASE__INST4_SEG0 0 > +#define HDP_BASE__INST4_SEG1 0 > +#define HDP_BASE__INST4_SEG2 0 > +#define HDP_BASE__INST4_SEG3 0 > +#define HDP_BASE__INST4_SEG4 0 > + > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 > +#define OSSSYS_BASE__INST0_SEG1 0 > +#define OSSSYS_BASE__INST0_SEG2 0 > +#define OSSSYS_BASE__INST0_SEG3 0 > +#define OSSSYS_BASE__INST0_SEG4 0 > + > +#define OSSSYS_BASE__INST1_SEG0 0 > +#define OSSSYS_BASE__INST1_SEG1 0 > +#define OSSSYS_BASE__INST1_SEG2 0 > +#define OSSSYS_BASE__INST1_SEG3 0 > +#define OSSSYS_BASE__INST1_SEG4 0 > + > +#define OSSSYS_BASE__INST2_SEG0 0 > +#define OSSSYS_BASE__INST2_SEG1 0 > +#define OSSSYS_BASE__INST2_SEG2 0 > +#define OSSSYS_BASE__INST2_SEG3 0 > +#define OSSSYS_BASE__INST2_SEG4 0 > + > +#define OSSSYS_BASE__INST3_SEG0 0 > +#define OSSSYS_BASE__INST3_SEG1 0 > +#define OSSSYS_BASE__INST3_SEG2 0 > +#define OSSSYS_BASE__INST3_SEG3 0 > +#define OSSSYS_BASE__INST3_SEG4 0 > + > +#define OSSSYS_BASE__INST4_SEG0 0 > +#define OSSSYS_BASE__INST4_SEG1 0 > +#define OSSSYS_BASE__INST4_SEG2 0 > +#define OSSSYS_BASE__INST4_SEG3 0 > +#define OSSSYS_BASE__INST4_SEG4 0 > + > +#define SDMA0_BASE__INST0_SEG0 0x00001260 > +#define SDMA0_BASE__INST0_SEG1 0 > +#define SDMA0_BASE__INST0_SEG2 0 > +#define SDMA0_BASE__INST0_SEG3 0 > +#define SDMA0_BASE__INST0_SEG4 0 > + > +#define SDMA0_BASE__INST1_SEG0 0 > +#define SDMA0_BASE__INST1_SEG1 0 > +#define SDMA0_BASE__INST1_SEG2 0 > +#define SDMA0_BASE__INST1_SEG3 0 > +#define SDMA0_BASE__INST1_SEG4 0 > + > +#define SDMA0_BASE__INST2_SEG0 0 > +#define SDMA0_BASE__INST2_SEG1 0 > +#define SDMA0_BASE__INST2_SEG2 0 > +#define SDMA0_BASE__INST2_SEG3 0 > +#define SDMA0_BASE__INST2_SEG4 0 > + > +#define SDMA0_BASE__INST3_SEG0 0 > +#define SDMA0_BASE__INST3_SEG1 0 > +#define SDMA0_BASE__INST3_SEG2 0 > +#define SDMA0_BASE__INST3_SEG3 0 > +#define SDMA0_BASE__INST3_SEG4 0 > + > +#define SDMA0_BASE__INST4_SEG0 0 > +#define SDMA0_BASE__INST4_SEG1 0 > +#define SDMA0_BASE__INST4_SEG2 0 > +#define SDMA0_BASE__INST4_SEG3 0 > +#define SDMA0_BASE__INST4_SEG4 0 > + > +#define SDMA1_BASE__INST0_SEG0 0x00001460 > +#define SDMA1_BASE__INST0_SEG1 0 > +#define SDMA1_BASE__INST0_SEG2 0 > +#define SDMA1_BASE__INST0_SEG3 0 > +#define SDMA1_BASE__INST0_SEG4 0 > + > +#define SDMA1_BASE__INST1_SEG0 0 > +#define SDMA1_BASE__INST1_SEG1 0 > +#define SDMA1_BASE__INST1_SEG2 0 > +#define SDMA1_BASE__INST1_SEG3 0 > +#define SDMA1_BASE__INST1_SEG4 0 > + > +#define SDMA1_BASE__INST2_SEG0 0 > +#define SDMA1_BASE__INST2_SEG1 0 > +#define SDMA1_BASE__INST2_SEG2 0 > +#define SDMA1_BASE__INST2_SEG3 0 > +#define SDMA1_BASE__INST2_SEG4 0 > + > +#define SDMA1_BASE__INST3_SEG0 0 > +#define SDMA1_BASE__INST3_SEG1 0 > +#define SDMA1_BASE__INST3_SEG2 0 > +#define SDMA1_BASE__INST3_SEG3 0 > +#define SDMA1_BASE__INST3_SEG4 0 > + > +#define SDMA1_BASE__INST4_SEG0 0 > +#define SDMA1_BASE__INST4_SEG1 0 > +#define SDMA1_BASE__INST4_SEG2 0 > +#define SDMA1_BASE__INST4_SEG3 0 > +#define SDMA1_BASE__INST4_SEG4 0 > + > +#define XDMA_BASE__INST0_SEG0 0x00003400 > +#define XDMA_BASE__INST0_SEG1 0 > +#define XDMA_BASE__INST0_SEG2 0 > +#define XDMA_BASE__INST0_SEG3 0 > +#define XDMA_BASE__INST0_SEG4 0 > + > +#define XDMA_BASE__INST1_SEG0 0 > +#define XDMA_BASE__INST1_SEG1 0 > +#define XDMA_BASE__INST1_SEG2 0 > +#define XDMA_BASE__INST1_SEG3 0 > +#define XDMA_BASE__INST1_SEG4 0 > + > +#define XDMA_BASE__INST2_SEG0 0 > +#define XDMA_BASE__INST2_SEG1 0 > +#define XDMA_BASE__INST2_SEG2 0 > +#define XDMA_BASE__INST2_SEG3 0 > +#define XDMA_BASE__INST2_SEG4 0 > + > +#define XDMA_BASE__INST3_SEG0 0 > +#define XDMA_BASE__INST3_SEG1 0 > +#define XDMA_BASE__INST3_SEG2 0 > +#define XDMA_BASE__INST3_SEG3 0 > +#define XDMA_BASE__INST3_SEG4 0 > + > +#define XDMA_BASE__INST4_SEG0 0 > +#define XDMA_BASE__INST4_SEG1 0 > +#define XDMA_BASE__INST4_SEG2 0 > +#define XDMA_BASE__INST4_SEG3 0 > +#define XDMA_BASE__INST4_SEG4 0 > + > +#define UMC_BASE__INST0_SEG0 0x00014000 > +#define UMC_BASE__INST0_SEG1 0 > +#define UMC_BASE__INST0_SEG2 0 > +#define UMC_BASE__INST0_SEG3 0 > +#define UMC_BASE__INST0_SEG4 0 > + > +#define UMC_BASE__INST1_SEG0 0 > +#define UMC_BASE__INST1_SEG1 0 > +#define UMC_BASE__INST1_SEG2 0 > +#define UMC_BASE__INST1_SEG3 0 > +#define UMC_BASE__INST1_SEG4 0 > + > +#define UMC_BASE__INST2_SEG0 0 > +#define UMC_BASE__INST2_SEG1 0 > +#define UMC_BASE__INST2_SEG2 0 > +#define UMC_BASE__INST2_SEG3 0 > +#define UMC_BASE__INST2_SEG4 0 > + > +#define UMC_BASE__INST3_SEG0 0 > +#define UMC_BASE__INST3_SEG1 0 > +#define UMC_BASE__INST3_SEG2 0 > +#define UMC_BASE__INST3_SEG3 0 > +#define UMC_BASE__INST3_SEG4 0 > + > +#define UMC_BASE__INST4_SEG0 0 > +#define UMC_BASE__INST4_SEG1 0 > +#define UMC_BASE__INST4_SEG2 0 > +#define UMC_BASE__INST4_SEG3 0 > +#define UMC_BASE__INST4_SEG4 0 > + > +#define THM_BASE__INST0_SEG0 0x00016600 > +#define THM_BASE__INST0_SEG1 0 > +#define THM_BASE__INST0_SEG2 0 > +#define THM_BASE__INST0_SEG3 0 > +#define THM_BASE__INST0_SEG4 0 > + > +#define THM_BASE__INST1_SEG0 0 > +#define THM_BASE__INST1_SEG1 0 > +#define THM_BASE__INST1_SEG2 0 > +#define THM_BASE__INST1_SEG3 0 > +#define THM_BASE__INST1_SEG4 0 > + > +#define THM_BASE__INST2_SEG0 0 > +#define THM_BASE__INST2_SEG1 0 > +#define THM_BASE__INST2_SEG2 0 > +#define THM_BASE__INST2_SEG3 0 > +#define THM_BASE__INST2_SEG4 0 > + > +#define THM_BASE__INST3_SEG0 0 > +#define THM_BASE__INST3_SEG1 0 > +#define THM_BASE__INST3_SEG2 0 > +#define THM_BASE__INST3_SEG3 0 > +#define THM_BASE__INST3_SEG4 0 > + > +#define THM_BASE__INST4_SEG0 0 > +#define THM_BASE__INST4_SEG1 0 > +#define THM_BASE__INST4_SEG2 0 > +#define THM_BASE__INST4_SEG3 0 > +#define THM_BASE__INST4_SEG4 0 > + > +#define SMUIO_BASE__INST0_SEG0 0x00016800 > +#define SMUIO_BASE__INST0_SEG1 0 > +#define SMUIO_BASE__INST0_SEG2 0 > +#define SMUIO_BASE__INST0_SEG3 0 > +#define SMUIO_BASE__INST0_SEG4 0 > + > +#define SMUIO_BASE__INST1_SEG0 0 > +#define SMUIO_BASE__INST1_SEG1 0 > +#define SMUIO_BASE__INST1_SEG2 0 > +#define SMUIO_BASE__INST1_SEG3 0 > +#define SMUIO_BASE__INST1_SEG4 0 > + > +#define SMUIO_BASE__INST2_SEG0 0 > +#define SMUIO_BASE__INST2_SEG1 0 > +#define SMUIO_BASE__INST2_SEG2 0 > +#define SMUIO_BASE__INST2_SEG3 0 > +#define SMUIO_BASE__INST2_SEG4 0 > + > +#define SMUIO_BASE__INST3_SEG0 0 > +#define SMUIO_BASE__INST3_SEG1 0 > +#define SMUIO_BASE__INST3_SEG2 0 > +#define SMUIO_BASE__INST3_SEG3 0 > +#define SMUIO_BASE__INST3_SEG4 0 > + > +#define SMUIO_BASE__INST4_SEG0 0 > +#define SMUIO_BASE__INST4_SEG1 0 > +#define SMUIO_BASE__INST4_SEG2 0 > +#define SMUIO_BASE__INST4_SEG3 0 > +#define SMUIO_BASE__INST4_SEG4 0 > + > +#define PWR_BASE__INST0_SEG0 0x00016A00 > +#define PWR_BASE__INST0_SEG1 0 > +#define PWR_BASE__INST0_SEG2 0 > +#define PWR_BASE__INST0_SEG3 0 > +#define PWR_BASE__INST0_SEG4 0 > + > +#define PWR_BASE__INST1_SEG0 0 > +#define PWR_BASE__INST1_SEG1 0 > +#define PWR_BASE__INST1_SEG2 0 > +#define PWR_BASE__INST1_SEG3 0 > +#define PWR_BASE__INST1_SEG4 0 > + > +#define PWR_BASE__INST2_SEG0 0 > +#define PWR_BASE__INST2_SEG1 0 > +#define PWR_BASE__INST2_SEG2 0 > +#define PWR_BASE__INST2_SEG3 0 > +#define PWR_BASE__INST2_SEG4 0 > + > +#define PWR_BASE__INST3_SEG0 0 > +#define PWR_BASE__INST3_SEG1 0 > +#define PWR_BASE__INST3_SEG2 0 > +#define PWR_BASE__INST3_SEG3 0 > +#define PWR_BASE__INST3_SEG4 0 > + > +#define PWR_BASE__INST4_SEG0 0 > +#define PWR_BASE__INST4_SEG1 0 > +#define PWR_BASE__INST4_SEG2 0 > +#define PWR_BASE__INST4_SEG3 0 > +#define PWR_BASE__INST4_SEG4 0 > + > +#define CLK_BASE__INST0_SEG0 0x00016C00 > +#define CLK_BASE__INST0_SEG1 0 > +#define CLK_BASE__INST0_SEG2 0 > +#define CLK_BASE__INST0_SEG3 0 > +#define CLK_BASE__INST0_SEG4 0 > + > +#define CLK_BASE__INST1_SEG0 0x00016E00 > +#define CLK_BASE__INST1_SEG1 0 > +#define CLK_BASE__INST1_SEG2 0 > +#define CLK_BASE__INST1_SEG3 0 > +#define CLK_BASE__INST1_SEG4 0 > + > +#define CLK_BASE__INST2_SEG0 0x00017000 > +#define CLK_BASE__INST2_SEG1 0 > +#define CLK_BASE__INST2_SEG2 0 > +#define CLK_BASE__INST2_SEG3 0 > +#define CLK_BASE__INST2_SEG4 0 > + > +#define CLK_BASE__INST3_SEG0 0x00017200 > +#define CLK_BASE__INST3_SEG1 0 > +#define CLK_BASE__INST3_SEG2 0 > +#define CLK_BASE__INST3_SEG3 0 > +#define CLK_BASE__INST3_SEG4 0 > + > +#define CLK_BASE__INST4_SEG0 0x00017E00 > +#define CLK_BASE__INST4_SEG1 0 > +#define CLK_BASE__INST4_SEG2 0 > +#define CLK_BASE__INST4_SEG3 0 > +#define CLK_BASE__INST4_SEG4 0 > + > +#define FUSE_BASE__INST0_SEG0 0x00017400 > +#define FUSE_BASE__INST0_SEG1 0 > +#define FUSE_BASE__INST0_SEG2 0 > +#define FUSE_BASE__INST0_SEG3 0 > +#define FUSE_BASE__INST0_SEG4 0 > + > +#define FUSE_BASE__INST1_SEG0 0 > +#define FUSE_BASE__INST1_SEG1 0 > +#define FUSE_BASE__INST1_SEG2 0 > +#define FUSE_BASE__INST1_SEG3 0 > +#define FUSE_BASE__INST1_SEG4 0 > + > +#define FUSE_BASE__INST2_SEG0 0 > +#define FUSE_BASE__INST2_SEG1 0 > +#define FUSE_BASE__INST2_SEG2 0 > +#define FUSE_BASE__INST2_SEG3 0 > +#define FUSE_BASE__INST2_SEG4 0 > + > +#define FUSE_BASE__INST3_SEG0 0 > +#define FUSE_BASE__INST3_SEG1 0 > +#define FUSE_BASE__INST3_SEG2 0 > +#define FUSE_BASE__INST3_SEG3 0 > +#define FUSE_BASE__INST3_SEG4 0 > + > +#define FUSE_BASE__INST4_SEG0 0 > +#define FUSE_BASE__INST4_SEG1 0 > +#define FUSE_BASE__INST4_SEG2 0 > +#define FUSE_BASE__INST4_SEG3 0 > +#define FUSE_BASE__INST4_SEG4 0 > + > + > +#endif > + > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <a831909b-4381-1a63-fba3-0eb816fa5e61-5C7GfCeVMHo@public.gmane.org>]
* RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <a831909b-4381-1a63-fba3-0eb816fa5e61-5C7GfCeVMHo@public.gmane.org> @ 2017-11-27 19:04 ` Liu, Shaoyun 0 siblings, 0 replies; 14+ messages in thread From: Liu, Shaoyun @ 2017-11-27 19:04 UTC (permalink / raw) To: StDenis, Tom, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Hi , This file is copied from HW asic bring up team . The defines here are the same as what we already have under amd/include/asic_reg/vega10/soc15ip.h . Compare to VEGA10, the same IP could have different base offset defines , so the original soc15ip.h will not works for other asic . In the future , when we bring up new asic , we may need to copy other ip_offset_*.h from HW . This ip_offset_1.h can be used for VEGA10 , RAVEN and VEGA12 as suggested by HW engineer . Regards Shaoyun.liu -----Original Message----- From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Tom St Denis Sent: Monday, November 27, 2017 1:54 PM To: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file On 27/11/17 01:30 PM, Shaoyun Liu wrote: > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> > --- > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++ > 1 file changed, 1248 insertions(+) > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > new file mode 100644 > index 0000000..76cb748 > --- /dev/null > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > @@ -0,0 +1,1248 @@ > +#ifndef _ip_offset_1_HEADER > +#define _ip_offset_1_HEADER > + > +#define MAX_INSTANCE 5 > +#define MAX_SEGMENT 5 > + > + > +struct IP_BASE_INSTANCE > +{ > + unsigned int segment[MAX_SEGMENT]; > +}; > + > +struct IP_BASE > +{ > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; > +}; > + > + > +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, > + { { 0x00016E00, 0, 0, 0, 0 } }, > + { { 0x00017000, 0, 0, 0, 0 } }, > + { { 0x00017200, 0, 0, 0, 0 } }, > + { { 0x00017E00, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; Since these are likely to be ASIC specific wouldn't it make more sense to organize these as one global struct/array per asic instead? Variables like FUSE_BASE don't take into account that future ASICs might also have a FUSE IP block but with different offsets. > + > + > +#define NBIF_BASE__INST0_SEG0 0x00000000 > +#define NBIF_BASE__INST0_SEG1 0x00000014 > +#define NBIF_BASE__INST0_SEG2 0x00000D20 > +#define NBIF_BASE__INST0_SEG3 0x00010400 > +#define NBIF_BASE__INST0_SEG4 0 If we have the arrays above why keep these? At the very least the two should be intertwined so changing one changes the other (if we don't drop the define blocks). Tom > + > +#define NBIF_BASE__INST1_SEG0 0 > +#define NBIF_BASE__INST1_SEG1 0 > +#define NBIF_BASE__INST1_SEG2 0 > +#define NBIF_BASE__INST1_SEG3 0 > +#define NBIF_BASE__INST1_SEG4 0 > + > +#define NBIF_BASE__INST2_SEG0 0 > +#define NBIF_BASE__INST2_SEG1 0 > +#define NBIF_BASE__INST2_SEG2 0 > +#define NBIF_BASE__INST2_SEG3 0 > +#define NBIF_BASE__INST2_SEG4 0 > + > +#define NBIF_BASE__INST3_SEG0 0 > +#define NBIF_BASE__INST3_SEG1 0 > +#define NBIF_BASE__INST3_SEG2 0 > +#define NBIF_BASE__INST3_SEG3 0 > +#define NBIF_BASE__INST3_SEG4 0 > + > +#define NBIF_BASE__INST4_SEG0 0 > +#define NBIF_BASE__INST4_SEG1 0 > +#define NBIF_BASE__INST4_SEG2 0 > +#define NBIF_BASE__INST4_SEG3 0 > +#define NBIF_BASE__INST4_SEG4 0 > + > +#define NBIO_BASE__INST0_SEG0 0x00000000 > +#define NBIO_BASE__INST0_SEG1 0x00000014 > +#define NBIO_BASE__INST0_SEG2 0x00000D20 > +#define NBIO_BASE__INST0_SEG3 0x00010400 > +#define NBIO_BASE__INST0_SEG4 0 > + > +#define NBIO_BASE__INST1_SEG0 0 > +#define NBIO_BASE__INST1_SEG1 0 > +#define NBIO_BASE__INST1_SEG2 0 > +#define NBIO_BASE__INST1_SEG3 0 > +#define NBIO_BASE__INST1_SEG4 0 > + > +#define NBIO_BASE__INST2_SEG0 0 > +#define NBIO_BASE__INST2_SEG1 0 > +#define NBIO_BASE__INST2_SEG2 0 > +#define NBIO_BASE__INST2_SEG3 0 > +#define NBIO_BASE__INST2_SEG4 0 > + > +#define NBIO_BASE__INST3_SEG0 0 > +#define NBIO_BASE__INST3_SEG1 0 > +#define NBIO_BASE__INST3_SEG2 0 > +#define NBIO_BASE__INST3_SEG3 0 > +#define NBIO_BASE__INST3_SEG4 0 > + > +#define NBIO_BASE__INST4_SEG0 0 > +#define NBIO_BASE__INST4_SEG1 0 > +#define NBIO_BASE__INST4_SEG2 0 > +#define NBIO_BASE__INST4_SEG3 0 > +#define NBIO_BASE__INST4_SEG4 0 > + > +#define DCE_BASE__INST0_SEG0 0x00000012 > +#define DCE_BASE__INST0_SEG1 0x000000C0 > +#define DCE_BASE__INST0_SEG2 0x000034C0 > +#define DCE_BASE__INST0_SEG3 0 > +#define DCE_BASE__INST0_SEG4 0 > + > +#define DCE_BASE__INST1_SEG0 0 > +#define DCE_BASE__INST1_SEG1 0 > +#define DCE_BASE__INST1_SEG2 0 > +#define DCE_BASE__INST1_SEG3 0 > +#define DCE_BASE__INST1_SEG4 0 > + > +#define DCE_BASE__INST2_SEG0 0 > +#define DCE_BASE__INST2_SEG1 0 > +#define DCE_BASE__INST2_SEG2 0 > +#define DCE_BASE__INST2_SEG3 0 > +#define DCE_BASE__INST2_SEG4 0 > + > +#define DCE_BASE__INST3_SEG0 0 > +#define DCE_BASE__INST3_SEG1 0 > +#define DCE_BASE__INST3_SEG2 0 > +#define DCE_BASE__INST3_SEG3 0 > +#define DCE_BASE__INST3_SEG4 0 > + > +#define DCE_BASE__INST4_SEG0 0 > +#define DCE_BASE__INST4_SEG1 0 > +#define DCE_BASE__INST4_SEG2 0 > +#define DCE_BASE__INST4_SEG3 0 > +#define DCE_BASE__INST4_SEG4 0 > + > +#define DCN_BASE__INST0_SEG0 0x00000012 > +#define DCN_BASE__INST0_SEG1 0x000000C0 > +#define DCN_BASE__INST0_SEG2 0x000034C0 > +#define DCN_BASE__INST0_SEG3 0 > +#define DCN_BASE__INST0_SEG4 0 > + > +#define DCN_BASE__INST1_SEG0 0 > +#define DCN_BASE__INST1_SEG1 0 > +#define DCN_BASE__INST1_SEG2 0 > +#define DCN_BASE__INST1_SEG3 0 > +#define DCN_BASE__INST1_SEG4 0 > + > +#define DCN_BASE__INST2_SEG0 0 > +#define DCN_BASE__INST2_SEG1 0 > +#define DCN_BASE__INST2_SEG2 0 > +#define DCN_BASE__INST2_SEG3 0 > +#define DCN_BASE__INST2_SEG4 0 > + > +#define DCN_BASE__INST3_SEG0 0 > +#define DCN_BASE__INST3_SEG1 0 > +#define DCN_BASE__INST3_SEG2 0 > +#define DCN_BASE__INST3_SEG3 0 > +#define DCN_BASE__INST3_SEG4 0 > + > +#define DCN_BASE__INST4_SEG0 0 > +#define DCN_BASE__INST4_SEG1 0 > +#define DCN_BASE__INST4_SEG2 0 > +#define DCN_BASE__INST4_SEG3 0 > +#define DCN_BASE__INST4_SEG4 0 > + > +#define MP0_BASE__INST0_SEG0 0x00016000 > +#define MP0_BASE__INST0_SEG1 0 > +#define MP0_BASE__INST0_SEG2 0 > +#define MP0_BASE__INST0_SEG3 0 > +#define MP0_BASE__INST0_SEG4 0 > + > +#define MP0_BASE__INST1_SEG0 0 > +#define MP0_BASE__INST1_SEG1 0 > +#define MP0_BASE__INST1_SEG2 0 > +#define MP0_BASE__INST1_SEG3 0 > +#define MP0_BASE__INST1_SEG4 0 > + > +#define MP0_BASE__INST2_SEG0 0 > +#define MP0_BASE__INST2_SEG1 0 > +#define MP0_BASE__INST2_SEG2 0 > +#define MP0_BASE__INST2_SEG3 0 > +#define MP0_BASE__INST2_SEG4 0 > + > +#define MP0_BASE__INST3_SEG0 0 > +#define MP0_BASE__INST3_SEG1 0 > +#define MP0_BASE__INST3_SEG2 0 > +#define MP0_BASE__INST3_SEG3 0 > +#define MP0_BASE__INST3_SEG4 0 > + > +#define MP0_BASE__INST4_SEG0 0 > +#define MP0_BASE__INST4_SEG1 0 > +#define MP0_BASE__INST4_SEG2 0 > +#define MP0_BASE__INST4_SEG3 0 > +#define MP0_BASE__INST4_SEG4 0 > + > +#define MP1_BASE__INST0_SEG0 0x00016000 > +#define MP1_BASE__INST0_SEG1 0 > +#define MP1_BASE__INST0_SEG2 0 > +#define MP1_BASE__INST0_SEG3 0 > +#define MP1_BASE__INST0_SEG4 0 > + > +#define MP1_BASE__INST1_SEG0 0 > +#define MP1_BASE__INST1_SEG1 0 > +#define MP1_BASE__INST1_SEG2 0 > +#define MP1_BASE__INST1_SEG3 0 > +#define MP1_BASE__INST1_SEG4 0 > + > +#define MP1_BASE__INST2_SEG0 0 > +#define MP1_BASE__INST2_SEG1 0 > +#define MP1_BASE__INST2_SEG2 0 > +#define MP1_BASE__INST2_SEG3 0 > +#define MP1_BASE__INST2_SEG4 0 > + > +#define MP1_BASE__INST3_SEG0 0 > +#define MP1_BASE__INST3_SEG1 0 > +#define MP1_BASE__INST3_SEG2 0 > +#define MP1_BASE__INST3_SEG3 0 > +#define MP1_BASE__INST3_SEG4 0 > + > +#define MP1_BASE__INST4_SEG0 0 > +#define MP1_BASE__INST4_SEG1 0 > +#define MP1_BASE__INST4_SEG2 0 > +#define MP1_BASE__INST4_SEG3 0 > +#define MP1_BASE__INST4_SEG4 0 > + > +#define MP2_BASE__INST0_SEG0 0x00016000 > +#define MP2_BASE__INST0_SEG1 0 > +#define MP2_BASE__INST0_SEG2 0 > +#define MP2_BASE__INST0_SEG3 0 > +#define MP2_BASE__INST0_SEG4 0 > + > +#define MP2_BASE__INST1_SEG0 0 > +#define MP2_BASE__INST1_SEG1 0 > +#define MP2_BASE__INST1_SEG2 0 > +#define MP2_BASE__INST1_SEG3 0 > +#define MP2_BASE__INST1_SEG4 0 > + > +#define MP2_BASE__INST2_SEG0 0 > +#define MP2_BASE__INST2_SEG1 0 > +#define MP2_BASE__INST2_SEG2 0 > +#define MP2_BASE__INST2_SEG3 0 > +#define MP2_BASE__INST2_SEG4 0 > + > +#define MP2_BASE__INST3_SEG0 0 > +#define MP2_BASE__INST3_SEG1 0 > +#define MP2_BASE__INST3_SEG2 0 > +#define MP2_BASE__INST3_SEG3 0 > +#define MP2_BASE__INST3_SEG4 0 > + > +#define MP2_BASE__INST4_SEG0 0 > +#define MP2_BASE__INST4_SEG1 0 > +#define MP2_BASE__INST4_SEG2 0 > +#define MP2_BASE__INST4_SEG3 0 > +#define MP2_BASE__INST4_SEG4 0 > + > +#define DF_BASE__INST0_SEG0 0x00007000 > +#define DF_BASE__INST0_SEG1 0 > +#define DF_BASE__INST0_SEG2 0 > +#define DF_BASE__INST0_SEG3 0 > +#define DF_BASE__INST0_SEG4 0 > + > +#define DF_BASE__INST1_SEG0 0 > +#define DF_BASE__INST1_SEG1 0 > +#define DF_BASE__INST1_SEG2 0 > +#define DF_BASE__INST1_SEG3 0 > +#define DF_BASE__INST1_SEG4 0 > + > +#define DF_BASE__INST2_SEG0 0 > +#define DF_BASE__INST2_SEG1 0 > +#define DF_BASE__INST2_SEG2 0 > +#define DF_BASE__INST2_SEG3 0 > +#define DF_BASE__INST2_SEG4 0 > + > +#define DF_BASE__INST3_SEG0 0 > +#define DF_BASE__INST3_SEG1 0 > +#define DF_BASE__INST3_SEG2 0 > +#define DF_BASE__INST3_SEG3 0 > +#define DF_BASE__INST3_SEG4 0 > + > +#define DF_BASE__INST4_SEG0 0 > +#define DF_BASE__INST4_SEG1 0 > +#define DF_BASE__INST4_SEG2 0 > +#define DF_BASE__INST4_SEG3 0 > +#define DF_BASE__INST4_SEG4 0 > + > +#define UVD_BASE__INST0_SEG0 0x00007800 > +#define UVD_BASE__INST0_SEG1 0x00007E00 > +#define UVD_BASE__INST0_SEG2 0 > +#define UVD_BASE__INST0_SEG3 0 > +#define UVD_BASE__INST0_SEG4 0 > + > +#define UVD_BASE__INST1_SEG0 0 > +#define UVD_BASE__INST1_SEG1 0 > +#define UVD_BASE__INST1_SEG2 0 > +#define UVD_BASE__INST1_SEG3 0 > +#define UVD_BASE__INST1_SEG4 0 > + > +#define UVD_BASE__INST2_SEG0 0 > +#define UVD_BASE__INST2_SEG1 0 > +#define UVD_BASE__INST2_SEG2 0 > +#define UVD_BASE__INST2_SEG3 0 > +#define UVD_BASE__INST2_SEG4 0 > + > +#define UVD_BASE__INST3_SEG0 0 > +#define UVD_BASE__INST3_SEG1 0 > +#define UVD_BASE__INST3_SEG2 0 > +#define UVD_BASE__INST3_SEG3 0 > +#define UVD_BASE__INST3_SEG4 0 > + > +#define UVD_BASE__INST4_SEG0 0 > +#define UVD_BASE__INST4_SEG1 0 > +#define UVD_BASE__INST4_SEG2 0 > +#define UVD_BASE__INST4_SEG3 0 > +#define UVD_BASE__INST4_SEG4 0 > + > +#define VCN_BASE__INST0_SEG0 0x00007800 > +#define VCN_BASE__INST0_SEG1 0x00007E00 > +#define VCN_BASE__INST0_SEG2 0 > +#define VCN_BASE__INST0_SEG3 0 > +#define VCN_BASE__INST0_SEG4 0 > + > +#define VCN_BASE__INST1_SEG0 0 > +#define VCN_BASE__INST1_SEG1 0 > +#define VCN_BASE__INST1_SEG2 0 > +#define VCN_BASE__INST1_SEG3 0 > +#define VCN_BASE__INST1_SEG4 0 > + > +#define VCN_BASE__INST2_SEG0 0 > +#define VCN_BASE__INST2_SEG1 0 > +#define VCN_BASE__INST2_SEG2 0 > +#define VCN_BASE__INST2_SEG3 0 > +#define VCN_BASE__INST2_SEG4 0 > + > +#define VCN_BASE__INST3_SEG0 0 > +#define VCN_BASE__INST3_SEG1 0 > +#define VCN_BASE__INST3_SEG2 0 > +#define VCN_BASE__INST3_SEG3 0 > +#define VCN_BASE__INST3_SEG4 0 > + > +#define VCN_BASE__INST4_SEG0 0 > +#define VCN_BASE__INST4_SEG1 0 > +#define VCN_BASE__INST4_SEG2 0 > +#define VCN_BASE__INST4_SEG3 0 > +#define VCN_BASE__INST4_SEG4 0 > + > +#define DBGU_BASE__INST0_SEG0 0x00000180 > +#define DBGU_BASE__INST0_SEG1 0x000001A0 > +#define DBGU_BASE__INST0_SEG2 0 > +#define DBGU_BASE__INST0_SEG3 0 > +#define DBGU_BASE__INST0_SEG4 0 > + > +#define DBGU_BASE__INST1_SEG0 0 > +#define DBGU_BASE__INST1_SEG1 0 > +#define DBGU_BASE__INST1_SEG2 0 > +#define DBGU_BASE__INST1_SEG3 0 > +#define DBGU_BASE__INST1_SEG4 0 > + > +#define DBGU_BASE__INST2_SEG0 0 > +#define DBGU_BASE__INST2_SEG1 0 > +#define DBGU_BASE__INST2_SEG2 0 > +#define DBGU_BASE__INST2_SEG3 0 > +#define DBGU_BASE__INST2_SEG4 0 > + > +#define DBGU_BASE__INST3_SEG0 0 > +#define DBGU_BASE__INST3_SEG1 0 > +#define DBGU_BASE__INST3_SEG2 0 > +#define DBGU_BASE__INST3_SEG3 0 > +#define DBGU_BASE__INST3_SEG4 0 > + > +#define DBGU_BASE__INST4_SEG0 0 > +#define DBGU_BASE__INST4_SEG1 0 > +#define DBGU_BASE__INST4_SEG2 0 > +#define DBGU_BASE__INST4_SEG3 0 > +#define DBGU_BASE__INST4_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 > +#define DBGU_NBIO_BASE__INST0_SEG1 0 > +#define DBGU_NBIO_BASE__INST0_SEG2 0 > +#define DBGU_NBIO_BASE__INST0_SEG3 0 > +#define DBGU_NBIO_BASE__INST0_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST1_SEG0 0 > +#define DBGU_NBIO_BASE__INST1_SEG1 0 > +#define DBGU_NBIO_BASE__INST1_SEG2 0 > +#define DBGU_NBIO_BASE__INST1_SEG3 0 > +#define DBGU_NBIO_BASE__INST1_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST2_SEG0 0 > +#define DBGU_NBIO_BASE__INST2_SEG1 0 > +#define DBGU_NBIO_BASE__INST2_SEG2 0 > +#define DBGU_NBIO_BASE__INST2_SEG3 0 > +#define DBGU_NBIO_BASE__INST2_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST3_SEG0 0 > +#define DBGU_NBIO_BASE__INST3_SEG1 0 > +#define DBGU_NBIO_BASE__INST3_SEG2 0 > +#define DBGU_NBIO_BASE__INST3_SEG3 0 > +#define DBGU_NBIO_BASE__INST3_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST4_SEG0 0 > +#define DBGU_NBIO_BASE__INST4_SEG1 0 > +#define DBGU_NBIO_BASE__INST4_SEG2 0 > +#define DBGU_NBIO_BASE__INST4_SEG3 0 > +#define DBGU_NBIO_BASE__INST4_SEG4 0 > + > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 > +#define DBGU_IO_BASE__INST0_SEG1 0 > +#define DBGU_IO_BASE__INST0_SEG2 0 > +#define DBGU_IO_BASE__INST0_SEG3 0 > +#define DBGU_IO_BASE__INST0_SEG4 0 > + > +#define DBGU_IO_BASE__INST1_SEG0 0 > +#define DBGU_IO_BASE__INST1_SEG1 0 > +#define DBGU_IO_BASE__INST1_SEG2 0 > +#define DBGU_IO_BASE__INST1_SEG3 0 > +#define DBGU_IO_BASE__INST1_SEG4 0 > + > +#define DBGU_IO_BASE__INST2_SEG0 0 > +#define DBGU_IO_BASE__INST2_SEG1 0 > +#define DBGU_IO_BASE__INST2_SEG2 0 > +#define DBGU_IO_BASE__INST2_SEG3 0 > +#define DBGU_IO_BASE__INST2_SEG4 0 > + > +#define DBGU_IO_BASE__INST3_SEG0 0 > +#define DBGU_IO_BASE__INST3_SEG1 0 > +#define DBGU_IO_BASE__INST3_SEG2 0 > +#define DBGU_IO_BASE__INST3_SEG3 0 > +#define DBGU_IO_BASE__INST3_SEG4 0 > + > +#define DBGU_IO_BASE__INST4_SEG0 0 > +#define DBGU_IO_BASE__INST4_SEG1 0 > +#define DBGU_IO_BASE__INST4_SEG2 0 > +#define DBGU_IO_BASE__INST4_SEG3 0 > +#define DBGU_IO_BASE__INST4_SEG4 0 > + > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 > +#define DFX_DAP_BASE__INST0_SEG1 0 > +#define DFX_DAP_BASE__INST0_SEG2 0 > +#define DFX_DAP_BASE__INST0_SEG3 0 > +#define DFX_DAP_BASE__INST0_SEG4 0 > + > +#define DFX_DAP_BASE__INST1_SEG0 0 > +#define DFX_DAP_BASE__INST1_SEG1 0 > +#define DFX_DAP_BASE__INST1_SEG2 0 > +#define DFX_DAP_BASE__INST1_SEG3 0 > +#define DFX_DAP_BASE__INST1_SEG4 0 > + > +#define DFX_DAP_BASE__INST2_SEG0 0 > +#define DFX_DAP_BASE__INST2_SEG1 0 > +#define DFX_DAP_BASE__INST2_SEG2 0 > +#define DFX_DAP_BASE__INST2_SEG3 0 > +#define DFX_DAP_BASE__INST2_SEG4 0 > + > +#define DFX_DAP_BASE__INST3_SEG0 0 > +#define DFX_DAP_BASE__INST3_SEG1 0 > +#define DFX_DAP_BASE__INST3_SEG2 0 > +#define DFX_DAP_BASE__INST3_SEG3 0 > +#define DFX_DAP_BASE__INST3_SEG4 0 > + > +#define DFX_DAP_BASE__INST4_SEG0 0 > +#define DFX_DAP_BASE__INST4_SEG1 0 > +#define DFX_DAP_BASE__INST4_SEG2 0 > +#define DFX_DAP_BASE__INST4_SEG3 0 > +#define DFX_DAP_BASE__INST4_SEG4 0 > + > +#define DFX_BASE__INST0_SEG0 0x00000580 > +#define DFX_BASE__INST0_SEG1 0 > +#define DFX_BASE__INST0_SEG2 0 > +#define DFX_BASE__INST0_SEG3 0 > +#define DFX_BASE__INST0_SEG4 0 > + > +#define DFX_BASE__INST1_SEG0 0 > +#define DFX_BASE__INST1_SEG1 0 > +#define DFX_BASE__INST1_SEG2 0 > +#define DFX_BASE__INST1_SEG3 0 > +#define DFX_BASE__INST1_SEG4 0 > + > +#define DFX_BASE__INST2_SEG0 0 > +#define DFX_BASE__INST2_SEG1 0 > +#define DFX_BASE__INST2_SEG2 0 > +#define DFX_BASE__INST2_SEG3 0 > +#define DFX_BASE__INST2_SEG4 0 > + > +#define DFX_BASE__INST3_SEG0 0 > +#define DFX_BASE__INST3_SEG1 0 > +#define DFX_BASE__INST3_SEG2 0 > +#define DFX_BASE__INST3_SEG3 0 > +#define DFX_BASE__INST3_SEG4 0 > + > +#define DFX_BASE__INST4_SEG0 0 > +#define DFX_BASE__INST4_SEG1 0 > +#define DFX_BASE__INST4_SEG2 0 > +#define DFX_BASE__INST4_SEG3 0 > +#define DFX_BASE__INST4_SEG4 0 > + > +#define ISP_BASE__INST0_SEG0 0x00018000 > +#define ISP_BASE__INST0_SEG1 0 > +#define ISP_BASE__INST0_SEG2 0 > +#define ISP_BASE__INST0_SEG3 0 > +#define ISP_BASE__INST0_SEG4 0 > + > +#define ISP_BASE__INST1_SEG0 0 > +#define ISP_BASE__INST1_SEG1 0 > +#define ISP_BASE__INST1_SEG2 0 > +#define ISP_BASE__INST1_SEG3 0 > +#define ISP_BASE__INST1_SEG4 0 > + > +#define ISP_BASE__INST2_SEG0 0 > +#define ISP_BASE__INST2_SEG1 0 > +#define ISP_BASE__INST2_SEG2 0 > +#define ISP_BASE__INST2_SEG3 0 > +#define ISP_BASE__INST2_SEG4 0 > + > +#define ISP_BASE__INST3_SEG0 0 > +#define ISP_BASE__INST3_SEG1 0 > +#define ISP_BASE__INST3_SEG2 0 > +#define ISP_BASE__INST3_SEG3 0 > +#define ISP_BASE__INST3_SEG4 0 > + > +#define ISP_BASE__INST4_SEG0 0 > +#define ISP_BASE__INST4_SEG1 0 > +#define ISP_BASE__INST4_SEG2 0 > +#define ISP_BASE__INST4_SEG3 0 > +#define ISP_BASE__INST4_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 > +#define SYSTEMHUB_BASE__INST0_SEG1 0 > +#define SYSTEMHUB_BASE__INST0_SEG2 0 > +#define SYSTEMHUB_BASE__INST0_SEG3 0 > +#define SYSTEMHUB_BASE__INST0_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST1_SEG0 0 > +#define SYSTEMHUB_BASE__INST1_SEG1 0 > +#define SYSTEMHUB_BASE__INST1_SEG2 0 > +#define SYSTEMHUB_BASE__INST1_SEG3 0 > +#define SYSTEMHUB_BASE__INST1_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST2_SEG0 0 > +#define SYSTEMHUB_BASE__INST2_SEG1 0 > +#define SYSTEMHUB_BASE__INST2_SEG2 0 > +#define SYSTEMHUB_BASE__INST2_SEG3 0 > +#define SYSTEMHUB_BASE__INST2_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST3_SEG0 0 > +#define SYSTEMHUB_BASE__INST3_SEG1 0 > +#define SYSTEMHUB_BASE__INST3_SEG2 0 > +#define SYSTEMHUB_BASE__INST3_SEG3 0 > +#define SYSTEMHUB_BASE__INST3_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST4_SEG0 0 > +#define SYSTEMHUB_BASE__INST4_SEG1 0 > +#define SYSTEMHUB_BASE__INST4_SEG2 0 > +#define SYSTEMHUB_BASE__INST4_SEG3 0 > +#define SYSTEMHUB_BASE__INST4_SEG4 0 > + > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 > +#define L2IMU_BASE__INST0_SEG1 0 > +#define L2IMU_BASE__INST0_SEG2 0 > +#define L2IMU_BASE__INST0_SEG3 0 > +#define L2IMU_BASE__INST0_SEG4 0 > + > +#define L2IMU_BASE__INST1_SEG0 0 > +#define L2IMU_BASE__INST1_SEG1 0 > +#define L2IMU_BASE__INST1_SEG2 0 > +#define L2IMU_BASE__INST1_SEG3 0 > +#define L2IMU_BASE__INST1_SEG4 0 > + > +#define L2IMU_BASE__INST2_SEG0 0 > +#define L2IMU_BASE__INST2_SEG1 0 > +#define L2IMU_BASE__INST2_SEG2 0 > +#define L2IMU_BASE__INST2_SEG3 0 > +#define L2IMU_BASE__INST2_SEG4 0 > + > +#define L2IMU_BASE__INST3_SEG0 0 > +#define L2IMU_BASE__INST3_SEG1 0 > +#define L2IMU_BASE__INST3_SEG2 0 > +#define L2IMU_BASE__INST3_SEG3 0 > +#define L2IMU_BASE__INST3_SEG4 0 > + > +#define L2IMU_BASE__INST4_SEG0 0 > +#define L2IMU_BASE__INST4_SEG1 0 > +#define L2IMU_BASE__INST4_SEG2 0 > +#define L2IMU_BASE__INST4_SEG3 0 > +#define L2IMU_BASE__INST4_SEG4 0 > + > +#define IOHC_BASE__INST0_SEG0 0x00010000 > +#define IOHC_BASE__INST0_SEG1 0 > +#define IOHC_BASE__INST0_SEG2 0 > +#define IOHC_BASE__INST0_SEG3 0 > +#define IOHC_BASE__INST0_SEG4 0 > + > +#define IOHC_BASE__INST1_SEG0 0 > +#define IOHC_BASE__INST1_SEG1 0 > +#define IOHC_BASE__INST1_SEG2 0 > +#define IOHC_BASE__INST1_SEG3 0 > +#define IOHC_BASE__INST1_SEG4 0 > + > +#define IOHC_BASE__INST2_SEG0 0 > +#define IOHC_BASE__INST2_SEG1 0 > +#define IOHC_BASE__INST2_SEG2 0 > +#define IOHC_BASE__INST2_SEG3 0 > +#define IOHC_BASE__INST2_SEG4 0 > + > +#define IOHC_BASE__INST3_SEG0 0 > +#define IOHC_BASE__INST3_SEG1 0 > +#define IOHC_BASE__INST3_SEG2 0 > +#define IOHC_BASE__INST3_SEG3 0 > +#define IOHC_BASE__INST3_SEG4 0 > + > +#define IOHC_BASE__INST4_SEG0 0 > +#define IOHC_BASE__INST4_SEG1 0 > +#define IOHC_BASE__INST4_SEG2 0 > +#define IOHC_BASE__INST4_SEG3 0 > +#define IOHC_BASE__INST4_SEG4 0 > + > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 > +#define ATHUB_BASE__INST0_SEG1 0 > +#define ATHUB_BASE__INST0_SEG2 0 > +#define ATHUB_BASE__INST0_SEG3 0 > +#define ATHUB_BASE__INST0_SEG4 0 > + > +#define ATHUB_BASE__INST1_SEG0 0 > +#define ATHUB_BASE__INST1_SEG1 0 > +#define ATHUB_BASE__INST1_SEG2 0 > +#define ATHUB_BASE__INST1_SEG3 0 > +#define ATHUB_BASE__INST1_SEG4 0 > + > +#define ATHUB_BASE__INST2_SEG0 0 > +#define ATHUB_BASE__INST2_SEG1 0 > +#define ATHUB_BASE__INST2_SEG2 0 > +#define ATHUB_BASE__INST2_SEG3 0 > +#define ATHUB_BASE__INST2_SEG4 0 > + > +#define ATHUB_BASE__INST3_SEG0 0 > +#define ATHUB_BASE__INST3_SEG1 0 > +#define ATHUB_BASE__INST3_SEG2 0 > +#define ATHUB_BASE__INST3_SEG3 0 > +#define ATHUB_BASE__INST3_SEG4 0 > + > +#define ATHUB_BASE__INST4_SEG0 0 > +#define ATHUB_BASE__INST4_SEG1 0 > +#define ATHUB_BASE__INST4_SEG2 0 > +#define ATHUB_BASE__INST4_SEG3 0 > +#define ATHUB_BASE__INST4_SEG4 0 > + > +#define VCE_BASE__INST0_SEG0 0x00007E00 > +#define VCE_BASE__INST0_SEG1 0x00048800 > +#define VCE_BASE__INST0_SEG2 0 > +#define VCE_BASE__INST0_SEG3 0 > +#define VCE_BASE__INST0_SEG4 0 > + > +#define VCE_BASE__INST1_SEG0 0 > +#define VCE_BASE__INST1_SEG1 0 > +#define VCE_BASE__INST1_SEG2 0 > +#define VCE_BASE__INST1_SEG3 0 > +#define VCE_BASE__INST1_SEG4 0 > + > +#define VCE_BASE__INST2_SEG0 0 > +#define VCE_BASE__INST2_SEG1 0 > +#define VCE_BASE__INST2_SEG2 0 > +#define VCE_BASE__INST2_SEG3 0 > +#define VCE_BASE__INST2_SEG4 0 > + > +#define VCE_BASE__INST3_SEG0 0 > +#define VCE_BASE__INST3_SEG1 0 > +#define VCE_BASE__INST3_SEG2 0 > +#define VCE_BASE__INST3_SEG3 0 > +#define VCE_BASE__INST3_SEG4 0 > + > +#define VCE_BASE__INST4_SEG0 0 > +#define VCE_BASE__INST4_SEG1 0 > +#define VCE_BASE__INST4_SEG2 0 > +#define VCE_BASE__INST4_SEG3 0 > +#define VCE_BASE__INST4_SEG4 0 > + > +#define GC_BASE__INST0_SEG0 0x00002000 > +#define GC_BASE__INST0_SEG1 0x0000A000 > +#define GC_BASE__INST0_SEG2 0 > +#define GC_BASE__INST0_SEG3 0 > +#define GC_BASE__INST0_SEG4 0 > + > +#define GC_BASE__INST1_SEG0 0 > +#define GC_BASE__INST1_SEG1 0 > +#define GC_BASE__INST1_SEG2 0 > +#define GC_BASE__INST1_SEG3 0 > +#define GC_BASE__INST1_SEG4 0 > + > +#define GC_BASE__INST2_SEG0 0 > +#define GC_BASE__INST2_SEG1 0 > +#define GC_BASE__INST2_SEG2 0 > +#define GC_BASE__INST2_SEG3 0 > +#define GC_BASE__INST2_SEG4 0 > + > +#define GC_BASE__INST3_SEG0 0 > +#define GC_BASE__INST3_SEG1 0 > +#define GC_BASE__INST3_SEG2 0 > +#define GC_BASE__INST3_SEG3 0 > +#define GC_BASE__INST3_SEG4 0 > + > +#define GC_BASE__INST4_SEG0 0 > +#define GC_BASE__INST4_SEG1 0 > +#define GC_BASE__INST4_SEG2 0 > +#define GC_BASE__INST4_SEG3 0 > +#define GC_BASE__INST4_SEG4 0 > + > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 > +#define MMHUB_BASE__INST0_SEG1 0 > +#define MMHUB_BASE__INST0_SEG2 0 > +#define MMHUB_BASE__INST0_SEG3 0 > +#define MMHUB_BASE__INST0_SEG4 0 > + > +#define MMHUB_BASE__INST1_SEG0 0 > +#define MMHUB_BASE__INST1_SEG1 0 > +#define MMHUB_BASE__INST1_SEG2 0 > +#define MMHUB_BASE__INST1_SEG3 0 > +#define MMHUB_BASE__INST1_SEG4 0 > + > +#define MMHUB_BASE__INST2_SEG0 0 > +#define MMHUB_BASE__INST2_SEG1 0 > +#define MMHUB_BASE__INST2_SEG2 0 > +#define MMHUB_BASE__INST2_SEG3 0 > +#define MMHUB_BASE__INST2_SEG4 0 > + > +#define MMHUB_BASE__INST3_SEG0 0 > +#define MMHUB_BASE__INST3_SEG1 0 > +#define MMHUB_BASE__INST3_SEG2 0 > +#define MMHUB_BASE__INST3_SEG3 0 > +#define MMHUB_BASE__INST3_SEG4 0 > + > +#define MMHUB_BASE__INST4_SEG0 0 > +#define MMHUB_BASE__INST4_SEG1 0 > +#define MMHUB_BASE__INST4_SEG2 0 > +#define MMHUB_BASE__INST4_SEG3 0 > +#define MMHUB_BASE__INST4_SEG4 0 > + > +#define RSMU_BASE__INST0_SEG0 0x00012000 > +#define RSMU_BASE__INST0_SEG1 0 > +#define RSMU_BASE__INST0_SEG2 0 > +#define RSMU_BASE__INST0_SEG3 0 > +#define RSMU_BASE__INST0_SEG4 0 > + > +#define RSMU_BASE__INST1_SEG0 0 > +#define RSMU_BASE__INST1_SEG1 0 > +#define RSMU_BASE__INST1_SEG2 0 > +#define RSMU_BASE__INST1_SEG3 0 > +#define RSMU_BASE__INST1_SEG4 0 > + > +#define RSMU_BASE__INST2_SEG0 0 > +#define RSMU_BASE__INST2_SEG1 0 > +#define RSMU_BASE__INST2_SEG2 0 > +#define RSMU_BASE__INST2_SEG3 0 > +#define RSMU_BASE__INST2_SEG4 0 > + > +#define RSMU_BASE__INST3_SEG0 0 > +#define RSMU_BASE__INST3_SEG1 0 > +#define RSMU_BASE__INST3_SEG2 0 > +#define RSMU_BASE__INST3_SEG3 0 > +#define RSMU_BASE__INST3_SEG4 0 > + > +#define RSMU_BASE__INST4_SEG0 0 > +#define RSMU_BASE__INST4_SEG1 0 > +#define RSMU_BASE__INST4_SEG2 0 > +#define RSMU_BASE__INST4_SEG3 0 > +#define RSMU_BASE__INST4_SEG4 0 > + > +#define HDP_BASE__INST0_SEG0 0x00000F20 > +#define HDP_BASE__INST0_SEG1 0 > +#define HDP_BASE__INST0_SEG2 0 > +#define HDP_BASE__INST0_SEG3 0 > +#define HDP_BASE__INST0_SEG4 0 > + > +#define HDP_BASE__INST1_SEG0 0 > +#define HDP_BASE__INST1_SEG1 0 > +#define HDP_BASE__INST1_SEG2 0 > +#define HDP_BASE__INST1_SEG3 0 > +#define HDP_BASE__INST1_SEG4 0 > + > +#define HDP_BASE__INST2_SEG0 0 > +#define HDP_BASE__INST2_SEG1 0 > +#define HDP_BASE__INST2_SEG2 0 > +#define HDP_BASE__INST2_SEG3 0 > +#define HDP_BASE__INST2_SEG4 0 > + > +#define HDP_BASE__INST3_SEG0 0 > +#define HDP_BASE__INST3_SEG1 0 > +#define HDP_BASE__INST3_SEG2 0 > +#define HDP_BASE__INST3_SEG3 0 > +#define HDP_BASE__INST3_SEG4 0 > + > +#define HDP_BASE__INST4_SEG0 0 > +#define HDP_BASE__INST4_SEG1 0 > +#define HDP_BASE__INST4_SEG2 0 > +#define HDP_BASE__INST4_SEG3 0 > +#define HDP_BASE__INST4_SEG4 0 > + > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 > +#define OSSSYS_BASE__INST0_SEG1 0 > +#define OSSSYS_BASE__INST0_SEG2 0 > +#define OSSSYS_BASE__INST0_SEG3 0 > +#define OSSSYS_BASE__INST0_SEG4 0 > + > +#define OSSSYS_BASE__INST1_SEG0 0 > +#define OSSSYS_BASE__INST1_SEG1 0 > +#define OSSSYS_BASE__INST1_SEG2 0 > +#define OSSSYS_BASE__INST1_SEG3 0 > +#define OSSSYS_BASE__INST1_SEG4 0 > + > +#define OSSSYS_BASE__INST2_SEG0 0 > +#define OSSSYS_BASE__INST2_SEG1 0 > +#define OSSSYS_BASE__INST2_SEG2 0 > +#define OSSSYS_BASE__INST2_SEG3 0 > +#define OSSSYS_BASE__INST2_SEG4 0 > + > +#define OSSSYS_BASE__INST3_SEG0 0 > +#define OSSSYS_BASE__INST3_SEG1 0 > +#define OSSSYS_BASE__INST3_SEG2 0 > +#define OSSSYS_BASE__INST3_SEG3 0 > +#define OSSSYS_BASE__INST3_SEG4 0 > + > +#define OSSSYS_BASE__INST4_SEG0 0 > +#define OSSSYS_BASE__INST4_SEG1 0 > +#define OSSSYS_BASE__INST4_SEG2 0 > +#define OSSSYS_BASE__INST4_SEG3 0 > +#define OSSSYS_BASE__INST4_SEG4 0 > + > +#define SDMA0_BASE__INST0_SEG0 0x00001260 > +#define SDMA0_BASE__INST0_SEG1 0 > +#define SDMA0_BASE__INST0_SEG2 0 > +#define SDMA0_BASE__INST0_SEG3 0 > +#define SDMA0_BASE__INST0_SEG4 0 > + > +#define SDMA0_BASE__INST1_SEG0 0 > +#define SDMA0_BASE__INST1_SEG1 0 > +#define SDMA0_BASE__INST1_SEG2 0 > +#define SDMA0_BASE__INST1_SEG3 0 > +#define SDMA0_BASE__INST1_SEG4 0 > + > +#define SDMA0_BASE__INST2_SEG0 0 > +#define SDMA0_BASE__INST2_SEG1 0 > +#define SDMA0_BASE__INST2_SEG2 0 > +#define SDMA0_BASE__INST2_SEG3 0 > +#define SDMA0_BASE__INST2_SEG4 0 > + > +#define SDMA0_BASE__INST3_SEG0 0 > +#define SDMA0_BASE__INST3_SEG1 0 > +#define SDMA0_BASE__INST3_SEG2 0 > +#define SDMA0_BASE__INST3_SEG3 0 > +#define SDMA0_BASE__INST3_SEG4 0 > + > +#define SDMA0_BASE__INST4_SEG0 0 > +#define SDMA0_BASE__INST4_SEG1 0 > +#define SDMA0_BASE__INST4_SEG2 0 > +#define SDMA0_BASE__INST4_SEG3 0 > +#define SDMA0_BASE__INST4_SEG4 0 > + > +#define SDMA1_BASE__INST0_SEG0 0x00001460 > +#define SDMA1_BASE__INST0_SEG1 0 > +#define SDMA1_BASE__INST0_SEG2 0 > +#define SDMA1_BASE__INST0_SEG3 0 > +#define SDMA1_BASE__INST0_SEG4 0 > + > +#define SDMA1_BASE__INST1_SEG0 0 > +#define SDMA1_BASE__INST1_SEG1 0 > +#define SDMA1_BASE__INST1_SEG2 0 > +#define SDMA1_BASE__INST1_SEG3 0 > +#define SDMA1_BASE__INST1_SEG4 0 > + > +#define SDMA1_BASE__INST2_SEG0 0 > +#define SDMA1_BASE__INST2_SEG1 0 > +#define SDMA1_BASE__INST2_SEG2 0 > +#define SDMA1_BASE__INST2_SEG3 0 > +#define SDMA1_BASE__INST2_SEG4 0 > + > +#define SDMA1_BASE__INST3_SEG0 0 > +#define SDMA1_BASE__INST3_SEG1 0 > +#define SDMA1_BASE__INST3_SEG2 0 > +#define SDMA1_BASE__INST3_SEG3 0 > +#define SDMA1_BASE__INST3_SEG4 0 > + > +#define SDMA1_BASE__INST4_SEG0 0 > +#define SDMA1_BASE__INST4_SEG1 0 > +#define SDMA1_BASE__INST4_SEG2 0 > +#define SDMA1_BASE__INST4_SEG3 0 > +#define SDMA1_BASE__INST4_SEG4 0 > + > +#define XDMA_BASE__INST0_SEG0 0x00003400 > +#define XDMA_BASE__INST0_SEG1 0 > +#define XDMA_BASE__INST0_SEG2 0 > +#define XDMA_BASE__INST0_SEG3 0 > +#define XDMA_BASE__INST0_SEG4 0 > + > +#define XDMA_BASE__INST1_SEG0 0 > +#define XDMA_BASE__INST1_SEG1 0 > +#define XDMA_BASE__INST1_SEG2 0 > +#define XDMA_BASE__INST1_SEG3 0 > +#define XDMA_BASE__INST1_SEG4 0 > + > +#define XDMA_BASE__INST2_SEG0 0 > +#define XDMA_BASE__INST2_SEG1 0 > +#define XDMA_BASE__INST2_SEG2 0 > +#define XDMA_BASE__INST2_SEG3 0 > +#define XDMA_BASE__INST2_SEG4 0 > + > +#define XDMA_BASE__INST3_SEG0 0 > +#define XDMA_BASE__INST3_SEG1 0 > +#define XDMA_BASE__INST3_SEG2 0 > +#define XDMA_BASE__INST3_SEG3 0 > +#define XDMA_BASE__INST3_SEG4 0 > + > +#define XDMA_BASE__INST4_SEG0 0 > +#define XDMA_BASE__INST4_SEG1 0 > +#define XDMA_BASE__INST4_SEG2 0 > +#define XDMA_BASE__INST4_SEG3 0 > +#define XDMA_BASE__INST4_SEG4 0 > + > +#define UMC_BASE__INST0_SEG0 0x00014000 > +#define UMC_BASE__INST0_SEG1 0 > +#define UMC_BASE__INST0_SEG2 0 > +#define UMC_BASE__INST0_SEG3 0 > +#define UMC_BASE__INST0_SEG4 0 > + > +#define UMC_BASE__INST1_SEG0 0 > +#define UMC_BASE__INST1_SEG1 0 > +#define UMC_BASE__INST1_SEG2 0 > +#define UMC_BASE__INST1_SEG3 0 > +#define UMC_BASE__INST1_SEG4 0 > + > +#define UMC_BASE__INST2_SEG0 0 > +#define UMC_BASE__INST2_SEG1 0 > +#define UMC_BASE__INST2_SEG2 0 > +#define UMC_BASE__INST2_SEG3 0 > +#define UMC_BASE__INST2_SEG4 0 > + > +#define UMC_BASE__INST3_SEG0 0 > +#define UMC_BASE__INST3_SEG1 0 > +#define UMC_BASE__INST3_SEG2 0 > +#define UMC_BASE__INST3_SEG3 0 > +#define UMC_BASE__INST3_SEG4 0 > + > +#define UMC_BASE__INST4_SEG0 0 > +#define UMC_BASE__INST4_SEG1 0 > +#define UMC_BASE__INST4_SEG2 0 > +#define UMC_BASE__INST4_SEG3 0 > +#define UMC_BASE__INST4_SEG4 0 > + > +#define THM_BASE__INST0_SEG0 0x00016600 > +#define THM_BASE__INST0_SEG1 0 > +#define THM_BASE__INST0_SEG2 0 > +#define THM_BASE__INST0_SEG3 0 > +#define THM_BASE__INST0_SEG4 0 > + > +#define THM_BASE__INST1_SEG0 0 > +#define THM_BASE__INST1_SEG1 0 > +#define THM_BASE__INST1_SEG2 0 > +#define THM_BASE__INST1_SEG3 0 > +#define THM_BASE__INST1_SEG4 0 > + > +#define THM_BASE__INST2_SEG0 0 > +#define THM_BASE__INST2_SEG1 0 > +#define THM_BASE__INST2_SEG2 0 > +#define THM_BASE__INST2_SEG3 0 > +#define THM_BASE__INST2_SEG4 0 > + > +#define THM_BASE__INST3_SEG0 0 > +#define THM_BASE__INST3_SEG1 0 > +#define THM_BASE__INST3_SEG2 0 > +#define THM_BASE__INST3_SEG3 0 > +#define THM_BASE__INST3_SEG4 0 > + > +#define THM_BASE__INST4_SEG0 0 > +#define THM_BASE__INST4_SEG1 0 > +#define THM_BASE__INST4_SEG2 0 > +#define THM_BASE__INST4_SEG3 0 > +#define THM_BASE__INST4_SEG4 0 > + > +#define SMUIO_BASE__INST0_SEG0 0x00016800 > +#define SMUIO_BASE__INST0_SEG1 0 > +#define SMUIO_BASE__INST0_SEG2 0 > +#define SMUIO_BASE__INST0_SEG3 0 > +#define SMUIO_BASE__INST0_SEG4 0 > + > +#define SMUIO_BASE__INST1_SEG0 0 > +#define SMUIO_BASE__INST1_SEG1 0 > +#define SMUIO_BASE__INST1_SEG2 0 > +#define SMUIO_BASE__INST1_SEG3 0 > +#define SMUIO_BASE__INST1_SEG4 0 > + > +#define SMUIO_BASE__INST2_SEG0 0 > +#define SMUIO_BASE__INST2_SEG1 0 > +#define SMUIO_BASE__INST2_SEG2 0 > +#define SMUIO_BASE__INST2_SEG3 0 > +#define SMUIO_BASE__INST2_SEG4 0 > + > +#define SMUIO_BASE__INST3_SEG0 0 > +#define SMUIO_BASE__INST3_SEG1 0 > +#define SMUIO_BASE__INST3_SEG2 0 > +#define SMUIO_BASE__INST3_SEG3 0 > +#define SMUIO_BASE__INST3_SEG4 0 > + > +#define SMUIO_BASE__INST4_SEG0 0 > +#define SMUIO_BASE__INST4_SEG1 0 > +#define SMUIO_BASE__INST4_SEG2 0 > +#define SMUIO_BASE__INST4_SEG3 0 > +#define SMUIO_BASE__INST4_SEG4 0 > + > +#define PWR_BASE__INST0_SEG0 0x00016A00 > +#define PWR_BASE__INST0_SEG1 0 > +#define PWR_BASE__INST0_SEG2 0 > +#define PWR_BASE__INST0_SEG3 0 > +#define PWR_BASE__INST0_SEG4 0 > + > +#define PWR_BASE__INST1_SEG0 0 > +#define PWR_BASE__INST1_SEG1 0 > +#define PWR_BASE__INST1_SEG2 0 > +#define PWR_BASE__INST1_SEG3 0 > +#define PWR_BASE__INST1_SEG4 0 > + > +#define PWR_BASE__INST2_SEG0 0 > +#define PWR_BASE__INST2_SEG1 0 > +#define PWR_BASE__INST2_SEG2 0 > +#define PWR_BASE__INST2_SEG3 0 > +#define PWR_BASE__INST2_SEG4 0 > + > +#define PWR_BASE__INST3_SEG0 0 > +#define PWR_BASE__INST3_SEG1 0 > +#define PWR_BASE__INST3_SEG2 0 > +#define PWR_BASE__INST3_SEG3 0 > +#define PWR_BASE__INST3_SEG4 0 > + > +#define PWR_BASE__INST4_SEG0 0 > +#define PWR_BASE__INST4_SEG1 0 > +#define PWR_BASE__INST4_SEG2 0 > +#define PWR_BASE__INST4_SEG3 0 > +#define PWR_BASE__INST4_SEG4 0 > + > +#define CLK_BASE__INST0_SEG0 0x00016C00 > +#define CLK_BASE__INST0_SEG1 0 > +#define CLK_BASE__INST0_SEG2 0 > +#define CLK_BASE__INST0_SEG3 0 > +#define CLK_BASE__INST0_SEG4 0 > + > +#define CLK_BASE__INST1_SEG0 0x00016E00 > +#define CLK_BASE__INST1_SEG1 0 > +#define CLK_BASE__INST1_SEG2 0 > +#define CLK_BASE__INST1_SEG3 0 > +#define CLK_BASE__INST1_SEG4 0 > + > +#define CLK_BASE__INST2_SEG0 0x00017000 > +#define CLK_BASE__INST2_SEG1 0 > +#define CLK_BASE__INST2_SEG2 0 > +#define CLK_BASE__INST2_SEG3 0 > +#define CLK_BASE__INST2_SEG4 0 > + > +#define CLK_BASE__INST3_SEG0 0x00017200 > +#define CLK_BASE__INST3_SEG1 0 > +#define CLK_BASE__INST3_SEG2 0 > +#define CLK_BASE__INST3_SEG3 0 > +#define CLK_BASE__INST3_SEG4 0 > + > +#define CLK_BASE__INST4_SEG0 0x00017E00 > +#define CLK_BASE__INST4_SEG1 0 > +#define CLK_BASE__INST4_SEG2 0 > +#define CLK_BASE__INST4_SEG3 0 > +#define CLK_BASE__INST4_SEG4 0 > + > +#define FUSE_BASE__INST0_SEG0 0x00017400 > +#define FUSE_BASE__INST0_SEG1 0 > +#define FUSE_BASE__INST0_SEG2 0 > +#define FUSE_BASE__INST0_SEG3 0 > +#define FUSE_BASE__INST0_SEG4 0 > + > +#define FUSE_BASE__INST1_SEG0 0 > +#define FUSE_BASE__INST1_SEG1 0 > +#define FUSE_BASE__INST1_SEG2 0 > +#define FUSE_BASE__INST1_SEG3 0 > +#define FUSE_BASE__INST1_SEG4 0 > + > +#define FUSE_BASE__INST2_SEG0 0 > +#define FUSE_BASE__INST2_SEG1 0 > +#define FUSE_BASE__INST2_SEG2 0 > +#define FUSE_BASE__INST2_SEG3 0 > +#define FUSE_BASE__INST2_SEG4 0 > + > +#define FUSE_BASE__INST3_SEG0 0 > +#define FUSE_BASE__INST3_SEG1 0 > +#define FUSE_BASE__INST3_SEG2 0 > +#define FUSE_BASE__INST3_SEG3 0 > +#define FUSE_BASE__INST3_SEG4 0 > + > +#define FUSE_BASE__INST4_SEG0 0 > +#define FUSE_BASE__INST4_SEG1 0 > +#define FUSE_BASE__INST4_SEG2 0 > +#define FUSE_BASE__INST4_SEG3 0 > +#define FUSE_BASE__INST4_SEG4 0 > + > + > +#endif > + > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org> 2017-11-27 18:54 ` Tom St Denis @ 2017-11-27 19:17 ` Christian König [not found] ` <2db922e4-fe49-7499-38f1-a3b2c8e07cf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 1 sibling, 1 reply; 14+ messages in thread From: Christian König @ 2017-11-27 19:17 UTC (permalink / raw) To: Shaoyun Liu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW First of let us fix the obvious style problems. Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> > --- > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++ > 1 file changed, 1248 insertions(+) > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > new file mode 100644 > index 0000000..76cb748 > --- /dev/null > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > @@ -0,0 +1,1248 @@ > +#ifndef _ip_offset_1_HEADER > +#define _ip_offset_1_HEADER Names for preprocessor defines should be capitable. > + > +#define MAX_INSTANCE 5 > +#define MAX_SEGMENT 5 > + > + > +struct IP_BASE_INSTANCE Structure names should be lower case. And we need an amdgpu_ or at least amd_ prefix here. Regards, Christian. > +{ > + unsigned int segment[MAX_SEGMENT]; > +}; > + > +struct IP_BASE > +{ > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; > +}; > + > + > +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment No "//" in kernel code please. > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, > + { { 0x00016E00, 0, 0, 0, 0 } }, > + { { 0x00017000, 0, 0, 0, 0 } }, > + { { 0x00017200, 0, 0, 0, 0 } }, > + { { 0x00017E00, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > + > + > +#define NBIF_BASE__INST0_SEG0 0x00000000 > +#define NBIF_BASE__INST0_SEG1 0x00000014 > +#define NBIF_BASE__INST0_SEG2 0x00000D20 > +#define NBIF_BASE__INST0_SEG3 0x00010400 > +#define NBIF_BASE__INST0_SEG4 0 > + > +#define NBIF_BASE__INST1_SEG0 0 > +#define NBIF_BASE__INST1_SEG1 0 > +#define NBIF_BASE__INST1_SEG2 0 > +#define NBIF_BASE__INST1_SEG3 0 > +#define NBIF_BASE__INST1_SEG4 0 > + > +#define NBIF_BASE__INST2_SEG0 0 > +#define NBIF_BASE__INST2_SEG1 0 > +#define NBIF_BASE__INST2_SEG2 0 > +#define NBIF_BASE__INST2_SEG3 0 > +#define NBIF_BASE__INST2_SEG4 0 > + > +#define NBIF_BASE__INST3_SEG0 0 > +#define NBIF_BASE__INST3_SEG1 0 > +#define NBIF_BASE__INST3_SEG2 0 > +#define NBIF_BASE__INST3_SEG3 0 > +#define NBIF_BASE__INST3_SEG4 0 > + > +#define NBIF_BASE__INST4_SEG0 0 > +#define NBIF_BASE__INST4_SEG1 0 > +#define NBIF_BASE__INST4_SEG2 0 > +#define NBIF_BASE__INST4_SEG3 0 > +#define NBIF_BASE__INST4_SEG4 0 > + > +#define NBIO_BASE__INST0_SEG0 0x00000000 > +#define NBIO_BASE__INST0_SEG1 0x00000014 > +#define NBIO_BASE__INST0_SEG2 0x00000D20 > +#define NBIO_BASE__INST0_SEG3 0x00010400 > +#define NBIO_BASE__INST0_SEG4 0 > + > +#define NBIO_BASE__INST1_SEG0 0 > +#define NBIO_BASE__INST1_SEG1 0 > +#define NBIO_BASE__INST1_SEG2 0 > +#define NBIO_BASE__INST1_SEG3 0 > +#define NBIO_BASE__INST1_SEG4 0 > + > +#define NBIO_BASE__INST2_SEG0 0 > +#define NBIO_BASE__INST2_SEG1 0 > +#define NBIO_BASE__INST2_SEG2 0 > +#define NBIO_BASE__INST2_SEG3 0 > +#define NBIO_BASE__INST2_SEG4 0 > + > +#define NBIO_BASE__INST3_SEG0 0 > +#define NBIO_BASE__INST3_SEG1 0 > +#define NBIO_BASE__INST3_SEG2 0 > +#define NBIO_BASE__INST3_SEG3 0 > +#define NBIO_BASE__INST3_SEG4 0 > + > +#define NBIO_BASE__INST4_SEG0 0 > +#define NBIO_BASE__INST4_SEG1 0 > +#define NBIO_BASE__INST4_SEG2 0 > +#define NBIO_BASE__INST4_SEG3 0 > +#define NBIO_BASE__INST4_SEG4 0 > + > +#define DCE_BASE__INST0_SEG0 0x00000012 > +#define DCE_BASE__INST0_SEG1 0x000000C0 > +#define DCE_BASE__INST0_SEG2 0x000034C0 > +#define DCE_BASE__INST0_SEG3 0 > +#define DCE_BASE__INST0_SEG4 0 > + > +#define DCE_BASE__INST1_SEG0 0 > +#define DCE_BASE__INST1_SEG1 0 > +#define DCE_BASE__INST1_SEG2 0 > +#define DCE_BASE__INST1_SEG3 0 > +#define DCE_BASE__INST1_SEG4 0 > + > +#define DCE_BASE__INST2_SEG0 0 > +#define DCE_BASE__INST2_SEG1 0 > +#define DCE_BASE__INST2_SEG2 0 > +#define DCE_BASE__INST2_SEG3 0 > +#define DCE_BASE__INST2_SEG4 0 > + > +#define DCE_BASE__INST3_SEG0 0 > +#define DCE_BASE__INST3_SEG1 0 > +#define DCE_BASE__INST3_SEG2 0 > +#define DCE_BASE__INST3_SEG3 0 > +#define DCE_BASE__INST3_SEG4 0 > + > +#define DCE_BASE__INST4_SEG0 0 > +#define DCE_BASE__INST4_SEG1 0 > +#define DCE_BASE__INST4_SEG2 0 > +#define DCE_BASE__INST4_SEG3 0 > +#define DCE_BASE__INST4_SEG4 0 > + > +#define DCN_BASE__INST0_SEG0 0x00000012 > +#define DCN_BASE__INST0_SEG1 0x000000C0 > +#define DCN_BASE__INST0_SEG2 0x000034C0 > +#define DCN_BASE__INST0_SEG3 0 > +#define DCN_BASE__INST0_SEG4 0 > + > +#define DCN_BASE__INST1_SEG0 0 > +#define DCN_BASE__INST1_SEG1 0 > +#define DCN_BASE__INST1_SEG2 0 > +#define DCN_BASE__INST1_SEG3 0 > +#define DCN_BASE__INST1_SEG4 0 > + > +#define DCN_BASE__INST2_SEG0 0 > +#define DCN_BASE__INST2_SEG1 0 > +#define DCN_BASE__INST2_SEG2 0 > +#define DCN_BASE__INST2_SEG3 0 > +#define DCN_BASE__INST2_SEG4 0 > + > +#define DCN_BASE__INST3_SEG0 0 > +#define DCN_BASE__INST3_SEG1 0 > +#define DCN_BASE__INST3_SEG2 0 > +#define DCN_BASE__INST3_SEG3 0 > +#define DCN_BASE__INST3_SEG4 0 > + > +#define DCN_BASE__INST4_SEG0 0 > +#define DCN_BASE__INST4_SEG1 0 > +#define DCN_BASE__INST4_SEG2 0 > +#define DCN_BASE__INST4_SEG3 0 > +#define DCN_BASE__INST4_SEG4 0 > + > +#define MP0_BASE__INST0_SEG0 0x00016000 > +#define MP0_BASE__INST0_SEG1 0 > +#define MP0_BASE__INST0_SEG2 0 > +#define MP0_BASE__INST0_SEG3 0 > +#define MP0_BASE__INST0_SEG4 0 > + > +#define MP0_BASE__INST1_SEG0 0 > +#define MP0_BASE__INST1_SEG1 0 > +#define MP0_BASE__INST1_SEG2 0 > +#define MP0_BASE__INST1_SEG3 0 > +#define MP0_BASE__INST1_SEG4 0 > + > +#define MP0_BASE__INST2_SEG0 0 > +#define MP0_BASE__INST2_SEG1 0 > +#define MP0_BASE__INST2_SEG2 0 > +#define MP0_BASE__INST2_SEG3 0 > +#define MP0_BASE__INST2_SEG4 0 > + > +#define MP0_BASE__INST3_SEG0 0 > +#define MP0_BASE__INST3_SEG1 0 > +#define MP0_BASE__INST3_SEG2 0 > +#define MP0_BASE__INST3_SEG3 0 > +#define MP0_BASE__INST3_SEG4 0 > + > +#define MP0_BASE__INST4_SEG0 0 > +#define MP0_BASE__INST4_SEG1 0 > +#define MP0_BASE__INST4_SEG2 0 > +#define MP0_BASE__INST4_SEG3 0 > +#define MP0_BASE__INST4_SEG4 0 > + > +#define MP1_BASE__INST0_SEG0 0x00016000 > +#define MP1_BASE__INST0_SEG1 0 > +#define MP1_BASE__INST0_SEG2 0 > +#define MP1_BASE__INST0_SEG3 0 > +#define MP1_BASE__INST0_SEG4 0 > + > +#define MP1_BASE__INST1_SEG0 0 > +#define MP1_BASE__INST1_SEG1 0 > +#define MP1_BASE__INST1_SEG2 0 > +#define MP1_BASE__INST1_SEG3 0 > +#define MP1_BASE__INST1_SEG4 0 > + > +#define MP1_BASE__INST2_SEG0 0 > +#define MP1_BASE__INST2_SEG1 0 > +#define MP1_BASE__INST2_SEG2 0 > +#define MP1_BASE__INST2_SEG3 0 > +#define MP1_BASE__INST2_SEG4 0 > + > +#define MP1_BASE__INST3_SEG0 0 > +#define MP1_BASE__INST3_SEG1 0 > +#define MP1_BASE__INST3_SEG2 0 > +#define MP1_BASE__INST3_SEG3 0 > +#define MP1_BASE__INST3_SEG4 0 > + > +#define MP1_BASE__INST4_SEG0 0 > +#define MP1_BASE__INST4_SEG1 0 > +#define MP1_BASE__INST4_SEG2 0 > +#define MP1_BASE__INST4_SEG3 0 > +#define MP1_BASE__INST4_SEG4 0 > + > +#define MP2_BASE__INST0_SEG0 0x00016000 > +#define MP2_BASE__INST0_SEG1 0 > +#define MP2_BASE__INST0_SEG2 0 > +#define MP2_BASE__INST0_SEG3 0 > +#define MP2_BASE__INST0_SEG4 0 > + > +#define MP2_BASE__INST1_SEG0 0 > +#define MP2_BASE__INST1_SEG1 0 > +#define MP2_BASE__INST1_SEG2 0 > +#define MP2_BASE__INST1_SEG3 0 > +#define MP2_BASE__INST1_SEG4 0 > + > +#define MP2_BASE__INST2_SEG0 0 > +#define MP2_BASE__INST2_SEG1 0 > +#define MP2_BASE__INST2_SEG2 0 > +#define MP2_BASE__INST2_SEG3 0 > +#define MP2_BASE__INST2_SEG4 0 > + > +#define MP2_BASE__INST3_SEG0 0 > +#define MP2_BASE__INST3_SEG1 0 > +#define MP2_BASE__INST3_SEG2 0 > +#define MP2_BASE__INST3_SEG3 0 > +#define MP2_BASE__INST3_SEG4 0 > + > +#define MP2_BASE__INST4_SEG0 0 > +#define MP2_BASE__INST4_SEG1 0 > +#define MP2_BASE__INST4_SEG2 0 > +#define MP2_BASE__INST4_SEG3 0 > +#define MP2_BASE__INST4_SEG4 0 > + > +#define DF_BASE__INST0_SEG0 0x00007000 > +#define DF_BASE__INST0_SEG1 0 > +#define DF_BASE__INST0_SEG2 0 > +#define DF_BASE__INST0_SEG3 0 > +#define DF_BASE__INST0_SEG4 0 > + > +#define DF_BASE__INST1_SEG0 0 > +#define DF_BASE__INST1_SEG1 0 > +#define DF_BASE__INST1_SEG2 0 > +#define DF_BASE__INST1_SEG3 0 > +#define DF_BASE__INST1_SEG4 0 > + > +#define DF_BASE__INST2_SEG0 0 > +#define DF_BASE__INST2_SEG1 0 > +#define DF_BASE__INST2_SEG2 0 > +#define DF_BASE__INST2_SEG3 0 > +#define DF_BASE__INST2_SEG4 0 > + > +#define DF_BASE__INST3_SEG0 0 > +#define DF_BASE__INST3_SEG1 0 > +#define DF_BASE__INST3_SEG2 0 > +#define DF_BASE__INST3_SEG3 0 > +#define DF_BASE__INST3_SEG4 0 > + > +#define DF_BASE__INST4_SEG0 0 > +#define DF_BASE__INST4_SEG1 0 > +#define DF_BASE__INST4_SEG2 0 > +#define DF_BASE__INST4_SEG3 0 > +#define DF_BASE__INST4_SEG4 0 > + > +#define UVD_BASE__INST0_SEG0 0x00007800 > +#define UVD_BASE__INST0_SEG1 0x00007E00 > +#define UVD_BASE__INST0_SEG2 0 > +#define UVD_BASE__INST0_SEG3 0 > +#define UVD_BASE__INST0_SEG4 0 > + > +#define UVD_BASE__INST1_SEG0 0 > +#define UVD_BASE__INST1_SEG1 0 > +#define UVD_BASE__INST1_SEG2 0 > +#define UVD_BASE__INST1_SEG3 0 > +#define UVD_BASE__INST1_SEG4 0 > + > +#define UVD_BASE__INST2_SEG0 0 > +#define UVD_BASE__INST2_SEG1 0 > +#define UVD_BASE__INST2_SEG2 0 > +#define UVD_BASE__INST2_SEG3 0 > +#define UVD_BASE__INST2_SEG4 0 > + > +#define UVD_BASE__INST3_SEG0 0 > +#define UVD_BASE__INST3_SEG1 0 > +#define UVD_BASE__INST3_SEG2 0 > +#define UVD_BASE__INST3_SEG3 0 > +#define UVD_BASE__INST3_SEG4 0 > + > +#define UVD_BASE__INST4_SEG0 0 > +#define UVD_BASE__INST4_SEG1 0 > +#define UVD_BASE__INST4_SEG2 0 > +#define UVD_BASE__INST4_SEG3 0 > +#define UVD_BASE__INST4_SEG4 0 > + > +#define VCN_BASE__INST0_SEG0 0x00007800 > +#define VCN_BASE__INST0_SEG1 0x00007E00 > +#define VCN_BASE__INST0_SEG2 0 > +#define VCN_BASE__INST0_SEG3 0 > +#define VCN_BASE__INST0_SEG4 0 > + > +#define VCN_BASE__INST1_SEG0 0 > +#define VCN_BASE__INST1_SEG1 0 > +#define VCN_BASE__INST1_SEG2 0 > +#define VCN_BASE__INST1_SEG3 0 > +#define VCN_BASE__INST1_SEG4 0 > + > +#define VCN_BASE__INST2_SEG0 0 > +#define VCN_BASE__INST2_SEG1 0 > +#define VCN_BASE__INST2_SEG2 0 > +#define VCN_BASE__INST2_SEG3 0 > +#define VCN_BASE__INST2_SEG4 0 > + > +#define VCN_BASE__INST3_SEG0 0 > +#define VCN_BASE__INST3_SEG1 0 > +#define VCN_BASE__INST3_SEG2 0 > +#define VCN_BASE__INST3_SEG3 0 > +#define VCN_BASE__INST3_SEG4 0 > + > +#define VCN_BASE__INST4_SEG0 0 > +#define VCN_BASE__INST4_SEG1 0 > +#define VCN_BASE__INST4_SEG2 0 > +#define VCN_BASE__INST4_SEG3 0 > +#define VCN_BASE__INST4_SEG4 0 > + > +#define DBGU_BASE__INST0_SEG0 0x00000180 > +#define DBGU_BASE__INST0_SEG1 0x000001A0 > +#define DBGU_BASE__INST0_SEG2 0 > +#define DBGU_BASE__INST0_SEG3 0 > +#define DBGU_BASE__INST0_SEG4 0 > + > +#define DBGU_BASE__INST1_SEG0 0 > +#define DBGU_BASE__INST1_SEG1 0 > +#define DBGU_BASE__INST1_SEG2 0 > +#define DBGU_BASE__INST1_SEG3 0 > +#define DBGU_BASE__INST1_SEG4 0 > + > +#define DBGU_BASE__INST2_SEG0 0 > +#define DBGU_BASE__INST2_SEG1 0 > +#define DBGU_BASE__INST2_SEG2 0 > +#define DBGU_BASE__INST2_SEG3 0 > +#define DBGU_BASE__INST2_SEG4 0 > + > +#define DBGU_BASE__INST3_SEG0 0 > +#define DBGU_BASE__INST3_SEG1 0 > +#define DBGU_BASE__INST3_SEG2 0 > +#define DBGU_BASE__INST3_SEG3 0 > +#define DBGU_BASE__INST3_SEG4 0 > + > +#define DBGU_BASE__INST4_SEG0 0 > +#define DBGU_BASE__INST4_SEG1 0 > +#define DBGU_BASE__INST4_SEG2 0 > +#define DBGU_BASE__INST4_SEG3 0 > +#define DBGU_BASE__INST4_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 > +#define DBGU_NBIO_BASE__INST0_SEG1 0 > +#define DBGU_NBIO_BASE__INST0_SEG2 0 > +#define DBGU_NBIO_BASE__INST0_SEG3 0 > +#define DBGU_NBIO_BASE__INST0_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST1_SEG0 0 > +#define DBGU_NBIO_BASE__INST1_SEG1 0 > +#define DBGU_NBIO_BASE__INST1_SEG2 0 > +#define DBGU_NBIO_BASE__INST1_SEG3 0 > +#define DBGU_NBIO_BASE__INST1_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST2_SEG0 0 > +#define DBGU_NBIO_BASE__INST2_SEG1 0 > +#define DBGU_NBIO_BASE__INST2_SEG2 0 > +#define DBGU_NBIO_BASE__INST2_SEG3 0 > +#define DBGU_NBIO_BASE__INST2_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST3_SEG0 0 > +#define DBGU_NBIO_BASE__INST3_SEG1 0 > +#define DBGU_NBIO_BASE__INST3_SEG2 0 > +#define DBGU_NBIO_BASE__INST3_SEG3 0 > +#define DBGU_NBIO_BASE__INST3_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST4_SEG0 0 > +#define DBGU_NBIO_BASE__INST4_SEG1 0 > +#define DBGU_NBIO_BASE__INST4_SEG2 0 > +#define DBGU_NBIO_BASE__INST4_SEG3 0 > +#define DBGU_NBIO_BASE__INST4_SEG4 0 > + > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 > +#define DBGU_IO_BASE__INST0_SEG1 0 > +#define DBGU_IO_BASE__INST0_SEG2 0 > +#define DBGU_IO_BASE__INST0_SEG3 0 > +#define DBGU_IO_BASE__INST0_SEG4 0 > + > +#define DBGU_IO_BASE__INST1_SEG0 0 > +#define DBGU_IO_BASE__INST1_SEG1 0 > +#define DBGU_IO_BASE__INST1_SEG2 0 > +#define DBGU_IO_BASE__INST1_SEG3 0 > +#define DBGU_IO_BASE__INST1_SEG4 0 > + > +#define DBGU_IO_BASE__INST2_SEG0 0 > +#define DBGU_IO_BASE__INST2_SEG1 0 > +#define DBGU_IO_BASE__INST2_SEG2 0 > +#define DBGU_IO_BASE__INST2_SEG3 0 > +#define DBGU_IO_BASE__INST2_SEG4 0 > + > +#define DBGU_IO_BASE__INST3_SEG0 0 > +#define DBGU_IO_BASE__INST3_SEG1 0 > +#define DBGU_IO_BASE__INST3_SEG2 0 > +#define DBGU_IO_BASE__INST3_SEG3 0 > +#define DBGU_IO_BASE__INST3_SEG4 0 > + > +#define DBGU_IO_BASE__INST4_SEG0 0 > +#define DBGU_IO_BASE__INST4_SEG1 0 > +#define DBGU_IO_BASE__INST4_SEG2 0 > +#define DBGU_IO_BASE__INST4_SEG3 0 > +#define DBGU_IO_BASE__INST4_SEG4 0 > + > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 > +#define DFX_DAP_BASE__INST0_SEG1 0 > +#define DFX_DAP_BASE__INST0_SEG2 0 > +#define DFX_DAP_BASE__INST0_SEG3 0 > +#define DFX_DAP_BASE__INST0_SEG4 0 > + > +#define DFX_DAP_BASE__INST1_SEG0 0 > +#define DFX_DAP_BASE__INST1_SEG1 0 > +#define DFX_DAP_BASE__INST1_SEG2 0 > +#define DFX_DAP_BASE__INST1_SEG3 0 > +#define DFX_DAP_BASE__INST1_SEG4 0 > + > +#define DFX_DAP_BASE__INST2_SEG0 0 > +#define DFX_DAP_BASE__INST2_SEG1 0 > +#define DFX_DAP_BASE__INST2_SEG2 0 > +#define DFX_DAP_BASE__INST2_SEG3 0 > +#define DFX_DAP_BASE__INST2_SEG4 0 > + > +#define DFX_DAP_BASE__INST3_SEG0 0 > +#define DFX_DAP_BASE__INST3_SEG1 0 > +#define DFX_DAP_BASE__INST3_SEG2 0 > +#define DFX_DAP_BASE__INST3_SEG3 0 > +#define DFX_DAP_BASE__INST3_SEG4 0 > + > +#define DFX_DAP_BASE__INST4_SEG0 0 > +#define DFX_DAP_BASE__INST4_SEG1 0 > +#define DFX_DAP_BASE__INST4_SEG2 0 > +#define DFX_DAP_BASE__INST4_SEG3 0 > +#define DFX_DAP_BASE__INST4_SEG4 0 > + > +#define DFX_BASE__INST0_SEG0 0x00000580 > +#define DFX_BASE__INST0_SEG1 0 > +#define DFX_BASE__INST0_SEG2 0 > +#define DFX_BASE__INST0_SEG3 0 > +#define DFX_BASE__INST0_SEG4 0 > + > +#define DFX_BASE__INST1_SEG0 0 > +#define DFX_BASE__INST1_SEG1 0 > +#define DFX_BASE__INST1_SEG2 0 > +#define DFX_BASE__INST1_SEG3 0 > +#define DFX_BASE__INST1_SEG4 0 > + > +#define DFX_BASE__INST2_SEG0 0 > +#define DFX_BASE__INST2_SEG1 0 > +#define DFX_BASE__INST2_SEG2 0 > +#define DFX_BASE__INST2_SEG3 0 > +#define DFX_BASE__INST2_SEG4 0 > + > +#define DFX_BASE__INST3_SEG0 0 > +#define DFX_BASE__INST3_SEG1 0 > +#define DFX_BASE__INST3_SEG2 0 > +#define DFX_BASE__INST3_SEG3 0 > +#define DFX_BASE__INST3_SEG4 0 > + > +#define DFX_BASE__INST4_SEG0 0 > +#define DFX_BASE__INST4_SEG1 0 > +#define DFX_BASE__INST4_SEG2 0 > +#define DFX_BASE__INST4_SEG3 0 > +#define DFX_BASE__INST4_SEG4 0 > + > +#define ISP_BASE__INST0_SEG0 0x00018000 > +#define ISP_BASE__INST0_SEG1 0 > +#define ISP_BASE__INST0_SEG2 0 > +#define ISP_BASE__INST0_SEG3 0 > +#define ISP_BASE__INST0_SEG4 0 > + > +#define ISP_BASE__INST1_SEG0 0 > +#define ISP_BASE__INST1_SEG1 0 > +#define ISP_BASE__INST1_SEG2 0 > +#define ISP_BASE__INST1_SEG3 0 > +#define ISP_BASE__INST1_SEG4 0 > + > +#define ISP_BASE__INST2_SEG0 0 > +#define ISP_BASE__INST2_SEG1 0 > +#define ISP_BASE__INST2_SEG2 0 > +#define ISP_BASE__INST2_SEG3 0 > +#define ISP_BASE__INST2_SEG4 0 > + > +#define ISP_BASE__INST3_SEG0 0 > +#define ISP_BASE__INST3_SEG1 0 > +#define ISP_BASE__INST3_SEG2 0 > +#define ISP_BASE__INST3_SEG3 0 > +#define ISP_BASE__INST3_SEG4 0 > + > +#define ISP_BASE__INST4_SEG0 0 > +#define ISP_BASE__INST4_SEG1 0 > +#define ISP_BASE__INST4_SEG2 0 > +#define ISP_BASE__INST4_SEG3 0 > +#define ISP_BASE__INST4_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 > +#define SYSTEMHUB_BASE__INST0_SEG1 0 > +#define SYSTEMHUB_BASE__INST0_SEG2 0 > +#define SYSTEMHUB_BASE__INST0_SEG3 0 > +#define SYSTEMHUB_BASE__INST0_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST1_SEG0 0 > +#define SYSTEMHUB_BASE__INST1_SEG1 0 > +#define SYSTEMHUB_BASE__INST1_SEG2 0 > +#define SYSTEMHUB_BASE__INST1_SEG3 0 > +#define SYSTEMHUB_BASE__INST1_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST2_SEG0 0 > +#define SYSTEMHUB_BASE__INST2_SEG1 0 > +#define SYSTEMHUB_BASE__INST2_SEG2 0 > +#define SYSTEMHUB_BASE__INST2_SEG3 0 > +#define SYSTEMHUB_BASE__INST2_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST3_SEG0 0 > +#define SYSTEMHUB_BASE__INST3_SEG1 0 > +#define SYSTEMHUB_BASE__INST3_SEG2 0 > +#define SYSTEMHUB_BASE__INST3_SEG3 0 > +#define SYSTEMHUB_BASE__INST3_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST4_SEG0 0 > +#define SYSTEMHUB_BASE__INST4_SEG1 0 > +#define SYSTEMHUB_BASE__INST4_SEG2 0 > +#define SYSTEMHUB_BASE__INST4_SEG3 0 > +#define SYSTEMHUB_BASE__INST4_SEG4 0 > + > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 > +#define L2IMU_BASE__INST0_SEG1 0 > +#define L2IMU_BASE__INST0_SEG2 0 > +#define L2IMU_BASE__INST0_SEG3 0 > +#define L2IMU_BASE__INST0_SEG4 0 > + > +#define L2IMU_BASE__INST1_SEG0 0 > +#define L2IMU_BASE__INST1_SEG1 0 > +#define L2IMU_BASE__INST1_SEG2 0 > +#define L2IMU_BASE__INST1_SEG3 0 > +#define L2IMU_BASE__INST1_SEG4 0 > + > +#define L2IMU_BASE__INST2_SEG0 0 > +#define L2IMU_BASE__INST2_SEG1 0 > +#define L2IMU_BASE__INST2_SEG2 0 > +#define L2IMU_BASE__INST2_SEG3 0 > +#define L2IMU_BASE__INST2_SEG4 0 > + > +#define L2IMU_BASE__INST3_SEG0 0 > +#define L2IMU_BASE__INST3_SEG1 0 > +#define L2IMU_BASE__INST3_SEG2 0 > +#define L2IMU_BASE__INST3_SEG3 0 > +#define L2IMU_BASE__INST3_SEG4 0 > + > +#define L2IMU_BASE__INST4_SEG0 0 > +#define L2IMU_BASE__INST4_SEG1 0 > +#define L2IMU_BASE__INST4_SEG2 0 > +#define L2IMU_BASE__INST4_SEG3 0 > +#define L2IMU_BASE__INST4_SEG4 0 > + > +#define IOHC_BASE__INST0_SEG0 0x00010000 > +#define IOHC_BASE__INST0_SEG1 0 > +#define IOHC_BASE__INST0_SEG2 0 > +#define IOHC_BASE__INST0_SEG3 0 > +#define IOHC_BASE__INST0_SEG4 0 > + > +#define IOHC_BASE__INST1_SEG0 0 > +#define IOHC_BASE__INST1_SEG1 0 > +#define IOHC_BASE__INST1_SEG2 0 > +#define IOHC_BASE__INST1_SEG3 0 > +#define IOHC_BASE__INST1_SEG4 0 > + > +#define IOHC_BASE__INST2_SEG0 0 > +#define IOHC_BASE__INST2_SEG1 0 > +#define IOHC_BASE__INST2_SEG2 0 > +#define IOHC_BASE__INST2_SEG3 0 > +#define IOHC_BASE__INST2_SEG4 0 > + > +#define IOHC_BASE__INST3_SEG0 0 > +#define IOHC_BASE__INST3_SEG1 0 > +#define IOHC_BASE__INST3_SEG2 0 > +#define IOHC_BASE__INST3_SEG3 0 > +#define IOHC_BASE__INST3_SEG4 0 > + > +#define IOHC_BASE__INST4_SEG0 0 > +#define IOHC_BASE__INST4_SEG1 0 > +#define IOHC_BASE__INST4_SEG2 0 > +#define IOHC_BASE__INST4_SEG3 0 > +#define IOHC_BASE__INST4_SEG4 0 > + > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 > +#define ATHUB_BASE__INST0_SEG1 0 > +#define ATHUB_BASE__INST0_SEG2 0 > +#define ATHUB_BASE__INST0_SEG3 0 > +#define ATHUB_BASE__INST0_SEG4 0 > + > +#define ATHUB_BASE__INST1_SEG0 0 > +#define ATHUB_BASE__INST1_SEG1 0 > +#define ATHUB_BASE__INST1_SEG2 0 > +#define ATHUB_BASE__INST1_SEG3 0 > +#define ATHUB_BASE__INST1_SEG4 0 > + > +#define ATHUB_BASE__INST2_SEG0 0 > +#define ATHUB_BASE__INST2_SEG1 0 > +#define ATHUB_BASE__INST2_SEG2 0 > +#define ATHUB_BASE__INST2_SEG3 0 > +#define ATHUB_BASE__INST2_SEG4 0 > + > +#define ATHUB_BASE__INST3_SEG0 0 > +#define ATHUB_BASE__INST3_SEG1 0 > +#define ATHUB_BASE__INST3_SEG2 0 > +#define ATHUB_BASE__INST3_SEG3 0 > +#define ATHUB_BASE__INST3_SEG4 0 > + > +#define ATHUB_BASE__INST4_SEG0 0 > +#define ATHUB_BASE__INST4_SEG1 0 > +#define ATHUB_BASE__INST4_SEG2 0 > +#define ATHUB_BASE__INST4_SEG3 0 > +#define ATHUB_BASE__INST4_SEG4 0 > + > +#define VCE_BASE__INST0_SEG0 0x00007E00 > +#define VCE_BASE__INST0_SEG1 0x00048800 > +#define VCE_BASE__INST0_SEG2 0 > +#define VCE_BASE__INST0_SEG3 0 > +#define VCE_BASE__INST0_SEG4 0 > + > +#define VCE_BASE__INST1_SEG0 0 > +#define VCE_BASE__INST1_SEG1 0 > +#define VCE_BASE__INST1_SEG2 0 > +#define VCE_BASE__INST1_SEG3 0 > +#define VCE_BASE__INST1_SEG4 0 > + > +#define VCE_BASE__INST2_SEG0 0 > +#define VCE_BASE__INST2_SEG1 0 > +#define VCE_BASE__INST2_SEG2 0 > +#define VCE_BASE__INST2_SEG3 0 > +#define VCE_BASE__INST2_SEG4 0 > + > +#define VCE_BASE__INST3_SEG0 0 > +#define VCE_BASE__INST3_SEG1 0 > +#define VCE_BASE__INST3_SEG2 0 > +#define VCE_BASE__INST3_SEG3 0 > +#define VCE_BASE__INST3_SEG4 0 > + > +#define VCE_BASE__INST4_SEG0 0 > +#define VCE_BASE__INST4_SEG1 0 > +#define VCE_BASE__INST4_SEG2 0 > +#define VCE_BASE__INST4_SEG3 0 > +#define VCE_BASE__INST4_SEG4 0 > + > +#define GC_BASE__INST0_SEG0 0x00002000 > +#define GC_BASE__INST0_SEG1 0x0000A000 > +#define GC_BASE__INST0_SEG2 0 > +#define GC_BASE__INST0_SEG3 0 > +#define GC_BASE__INST0_SEG4 0 > + > +#define GC_BASE__INST1_SEG0 0 > +#define GC_BASE__INST1_SEG1 0 > +#define GC_BASE__INST1_SEG2 0 > +#define GC_BASE__INST1_SEG3 0 > +#define GC_BASE__INST1_SEG4 0 > + > +#define GC_BASE__INST2_SEG0 0 > +#define GC_BASE__INST2_SEG1 0 > +#define GC_BASE__INST2_SEG2 0 > +#define GC_BASE__INST2_SEG3 0 > +#define GC_BASE__INST2_SEG4 0 > + > +#define GC_BASE__INST3_SEG0 0 > +#define GC_BASE__INST3_SEG1 0 > +#define GC_BASE__INST3_SEG2 0 > +#define GC_BASE__INST3_SEG3 0 > +#define GC_BASE__INST3_SEG4 0 > + > +#define GC_BASE__INST4_SEG0 0 > +#define GC_BASE__INST4_SEG1 0 > +#define GC_BASE__INST4_SEG2 0 > +#define GC_BASE__INST4_SEG3 0 > +#define GC_BASE__INST4_SEG4 0 > + > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 > +#define MMHUB_BASE__INST0_SEG1 0 > +#define MMHUB_BASE__INST0_SEG2 0 > +#define MMHUB_BASE__INST0_SEG3 0 > +#define MMHUB_BASE__INST0_SEG4 0 > + > +#define MMHUB_BASE__INST1_SEG0 0 > +#define MMHUB_BASE__INST1_SEG1 0 > +#define MMHUB_BASE__INST1_SEG2 0 > +#define MMHUB_BASE__INST1_SEG3 0 > +#define MMHUB_BASE__INST1_SEG4 0 > + > +#define MMHUB_BASE__INST2_SEG0 0 > +#define MMHUB_BASE__INST2_SEG1 0 > +#define MMHUB_BASE__INST2_SEG2 0 > +#define MMHUB_BASE__INST2_SEG3 0 > +#define MMHUB_BASE__INST2_SEG4 0 > + > +#define MMHUB_BASE__INST3_SEG0 0 > +#define MMHUB_BASE__INST3_SEG1 0 > +#define MMHUB_BASE__INST3_SEG2 0 > +#define MMHUB_BASE__INST3_SEG3 0 > +#define MMHUB_BASE__INST3_SEG4 0 > + > +#define MMHUB_BASE__INST4_SEG0 0 > +#define MMHUB_BASE__INST4_SEG1 0 > +#define MMHUB_BASE__INST4_SEG2 0 > +#define MMHUB_BASE__INST4_SEG3 0 > +#define MMHUB_BASE__INST4_SEG4 0 > + > +#define RSMU_BASE__INST0_SEG0 0x00012000 > +#define RSMU_BASE__INST0_SEG1 0 > +#define RSMU_BASE__INST0_SEG2 0 > +#define RSMU_BASE__INST0_SEG3 0 > +#define RSMU_BASE__INST0_SEG4 0 > + > +#define RSMU_BASE__INST1_SEG0 0 > +#define RSMU_BASE__INST1_SEG1 0 > +#define RSMU_BASE__INST1_SEG2 0 > +#define RSMU_BASE__INST1_SEG3 0 > +#define RSMU_BASE__INST1_SEG4 0 > + > +#define RSMU_BASE__INST2_SEG0 0 > +#define RSMU_BASE__INST2_SEG1 0 > +#define RSMU_BASE__INST2_SEG2 0 > +#define RSMU_BASE__INST2_SEG3 0 > +#define RSMU_BASE__INST2_SEG4 0 > + > +#define RSMU_BASE__INST3_SEG0 0 > +#define RSMU_BASE__INST3_SEG1 0 > +#define RSMU_BASE__INST3_SEG2 0 > +#define RSMU_BASE__INST3_SEG3 0 > +#define RSMU_BASE__INST3_SEG4 0 > + > +#define RSMU_BASE__INST4_SEG0 0 > +#define RSMU_BASE__INST4_SEG1 0 > +#define RSMU_BASE__INST4_SEG2 0 > +#define RSMU_BASE__INST4_SEG3 0 > +#define RSMU_BASE__INST4_SEG4 0 > + > +#define HDP_BASE__INST0_SEG0 0x00000F20 > +#define HDP_BASE__INST0_SEG1 0 > +#define HDP_BASE__INST0_SEG2 0 > +#define HDP_BASE__INST0_SEG3 0 > +#define HDP_BASE__INST0_SEG4 0 > + > +#define HDP_BASE__INST1_SEG0 0 > +#define HDP_BASE__INST1_SEG1 0 > +#define HDP_BASE__INST1_SEG2 0 > +#define HDP_BASE__INST1_SEG3 0 > +#define HDP_BASE__INST1_SEG4 0 > + > +#define HDP_BASE__INST2_SEG0 0 > +#define HDP_BASE__INST2_SEG1 0 > +#define HDP_BASE__INST2_SEG2 0 > +#define HDP_BASE__INST2_SEG3 0 > +#define HDP_BASE__INST2_SEG4 0 > + > +#define HDP_BASE__INST3_SEG0 0 > +#define HDP_BASE__INST3_SEG1 0 > +#define HDP_BASE__INST3_SEG2 0 > +#define HDP_BASE__INST3_SEG3 0 > +#define HDP_BASE__INST3_SEG4 0 > + > +#define HDP_BASE__INST4_SEG0 0 > +#define HDP_BASE__INST4_SEG1 0 > +#define HDP_BASE__INST4_SEG2 0 > +#define HDP_BASE__INST4_SEG3 0 > +#define HDP_BASE__INST4_SEG4 0 > + > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 > +#define OSSSYS_BASE__INST0_SEG1 0 > +#define OSSSYS_BASE__INST0_SEG2 0 > +#define OSSSYS_BASE__INST0_SEG3 0 > +#define OSSSYS_BASE__INST0_SEG4 0 > + > +#define OSSSYS_BASE__INST1_SEG0 0 > +#define OSSSYS_BASE__INST1_SEG1 0 > +#define OSSSYS_BASE__INST1_SEG2 0 > +#define OSSSYS_BASE__INST1_SEG3 0 > +#define OSSSYS_BASE__INST1_SEG4 0 > + > +#define OSSSYS_BASE__INST2_SEG0 0 > +#define OSSSYS_BASE__INST2_SEG1 0 > +#define OSSSYS_BASE__INST2_SEG2 0 > +#define OSSSYS_BASE__INST2_SEG3 0 > +#define OSSSYS_BASE__INST2_SEG4 0 > + > +#define OSSSYS_BASE__INST3_SEG0 0 > +#define OSSSYS_BASE__INST3_SEG1 0 > +#define OSSSYS_BASE__INST3_SEG2 0 > +#define OSSSYS_BASE__INST3_SEG3 0 > +#define OSSSYS_BASE__INST3_SEG4 0 > + > +#define OSSSYS_BASE__INST4_SEG0 0 > +#define OSSSYS_BASE__INST4_SEG1 0 > +#define OSSSYS_BASE__INST4_SEG2 0 > +#define OSSSYS_BASE__INST4_SEG3 0 > +#define OSSSYS_BASE__INST4_SEG4 0 > + > +#define SDMA0_BASE__INST0_SEG0 0x00001260 > +#define SDMA0_BASE__INST0_SEG1 0 > +#define SDMA0_BASE__INST0_SEG2 0 > +#define SDMA0_BASE__INST0_SEG3 0 > +#define SDMA0_BASE__INST0_SEG4 0 > + > +#define SDMA0_BASE__INST1_SEG0 0 > +#define SDMA0_BASE__INST1_SEG1 0 > +#define SDMA0_BASE__INST1_SEG2 0 > +#define SDMA0_BASE__INST1_SEG3 0 > +#define SDMA0_BASE__INST1_SEG4 0 > + > +#define SDMA0_BASE__INST2_SEG0 0 > +#define SDMA0_BASE__INST2_SEG1 0 > +#define SDMA0_BASE__INST2_SEG2 0 > +#define SDMA0_BASE__INST2_SEG3 0 > +#define SDMA0_BASE__INST2_SEG4 0 > + > +#define SDMA0_BASE__INST3_SEG0 0 > +#define SDMA0_BASE__INST3_SEG1 0 > +#define SDMA0_BASE__INST3_SEG2 0 > +#define SDMA0_BASE__INST3_SEG3 0 > +#define SDMA0_BASE__INST3_SEG4 0 > + > +#define SDMA0_BASE__INST4_SEG0 0 > +#define SDMA0_BASE__INST4_SEG1 0 > +#define SDMA0_BASE__INST4_SEG2 0 > +#define SDMA0_BASE__INST4_SEG3 0 > +#define SDMA0_BASE__INST4_SEG4 0 > + > +#define SDMA1_BASE__INST0_SEG0 0x00001460 > +#define SDMA1_BASE__INST0_SEG1 0 > +#define SDMA1_BASE__INST0_SEG2 0 > +#define SDMA1_BASE__INST0_SEG3 0 > +#define SDMA1_BASE__INST0_SEG4 0 > + > +#define SDMA1_BASE__INST1_SEG0 0 > +#define SDMA1_BASE__INST1_SEG1 0 > +#define SDMA1_BASE__INST1_SEG2 0 > +#define SDMA1_BASE__INST1_SEG3 0 > +#define SDMA1_BASE__INST1_SEG4 0 > + > +#define SDMA1_BASE__INST2_SEG0 0 > +#define SDMA1_BASE__INST2_SEG1 0 > +#define SDMA1_BASE__INST2_SEG2 0 > +#define SDMA1_BASE__INST2_SEG3 0 > +#define SDMA1_BASE__INST2_SEG4 0 > + > +#define SDMA1_BASE__INST3_SEG0 0 > +#define SDMA1_BASE__INST3_SEG1 0 > +#define SDMA1_BASE__INST3_SEG2 0 > +#define SDMA1_BASE__INST3_SEG3 0 > +#define SDMA1_BASE__INST3_SEG4 0 > + > +#define SDMA1_BASE__INST4_SEG0 0 > +#define SDMA1_BASE__INST4_SEG1 0 > +#define SDMA1_BASE__INST4_SEG2 0 > +#define SDMA1_BASE__INST4_SEG3 0 > +#define SDMA1_BASE__INST4_SEG4 0 > + > +#define XDMA_BASE__INST0_SEG0 0x00003400 > +#define XDMA_BASE__INST0_SEG1 0 > +#define XDMA_BASE__INST0_SEG2 0 > +#define XDMA_BASE__INST0_SEG3 0 > +#define XDMA_BASE__INST0_SEG4 0 > + > +#define XDMA_BASE__INST1_SEG0 0 > +#define XDMA_BASE__INST1_SEG1 0 > +#define XDMA_BASE__INST1_SEG2 0 > +#define XDMA_BASE__INST1_SEG3 0 > +#define XDMA_BASE__INST1_SEG4 0 > + > +#define XDMA_BASE__INST2_SEG0 0 > +#define XDMA_BASE__INST2_SEG1 0 > +#define XDMA_BASE__INST2_SEG2 0 > +#define XDMA_BASE__INST2_SEG3 0 > +#define XDMA_BASE__INST2_SEG4 0 > + > +#define XDMA_BASE__INST3_SEG0 0 > +#define XDMA_BASE__INST3_SEG1 0 > +#define XDMA_BASE__INST3_SEG2 0 > +#define XDMA_BASE__INST3_SEG3 0 > +#define XDMA_BASE__INST3_SEG4 0 > + > +#define XDMA_BASE__INST4_SEG0 0 > +#define XDMA_BASE__INST4_SEG1 0 > +#define XDMA_BASE__INST4_SEG2 0 > +#define XDMA_BASE__INST4_SEG3 0 > +#define XDMA_BASE__INST4_SEG4 0 > + > +#define UMC_BASE__INST0_SEG0 0x00014000 > +#define UMC_BASE__INST0_SEG1 0 > +#define UMC_BASE__INST0_SEG2 0 > +#define UMC_BASE__INST0_SEG3 0 > +#define UMC_BASE__INST0_SEG4 0 > + > +#define UMC_BASE__INST1_SEG0 0 > +#define UMC_BASE__INST1_SEG1 0 > +#define UMC_BASE__INST1_SEG2 0 > +#define UMC_BASE__INST1_SEG3 0 > +#define UMC_BASE__INST1_SEG4 0 > + > +#define UMC_BASE__INST2_SEG0 0 > +#define UMC_BASE__INST2_SEG1 0 > +#define UMC_BASE__INST2_SEG2 0 > +#define UMC_BASE__INST2_SEG3 0 > +#define UMC_BASE__INST2_SEG4 0 > + > +#define UMC_BASE__INST3_SEG0 0 > +#define UMC_BASE__INST3_SEG1 0 > +#define UMC_BASE__INST3_SEG2 0 > +#define UMC_BASE__INST3_SEG3 0 > +#define UMC_BASE__INST3_SEG4 0 > + > +#define UMC_BASE__INST4_SEG0 0 > +#define UMC_BASE__INST4_SEG1 0 > +#define UMC_BASE__INST4_SEG2 0 > +#define UMC_BASE__INST4_SEG3 0 > +#define UMC_BASE__INST4_SEG4 0 > + > +#define THM_BASE__INST0_SEG0 0x00016600 > +#define THM_BASE__INST0_SEG1 0 > +#define THM_BASE__INST0_SEG2 0 > +#define THM_BASE__INST0_SEG3 0 > +#define THM_BASE__INST0_SEG4 0 > + > +#define THM_BASE__INST1_SEG0 0 > +#define THM_BASE__INST1_SEG1 0 > +#define THM_BASE__INST1_SEG2 0 > +#define THM_BASE__INST1_SEG3 0 > +#define THM_BASE__INST1_SEG4 0 > + > +#define THM_BASE__INST2_SEG0 0 > +#define THM_BASE__INST2_SEG1 0 > +#define THM_BASE__INST2_SEG2 0 > +#define THM_BASE__INST2_SEG3 0 > +#define THM_BASE__INST2_SEG4 0 > + > +#define THM_BASE__INST3_SEG0 0 > +#define THM_BASE__INST3_SEG1 0 > +#define THM_BASE__INST3_SEG2 0 > +#define THM_BASE__INST3_SEG3 0 > +#define THM_BASE__INST3_SEG4 0 > + > +#define THM_BASE__INST4_SEG0 0 > +#define THM_BASE__INST4_SEG1 0 > +#define THM_BASE__INST4_SEG2 0 > +#define THM_BASE__INST4_SEG3 0 > +#define THM_BASE__INST4_SEG4 0 > + > +#define SMUIO_BASE__INST0_SEG0 0x00016800 > +#define SMUIO_BASE__INST0_SEG1 0 > +#define SMUIO_BASE__INST0_SEG2 0 > +#define SMUIO_BASE__INST0_SEG3 0 > +#define SMUIO_BASE__INST0_SEG4 0 > + > +#define SMUIO_BASE__INST1_SEG0 0 > +#define SMUIO_BASE__INST1_SEG1 0 > +#define SMUIO_BASE__INST1_SEG2 0 > +#define SMUIO_BASE__INST1_SEG3 0 > +#define SMUIO_BASE__INST1_SEG4 0 > + > +#define SMUIO_BASE__INST2_SEG0 0 > +#define SMUIO_BASE__INST2_SEG1 0 > +#define SMUIO_BASE__INST2_SEG2 0 > +#define SMUIO_BASE__INST2_SEG3 0 > +#define SMUIO_BASE__INST2_SEG4 0 > + > +#define SMUIO_BASE__INST3_SEG0 0 > +#define SMUIO_BASE__INST3_SEG1 0 > +#define SMUIO_BASE__INST3_SEG2 0 > +#define SMUIO_BASE__INST3_SEG3 0 > +#define SMUIO_BASE__INST3_SEG4 0 > + > +#define SMUIO_BASE__INST4_SEG0 0 > +#define SMUIO_BASE__INST4_SEG1 0 > +#define SMUIO_BASE__INST4_SEG2 0 > +#define SMUIO_BASE__INST4_SEG3 0 > +#define SMUIO_BASE__INST4_SEG4 0 > + > +#define PWR_BASE__INST0_SEG0 0x00016A00 > +#define PWR_BASE__INST0_SEG1 0 > +#define PWR_BASE__INST0_SEG2 0 > +#define PWR_BASE__INST0_SEG3 0 > +#define PWR_BASE__INST0_SEG4 0 > + > +#define PWR_BASE__INST1_SEG0 0 > +#define PWR_BASE__INST1_SEG1 0 > +#define PWR_BASE__INST1_SEG2 0 > +#define PWR_BASE__INST1_SEG3 0 > +#define PWR_BASE__INST1_SEG4 0 > + > +#define PWR_BASE__INST2_SEG0 0 > +#define PWR_BASE__INST2_SEG1 0 > +#define PWR_BASE__INST2_SEG2 0 > +#define PWR_BASE__INST2_SEG3 0 > +#define PWR_BASE__INST2_SEG4 0 > + > +#define PWR_BASE__INST3_SEG0 0 > +#define PWR_BASE__INST3_SEG1 0 > +#define PWR_BASE__INST3_SEG2 0 > +#define PWR_BASE__INST3_SEG3 0 > +#define PWR_BASE__INST3_SEG4 0 > + > +#define PWR_BASE__INST4_SEG0 0 > +#define PWR_BASE__INST4_SEG1 0 > +#define PWR_BASE__INST4_SEG2 0 > +#define PWR_BASE__INST4_SEG3 0 > +#define PWR_BASE__INST4_SEG4 0 > + > +#define CLK_BASE__INST0_SEG0 0x00016C00 > +#define CLK_BASE__INST0_SEG1 0 > +#define CLK_BASE__INST0_SEG2 0 > +#define CLK_BASE__INST0_SEG3 0 > +#define CLK_BASE__INST0_SEG4 0 > + > +#define CLK_BASE__INST1_SEG0 0x00016E00 > +#define CLK_BASE__INST1_SEG1 0 > +#define CLK_BASE__INST1_SEG2 0 > +#define CLK_BASE__INST1_SEG3 0 > +#define CLK_BASE__INST1_SEG4 0 > + > +#define CLK_BASE__INST2_SEG0 0x00017000 > +#define CLK_BASE__INST2_SEG1 0 > +#define CLK_BASE__INST2_SEG2 0 > +#define CLK_BASE__INST2_SEG3 0 > +#define CLK_BASE__INST2_SEG4 0 > + > +#define CLK_BASE__INST3_SEG0 0x00017200 > +#define CLK_BASE__INST3_SEG1 0 > +#define CLK_BASE__INST3_SEG2 0 > +#define CLK_BASE__INST3_SEG3 0 > +#define CLK_BASE__INST3_SEG4 0 > + > +#define CLK_BASE__INST4_SEG0 0x00017E00 > +#define CLK_BASE__INST4_SEG1 0 > +#define CLK_BASE__INST4_SEG2 0 > +#define CLK_BASE__INST4_SEG3 0 > +#define CLK_BASE__INST4_SEG4 0 > + > +#define FUSE_BASE__INST0_SEG0 0x00017400 > +#define FUSE_BASE__INST0_SEG1 0 > +#define FUSE_BASE__INST0_SEG2 0 > +#define FUSE_BASE__INST0_SEG3 0 > +#define FUSE_BASE__INST0_SEG4 0 > + > +#define FUSE_BASE__INST1_SEG0 0 > +#define FUSE_BASE__INST1_SEG1 0 > +#define FUSE_BASE__INST1_SEG2 0 > +#define FUSE_BASE__INST1_SEG3 0 > +#define FUSE_BASE__INST1_SEG4 0 > + > +#define FUSE_BASE__INST2_SEG0 0 > +#define FUSE_BASE__INST2_SEG1 0 > +#define FUSE_BASE__INST2_SEG2 0 > +#define FUSE_BASE__INST2_SEG3 0 > +#define FUSE_BASE__INST2_SEG4 0 > + > +#define FUSE_BASE__INST3_SEG0 0 > +#define FUSE_BASE__INST3_SEG1 0 > +#define FUSE_BASE__INST3_SEG2 0 > +#define FUSE_BASE__INST3_SEG3 0 > +#define FUSE_BASE__INST3_SEG4 0 > + > +#define FUSE_BASE__INST4_SEG0 0 > +#define FUSE_BASE__INST4_SEG1 0 > +#define FUSE_BASE__INST4_SEG2 0 > +#define FUSE_BASE__INST4_SEG3 0 > +#define FUSE_BASE__INST4_SEG4 0 > + > + > +#endif > + _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <2db922e4-fe49-7499-38f1-a3b2c8e07cf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <2db922e4-fe49-7499-38f1-a3b2c8e07cf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2017-11-27 19:29 ` Liu, Shaoyun 0 siblings, 0 replies; 14+ messages in thread From: Liu, Shaoyun @ 2017-11-27 19:29 UTC (permalink / raw) To: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW I agree that this HW engineer generated file doesn't match the coding style from linux software engineer point of view , but since we already import other similar " HW engineer style" files under include/asic_reg/vega10/, I don't see a reason to specially change this file without touch else . This file is actually almost identical as soc15ip.h . I think it's easier for us to import other offset file in the future if we keep them un-touched . Regards Shaoyun.liu -----Original Message----- From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] Sent: Monday, November 27, 2017 2:17 PM To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file First of let us fix the obvious style problems. Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> > --- > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++ > 1 file changed, 1248 insertions(+) > create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > new file mode 100644 > index 0000000..76cb748 > --- /dev/null > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > @@ -0,0 +1,1248 @@ > +#ifndef _ip_offset_1_HEADER > +#define _ip_offset_1_HEADER Names for preprocessor defines should be capitable. > + > +#define MAX_INSTANCE 5 > +#define MAX_SEGMENT 5 > + > + > +struct IP_BASE_INSTANCE Structure names should be lower case. And we need an amdgpu_ or at least amd_ prefix here. Regards, Christian. > +{ > + unsigned int segment[MAX_SEGMENT]; > +}; > + > +struct IP_BASE > +{ > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; > +}; > + > + > +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment No "//" in kernel code please. > +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers > +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; // not exist > +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, > + { { 0x00016E00, 0, 0, 0, 0 } }, > + { { 0x00017000, 0, 0, 0, 0 } }, > + { { 0x00017200, 0, 0, 0, 0 } }, > + { { 0x00017E00, 0, 0, 0, 0 } } } }; > +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } }, > + { { 0, 0, 0, 0, 0 } } } }; > + > + > +#define NBIF_BASE__INST0_SEG0 0x00000000 > +#define NBIF_BASE__INST0_SEG1 0x00000014 > +#define NBIF_BASE__INST0_SEG2 0x00000D20 > +#define NBIF_BASE__INST0_SEG3 0x00010400 > +#define NBIF_BASE__INST0_SEG4 0 > + > +#define NBIF_BASE__INST1_SEG0 0 > +#define NBIF_BASE__INST1_SEG1 0 > +#define NBIF_BASE__INST1_SEG2 0 > +#define NBIF_BASE__INST1_SEG3 0 > +#define NBIF_BASE__INST1_SEG4 0 > + > +#define NBIF_BASE__INST2_SEG0 0 > +#define NBIF_BASE__INST2_SEG1 0 > +#define NBIF_BASE__INST2_SEG2 0 > +#define NBIF_BASE__INST2_SEG3 0 > +#define NBIF_BASE__INST2_SEG4 0 > + > +#define NBIF_BASE__INST3_SEG0 0 > +#define NBIF_BASE__INST3_SEG1 0 > +#define NBIF_BASE__INST3_SEG2 0 > +#define NBIF_BASE__INST3_SEG3 0 > +#define NBIF_BASE__INST3_SEG4 0 > + > +#define NBIF_BASE__INST4_SEG0 0 > +#define NBIF_BASE__INST4_SEG1 0 > +#define NBIF_BASE__INST4_SEG2 0 > +#define NBIF_BASE__INST4_SEG3 0 > +#define NBIF_BASE__INST4_SEG4 0 > + > +#define NBIO_BASE__INST0_SEG0 0x00000000 > +#define NBIO_BASE__INST0_SEG1 0x00000014 > +#define NBIO_BASE__INST0_SEG2 0x00000D20 > +#define NBIO_BASE__INST0_SEG3 0x00010400 > +#define NBIO_BASE__INST0_SEG4 0 > + > +#define NBIO_BASE__INST1_SEG0 0 > +#define NBIO_BASE__INST1_SEG1 0 > +#define NBIO_BASE__INST1_SEG2 0 > +#define NBIO_BASE__INST1_SEG3 0 > +#define NBIO_BASE__INST1_SEG4 0 > + > +#define NBIO_BASE__INST2_SEG0 0 > +#define NBIO_BASE__INST2_SEG1 0 > +#define NBIO_BASE__INST2_SEG2 0 > +#define NBIO_BASE__INST2_SEG3 0 > +#define NBIO_BASE__INST2_SEG4 0 > + > +#define NBIO_BASE__INST3_SEG0 0 > +#define NBIO_BASE__INST3_SEG1 0 > +#define NBIO_BASE__INST3_SEG2 0 > +#define NBIO_BASE__INST3_SEG3 0 > +#define NBIO_BASE__INST3_SEG4 0 > + > +#define NBIO_BASE__INST4_SEG0 0 > +#define NBIO_BASE__INST4_SEG1 0 > +#define NBIO_BASE__INST4_SEG2 0 > +#define NBIO_BASE__INST4_SEG3 0 > +#define NBIO_BASE__INST4_SEG4 0 > + > +#define DCE_BASE__INST0_SEG0 0x00000012 > +#define DCE_BASE__INST0_SEG1 0x000000C0 > +#define DCE_BASE__INST0_SEG2 0x000034C0 > +#define DCE_BASE__INST0_SEG3 0 > +#define DCE_BASE__INST0_SEG4 0 > + > +#define DCE_BASE__INST1_SEG0 0 > +#define DCE_BASE__INST1_SEG1 0 > +#define DCE_BASE__INST1_SEG2 0 > +#define DCE_BASE__INST1_SEG3 0 > +#define DCE_BASE__INST1_SEG4 0 > + > +#define DCE_BASE__INST2_SEG0 0 > +#define DCE_BASE__INST2_SEG1 0 > +#define DCE_BASE__INST2_SEG2 0 > +#define DCE_BASE__INST2_SEG3 0 > +#define DCE_BASE__INST2_SEG4 0 > + > +#define DCE_BASE__INST3_SEG0 0 > +#define DCE_BASE__INST3_SEG1 0 > +#define DCE_BASE__INST3_SEG2 0 > +#define DCE_BASE__INST3_SEG3 0 > +#define DCE_BASE__INST3_SEG4 0 > + > +#define DCE_BASE__INST4_SEG0 0 > +#define DCE_BASE__INST4_SEG1 0 > +#define DCE_BASE__INST4_SEG2 0 > +#define DCE_BASE__INST4_SEG3 0 > +#define DCE_BASE__INST4_SEG4 0 > + > +#define DCN_BASE__INST0_SEG0 0x00000012 > +#define DCN_BASE__INST0_SEG1 0x000000C0 > +#define DCN_BASE__INST0_SEG2 0x000034C0 > +#define DCN_BASE__INST0_SEG3 0 > +#define DCN_BASE__INST0_SEG4 0 > + > +#define DCN_BASE__INST1_SEG0 0 > +#define DCN_BASE__INST1_SEG1 0 > +#define DCN_BASE__INST1_SEG2 0 > +#define DCN_BASE__INST1_SEG3 0 > +#define DCN_BASE__INST1_SEG4 0 > + > +#define DCN_BASE__INST2_SEG0 0 > +#define DCN_BASE__INST2_SEG1 0 > +#define DCN_BASE__INST2_SEG2 0 > +#define DCN_BASE__INST2_SEG3 0 > +#define DCN_BASE__INST2_SEG4 0 > + > +#define DCN_BASE__INST3_SEG0 0 > +#define DCN_BASE__INST3_SEG1 0 > +#define DCN_BASE__INST3_SEG2 0 > +#define DCN_BASE__INST3_SEG3 0 > +#define DCN_BASE__INST3_SEG4 0 > + > +#define DCN_BASE__INST4_SEG0 0 > +#define DCN_BASE__INST4_SEG1 0 > +#define DCN_BASE__INST4_SEG2 0 > +#define DCN_BASE__INST4_SEG3 0 > +#define DCN_BASE__INST4_SEG4 0 > + > +#define MP0_BASE__INST0_SEG0 0x00016000 > +#define MP0_BASE__INST0_SEG1 0 > +#define MP0_BASE__INST0_SEG2 0 > +#define MP0_BASE__INST0_SEG3 0 > +#define MP0_BASE__INST0_SEG4 0 > + > +#define MP0_BASE__INST1_SEG0 0 > +#define MP0_BASE__INST1_SEG1 0 > +#define MP0_BASE__INST1_SEG2 0 > +#define MP0_BASE__INST1_SEG3 0 > +#define MP0_BASE__INST1_SEG4 0 > + > +#define MP0_BASE__INST2_SEG0 0 > +#define MP0_BASE__INST2_SEG1 0 > +#define MP0_BASE__INST2_SEG2 0 > +#define MP0_BASE__INST2_SEG3 0 > +#define MP0_BASE__INST2_SEG4 0 > + > +#define MP0_BASE__INST3_SEG0 0 > +#define MP0_BASE__INST3_SEG1 0 > +#define MP0_BASE__INST3_SEG2 0 > +#define MP0_BASE__INST3_SEG3 0 > +#define MP0_BASE__INST3_SEG4 0 > + > +#define MP0_BASE__INST4_SEG0 0 > +#define MP0_BASE__INST4_SEG1 0 > +#define MP0_BASE__INST4_SEG2 0 > +#define MP0_BASE__INST4_SEG3 0 > +#define MP0_BASE__INST4_SEG4 0 > + > +#define MP1_BASE__INST0_SEG0 0x00016000 > +#define MP1_BASE__INST0_SEG1 0 > +#define MP1_BASE__INST0_SEG2 0 > +#define MP1_BASE__INST0_SEG3 0 > +#define MP1_BASE__INST0_SEG4 0 > + > +#define MP1_BASE__INST1_SEG0 0 > +#define MP1_BASE__INST1_SEG1 0 > +#define MP1_BASE__INST1_SEG2 0 > +#define MP1_BASE__INST1_SEG3 0 > +#define MP1_BASE__INST1_SEG4 0 > + > +#define MP1_BASE__INST2_SEG0 0 > +#define MP1_BASE__INST2_SEG1 0 > +#define MP1_BASE__INST2_SEG2 0 > +#define MP1_BASE__INST2_SEG3 0 > +#define MP1_BASE__INST2_SEG4 0 > + > +#define MP1_BASE__INST3_SEG0 0 > +#define MP1_BASE__INST3_SEG1 0 > +#define MP1_BASE__INST3_SEG2 0 > +#define MP1_BASE__INST3_SEG3 0 > +#define MP1_BASE__INST3_SEG4 0 > + > +#define MP1_BASE__INST4_SEG0 0 > +#define MP1_BASE__INST4_SEG1 0 > +#define MP1_BASE__INST4_SEG2 0 > +#define MP1_BASE__INST4_SEG3 0 > +#define MP1_BASE__INST4_SEG4 0 > + > +#define MP2_BASE__INST0_SEG0 0x00016000 > +#define MP2_BASE__INST0_SEG1 0 > +#define MP2_BASE__INST0_SEG2 0 > +#define MP2_BASE__INST0_SEG3 0 > +#define MP2_BASE__INST0_SEG4 0 > + > +#define MP2_BASE__INST1_SEG0 0 > +#define MP2_BASE__INST1_SEG1 0 > +#define MP2_BASE__INST1_SEG2 0 > +#define MP2_BASE__INST1_SEG3 0 > +#define MP2_BASE__INST1_SEG4 0 > + > +#define MP2_BASE__INST2_SEG0 0 > +#define MP2_BASE__INST2_SEG1 0 > +#define MP2_BASE__INST2_SEG2 0 > +#define MP2_BASE__INST2_SEG3 0 > +#define MP2_BASE__INST2_SEG4 0 > + > +#define MP2_BASE__INST3_SEG0 0 > +#define MP2_BASE__INST3_SEG1 0 > +#define MP2_BASE__INST3_SEG2 0 > +#define MP2_BASE__INST3_SEG3 0 > +#define MP2_BASE__INST3_SEG4 0 > + > +#define MP2_BASE__INST4_SEG0 0 > +#define MP2_BASE__INST4_SEG1 0 > +#define MP2_BASE__INST4_SEG2 0 > +#define MP2_BASE__INST4_SEG3 0 > +#define MP2_BASE__INST4_SEG4 0 > + > +#define DF_BASE__INST0_SEG0 0x00007000 > +#define DF_BASE__INST0_SEG1 0 > +#define DF_BASE__INST0_SEG2 0 > +#define DF_BASE__INST0_SEG3 0 > +#define DF_BASE__INST0_SEG4 0 > + > +#define DF_BASE__INST1_SEG0 0 > +#define DF_BASE__INST1_SEG1 0 > +#define DF_BASE__INST1_SEG2 0 > +#define DF_BASE__INST1_SEG3 0 > +#define DF_BASE__INST1_SEG4 0 > + > +#define DF_BASE__INST2_SEG0 0 > +#define DF_BASE__INST2_SEG1 0 > +#define DF_BASE__INST2_SEG2 0 > +#define DF_BASE__INST2_SEG3 0 > +#define DF_BASE__INST2_SEG4 0 > + > +#define DF_BASE__INST3_SEG0 0 > +#define DF_BASE__INST3_SEG1 0 > +#define DF_BASE__INST3_SEG2 0 > +#define DF_BASE__INST3_SEG3 0 > +#define DF_BASE__INST3_SEG4 0 > + > +#define DF_BASE__INST4_SEG0 0 > +#define DF_BASE__INST4_SEG1 0 > +#define DF_BASE__INST4_SEG2 0 > +#define DF_BASE__INST4_SEG3 0 > +#define DF_BASE__INST4_SEG4 0 > + > +#define UVD_BASE__INST0_SEG0 0x00007800 > +#define UVD_BASE__INST0_SEG1 0x00007E00 > +#define UVD_BASE__INST0_SEG2 0 > +#define UVD_BASE__INST0_SEG3 0 > +#define UVD_BASE__INST0_SEG4 0 > + > +#define UVD_BASE__INST1_SEG0 0 > +#define UVD_BASE__INST1_SEG1 0 > +#define UVD_BASE__INST1_SEG2 0 > +#define UVD_BASE__INST1_SEG3 0 > +#define UVD_BASE__INST1_SEG4 0 > + > +#define UVD_BASE__INST2_SEG0 0 > +#define UVD_BASE__INST2_SEG1 0 > +#define UVD_BASE__INST2_SEG2 0 > +#define UVD_BASE__INST2_SEG3 0 > +#define UVD_BASE__INST2_SEG4 0 > + > +#define UVD_BASE__INST3_SEG0 0 > +#define UVD_BASE__INST3_SEG1 0 > +#define UVD_BASE__INST3_SEG2 0 > +#define UVD_BASE__INST3_SEG3 0 > +#define UVD_BASE__INST3_SEG4 0 > + > +#define UVD_BASE__INST4_SEG0 0 > +#define UVD_BASE__INST4_SEG1 0 > +#define UVD_BASE__INST4_SEG2 0 > +#define UVD_BASE__INST4_SEG3 0 > +#define UVD_BASE__INST4_SEG4 0 > + > +#define VCN_BASE__INST0_SEG0 0x00007800 > +#define VCN_BASE__INST0_SEG1 0x00007E00 > +#define VCN_BASE__INST0_SEG2 0 > +#define VCN_BASE__INST0_SEG3 0 > +#define VCN_BASE__INST0_SEG4 0 > + > +#define VCN_BASE__INST1_SEG0 0 > +#define VCN_BASE__INST1_SEG1 0 > +#define VCN_BASE__INST1_SEG2 0 > +#define VCN_BASE__INST1_SEG3 0 > +#define VCN_BASE__INST1_SEG4 0 > + > +#define VCN_BASE__INST2_SEG0 0 > +#define VCN_BASE__INST2_SEG1 0 > +#define VCN_BASE__INST2_SEG2 0 > +#define VCN_BASE__INST2_SEG3 0 > +#define VCN_BASE__INST2_SEG4 0 > + > +#define VCN_BASE__INST3_SEG0 0 > +#define VCN_BASE__INST3_SEG1 0 > +#define VCN_BASE__INST3_SEG2 0 > +#define VCN_BASE__INST3_SEG3 0 > +#define VCN_BASE__INST3_SEG4 0 > + > +#define VCN_BASE__INST4_SEG0 0 > +#define VCN_BASE__INST4_SEG1 0 > +#define VCN_BASE__INST4_SEG2 0 > +#define VCN_BASE__INST4_SEG3 0 > +#define VCN_BASE__INST4_SEG4 0 > + > +#define DBGU_BASE__INST0_SEG0 0x00000180 > +#define DBGU_BASE__INST0_SEG1 0x000001A0 > +#define DBGU_BASE__INST0_SEG2 0 > +#define DBGU_BASE__INST0_SEG3 0 > +#define DBGU_BASE__INST0_SEG4 0 > + > +#define DBGU_BASE__INST1_SEG0 0 > +#define DBGU_BASE__INST1_SEG1 0 > +#define DBGU_BASE__INST1_SEG2 0 > +#define DBGU_BASE__INST1_SEG3 0 > +#define DBGU_BASE__INST1_SEG4 0 > + > +#define DBGU_BASE__INST2_SEG0 0 > +#define DBGU_BASE__INST2_SEG1 0 > +#define DBGU_BASE__INST2_SEG2 0 > +#define DBGU_BASE__INST2_SEG3 0 > +#define DBGU_BASE__INST2_SEG4 0 > + > +#define DBGU_BASE__INST3_SEG0 0 > +#define DBGU_BASE__INST3_SEG1 0 > +#define DBGU_BASE__INST3_SEG2 0 > +#define DBGU_BASE__INST3_SEG3 0 > +#define DBGU_BASE__INST3_SEG4 0 > + > +#define DBGU_BASE__INST4_SEG0 0 > +#define DBGU_BASE__INST4_SEG1 0 > +#define DBGU_BASE__INST4_SEG2 0 > +#define DBGU_BASE__INST4_SEG3 0 > +#define DBGU_BASE__INST4_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 > +#define DBGU_NBIO_BASE__INST0_SEG1 0 > +#define DBGU_NBIO_BASE__INST0_SEG2 0 > +#define DBGU_NBIO_BASE__INST0_SEG3 0 > +#define DBGU_NBIO_BASE__INST0_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST1_SEG0 0 > +#define DBGU_NBIO_BASE__INST1_SEG1 0 > +#define DBGU_NBIO_BASE__INST1_SEG2 0 > +#define DBGU_NBIO_BASE__INST1_SEG3 0 > +#define DBGU_NBIO_BASE__INST1_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST2_SEG0 0 > +#define DBGU_NBIO_BASE__INST2_SEG1 0 > +#define DBGU_NBIO_BASE__INST2_SEG2 0 > +#define DBGU_NBIO_BASE__INST2_SEG3 0 > +#define DBGU_NBIO_BASE__INST2_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST3_SEG0 0 > +#define DBGU_NBIO_BASE__INST3_SEG1 0 > +#define DBGU_NBIO_BASE__INST3_SEG2 0 > +#define DBGU_NBIO_BASE__INST3_SEG3 0 > +#define DBGU_NBIO_BASE__INST3_SEG4 0 > + > +#define DBGU_NBIO_BASE__INST4_SEG0 0 > +#define DBGU_NBIO_BASE__INST4_SEG1 0 > +#define DBGU_NBIO_BASE__INST4_SEG2 0 > +#define DBGU_NBIO_BASE__INST4_SEG3 0 > +#define DBGU_NBIO_BASE__INST4_SEG4 0 > + > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 > +#define DBGU_IO_BASE__INST0_SEG1 0 > +#define DBGU_IO_BASE__INST0_SEG2 0 > +#define DBGU_IO_BASE__INST0_SEG3 0 > +#define DBGU_IO_BASE__INST0_SEG4 0 > + > +#define DBGU_IO_BASE__INST1_SEG0 0 > +#define DBGU_IO_BASE__INST1_SEG1 0 > +#define DBGU_IO_BASE__INST1_SEG2 0 > +#define DBGU_IO_BASE__INST1_SEG3 0 > +#define DBGU_IO_BASE__INST1_SEG4 0 > + > +#define DBGU_IO_BASE__INST2_SEG0 0 > +#define DBGU_IO_BASE__INST2_SEG1 0 > +#define DBGU_IO_BASE__INST2_SEG2 0 > +#define DBGU_IO_BASE__INST2_SEG3 0 > +#define DBGU_IO_BASE__INST2_SEG4 0 > + > +#define DBGU_IO_BASE__INST3_SEG0 0 > +#define DBGU_IO_BASE__INST3_SEG1 0 > +#define DBGU_IO_BASE__INST3_SEG2 0 > +#define DBGU_IO_BASE__INST3_SEG3 0 > +#define DBGU_IO_BASE__INST3_SEG4 0 > + > +#define DBGU_IO_BASE__INST4_SEG0 0 > +#define DBGU_IO_BASE__INST4_SEG1 0 > +#define DBGU_IO_BASE__INST4_SEG2 0 > +#define DBGU_IO_BASE__INST4_SEG3 0 > +#define DBGU_IO_BASE__INST4_SEG4 0 > + > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 > +#define DFX_DAP_BASE__INST0_SEG1 0 > +#define DFX_DAP_BASE__INST0_SEG2 0 > +#define DFX_DAP_BASE__INST0_SEG3 0 > +#define DFX_DAP_BASE__INST0_SEG4 0 > + > +#define DFX_DAP_BASE__INST1_SEG0 0 > +#define DFX_DAP_BASE__INST1_SEG1 0 > +#define DFX_DAP_BASE__INST1_SEG2 0 > +#define DFX_DAP_BASE__INST1_SEG3 0 > +#define DFX_DAP_BASE__INST1_SEG4 0 > + > +#define DFX_DAP_BASE__INST2_SEG0 0 > +#define DFX_DAP_BASE__INST2_SEG1 0 > +#define DFX_DAP_BASE__INST2_SEG2 0 > +#define DFX_DAP_BASE__INST2_SEG3 0 > +#define DFX_DAP_BASE__INST2_SEG4 0 > + > +#define DFX_DAP_BASE__INST3_SEG0 0 > +#define DFX_DAP_BASE__INST3_SEG1 0 > +#define DFX_DAP_BASE__INST3_SEG2 0 > +#define DFX_DAP_BASE__INST3_SEG3 0 > +#define DFX_DAP_BASE__INST3_SEG4 0 > + > +#define DFX_DAP_BASE__INST4_SEG0 0 > +#define DFX_DAP_BASE__INST4_SEG1 0 > +#define DFX_DAP_BASE__INST4_SEG2 0 > +#define DFX_DAP_BASE__INST4_SEG3 0 > +#define DFX_DAP_BASE__INST4_SEG4 0 > + > +#define DFX_BASE__INST0_SEG0 0x00000580 > +#define DFX_BASE__INST0_SEG1 0 > +#define DFX_BASE__INST0_SEG2 0 > +#define DFX_BASE__INST0_SEG3 0 > +#define DFX_BASE__INST0_SEG4 0 > + > +#define DFX_BASE__INST1_SEG0 0 > +#define DFX_BASE__INST1_SEG1 0 > +#define DFX_BASE__INST1_SEG2 0 > +#define DFX_BASE__INST1_SEG3 0 > +#define DFX_BASE__INST1_SEG4 0 > + > +#define DFX_BASE__INST2_SEG0 0 > +#define DFX_BASE__INST2_SEG1 0 > +#define DFX_BASE__INST2_SEG2 0 > +#define DFX_BASE__INST2_SEG3 0 > +#define DFX_BASE__INST2_SEG4 0 > + > +#define DFX_BASE__INST3_SEG0 0 > +#define DFX_BASE__INST3_SEG1 0 > +#define DFX_BASE__INST3_SEG2 0 > +#define DFX_BASE__INST3_SEG3 0 > +#define DFX_BASE__INST3_SEG4 0 > + > +#define DFX_BASE__INST4_SEG0 0 > +#define DFX_BASE__INST4_SEG1 0 > +#define DFX_BASE__INST4_SEG2 0 > +#define DFX_BASE__INST4_SEG3 0 > +#define DFX_BASE__INST4_SEG4 0 > + > +#define ISP_BASE__INST0_SEG0 0x00018000 > +#define ISP_BASE__INST0_SEG1 0 > +#define ISP_BASE__INST0_SEG2 0 > +#define ISP_BASE__INST0_SEG3 0 > +#define ISP_BASE__INST0_SEG4 0 > + > +#define ISP_BASE__INST1_SEG0 0 > +#define ISP_BASE__INST1_SEG1 0 > +#define ISP_BASE__INST1_SEG2 0 > +#define ISP_BASE__INST1_SEG3 0 > +#define ISP_BASE__INST1_SEG4 0 > + > +#define ISP_BASE__INST2_SEG0 0 > +#define ISP_BASE__INST2_SEG1 0 > +#define ISP_BASE__INST2_SEG2 0 > +#define ISP_BASE__INST2_SEG3 0 > +#define ISP_BASE__INST2_SEG4 0 > + > +#define ISP_BASE__INST3_SEG0 0 > +#define ISP_BASE__INST3_SEG1 0 > +#define ISP_BASE__INST3_SEG2 0 > +#define ISP_BASE__INST3_SEG3 0 > +#define ISP_BASE__INST3_SEG4 0 > + > +#define ISP_BASE__INST4_SEG0 0 > +#define ISP_BASE__INST4_SEG1 0 > +#define ISP_BASE__INST4_SEG2 0 > +#define ISP_BASE__INST4_SEG3 0 > +#define ISP_BASE__INST4_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 > +#define SYSTEMHUB_BASE__INST0_SEG1 0 > +#define SYSTEMHUB_BASE__INST0_SEG2 0 > +#define SYSTEMHUB_BASE__INST0_SEG3 0 > +#define SYSTEMHUB_BASE__INST0_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST1_SEG0 0 > +#define SYSTEMHUB_BASE__INST1_SEG1 0 > +#define SYSTEMHUB_BASE__INST1_SEG2 0 > +#define SYSTEMHUB_BASE__INST1_SEG3 0 > +#define SYSTEMHUB_BASE__INST1_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST2_SEG0 0 > +#define SYSTEMHUB_BASE__INST2_SEG1 0 > +#define SYSTEMHUB_BASE__INST2_SEG2 0 > +#define SYSTEMHUB_BASE__INST2_SEG3 0 > +#define SYSTEMHUB_BASE__INST2_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST3_SEG0 0 > +#define SYSTEMHUB_BASE__INST3_SEG1 0 > +#define SYSTEMHUB_BASE__INST3_SEG2 0 > +#define SYSTEMHUB_BASE__INST3_SEG3 0 > +#define SYSTEMHUB_BASE__INST3_SEG4 0 > + > +#define SYSTEMHUB_BASE__INST4_SEG0 0 > +#define SYSTEMHUB_BASE__INST4_SEG1 0 > +#define SYSTEMHUB_BASE__INST4_SEG2 0 > +#define SYSTEMHUB_BASE__INST4_SEG3 0 > +#define SYSTEMHUB_BASE__INST4_SEG4 0 > + > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 > +#define L2IMU_BASE__INST0_SEG1 0 > +#define L2IMU_BASE__INST0_SEG2 0 > +#define L2IMU_BASE__INST0_SEG3 0 > +#define L2IMU_BASE__INST0_SEG4 0 > + > +#define L2IMU_BASE__INST1_SEG0 0 > +#define L2IMU_BASE__INST1_SEG1 0 > +#define L2IMU_BASE__INST1_SEG2 0 > +#define L2IMU_BASE__INST1_SEG3 0 > +#define L2IMU_BASE__INST1_SEG4 0 > + > +#define L2IMU_BASE__INST2_SEG0 0 > +#define L2IMU_BASE__INST2_SEG1 0 > +#define L2IMU_BASE__INST2_SEG2 0 > +#define L2IMU_BASE__INST2_SEG3 0 > +#define L2IMU_BASE__INST2_SEG4 0 > + > +#define L2IMU_BASE__INST3_SEG0 0 > +#define L2IMU_BASE__INST3_SEG1 0 > +#define L2IMU_BASE__INST3_SEG2 0 > +#define L2IMU_BASE__INST3_SEG3 0 > +#define L2IMU_BASE__INST3_SEG4 0 > + > +#define L2IMU_BASE__INST4_SEG0 0 > +#define L2IMU_BASE__INST4_SEG1 0 > +#define L2IMU_BASE__INST4_SEG2 0 > +#define L2IMU_BASE__INST4_SEG3 0 > +#define L2IMU_BASE__INST4_SEG4 0 > + > +#define IOHC_BASE__INST0_SEG0 0x00010000 > +#define IOHC_BASE__INST0_SEG1 0 > +#define IOHC_BASE__INST0_SEG2 0 > +#define IOHC_BASE__INST0_SEG3 0 > +#define IOHC_BASE__INST0_SEG4 0 > + > +#define IOHC_BASE__INST1_SEG0 0 > +#define IOHC_BASE__INST1_SEG1 0 > +#define IOHC_BASE__INST1_SEG2 0 > +#define IOHC_BASE__INST1_SEG3 0 > +#define IOHC_BASE__INST1_SEG4 0 > + > +#define IOHC_BASE__INST2_SEG0 0 > +#define IOHC_BASE__INST2_SEG1 0 > +#define IOHC_BASE__INST2_SEG2 0 > +#define IOHC_BASE__INST2_SEG3 0 > +#define IOHC_BASE__INST2_SEG4 0 > + > +#define IOHC_BASE__INST3_SEG0 0 > +#define IOHC_BASE__INST3_SEG1 0 > +#define IOHC_BASE__INST3_SEG2 0 > +#define IOHC_BASE__INST3_SEG3 0 > +#define IOHC_BASE__INST3_SEG4 0 > + > +#define IOHC_BASE__INST4_SEG0 0 > +#define IOHC_BASE__INST4_SEG1 0 > +#define IOHC_BASE__INST4_SEG2 0 > +#define IOHC_BASE__INST4_SEG3 0 > +#define IOHC_BASE__INST4_SEG4 0 > + > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 > +#define ATHUB_BASE__INST0_SEG1 0 > +#define ATHUB_BASE__INST0_SEG2 0 > +#define ATHUB_BASE__INST0_SEG3 0 > +#define ATHUB_BASE__INST0_SEG4 0 > + > +#define ATHUB_BASE__INST1_SEG0 0 > +#define ATHUB_BASE__INST1_SEG1 0 > +#define ATHUB_BASE__INST1_SEG2 0 > +#define ATHUB_BASE__INST1_SEG3 0 > +#define ATHUB_BASE__INST1_SEG4 0 > + > +#define ATHUB_BASE__INST2_SEG0 0 > +#define ATHUB_BASE__INST2_SEG1 0 > +#define ATHUB_BASE__INST2_SEG2 0 > +#define ATHUB_BASE__INST2_SEG3 0 > +#define ATHUB_BASE__INST2_SEG4 0 > + > +#define ATHUB_BASE__INST3_SEG0 0 > +#define ATHUB_BASE__INST3_SEG1 0 > +#define ATHUB_BASE__INST3_SEG2 0 > +#define ATHUB_BASE__INST3_SEG3 0 > +#define ATHUB_BASE__INST3_SEG4 0 > + > +#define ATHUB_BASE__INST4_SEG0 0 > +#define ATHUB_BASE__INST4_SEG1 0 > +#define ATHUB_BASE__INST4_SEG2 0 > +#define ATHUB_BASE__INST4_SEG3 0 > +#define ATHUB_BASE__INST4_SEG4 0 > + > +#define VCE_BASE__INST0_SEG0 0x00007E00 > +#define VCE_BASE__INST0_SEG1 0x00048800 > +#define VCE_BASE__INST0_SEG2 0 > +#define VCE_BASE__INST0_SEG3 0 > +#define VCE_BASE__INST0_SEG4 0 > + > +#define VCE_BASE__INST1_SEG0 0 > +#define VCE_BASE__INST1_SEG1 0 > +#define VCE_BASE__INST1_SEG2 0 > +#define VCE_BASE__INST1_SEG3 0 > +#define VCE_BASE__INST1_SEG4 0 > + > +#define VCE_BASE__INST2_SEG0 0 > +#define VCE_BASE__INST2_SEG1 0 > +#define VCE_BASE__INST2_SEG2 0 > +#define VCE_BASE__INST2_SEG3 0 > +#define VCE_BASE__INST2_SEG4 0 > + > +#define VCE_BASE__INST3_SEG0 0 > +#define VCE_BASE__INST3_SEG1 0 > +#define VCE_BASE__INST3_SEG2 0 > +#define VCE_BASE__INST3_SEG3 0 > +#define VCE_BASE__INST3_SEG4 0 > + > +#define VCE_BASE__INST4_SEG0 0 > +#define VCE_BASE__INST4_SEG1 0 > +#define VCE_BASE__INST4_SEG2 0 > +#define VCE_BASE__INST4_SEG3 0 > +#define VCE_BASE__INST4_SEG4 0 > + > +#define GC_BASE__INST0_SEG0 0x00002000 > +#define GC_BASE__INST0_SEG1 0x0000A000 > +#define GC_BASE__INST0_SEG2 0 > +#define GC_BASE__INST0_SEG3 0 > +#define GC_BASE__INST0_SEG4 0 > + > +#define GC_BASE__INST1_SEG0 0 > +#define GC_BASE__INST1_SEG1 0 > +#define GC_BASE__INST1_SEG2 0 > +#define GC_BASE__INST1_SEG3 0 > +#define GC_BASE__INST1_SEG4 0 > + > +#define GC_BASE__INST2_SEG0 0 > +#define GC_BASE__INST2_SEG1 0 > +#define GC_BASE__INST2_SEG2 0 > +#define GC_BASE__INST2_SEG3 0 > +#define GC_BASE__INST2_SEG4 0 > + > +#define GC_BASE__INST3_SEG0 0 > +#define GC_BASE__INST3_SEG1 0 > +#define GC_BASE__INST3_SEG2 0 > +#define GC_BASE__INST3_SEG3 0 > +#define GC_BASE__INST3_SEG4 0 > + > +#define GC_BASE__INST4_SEG0 0 > +#define GC_BASE__INST4_SEG1 0 > +#define GC_BASE__INST4_SEG2 0 > +#define GC_BASE__INST4_SEG3 0 > +#define GC_BASE__INST4_SEG4 0 > + > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 > +#define MMHUB_BASE__INST0_SEG1 0 > +#define MMHUB_BASE__INST0_SEG2 0 > +#define MMHUB_BASE__INST0_SEG3 0 > +#define MMHUB_BASE__INST0_SEG4 0 > + > +#define MMHUB_BASE__INST1_SEG0 0 > +#define MMHUB_BASE__INST1_SEG1 0 > +#define MMHUB_BASE__INST1_SEG2 0 > +#define MMHUB_BASE__INST1_SEG3 0 > +#define MMHUB_BASE__INST1_SEG4 0 > + > +#define MMHUB_BASE__INST2_SEG0 0 > +#define MMHUB_BASE__INST2_SEG1 0 > +#define MMHUB_BASE__INST2_SEG2 0 > +#define MMHUB_BASE__INST2_SEG3 0 > +#define MMHUB_BASE__INST2_SEG4 0 > + > +#define MMHUB_BASE__INST3_SEG0 0 > +#define MMHUB_BASE__INST3_SEG1 0 > +#define MMHUB_BASE__INST3_SEG2 0 > +#define MMHUB_BASE__INST3_SEG3 0 > +#define MMHUB_BASE__INST3_SEG4 0 > + > +#define MMHUB_BASE__INST4_SEG0 0 > +#define MMHUB_BASE__INST4_SEG1 0 > +#define MMHUB_BASE__INST4_SEG2 0 > +#define MMHUB_BASE__INST4_SEG3 0 > +#define MMHUB_BASE__INST4_SEG4 0 > + > +#define RSMU_BASE__INST0_SEG0 0x00012000 > +#define RSMU_BASE__INST0_SEG1 0 > +#define RSMU_BASE__INST0_SEG2 0 > +#define RSMU_BASE__INST0_SEG3 0 > +#define RSMU_BASE__INST0_SEG4 0 > + > +#define RSMU_BASE__INST1_SEG0 0 > +#define RSMU_BASE__INST1_SEG1 0 > +#define RSMU_BASE__INST1_SEG2 0 > +#define RSMU_BASE__INST1_SEG3 0 > +#define RSMU_BASE__INST1_SEG4 0 > + > +#define RSMU_BASE__INST2_SEG0 0 > +#define RSMU_BASE__INST2_SEG1 0 > +#define RSMU_BASE__INST2_SEG2 0 > +#define RSMU_BASE__INST2_SEG3 0 > +#define RSMU_BASE__INST2_SEG4 0 > + > +#define RSMU_BASE__INST3_SEG0 0 > +#define RSMU_BASE__INST3_SEG1 0 > +#define RSMU_BASE__INST3_SEG2 0 > +#define RSMU_BASE__INST3_SEG3 0 > +#define RSMU_BASE__INST3_SEG4 0 > + > +#define RSMU_BASE__INST4_SEG0 0 > +#define RSMU_BASE__INST4_SEG1 0 > +#define RSMU_BASE__INST4_SEG2 0 > +#define RSMU_BASE__INST4_SEG3 0 > +#define RSMU_BASE__INST4_SEG4 0 > + > +#define HDP_BASE__INST0_SEG0 0x00000F20 > +#define HDP_BASE__INST0_SEG1 0 > +#define HDP_BASE__INST0_SEG2 0 > +#define HDP_BASE__INST0_SEG3 0 > +#define HDP_BASE__INST0_SEG4 0 > + > +#define HDP_BASE__INST1_SEG0 0 > +#define HDP_BASE__INST1_SEG1 0 > +#define HDP_BASE__INST1_SEG2 0 > +#define HDP_BASE__INST1_SEG3 0 > +#define HDP_BASE__INST1_SEG4 0 > + > +#define HDP_BASE__INST2_SEG0 0 > +#define HDP_BASE__INST2_SEG1 0 > +#define HDP_BASE__INST2_SEG2 0 > +#define HDP_BASE__INST2_SEG3 0 > +#define HDP_BASE__INST2_SEG4 0 > + > +#define HDP_BASE__INST3_SEG0 0 > +#define HDP_BASE__INST3_SEG1 0 > +#define HDP_BASE__INST3_SEG2 0 > +#define HDP_BASE__INST3_SEG3 0 > +#define HDP_BASE__INST3_SEG4 0 > + > +#define HDP_BASE__INST4_SEG0 0 > +#define HDP_BASE__INST4_SEG1 0 > +#define HDP_BASE__INST4_SEG2 0 > +#define HDP_BASE__INST4_SEG3 0 > +#define HDP_BASE__INST4_SEG4 0 > + > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 > +#define OSSSYS_BASE__INST0_SEG1 0 > +#define OSSSYS_BASE__INST0_SEG2 0 > +#define OSSSYS_BASE__INST0_SEG3 0 > +#define OSSSYS_BASE__INST0_SEG4 0 > + > +#define OSSSYS_BASE__INST1_SEG0 0 > +#define OSSSYS_BASE__INST1_SEG1 0 > +#define OSSSYS_BASE__INST1_SEG2 0 > +#define OSSSYS_BASE__INST1_SEG3 0 > +#define OSSSYS_BASE__INST1_SEG4 0 > + > +#define OSSSYS_BASE__INST2_SEG0 0 > +#define OSSSYS_BASE__INST2_SEG1 0 > +#define OSSSYS_BASE__INST2_SEG2 0 > +#define OSSSYS_BASE__INST2_SEG3 0 > +#define OSSSYS_BASE__INST2_SEG4 0 > + > +#define OSSSYS_BASE__INST3_SEG0 0 > +#define OSSSYS_BASE__INST3_SEG1 0 > +#define OSSSYS_BASE__INST3_SEG2 0 > +#define OSSSYS_BASE__INST3_SEG3 0 > +#define OSSSYS_BASE__INST3_SEG4 0 > + > +#define OSSSYS_BASE__INST4_SEG0 0 > +#define OSSSYS_BASE__INST4_SEG1 0 > +#define OSSSYS_BASE__INST4_SEG2 0 > +#define OSSSYS_BASE__INST4_SEG3 0 > +#define OSSSYS_BASE__INST4_SEG4 0 > + > +#define SDMA0_BASE__INST0_SEG0 0x00001260 > +#define SDMA0_BASE__INST0_SEG1 0 > +#define SDMA0_BASE__INST0_SEG2 0 > +#define SDMA0_BASE__INST0_SEG3 0 > +#define SDMA0_BASE__INST0_SEG4 0 > + > +#define SDMA0_BASE__INST1_SEG0 0 > +#define SDMA0_BASE__INST1_SEG1 0 > +#define SDMA0_BASE__INST1_SEG2 0 > +#define SDMA0_BASE__INST1_SEG3 0 > +#define SDMA0_BASE__INST1_SEG4 0 > + > +#define SDMA0_BASE__INST2_SEG0 0 > +#define SDMA0_BASE__INST2_SEG1 0 > +#define SDMA0_BASE__INST2_SEG2 0 > +#define SDMA0_BASE__INST2_SEG3 0 > +#define SDMA0_BASE__INST2_SEG4 0 > + > +#define SDMA0_BASE__INST3_SEG0 0 > +#define SDMA0_BASE__INST3_SEG1 0 > +#define SDMA0_BASE__INST3_SEG2 0 > +#define SDMA0_BASE__INST3_SEG3 0 > +#define SDMA0_BASE__INST3_SEG4 0 > + > +#define SDMA0_BASE__INST4_SEG0 0 > +#define SDMA0_BASE__INST4_SEG1 0 > +#define SDMA0_BASE__INST4_SEG2 0 > +#define SDMA0_BASE__INST4_SEG3 0 > +#define SDMA0_BASE__INST4_SEG4 0 > + > +#define SDMA1_BASE__INST0_SEG0 0x00001460 > +#define SDMA1_BASE__INST0_SEG1 0 > +#define SDMA1_BASE__INST0_SEG2 0 > +#define SDMA1_BASE__INST0_SEG3 0 > +#define SDMA1_BASE__INST0_SEG4 0 > + > +#define SDMA1_BASE__INST1_SEG0 0 > +#define SDMA1_BASE__INST1_SEG1 0 > +#define SDMA1_BASE__INST1_SEG2 0 > +#define SDMA1_BASE__INST1_SEG3 0 > +#define SDMA1_BASE__INST1_SEG4 0 > + > +#define SDMA1_BASE__INST2_SEG0 0 > +#define SDMA1_BASE__INST2_SEG1 0 > +#define SDMA1_BASE__INST2_SEG2 0 > +#define SDMA1_BASE__INST2_SEG3 0 > +#define SDMA1_BASE__INST2_SEG4 0 > + > +#define SDMA1_BASE__INST3_SEG0 0 > +#define SDMA1_BASE__INST3_SEG1 0 > +#define SDMA1_BASE__INST3_SEG2 0 > +#define SDMA1_BASE__INST3_SEG3 0 > +#define SDMA1_BASE__INST3_SEG4 0 > + > +#define SDMA1_BASE__INST4_SEG0 0 > +#define SDMA1_BASE__INST4_SEG1 0 > +#define SDMA1_BASE__INST4_SEG2 0 > +#define SDMA1_BASE__INST4_SEG3 0 > +#define SDMA1_BASE__INST4_SEG4 0 > + > +#define XDMA_BASE__INST0_SEG0 0x00003400 > +#define XDMA_BASE__INST0_SEG1 0 > +#define XDMA_BASE__INST0_SEG2 0 > +#define XDMA_BASE__INST0_SEG3 0 > +#define XDMA_BASE__INST0_SEG4 0 > + > +#define XDMA_BASE__INST1_SEG0 0 > +#define XDMA_BASE__INST1_SEG1 0 > +#define XDMA_BASE__INST1_SEG2 0 > +#define XDMA_BASE__INST1_SEG3 0 > +#define XDMA_BASE__INST1_SEG4 0 > + > +#define XDMA_BASE__INST2_SEG0 0 > +#define XDMA_BASE__INST2_SEG1 0 > +#define XDMA_BASE__INST2_SEG2 0 > +#define XDMA_BASE__INST2_SEG3 0 > +#define XDMA_BASE__INST2_SEG4 0 > + > +#define XDMA_BASE__INST3_SEG0 0 > +#define XDMA_BASE__INST3_SEG1 0 > +#define XDMA_BASE__INST3_SEG2 0 > +#define XDMA_BASE__INST3_SEG3 0 > +#define XDMA_BASE__INST3_SEG4 0 > + > +#define XDMA_BASE__INST4_SEG0 0 > +#define XDMA_BASE__INST4_SEG1 0 > +#define XDMA_BASE__INST4_SEG2 0 > +#define XDMA_BASE__INST4_SEG3 0 > +#define XDMA_BASE__INST4_SEG4 0 > + > +#define UMC_BASE__INST0_SEG0 0x00014000 > +#define UMC_BASE__INST0_SEG1 0 > +#define UMC_BASE__INST0_SEG2 0 > +#define UMC_BASE__INST0_SEG3 0 > +#define UMC_BASE__INST0_SEG4 0 > + > +#define UMC_BASE__INST1_SEG0 0 > +#define UMC_BASE__INST1_SEG1 0 > +#define UMC_BASE__INST1_SEG2 0 > +#define UMC_BASE__INST1_SEG3 0 > +#define UMC_BASE__INST1_SEG4 0 > + > +#define UMC_BASE__INST2_SEG0 0 > +#define UMC_BASE__INST2_SEG1 0 > +#define UMC_BASE__INST2_SEG2 0 > +#define UMC_BASE__INST2_SEG3 0 > +#define UMC_BASE__INST2_SEG4 0 > + > +#define UMC_BASE__INST3_SEG0 0 > +#define UMC_BASE__INST3_SEG1 0 > +#define UMC_BASE__INST3_SEG2 0 > +#define UMC_BASE__INST3_SEG3 0 > +#define UMC_BASE__INST3_SEG4 0 > + > +#define UMC_BASE__INST4_SEG0 0 > +#define UMC_BASE__INST4_SEG1 0 > +#define UMC_BASE__INST4_SEG2 0 > +#define UMC_BASE__INST4_SEG3 0 > +#define UMC_BASE__INST4_SEG4 0 > + > +#define THM_BASE__INST0_SEG0 0x00016600 > +#define THM_BASE__INST0_SEG1 0 > +#define THM_BASE__INST0_SEG2 0 > +#define THM_BASE__INST0_SEG3 0 > +#define THM_BASE__INST0_SEG4 0 > + > +#define THM_BASE__INST1_SEG0 0 > +#define THM_BASE__INST1_SEG1 0 > +#define THM_BASE__INST1_SEG2 0 > +#define THM_BASE__INST1_SEG3 0 > +#define THM_BASE__INST1_SEG4 0 > + > +#define THM_BASE__INST2_SEG0 0 > +#define THM_BASE__INST2_SEG1 0 > +#define THM_BASE__INST2_SEG2 0 > +#define THM_BASE__INST2_SEG3 0 > +#define THM_BASE__INST2_SEG4 0 > + > +#define THM_BASE__INST3_SEG0 0 > +#define THM_BASE__INST3_SEG1 0 > +#define THM_BASE__INST3_SEG2 0 > +#define THM_BASE__INST3_SEG3 0 > +#define THM_BASE__INST3_SEG4 0 > + > +#define THM_BASE__INST4_SEG0 0 > +#define THM_BASE__INST4_SEG1 0 > +#define THM_BASE__INST4_SEG2 0 > +#define THM_BASE__INST4_SEG3 0 > +#define THM_BASE__INST4_SEG4 0 > + > +#define SMUIO_BASE__INST0_SEG0 0x00016800 > +#define SMUIO_BASE__INST0_SEG1 0 > +#define SMUIO_BASE__INST0_SEG2 0 > +#define SMUIO_BASE__INST0_SEG3 0 > +#define SMUIO_BASE__INST0_SEG4 0 > + > +#define SMUIO_BASE__INST1_SEG0 0 > +#define SMUIO_BASE__INST1_SEG1 0 > +#define SMUIO_BASE__INST1_SEG2 0 > +#define SMUIO_BASE__INST1_SEG3 0 > +#define SMUIO_BASE__INST1_SEG4 0 > + > +#define SMUIO_BASE__INST2_SEG0 0 > +#define SMUIO_BASE__INST2_SEG1 0 > +#define SMUIO_BASE__INST2_SEG2 0 > +#define SMUIO_BASE__INST2_SEG3 0 > +#define SMUIO_BASE__INST2_SEG4 0 > + > +#define SMUIO_BASE__INST3_SEG0 0 > +#define SMUIO_BASE__INST3_SEG1 0 > +#define SMUIO_BASE__INST3_SEG2 0 > +#define SMUIO_BASE__INST3_SEG3 0 > +#define SMUIO_BASE__INST3_SEG4 0 > + > +#define SMUIO_BASE__INST4_SEG0 0 > +#define SMUIO_BASE__INST4_SEG1 0 > +#define SMUIO_BASE__INST4_SEG2 0 > +#define SMUIO_BASE__INST4_SEG3 0 > +#define SMUIO_BASE__INST4_SEG4 0 > + > +#define PWR_BASE__INST0_SEG0 0x00016A00 > +#define PWR_BASE__INST0_SEG1 0 > +#define PWR_BASE__INST0_SEG2 0 > +#define PWR_BASE__INST0_SEG3 0 > +#define PWR_BASE__INST0_SEG4 0 > + > +#define PWR_BASE__INST1_SEG0 0 > +#define PWR_BASE__INST1_SEG1 0 > +#define PWR_BASE__INST1_SEG2 0 > +#define PWR_BASE__INST1_SEG3 0 > +#define PWR_BASE__INST1_SEG4 0 > + > +#define PWR_BASE__INST2_SEG0 0 > +#define PWR_BASE__INST2_SEG1 0 > +#define PWR_BASE__INST2_SEG2 0 > +#define PWR_BASE__INST2_SEG3 0 > +#define PWR_BASE__INST2_SEG4 0 > + > +#define PWR_BASE__INST3_SEG0 0 > +#define PWR_BASE__INST3_SEG1 0 > +#define PWR_BASE__INST3_SEG2 0 > +#define PWR_BASE__INST3_SEG3 0 > +#define PWR_BASE__INST3_SEG4 0 > + > +#define PWR_BASE__INST4_SEG0 0 > +#define PWR_BASE__INST4_SEG1 0 > +#define PWR_BASE__INST4_SEG2 0 > +#define PWR_BASE__INST4_SEG3 0 > +#define PWR_BASE__INST4_SEG4 0 > + > +#define CLK_BASE__INST0_SEG0 0x00016C00 > +#define CLK_BASE__INST0_SEG1 0 > +#define CLK_BASE__INST0_SEG2 0 > +#define CLK_BASE__INST0_SEG3 0 > +#define CLK_BASE__INST0_SEG4 0 > + > +#define CLK_BASE__INST1_SEG0 0x00016E00 > +#define CLK_BASE__INST1_SEG1 0 > +#define CLK_BASE__INST1_SEG2 0 > +#define CLK_BASE__INST1_SEG3 0 > +#define CLK_BASE__INST1_SEG4 0 > + > +#define CLK_BASE__INST2_SEG0 0x00017000 > +#define CLK_BASE__INST2_SEG1 0 > +#define CLK_BASE__INST2_SEG2 0 > +#define CLK_BASE__INST2_SEG3 0 > +#define CLK_BASE__INST2_SEG4 0 > + > +#define CLK_BASE__INST3_SEG0 0x00017200 > +#define CLK_BASE__INST3_SEG1 0 > +#define CLK_BASE__INST3_SEG2 0 > +#define CLK_BASE__INST3_SEG3 0 > +#define CLK_BASE__INST3_SEG4 0 > + > +#define CLK_BASE__INST4_SEG0 0x00017E00 > +#define CLK_BASE__INST4_SEG1 0 > +#define CLK_BASE__INST4_SEG2 0 > +#define CLK_BASE__INST4_SEG3 0 > +#define CLK_BASE__INST4_SEG4 0 > + > +#define FUSE_BASE__INST0_SEG0 0x00017400 > +#define FUSE_BASE__INST0_SEG1 0 > +#define FUSE_BASE__INST0_SEG2 0 > +#define FUSE_BASE__INST0_SEG3 0 > +#define FUSE_BASE__INST0_SEG4 0 > + > +#define FUSE_BASE__INST1_SEG0 0 > +#define FUSE_BASE__INST1_SEG1 0 > +#define FUSE_BASE__INST1_SEG2 0 > +#define FUSE_BASE__INST1_SEG3 0 > +#define FUSE_BASE__INST1_SEG4 0 > + > +#define FUSE_BASE__INST2_SEG0 0 > +#define FUSE_BASE__INST2_SEG1 0 > +#define FUSE_BASE__INST2_SEG2 0 > +#define FUSE_BASE__INST2_SEG3 0 > +#define FUSE_BASE__INST2_SEG4 0 > + > +#define FUSE_BASE__INST3_SEG0 0 > +#define FUSE_BASE__INST3_SEG1 0 > +#define FUSE_BASE__INST3_SEG2 0 > +#define FUSE_BASE__INST3_SEG3 0 > +#define FUSE_BASE__INST3_SEG4 0 > + > +#define FUSE_BASE__INST4_SEG0 0 > +#define FUSE_BASE__INST4_SEG1 0 > +#define FUSE_BASE__INST4_SEG2 0 > +#define FUSE_BASE__INST4_SEG3 0 > +#define FUSE_BASE__INST4_SEG4 0 > + > + > +#endif > + _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file
@ 2017-11-27 19:37 Koenig, Christian
[not found] ` <2a0a3687-0207-4ea0-bb2c-20750a1d2bb3-2ueSQiBKiTY7tOexoI0I+QC/G2K4zDHf@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Koenig, Christian @ 2017-11-27 19:37 UTC (permalink / raw)
To: Liu, Shaoyun; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 61541 bytes --]
And that is a clear NAK to this approach.
Please start by fixing at least the obvious style problems before resending.
Thanks,
Christian.
Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>:
I agree that this HW engineer generated file doesn't match the coding style from linux software engineer point of view , but since we already import other similar " HW engineer style" files under include/asic_reg/vega10/, I don't see a reason to specially change this file without touch else . This file is actually almost identical as soc15ip.h . I think it's easier for us to import other offset file in the future if we keep them un-touched .
Regards
Shaoyun.liu
-----Original Message-----
From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com]
Sent: Monday, November 27, 2017 2:17 PM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file
First of let us fix the obvious style problems.
Am 27.11.2017 um 19:30 schrieb Shaoyun Liu:
> Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c
> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
> ---
> .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 ++++++++++++++++++++
> 1 file changed, 1248 insertions(+)
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
> new file mode 100644
> index 0000000..76cb748
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h
> @@ -0,0 +1,1248 @@
> +#ifndef _ip_offset_1_HEADER
> +#define _ip_offset_1_HEADER
Names for preprocessor defines should be capitable.
> +
> +#define MAX_INSTANCE 5
> +#define MAX_SEGMENT 5
> +
> +
> +struct IP_BASE_INSTANCE
Structure names should be lower case. And we need an amdgpu_ or at least
amd_ prefix here.
Regards,
Christian.
> +{
> + unsigned int segment[MAX_SEGMENT];
> +};
> +
> +struct IP_BASE
> +{
> + struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
> +};
> +
> +
> +static const struct IP_BASE NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
No "//" in kernel code please.
> +static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
> +static const struct IP_BASE DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
> +static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } }; // not exist
> +static const struct IP_BASE L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
> + { { 0x00016E00, 0, 0, 0, 0 } },
> + { { 0x00017000, 0, 0, 0, 0 } },
> + { { 0x00017200, 0, 0, 0, 0 } },
> + { { 0x00017E00, 0, 0, 0, 0 } } } };
> +static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } },
> + { { 0, 0, 0, 0, 0 } } } };
> +
> +
> +#define NBIF_BASE__INST0_SEG0 0x00000000
> +#define NBIF_BASE__INST0_SEG1 0x00000014
> +#define NBIF_BASE__INST0_SEG2 0x00000D20
> +#define NBIF_BASE__INST0_SEG3 0x00010400
> +#define NBIF_BASE__INST0_SEG4 0
> +
> +#define NBIF_BASE__INST1_SEG0 0
> +#define NBIF_BASE__INST1_SEG1 0
> +#define NBIF_BASE__INST1_SEG2 0
> +#define NBIF_BASE__INST1_SEG3 0
> +#define NBIF_BASE__INST1_SEG4 0
> +
> +#define NBIF_BASE__INST2_SEG0 0
> +#define NBIF_BASE__INST2_SEG1 0
> +#define NBIF_BASE__INST2_SEG2 0
> +#define NBIF_BASE__INST2_SEG3 0
> +#define NBIF_BASE__INST2_SEG4 0
> +
> +#define NBIF_BASE__INST3_SEG0 0
> +#define NBIF_BASE__INST3_SEG1 0
> +#define NBIF_BASE__INST3_SEG2 0
> +#define NBIF_BASE__INST3_SEG3 0
> +#define NBIF_BASE__INST3_SEG4 0
> +
> +#define NBIF_BASE__INST4_SEG0 0
> +#define NBIF_BASE__INST4_SEG1 0
> +#define NBIF_BASE__INST4_SEG2 0
> +#define NBIF_BASE__INST4_SEG3 0
> +#define NBIF_BASE__INST4_SEG4 0
> +
> +#define NBIO_BASE__INST0_SEG0 0x00000000
> +#define NBIO_BASE__INST0_SEG1 0x00000014
> +#define NBIO_BASE__INST0_SEG2 0x00000D20
> +#define NBIO_BASE__INST0_SEG3 0x00010400
> +#define NBIO_BASE__INST0_SEG4 0
> +
> +#define NBIO_BASE__INST1_SEG0 0
> +#define NBIO_BASE__INST1_SEG1 0
> +#define NBIO_BASE__INST1_SEG2 0
> +#define NBIO_BASE__INST1_SEG3 0
> +#define NBIO_BASE__INST1_SEG4 0
> +
> +#define NBIO_BASE__INST2_SEG0 0
> +#define NBIO_BASE__INST2_SEG1 0
> +#define NBIO_BASE__INST2_SEG2 0
> +#define NBIO_BASE__INST2_SEG3 0
> +#define NBIO_BASE__INST2_SEG4 0
> +
> +#define NBIO_BASE__INST3_SEG0 0
> +#define NBIO_BASE__INST3_SEG1 0
> +#define NBIO_BASE__INST3_SEG2 0
> +#define NBIO_BASE__INST3_SEG3 0
> +#define NBIO_BASE__INST3_SEG4 0
> +
> +#define NBIO_BASE__INST4_SEG0 0
> +#define NBIO_BASE__INST4_SEG1 0
> +#define NBIO_BASE__INST4_SEG2 0
> +#define NBIO_BASE__INST4_SEG3 0
> +#define NBIO_BASE__INST4_SEG4 0
> +
> +#define DCE_BASE__INST0_SEG0 0x00000012
> +#define DCE_BASE__INST0_SEG1 0x000000C0
> +#define DCE_BASE__INST0_SEG2 0x000034C0
> +#define DCE_BASE__INST0_SEG3 0
> +#define DCE_BASE__INST0_SEG4 0
> +
> +#define DCE_BASE__INST1_SEG0 0
> +#define DCE_BASE__INST1_SEG1 0
> +#define DCE_BASE__INST1_SEG2 0
> +#define DCE_BASE__INST1_SEG3 0
> +#define DCE_BASE__INST1_SEG4 0
> +
> +#define DCE_BASE__INST2_SEG0 0
> +#define DCE_BASE__INST2_SEG1 0
> +#define DCE_BASE__INST2_SEG2 0
> +#define DCE_BASE__INST2_SEG3 0
> +#define DCE_BASE__INST2_SEG4 0
> +
> +#define DCE_BASE__INST3_SEG0 0
> +#define DCE_BASE__INST3_SEG1 0
> +#define DCE_BASE__INST3_SEG2 0
> +#define DCE_BASE__INST3_SEG3 0
> +#define DCE_BASE__INST3_SEG4 0
> +
> +#define DCE_BASE__INST4_SEG0 0
> +#define DCE_BASE__INST4_SEG1 0
> +#define DCE_BASE__INST4_SEG2 0
> +#define DCE_BASE__INST4_SEG3 0
> +#define DCE_BASE__INST4_SEG4 0
> +
> +#define DCN_BASE__INST0_SEG0 0x00000012
> +#define DCN_BASE__INST0_SEG1 0x000000C0
> +#define DCN_BASE__INST0_SEG2 0x000034C0
> +#define DCN_BASE__INST0_SEG3 0
> +#define DCN_BASE__INST0_SEG4 0
> +
> +#define DCN_BASE__INST1_SEG0 0
> +#define DCN_BASE__INST1_SEG1 0
> +#define DCN_BASE__INST1_SEG2 0
> +#define DCN_BASE__INST1_SEG3 0
> +#define DCN_BASE__INST1_SEG4 0
> +
> +#define DCN_BASE__INST2_SEG0 0
> +#define DCN_BASE__INST2_SEG1 0
> +#define DCN_BASE__INST2_SEG2 0
> +#define DCN_BASE__INST2_SEG3 0
> +#define DCN_BASE__INST2_SEG4 0
> +
> +#define DCN_BASE__INST3_SEG0 0
> +#define DCN_BASE__INST3_SEG1 0
> +#define DCN_BASE__INST3_SEG2 0
> +#define DCN_BASE__INST3_SEG3 0
> +#define DCN_BASE__INST3_SEG4 0
> +
> +#define DCN_BASE__INST4_SEG0 0
> +#define DCN_BASE__INST4_SEG1 0
> +#define DCN_BASE__INST4_SEG2 0
> +#define DCN_BASE__INST4_SEG3 0
> +#define DCN_BASE__INST4_SEG4 0
> +
> +#define MP0_BASE__INST0_SEG0 0x00016000
> +#define MP0_BASE__INST0_SEG1 0
> +#define MP0_BASE__INST0_SEG2 0
> +#define MP0_BASE__INST0_SEG3 0
> +#define MP0_BASE__INST0_SEG4 0
> +
> +#define MP0_BASE__INST1_SEG0 0
> +#define MP0_BASE__INST1_SEG1 0
> +#define MP0_BASE__INST1_SEG2 0
> +#define MP0_BASE__INST1_SEG3 0
> +#define MP0_BASE__INST1_SEG4 0
> +
> +#define MP0_BASE__INST2_SEG0 0
> +#define MP0_BASE__INST2_SEG1 0
> +#define MP0_BASE__INST2_SEG2 0
> +#define MP0_BASE__INST2_SEG3 0
> +#define MP0_BASE__INST2_SEG4 0
> +
> +#define MP0_BASE__INST3_SEG0 0
> +#define MP0_BASE__INST3_SEG1 0
> +#define MP0_BASE__INST3_SEG2 0
> +#define MP0_BASE__INST3_SEG3 0
> +#define MP0_BASE__INST3_SEG4 0
> +
> +#define MP0_BASE__INST4_SEG0 0
> +#define MP0_BASE__INST4_SEG1 0
> +#define MP0_BASE__INST4_SEG2 0
> +#define MP0_BASE__INST4_SEG3 0
> +#define MP0_BASE__INST4_SEG4 0
> +
> +#define MP1_BASE__INST0_SEG0 0x00016000
> +#define MP1_BASE__INST0_SEG1 0
> +#define MP1_BASE__INST0_SEG2 0
> +#define MP1_BASE__INST0_SEG3 0
> +#define MP1_BASE__INST0_SEG4 0
> +
> +#define MP1_BASE__INST1_SEG0 0
> +#define MP1_BASE__INST1_SEG1 0
> +#define MP1_BASE__INST1_SEG2 0
> +#define MP1_BASE__INST1_SEG3 0
> +#define MP1_BASE__INST1_SEG4 0
> +
> +#define MP1_BASE__INST2_SEG0 0
> +#define MP1_BASE__INST2_SEG1 0
> +#define MP1_BASE__INST2_SEG2 0
> +#define MP1_BASE__INST2_SEG3 0
> +#define MP1_BASE__INST2_SEG4 0
> +
> +#define MP1_BASE__INST3_SEG0 0
> +#define MP1_BASE__INST3_SEG1 0
> +#define MP1_BASE__INST3_SEG2 0
> +#define MP1_BASE__INST3_SEG3 0
> +#define MP1_BASE__INST3_SEG4 0
> +
> +#define MP1_BASE__INST4_SEG0 0
> +#define MP1_BASE__INST4_SEG1 0
> +#define MP1_BASE__INST4_SEG2 0
> +#define MP1_BASE__INST4_SEG3 0
> +#define MP1_BASE__INST4_SEG4 0
> +
> +#define MP2_BASE__INST0_SEG0 0x00016000
> +#define MP2_BASE__INST0_SEG1 0
> +#define MP2_BASE__INST0_SEG2 0
> +#define MP2_BASE__INST0_SEG3 0
> +#define MP2_BASE__INST0_SEG4 0
> +
> +#define MP2_BASE__INST1_SEG0 0
> +#define MP2_BASE__INST1_SEG1 0
> +#define MP2_BASE__INST1_SEG2 0
> +#define MP2_BASE__INST1_SEG3 0
> +#define MP2_BASE__INST1_SEG4 0
> +
> +#define MP2_BASE__INST2_SEG0 0
> +#define MP2_BASE__INST2_SEG1 0
> +#define MP2_BASE__INST2_SEG2 0
> +#define MP2_BASE__INST2_SEG3 0
> +#define MP2_BASE__INST2_SEG4 0
> +
> +#define MP2_BASE__INST3_SEG0 0
> +#define MP2_BASE__INST3_SEG1 0
> +#define MP2_BASE__INST3_SEG2 0
> +#define MP2_BASE__INST3_SEG3 0
> +#define MP2_BASE__INST3_SEG4 0
> +
> +#define MP2_BASE__INST4_SEG0 0
> +#define MP2_BASE__INST4_SEG1 0
> +#define MP2_BASE__INST4_SEG2 0
> +#define MP2_BASE__INST4_SEG3 0
> +#define MP2_BASE__INST4_SEG4 0
> +
> +#define DF_BASE__INST0_SEG0 0x00007000
> +#define DF_BASE__INST0_SEG1 0
> +#define DF_BASE__INST0_SEG2 0
> +#define DF_BASE__INST0_SEG3 0
> +#define DF_BASE__INST0_SEG4 0
> +
> +#define DF_BASE__INST1_SEG0 0
> +#define DF_BASE__INST1_SEG1 0
> +#define DF_BASE__INST1_SEG2 0
> +#define DF_BASE__INST1_SEG3 0
> +#define DF_BASE__INST1_SEG4 0
> +
> +#define DF_BASE__INST2_SEG0 0
> +#define DF_BASE__INST2_SEG1 0
> +#define DF_BASE__INST2_SEG2 0
> +#define DF_BASE__INST2_SEG3 0
> +#define DF_BASE__INST2_SEG4 0
> +
> +#define DF_BASE__INST3_SEG0 0
> +#define DF_BASE__INST3_SEG1 0
> +#define DF_BASE__INST3_SEG2 0
> +#define DF_BASE__INST3_SEG3 0
> +#define DF_BASE__INST3_SEG4 0
> +
> +#define DF_BASE__INST4_SEG0 0
> +#define DF_BASE__INST4_SEG1 0
> +#define DF_BASE__INST4_SEG2 0
> +#define DF_BASE__INST4_SEG3 0
> +#define DF_BASE__INST4_SEG4 0
> +
> +#define UVD_BASE__INST0_SEG0 0x00007800
> +#define UVD_BASE__INST0_SEG1 0x00007E00
> +#define UVD_BASE__INST0_SEG2 0
> +#define UVD_BASE__INST0_SEG3 0
> +#define UVD_BASE__INST0_SEG4 0
> +
> +#define UVD_BASE__INST1_SEG0 0
> +#define UVD_BASE__INST1_SEG1 0
> +#define UVD_BASE__INST1_SEG2 0
> +#define UVD_BASE__INST1_SEG3 0
> +#define UVD_BASE__INST1_SEG4 0
> +
> +#define UVD_BASE__INST2_SEG0 0
> +#define UVD_BASE__INST2_SEG1 0
> +#define UVD_BASE__INST2_SEG2 0
> +#define UVD_BASE__INST2_SEG3 0
> +#define UVD_BASE__INST2_SEG4 0
> +
> +#define UVD_BASE__INST3_SEG0 0
> +#define UVD_BASE__INST3_SEG1 0
> +#define UVD_BASE__INST3_SEG2 0
> +#define UVD_BASE__INST3_SEG3 0
> +#define UVD_BASE__INST3_SEG4 0
> +
> +#define UVD_BASE__INST4_SEG0 0
> +#define UVD_BASE__INST4_SEG1 0
> +#define UVD_BASE__INST4_SEG2 0
> +#define UVD_BASE__INST4_SEG3 0
> +#define UVD_BASE__INST4_SEG4 0
> +
> +#define VCN_BASE__INST0_SEG0 0x00007800
> +#define VCN_BASE__INST0_SEG1 0x00007E00
> +#define VCN_BASE__INST0_SEG2 0
> +#define VCN_BASE__INST0_SEG3 0
> +#define VCN_BASE__INST0_SEG4 0
> +
> +#define VCN_BASE__INST1_SEG0 0
> +#define VCN_BASE__INST1_SEG1 0
> +#define VCN_BASE__INST1_SEG2 0
> +#define VCN_BASE__INST1_SEG3 0
> +#define VCN_BASE__INST1_SEG4 0
> +
> +#define VCN_BASE__INST2_SEG0 0
> +#define VCN_BASE__INST2_SEG1 0
> +#define VCN_BASE__INST2_SEG2 0
> +#define VCN_BASE__INST2_SEG3 0
> +#define VCN_BASE__INST2_SEG4 0
> +
> +#define VCN_BASE__INST3_SEG0 0
> +#define VCN_BASE__INST3_SEG1 0
> +#define VCN_BASE__INST3_SEG2 0
> +#define VCN_BASE__INST3_SEG3 0
> +#define VCN_BASE__INST3_SEG4 0
> +
> +#define VCN_BASE__INST4_SEG0 0
> +#define VCN_BASE__INST4_SEG1 0
> +#define VCN_BASE__INST4_SEG2 0
> +#define VCN_BASE__INST4_SEG3 0
> +#define VCN_BASE__INST4_SEG4 0
> +
> +#define DBGU_BASE__INST0_SEG0 0x00000180
> +#define DBGU_BASE__INST0_SEG1 0x000001A0
> +#define DBGU_BASE__INST0_SEG2 0
> +#define DBGU_BASE__INST0_SEG3 0
> +#define DBGU_BASE__INST0_SEG4 0
> +
> +#define DBGU_BASE__INST1_SEG0 0
> +#define DBGU_BASE__INST1_SEG1 0
> +#define DBGU_BASE__INST1_SEG2 0
> +#define DBGU_BASE__INST1_SEG3 0
> +#define DBGU_BASE__INST1_SEG4 0
> +
> +#define DBGU_BASE__INST2_SEG0 0
> +#define DBGU_BASE__INST2_SEG1 0
> +#define DBGU_BASE__INST2_SEG2 0
> +#define DBGU_BASE__INST2_SEG3 0
> +#define DBGU_BASE__INST2_SEG4 0
> +
> +#define DBGU_BASE__INST3_SEG0 0
> +#define DBGU_BASE__INST3_SEG1 0
> +#define DBGU_BASE__INST3_SEG2 0
> +#define DBGU_BASE__INST3_SEG3 0
> +#define DBGU_BASE__INST3_SEG4 0
> +
> +#define DBGU_BASE__INST4_SEG0 0
> +#define DBGU_BASE__INST4_SEG1 0
> +#define DBGU_BASE__INST4_SEG2 0
> +#define DBGU_BASE__INST4_SEG3 0
> +#define DBGU_BASE__INST4_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
> +#define DBGU_NBIO_BASE__INST0_SEG1 0
> +#define DBGU_NBIO_BASE__INST0_SEG2 0
> +#define DBGU_NBIO_BASE__INST0_SEG3 0
> +#define DBGU_NBIO_BASE__INST0_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST1_SEG0 0
> +#define DBGU_NBIO_BASE__INST1_SEG1 0
> +#define DBGU_NBIO_BASE__INST1_SEG2 0
> +#define DBGU_NBIO_BASE__INST1_SEG3 0
> +#define DBGU_NBIO_BASE__INST1_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST2_SEG0 0
> +#define DBGU_NBIO_BASE__INST2_SEG1 0
> +#define DBGU_NBIO_BASE__INST2_SEG2 0
> +#define DBGU_NBIO_BASE__INST2_SEG3 0
> +#define DBGU_NBIO_BASE__INST2_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST3_SEG0 0
> +#define DBGU_NBIO_BASE__INST3_SEG1 0
> +#define DBGU_NBIO_BASE__INST3_SEG2 0
> +#define DBGU_NBIO_BASE__INST3_SEG3 0
> +#define DBGU_NBIO_BASE__INST3_SEG4 0
> +
> +#define DBGU_NBIO_BASE__INST4_SEG0 0
> +#define DBGU_NBIO_BASE__INST4_SEG1 0
> +#define DBGU_NBIO_BASE__INST4_SEG2 0
> +#define DBGU_NBIO_BASE__INST4_SEG3 0
> +#define DBGU_NBIO_BASE__INST4_SEG4 0
> +
> +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
> +#define DBGU_IO_BASE__INST0_SEG1 0
> +#define DBGU_IO_BASE__INST0_SEG2 0
> +#define DBGU_IO_BASE__INST0_SEG3 0
> +#define DBGU_IO_BASE__INST0_SEG4 0
> +
> +#define DBGU_IO_BASE__INST1_SEG0 0
> +#define DBGU_IO_BASE__INST1_SEG1 0
> +#define DBGU_IO_BASE__INST1_SEG2 0
> +#define DBGU_IO_BASE__INST1_SEG3 0
> +#define DBGU_IO_BASE__INST1_SEG4 0
> +
> +#define DBGU_IO_BASE__INST2_SEG0 0
> +#define DBGU_IO_BASE__INST2_SEG1 0
> +#define DBGU_IO_BASE__INST2_SEG2 0
> +#define DBGU_IO_BASE__INST2_SEG3 0
> +#define DBGU_IO_BASE__INST2_SEG4 0
> +
> +#define DBGU_IO_BASE__INST3_SEG0 0
> +#define DBGU_IO_BASE__INST3_SEG1 0
> +#define DBGU_IO_BASE__INST3_SEG2 0
> +#define DBGU_IO_BASE__INST3_SEG3 0
> +#define DBGU_IO_BASE__INST3_SEG4 0
> +
> +#define DBGU_IO_BASE__INST4_SEG0 0
> +#define DBGU_IO_BASE__INST4_SEG1 0
> +#define DBGU_IO_BASE__INST4_SEG2 0
> +#define DBGU_IO_BASE__INST4_SEG3 0
> +#define DBGU_IO_BASE__INST4_SEG4 0
> +
> +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
> +#define DFX_DAP_BASE__INST0_SEG1 0
> +#define DFX_DAP_BASE__INST0_SEG2 0
> +#define DFX_DAP_BASE__INST0_SEG3 0
> +#define DFX_DAP_BASE__INST0_SEG4 0
> +
> +#define DFX_DAP_BASE__INST1_SEG0 0
> +#define DFX_DAP_BASE__INST1_SEG1 0
> +#define DFX_DAP_BASE__INST1_SEG2 0
> +#define DFX_DAP_BASE__INST1_SEG3 0
> +#define DFX_DAP_BASE__INST1_SEG4 0
> +
> +#define DFX_DAP_BASE__INST2_SEG0 0
> +#define DFX_DAP_BASE__INST2_SEG1 0
> +#define DFX_DAP_BASE__INST2_SEG2 0
> +#define DFX_DAP_BASE__INST2_SEG3 0
> +#define DFX_DAP_BASE__INST2_SEG4 0
> +
> +#define DFX_DAP_BASE__INST3_SEG0 0
> +#define DFX_DAP_BASE__INST3_SEG1 0
> +#define DFX_DAP_BASE__INST3_SEG2 0
> +#define DFX_DAP_BASE__INST3_SEG3 0
> +#define DFX_DAP_BASE__INST3_SEG4 0
> +
> +#define DFX_DAP_BASE__INST4_SEG0 0
> +#define DFX_DAP_BASE__INST4_SEG1 0
> +#define DFX_DAP_BASE__INST4_SEG2 0
> +#define DFX_DAP_BASE__INST4_SEG3 0
> +#define DFX_DAP_BASE__INST4_SEG4 0
> +
> +#define DFX_BASE__INST0_SEG0 0x00000580
> +#define DFX_BASE__INST0_SEG1 0
> +#define DFX_BASE__INST0_SEG2 0
> +#define DFX_BASE__INST0_SEG3 0
> +#define DFX_BASE__INST0_SEG4 0
> +
> +#define DFX_BASE__INST1_SEG0 0
> +#define DFX_BASE__INST1_SEG1 0
> +#define DFX_BASE__INST1_SEG2 0
> +#define DFX_BASE__INST1_SEG3 0
> +#define DFX_BASE__INST1_SEG4 0
> +
> +#define DFX_BASE__INST2_SEG0 0
> +#define DFX_BASE__INST2_SEG1 0
> +#define DFX_BASE__INST2_SEG2 0
> +#define DFX_BASE__INST2_SEG3 0
> +#define DFX_BASE__INST2_SEG4 0
> +
> +#define DFX_BASE__INST3_SEG0 0
> +#define DFX_BASE__INST3_SEG1 0
> +#define DFX_BASE__INST3_SEG2 0
> +#define DFX_BASE__INST3_SEG3 0
> +#define DFX_BASE__INST3_SEG4 0
> +
> +#define DFX_BASE__INST4_SEG0 0
> +#define DFX_BASE__INST4_SEG1 0
> +#define DFX_BASE__INST4_SEG2 0
> +#define DFX_BASE__INST4_SEG3 0
> +#define DFX_BASE__INST4_SEG4 0
> +
> +#define ISP_BASE__INST0_SEG0 0x00018000
> +#define ISP_BASE__INST0_SEG1 0
> +#define ISP_BASE__INST0_SEG2 0
> +#define ISP_BASE__INST0_SEG3 0
> +#define ISP_BASE__INST0_SEG4 0
> +
> +#define ISP_BASE__INST1_SEG0 0
> +#define ISP_BASE__INST1_SEG1 0
> +#define ISP_BASE__INST1_SEG2 0
> +#define ISP_BASE__INST1_SEG3 0
> +#define ISP_BASE__INST1_SEG4 0
> +
> +#define ISP_BASE__INST2_SEG0 0
> +#define ISP_BASE__INST2_SEG1 0
> +#define ISP_BASE__INST2_SEG2 0
> +#define ISP_BASE__INST2_SEG3 0
> +#define ISP_BASE__INST2_SEG4 0
> +
> +#define ISP_BASE__INST3_SEG0 0
> +#define ISP_BASE__INST3_SEG1 0
> +#define ISP_BASE__INST3_SEG2 0
> +#define ISP_BASE__INST3_SEG3 0
> +#define ISP_BASE__INST3_SEG4 0
> +
> +#define ISP_BASE__INST4_SEG0 0
> +#define ISP_BASE__INST4_SEG1 0
> +#define ISP_BASE__INST4_SEG2 0
> +#define ISP_BASE__INST4_SEG3 0
> +#define ISP_BASE__INST4_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
> +#define SYSTEMHUB_BASE__INST0_SEG1 0
> +#define SYSTEMHUB_BASE__INST0_SEG2 0
> +#define SYSTEMHUB_BASE__INST0_SEG3 0
> +#define SYSTEMHUB_BASE__INST0_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST1_SEG0 0
> +#define SYSTEMHUB_BASE__INST1_SEG1 0
> +#define SYSTEMHUB_BASE__INST1_SEG2 0
> +#define SYSTEMHUB_BASE__INST1_SEG3 0
> +#define SYSTEMHUB_BASE__INST1_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST2_SEG0 0
> +#define SYSTEMHUB_BASE__INST2_SEG1 0
> +#define SYSTEMHUB_BASE__INST2_SEG2 0
> +#define SYSTEMHUB_BASE__INST2_SEG3 0
> +#define SYSTEMHUB_BASE__INST2_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST3_SEG0 0
> +#define SYSTEMHUB_BASE__INST3_SEG1 0
> +#define SYSTEMHUB_BASE__INST3_SEG2 0
> +#define SYSTEMHUB_BASE__INST3_SEG3 0
> +#define SYSTEMHUB_BASE__INST3_SEG4 0
> +
> +#define SYSTEMHUB_BASE__INST4_SEG0 0
> +#define SYSTEMHUB_BASE__INST4_SEG1 0
> +#define SYSTEMHUB_BASE__INST4_SEG2 0
> +#define SYSTEMHUB_BASE__INST4_SEG3 0
> +#define SYSTEMHUB_BASE__INST4_SEG4 0
> +
> +#define L2IMU_BASE__INST0_SEG0 0x00007DC0
> +#define L2IMU_BASE__INST0_SEG1 0
> +#define L2IMU_BASE__INST0_SEG2 0
> +#define L2IMU_BASE__INST0_SEG3 0
> +#define L2IMU_BASE__INST0_SEG4 0
> +
> +#define L2IMU_BASE__INST1_SEG0 0
> +#define L2IMU_BASE__INST1_SEG1 0
> +#define L2IMU_BASE__INST1_SEG2 0
> +#define L2IMU_BASE__INST1_SEG3 0
> +#define L2IMU_BASE__INST1_SEG4 0
> +
> +#define L2IMU_BASE__INST2_SEG0 0
> +#define L2IMU_BASE__INST2_SEG1 0
> +#define L2IMU_BASE__INST2_SEG2 0
> +#define L2IMU_BASE__INST2_SEG3 0
> +#define L2IMU_BASE__INST2_SEG4 0
> +
> +#define L2IMU_BASE__INST3_SEG0 0
> +#define L2IMU_BASE__INST3_SEG1 0
> +#define L2IMU_BASE__INST3_SEG2 0
> +#define L2IMU_BASE__INST3_SEG3 0
> +#define L2IMU_BASE__INST3_SEG4 0
> +
> +#define L2IMU_BASE__INST4_SEG0 0
> +#define L2IMU_BASE__INST4_SEG1 0
> +#define L2IMU_BASE__INST4_SEG2 0
> +#define L2IMU_BASE__INST4_SEG3 0
> +#define L2IMU_BASE__INST4_SEG4 0
> +
> +#define IOHC_BASE__INST0_SEG0 0x00010000
> +#define IOHC_BASE__INST0_SEG1 0
> +#define IOHC_BASE__INST0_SEG2 0
> +#define IOHC_BASE__INST0_SEG3 0
> +#define IOHC_BASE__INST0_SEG4 0
> +
> +#define IOHC_BASE__INST1_SEG0 0
> +#define IOHC_BASE__INST1_SEG1 0
> +#define IOHC_BASE__INST1_SEG2 0
> +#define IOHC_BASE__INST1_SEG3 0
> +#define IOHC_BASE__INST1_SEG4 0
> +
> +#define IOHC_BASE__INST2_SEG0 0
> +#define IOHC_BASE__INST2_SEG1 0
> +#define IOHC_BASE__INST2_SEG2 0
> +#define IOHC_BASE__INST2_SEG3 0
> +#define IOHC_BASE__INST2_SEG4 0
> +
> +#define IOHC_BASE__INST3_SEG0 0
> +#define IOHC_BASE__INST3_SEG1 0
> +#define IOHC_BASE__INST3_SEG2 0
> +#define IOHC_BASE__INST3_SEG3 0
> +#define IOHC_BASE__INST3_SEG4 0
> +
> +#define IOHC_BASE__INST4_SEG0 0
> +#define IOHC_BASE__INST4_SEG1 0
> +#define IOHC_BASE__INST4_SEG2 0
> +#define IOHC_BASE__INST4_SEG3 0
> +#define IOHC_BASE__INST4_SEG4 0
> +
> +#define ATHUB_BASE__INST0_SEG0 0x00000C20
> +#define ATHUB_BASE__INST0_SEG1 0
> +#define ATHUB_BASE__INST0_SEG2 0
> +#define ATHUB_BASE__INST0_SEG3 0
> +#define ATHUB_BASE__INST0_SEG4 0
> +
> +#define ATHUB_BASE__INST1_SEG0 0
> +#define ATHUB_BASE__INST1_SEG1 0
> +#define ATHUB_BASE__INST1_SEG2 0
> +#define ATHUB_BASE__INST1_SEG3 0
> +#define ATHUB_BASE__INST1_SEG4 0
> +
> +#define ATHUB_BASE__INST2_SEG0 0
> +#define ATHUB_BASE__INST2_SEG1 0
> +#define ATHUB_BASE__INST2_SEG2 0
> +#define ATHUB_BASE__INST2_SEG3 0
> +#define ATHUB_BASE__INST2_SEG4 0
> +
> +#define ATHUB_BASE__INST3_SEG0 0
> +#define ATHUB_BASE__INST3_SEG1 0
> +#define ATHUB_BASE__INST3_SEG2 0
> +#define ATHUB_BASE__INST3_SEG3 0
> +#define ATHUB_BASE__INST3_SEG4 0
> +
> +#define ATHUB_BASE__INST4_SEG0 0
> +#define ATHUB_BASE__INST4_SEG1 0
> +#define ATHUB_BASE__INST4_SEG2 0
> +#define ATHUB_BASE__INST4_SEG3 0
> +#define ATHUB_BASE__INST4_SEG4 0
> +
> +#define VCE_BASE__INST0_SEG0 0x00007E00
> +#define VCE_BASE__INST0_SEG1 0x00048800
> +#define VCE_BASE__INST0_SEG2 0
> +#define VCE_BASE__INST0_SEG3 0
> +#define VCE_BASE__INST0_SEG4 0
> +
> +#define VCE_BASE__INST1_SEG0 0
> +#define VCE_BASE__INST1_SEG1 0
> +#define VCE_BASE__INST1_SEG2 0
> +#define VCE_BASE__INST1_SEG3 0
> +#define VCE_BASE__INST1_SEG4 0
> +
> +#define VCE_BASE__INST2_SEG0 0
> +#define VCE_BASE__INST2_SEG1 0
> +#define VCE_BASE__INST2_SEG2 0
> +#define VCE_BASE__INST2_SEG3 0
> +#define VCE_BASE__INST2_SEG4 0
> +
> +#define VCE_BASE__INST3_SEG0 0
> +#define VCE_BASE__INST3_SEG1 0
> +#define VCE_BASE__INST3_SEG2 0
> +#define VCE_BASE__INST3_SEG3 0
> +#define VCE_BASE__INST3_SEG4 0
> +
> +#define VCE_BASE__INST4_SEG0 0
> +#define VCE_BASE__INST4_SEG1 0
> +#define VCE_BASE__INST4_SEG2 0
> +#define VCE_BASE__INST4_SEG3 0
> +#define VCE_BASE__INST4_SEG4 0
> +
> +#define GC_BASE__INST0_SEG0 0x00002000
> +#define GC_BASE__INST0_SEG1 0x0000A000
> +#define GC_BASE__INST0_SEG2 0
> +#define GC_BASE__INST0_SEG3 0
> +#define GC_BASE__INST0_SEG4 0
> +
> +#define GC_BASE__INST1_SEG0 0
> +#define GC_BASE__INST1_SEG1 0
> +#define GC_BASE__INST1_SEG2 0
> +#define GC_BASE__INST1_SEG3 0
> +#define GC_BASE__INST1_SEG4 0
> +
> +#define GC_BASE__INST2_SEG0 0
> +#define GC_BASE__INST2_SEG1 0
> +#define GC_BASE__INST2_SEG2 0
> +#define GC_BASE__INST2_SEG3 0
> +#define GC_BASE__INST2_SEG4 0
> +
> +#define GC_BASE__INST3_SEG0 0
> +#define GC_BASE__INST3_SEG1 0
> +#define GC_BASE__INST3_SEG2 0
> +#define GC_BASE__INST3_SEG3 0
> +#define GC_BASE__INST3_SEG4 0
> +
> +#define GC_BASE__INST4_SEG0 0
> +#define GC_BASE__INST4_SEG1 0
> +#define GC_BASE__INST4_SEG2 0
> +#define GC_BASE__INST4_SEG3 0
> +#define GC_BASE__INST4_SEG4 0
> +
> +#define MMHUB_BASE__INST0_SEG0 0x0001A000
> +#define MMHUB_BASE__INST0_SEG1 0
> +#define MMHUB_BASE__INST0_SEG2 0
> +#define MMHUB_BASE__INST0_SEG3 0
> +#define MMHUB_BASE__INST0_SEG4 0
> +
> +#define MMHUB_BASE__INST1_SEG0 0
> +#define MMHUB_BASE__INST1_SEG1 0
> +#define MMHUB_BASE__INST1_SEG2 0
> +#define MMHUB_BASE__INST1_SEG3 0
> +#define MMHUB_BASE__INST1_SEG4 0
> +
> +#define MMHUB_BASE__INST2_SEG0 0
> +#define MMHUB_BASE__INST2_SEG1 0
> +#define MMHUB_BASE__INST2_SEG2 0
> +#define MMHUB_BASE__INST2_SEG3 0
> +#define MMHUB_BASE__INST2_SEG4 0
> +
> +#define MMHUB_BASE__INST3_SEG0 0
> +#define MMHUB_BASE__INST3_SEG1 0
> +#define MMHUB_BASE__INST3_SEG2 0
> +#define MMHUB_BASE__INST3_SEG3 0
> +#define MMHUB_BASE__INST3_SEG4 0
> +
> +#define MMHUB_BASE__INST4_SEG0 0
> +#define MMHUB_BASE__INST4_SEG1 0
> +#define MMHUB_BASE__INST4_SEG2 0
> +#define MMHUB_BASE__INST4_SEG3 0
> +#define MMHUB_BASE__INST4_SEG4 0
> +
> +#define RSMU_BASE__INST0_SEG0 0x00012000
> +#define RSMU_BASE__INST0_SEG1 0
> +#define RSMU_BASE__INST0_SEG2 0
> +#define RSMU_BASE__INST0_SEG3 0
> +#define RSMU_BASE__INST0_SEG4 0
> +
> +#define RSMU_BASE__INST1_SEG0 0
> +#define RSMU_BASE__INST1_SEG1 0
> +#define RSMU_BASE__INST1_SEG2 0
> +#define RSMU_BASE__INST1_SEG3 0
> +#define RSMU_BASE__INST1_SEG4 0
> +
> +#define RSMU_BASE__INST2_SEG0 0
> +#define RSMU_BASE__INST2_SEG1 0
> +#define RSMU_BASE__INST2_SEG2 0
> +#define RSMU_BASE__INST2_SEG3 0
> +#define RSMU_BASE__INST2_SEG4 0
> +
> +#define RSMU_BASE__INST3_SEG0 0
> +#define RSMU_BASE__INST3_SEG1 0
> +#define RSMU_BASE__INST3_SEG2 0
> +#define RSMU_BASE__INST3_SEG3 0
> +#define RSMU_BASE__INST3_SEG4 0
> +
> +#define RSMU_BASE__INST4_SEG0 0
> +#define RSMU_BASE__INST4_SEG1 0
> +#define RSMU_BASE__INST4_SEG2 0
> +#define RSMU_BASE__INST4_SEG3 0
> +#define RSMU_BASE__INST4_SEG4 0
> +
> +#define HDP_BASE__INST0_SEG0 0x00000F20
> +#define HDP_BASE__INST0_SEG1 0
> +#define HDP_BASE__INST0_SEG2 0
> +#define HDP_BASE__INST0_SEG3 0
> +#define HDP_BASE__INST0_SEG4 0
> +
> +#define HDP_BASE__INST1_SEG0 0
> +#define HDP_BASE__INST1_SEG1 0
> +#define HDP_BASE__INST1_SEG2 0
> +#define HDP_BASE__INST1_SEG3 0
> +#define HDP_BASE__INST1_SEG4 0
> +
> +#define HDP_BASE__INST2_SEG0 0
> +#define HDP_BASE__INST2_SEG1 0
> +#define HDP_BASE__INST2_SEG2 0
> +#define HDP_BASE__INST2_SEG3 0
> +#define HDP_BASE__INST2_SEG4 0
> +
> +#define HDP_BASE__INST3_SEG0 0
> +#define HDP_BASE__INST3_SEG1 0
> +#define HDP_BASE__INST3_SEG2 0
> +#define HDP_BASE__INST3_SEG3 0
> +#define HDP_BASE__INST3_SEG4 0
> +
> +#define HDP_BASE__INST4_SEG0 0
> +#define HDP_BASE__INST4_SEG1 0
> +#define HDP_BASE__INST4_SEG2 0
> +#define HDP_BASE__INST4_SEG3 0
> +#define HDP_BASE__INST4_SEG4 0
> +
> +#define OSSSYS_BASE__INST0_SEG0 0x000010A0
> +#define OSSSYS_BASE__INST0_SEG1 0
> +#define OSSSYS_BASE__INST0_SEG2 0
> +#define OSSSYS_BASE__INST0_SEG3 0
> +#define OSSSYS_BASE__INST0_SEG4 0
> +
> +#define OSSSYS_BASE__INST1_SEG0 0
> +#define OSSSYS_BASE__INST1_SEG1 0
> +#define OSSSYS_BASE__INST1_SEG2 0
> +#define OSSSYS_BASE__INST1_SEG3 0
> +#define OSSSYS_BASE__INST1_SEG4 0
> +
> +#define OSSSYS_BASE__INST2_SEG0 0
> +#define OSSSYS_BASE__INST2_SEG1 0
> +#define OSSSYS_BASE__INST2_SEG2 0
> +#define OSSSYS_BASE__INST2_SEG3 0
> +#define OSSSYS_BASE__INST2_SEG4 0
> +
> +#define OSSSYS_BASE__INST3_SEG0 0
> +#define OSSSYS_BASE__INST3_SEG1 0
> +#define OSSSYS_BASE__INST3_SEG2 0
> +#define OSSSYS_BASE__INST3_SEG3 0
> +#define OSSSYS_BASE__INST3_SEG4 0
> +
> +#define OSSSYS_BASE__INST4_SEG0 0
> +#define OSSSYS_BASE__INST4_SEG1 0
> +#define OSSSYS_BASE__INST4_SEG2 0
> +#define OSSSYS_BASE__INST4_SEG3 0
> +#define OSSSYS_BASE__INST4_SEG4 0
> +
> +#define SDMA0_BASE__INST0_SEG0 0x00001260
> +#define SDMA0_BASE__INST0_SEG1 0
> +#define SDMA0_BASE__INST0_SEG2 0
> +#define SDMA0_BASE__INST0_SEG3 0
> +#define SDMA0_BASE__INST0_SEG4 0
> +
> +#define SDMA0_BASE__INST1_SEG0 0
> +#define SDMA0_BASE__INST1_SEG1 0
> +#define SDMA0_BASE__INST1_SEG2 0
> +#define SDMA0_BASE__INST1_SEG3 0
> +#define SDMA0_BASE__INST1_SEG4 0
> +
> +#define SDMA0_BASE__INST2_SEG0 0
> +#define SDMA0_BASE__INST2_SEG1 0
> +#define SDMA0_BASE__INST2_SEG2 0
> +#define SDMA0_BASE__INST2_SEG3 0
> +#define SDMA0_BASE__INST2_SEG4 0
> +
> +#define SDMA0_BASE__INST3_SEG0 0
> +#define SDMA0_BASE__INST3_SEG1 0
> +#define SDMA0_BASE__INST3_SEG2 0
> +#define SDMA0_BASE__INST3_SEG3 0
> +#define SDMA0_BASE__INST3_SEG4 0
> +
> +#define SDMA0_BASE__INST4_SEG0 0
> +#define SDMA0_BASE__INST4_SEG1 0
> +#define SDMA0_BASE__INST4_SEG2 0
> +#define SDMA0_BASE__INST4_SEG3 0
> +#define SDMA0_BASE__INST4_SEG4 0
> +
> +#define SDMA1_BASE__INST0_SEG0 0x00001460
> +#define SDMA1_BASE__INST0_SEG1 0
> +#define SDMA1_BASE__INST0_SEG2 0
> +#define SDMA1_BASE__INST0_SEG3 0
> +#define SDMA1_BASE__INST0_SEG4 0
> +
> +#define SDMA1_BASE__INST1_SEG0 0
> +#define SDMA1_BASE__INST1_SEG1 0
> +#define SDMA1_BASE__INST1_SEG2 0
> +#define SDMA1_BASE__INST1_SEG3 0
> +#define SDMA1_BASE__INST1_SEG4 0
> +
> +#define SDMA1_BASE__INST2_SEG0 0
> +#define SDMA1_BASE__INST2_SEG1 0
> +#define SDMA1_BASE__INST2_SEG2 0
> +#define SDMA1_BASE__INST2_SEG3 0
> +#define SDMA1_BASE__INST2_SEG4 0
> +
> +#define SDMA1_BASE__INST3_SEG0 0
> +#define SDMA1_BASE__INST3_SEG1 0
> +#define SDMA1_BASE__INST3_SEG2 0
> +#define SDMA1_BASE__INST3_SEG3 0
> +#define SDMA1_BASE__INST3_SEG4 0
> +
> +#define SDMA1_BASE__INST4_SEG0 0
> +#define SDMA1_BASE__INST4_SEG1 0
> +#define SDMA1_BASE__INST4_SEG2 0
> +#define SDMA1_BASE__INST4_SEG3 0
> +#define SDMA1_BASE__INST4_SEG4 0
> +
> +#define XDMA_BASE__INST0_SEG0 0x00003400
> +#define XDMA_BASE__INST0_SEG1 0
> +#define XDMA_BASE__INST0_SEG2 0
> +#define XDMA_BASE__INST0_SEG3 0
> +#define XDMA_BASE__INST0_SEG4 0
> +
> +#define XDMA_BASE__INST1_SEG0 0
> +#define XDMA_BASE__INST1_SEG1 0
> +#define XDMA_BASE__INST1_SEG2 0
> +#define XDMA_BASE__INST1_SEG3 0
>
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^ permalink raw reply [flat|nested] 14+ messages in thread[parent not found: <2a0a3687-0207-4ea0-bb2c-20750a1d2bb3-2ueSQiBKiTY7tOexoI0I+QC/G2K4zDHf@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <2a0a3687-0207-4ea0-bb2c-20750a1d2bb3-2ueSQiBKiTY7tOexoI0I+QC/G2K4zDHf@public.gmane.org> @ 2017-11-27 20:01 ` Felix Kuehling [not found] ` <702bfce6-78ef-0284-6306-f4b3366d34f7-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: Felix Kuehling @ 2017-11-27 20:01 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Christian König On 2017-11-27 02:37 PM, Koenig, Christian wrote: > And that is a clear NAK to this approach. Hi Christian, Do you have other objections than the style issues? If so, please explain. Please clarify, why this file needs to be treated differently from other files under include/asic_reg? All those files are auto-generated by HW teams. Fixing the coding style adds no value and makes future updates more complicated. Like Shaoyun pointed out for example, the existing file include/asic_reg/vega10/soc15ip.h has the same style issues. Regards, Felix > > Please start by fixing at least the obvious style problems before > resending. > > Thanks, > Christian. > > Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: > > I agree that this HW engineer generated file doesn't match the > coding style from linux software engineer point of view , but > since we already import other similar " HW engineer style" files > under include/asic_reg/vega10/, I don't see a reason to specially > change this file without touch else . This file is actually almost > identical as soc15ip.h . I think it's easier for us to import > other offset file in the future if we keep them un-touched . > > Regards > Shaoyun.liu > > > -----Original Message----- > From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] > Sent: Monday, November 27, 2017 2:17 PM > To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file > > First of let us fix the obvious style problems. > > Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: > > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c > > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> > > --- > > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 > ++++++++++++++++++++ > > 1 file changed, 1248 insertions(+) > > create mode 100644 > drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > > > diff --git > a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > new file mode 100644 > > index 0000000..76cb748 > > --- /dev/null > > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h > > @@ -0,0 +1,1248 @@ > > +#ifndef _ip_offset_1_HEADER > > +#define _ip_offset_1_HEADER > Names for preprocessor defines should be capitable. > > > + > > +#define MAX_INSTANCE 5 > > +#define MAX_SEGMENT 5 > > + > > + > > +struct IP_BASE_INSTANCE > > Structure names should be lower case. And we need an amdgpu_ or at > least > amd_ prefix here. > > Regards, > Christian. > > > +{ > > + unsigned int segment[MAX_SEGMENT]; > > +}; > > + > > +struct IP_BASE > > +{ > > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; > > +}; > > + > > + > > +static const struct IP_BASE NBIF_BASE = > { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE NBIO_BASE = > { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE DCE_BASE = { { { { > 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE DCN_BASE = { { { { > 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE MP0_BASE = { { { { > 0x00016000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE MP1_BASE = { { { { > 0x00016000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE MP2_BASE = { { { { > 0x00016000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE DF_BASE = { { { { > 0x00007000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE UVD_BASE = { { { { > 0x00007800, 0x00007E00, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > > No "//" in kernel code please. > > > +static const struct IP_BASE VCN_BASE = { { { { > 0x00007800, 0x00007E00, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment > > +static const struct IP_BASE DBGU_BASE = > { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { > 0x000001C0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE DBGU_IO_BASE = { { { { > 0x000001E0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE DFX_DAP_BASE = { { { { > 0x000005A0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE DFX_BASE = { { { { > 0x00000580, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers > > +static const struct IP_BASE ISP_BASE = { { { { > 0x00018000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { > 0x00000EA0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; // not exist > > +static const struct IP_BASE L2IMU_BASE = > { { { { 0x00007DC0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE IOHC_BASE = > { { { { 0x00010000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE ATHUB_BASE = > { { { { 0x00000C20, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE VCE_BASE = { { { { > 0x00007E00, 0x00048800, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE GC_BASE = { { { { > 0x00002000, 0x0000A000, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE MMHUB_BASE = > { { { { 0x0001A000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE RSMU_BASE = > { { { { 0x00012000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE HDP_BASE = { { { { > 0x00000F20, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE OSSSYS_BASE = { { { { > 0x000010A0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE SDMA0_BASE = > { { { { 0x00001260, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE SDMA1_BASE = > { { { { 0x00001460, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE XDMA_BASE = > { { { { 0x00003400, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE UMC_BASE = { { { { > 0x00014000, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE THM_BASE = { { { { > 0x00016600, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE SMUIO_BASE = > { { { { 0x00016800, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE PWR_BASE = { { { { > 0x00016A00, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE CLK_BASE = { { { { > 0x00016C00, 0, 0, 0, 0 } }, > > > + > { { 0x00016E00, 0, 0, 0, 0 } }, > > > + > { { 0x00017000, 0, 0, 0, 0 } }, > > + { { 0x00017200, 0, 0, > 0, 0 } }, > > + { > { 0x00017E00, 0, 0, 0, 0 } } } }; > > +static const struct IP_BASE FUSE_BASE = > { { { { 0x00017400, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } }, > > > + > { { 0, 0, 0, 0, 0 } } } }; > > + > > + > > +#define NBIF_BASE__INST0_SEG0 0x00000000 > > +#define NBIF_BASE__INST0_SEG1 0x00000014 > > +#define NBIF_BASE__INST0_SEG2 0x00000D20 > > +#define NBIF_BASE__INST0_SEG3 0x00010400 > > +#define NBIF_BASE__INST0_SEG4 0 > > + > > +#define NBIF_BASE__INST1_SEG0 0 > > +#define NBIF_BASE__INST1_SEG1 0 > > +#define NBIF_BASE__INST1_SEG2 0 > > +#define NBIF_BASE__INST1_SEG3 0 > > +#define NBIF_BASE__INST1_SEG4 0 > > + > > +#define NBIF_BASE__INST2_SEG0 0 > > +#define NBIF_BASE__INST2_SEG1 0 > > +#define NBIF_BASE__INST2_SEG2 0 > > +#define NBIF_BASE__INST2_SEG3 0 > > +#define NBIF_BASE__INST2_SEG4 0 > > + > > +#define NBIF_BASE__INST3_SEG0 0 > > +#define NBIF_BASE__INST3_SEG1 0 > > +#define NBIF_BASE__INST3_SEG2 0 > > +#define NBIF_BASE__INST3_SEG3 0 > > +#define NBIF_BASE__INST3_SEG4 0 > > + > > +#define NBIF_BASE__INST4_SEG0 0 > > +#define NBIF_BASE__INST4_SEG1 0 > > +#define NBIF_BASE__INST4_SEG2 0 > > +#define NBIF_BASE__INST4_SEG3 0 > > +#define NBIF_BASE__INST4_SEG4 0 > > + > > +#define NBIO_BASE__INST0_SEG0 0x00000000 > > +#define NBIO_BASE__INST0_SEG1 0x00000014 > > +#define NBIO_BASE__INST0_SEG2 0x00000D20 > > +#define NBIO_BASE__INST0_SEG3 0x00010400 > > +#define NBIO_BASE__INST0_SEG4 0 > > + > > +#define NBIO_BASE__INST1_SEG0 0 > > +#define NBIO_BASE__INST1_SEG1 0 > > +#define NBIO_BASE__INST1_SEG2 0 > > +#define NBIO_BASE__INST1_SEG3 0 > > +#define NBIO_BASE__INST1_SEG4 0 > > + > > +#define NBIO_BASE__INST2_SEG0 0 > > +#define NBIO_BASE__INST2_SEG1 0 > > +#define NBIO_BASE__INST2_SEG2 0 > > +#define NBIO_BASE__INST2_SEG3 0 > > +#define NBIO_BASE__INST2_SEG4 0 > > + > > +#define NBIO_BASE__INST3_SEG0 0 > > +#define NBIO_BASE__INST3_SEG1 0 > > +#define NBIO_BASE__INST3_SEG2 0 > > +#define NBIO_BASE__INST3_SEG3 0 > > +#define NBIO_BASE__INST3_SEG4 0 > > + > > +#define NBIO_BASE__INST4_SEG0 0 > > +#define NBIO_BASE__INST4_SEG1 0 > > +#define NBIO_BASE__INST4_SEG2 0 > > +#define NBIO_BASE__INST4_SEG3 0 > > +#define NBIO_BASE__INST4_SEG4 0 > > + > > +#define DCE_BASE__INST0_SEG0 0x00000012 > > +#define DCE_BASE__INST0_SEG1 0x000000C0 > > +#define DCE_BASE__INST0_SEG2 0x000034C0 > > +#define DCE_BASE__INST0_SEG3 0 > > +#define DCE_BASE__INST0_SEG4 0 > > + > > +#define DCE_BASE__INST1_SEG0 0 > > +#define DCE_BASE__INST1_SEG1 0 > > +#define DCE_BASE__INST1_SEG2 0 > > +#define DCE_BASE__INST1_SEG3 0 > > +#define DCE_BASE__INST1_SEG4 0 > > + > > +#define DCE_BASE__INST2_SEG0 0 > > +#define DCE_BASE__INST2_SEG1 0 > > +#define DCE_BASE__INST2_SEG2 0 > > +#define DCE_BASE__INST2_SEG3 0 > > +#define DCE_BASE__INST2_SEG4 0 > > + > > +#define DCE_BASE__INST3_SEG0 0 > > +#define DCE_BASE__INST3_SEG1 0 > > +#define DCE_BASE__INST3_SEG2 0 > > +#define DCE_BASE__INST3_SEG3 0 > > +#define DCE_BASE__INST3_SEG4 0 > > + > > +#define DCE_BASE__INST4_SEG0 0 > > +#define DCE_BASE__INST4_SEG1 0 > > +#define DCE_BASE__INST4_SEG2 0 > > +#define DCE_BASE__INST4_SEG3 0 > > +#define DCE_BASE__INST4_SEG4 0 > > + > > +#define DCN_BASE__INST0_SEG0 0x00000012 > > +#define DCN_BASE__INST0_SEG1 0x000000C0 > > +#define DCN_BASE__INST0_SEG2 0x000034C0 > > +#define DCN_BASE__INST0_SEG3 0 > > +#define DCN_BASE__INST0_SEG4 0 > > + > > +#define DCN_BASE__INST1_SEG0 0 > > +#define DCN_BASE__INST1_SEG1 0 > > +#define DCN_BASE__INST1_SEG2 0 > > +#define DCN_BASE__INST1_SEG3 0 > > +#define DCN_BASE__INST1_SEG4 0 > > + > > +#define DCN_BASE__INST2_SEG0 0 > > +#define DCN_BASE__INST2_SEG1 0 > > +#define DCN_BASE__INST2_SEG2 0 > > +#define DCN_BASE__INST2_SEG3 0 > > +#define DCN_BASE__INST2_SEG4 0 > > + > > +#define DCN_BASE__INST3_SEG0 0 > > +#define DCN_BASE__INST3_SEG1 0 > > +#define DCN_BASE__INST3_SEG2 0 > > +#define DCN_BASE__INST3_SEG3 0 > > +#define DCN_BASE__INST3_SEG4 0 > > + > > +#define DCN_BASE__INST4_SEG0 0 > > +#define DCN_BASE__INST4_SEG1 0 > > +#define DCN_BASE__INST4_SEG2 0 > > +#define DCN_BASE__INST4_SEG3 0 > > +#define DCN_BASE__INST4_SEG4 0 > > + > > +#define MP0_BASE__INST0_SEG0 0x00016000 > > +#define MP0_BASE__INST0_SEG1 0 > > +#define MP0_BASE__INST0_SEG2 0 > > +#define MP0_BASE__INST0_SEG3 0 > > +#define MP0_BASE__INST0_SEG4 0 > > + > > +#define MP0_BASE__INST1_SEG0 0 > > +#define MP0_BASE__INST1_SEG1 0 > > +#define MP0_BASE__INST1_SEG2 0 > > +#define MP0_BASE__INST1_SEG3 0 > > +#define MP0_BASE__INST1_SEG4 0 > > + > > +#define MP0_BASE__INST2_SEG0 0 > > +#define MP0_BASE__INST2_SEG1 0 > > +#define MP0_BASE__INST2_SEG2 0 > > +#define MP0_BASE__INST2_SEG3 0 > > +#define MP0_BASE__INST2_SEG4 0 > > + > > +#define MP0_BASE__INST3_SEG0 0 > > +#define MP0_BASE__INST3_SEG1 0 > > +#define MP0_BASE__INST3_SEG2 0 > > +#define MP0_BASE__INST3_SEG3 0 > > +#define MP0_BASE__INST3_SEG4 0 > > + > > +#define MP0_BASE__INST4_SEG0 0 > > +#define MP0_BASE__INST4_SEG1 0 > > +#define MP0_BASE__INST4_SEG2 0 > > +#define MP0_BASE__INST4_SEG3 0 > > +#define MP0_BASE__INST4_SEG4 0 > > + > > +#define MP1_BASE__INST0_SEG0 0x00016000 > > +#define MP1_BASE__INST0_SEG1 0 > > +#define MP1_BASE__INST0_SEG2 0 > > +#define MP1_BASE__INST0_SEG3 0 > > +#define MP1_BASE__INST0_SEG4 0 > > + > > +#define MP1_BASE__INST1_SEG0 0 > > +#define MP1_BASE__INST1_SEG1 0 > > +#define MP1_BASE__INST1_SEG2 0 > > +#define MP1_BASE__INST1_SEG3 0 > > +#define MP1_BASE__INST1_SEG4 0 > > + > > +#define MP1_BASE__INST2_SEG0 0 > > +#define MP1_BASE__INST2_SEG1 0 > > +#define MP1_BASE__INST2_SEG2 0 > > +#define MP1_BASE__INST2_SEG3 0 > > +#define MP1_BASE__INST2_SEG4 0 > > + > > +#define MP1_BASE__INST3_SEG0 0 > > +#define MP1_BASE__INST3_SEG1 0 > > +#define MP1_BASE__INST3_SEG2 0 > > +#define MP1_BASE__INST3_SEG3 0 > > +#define MP1_BASE__INST3_SEG4 0 > > + > > +#define MP1_BASE__INST4_SEG0 0 > > +#define MP1_BASE__INST4_SEG1 0 > > +#define MP1_BASE__INST4_SEG2 0 > > +#define MP1_BASE__INST4_SEG3 0 > > +#define MP1_BASE__INST4_SEG4 0 > > + > > +#define MP2_BASE__INST0_SEG0 0x00016000 > > +#define MP2_BASE__INST0_SEG1 0 > > +#define MP2_BASE__INST0_SEG2 0 > > +#define MP2_BASE__INST0_SEG3 0 > > +#define MP2_BASE__INST0_SEG4 0 > > + > > +#define MP2_BASE__INST1_SEG0 0 > > +#define MP2_BASE__INST1_SEG1 0 > > +#define MP2_BASE__INST1_SEG2 0 > > +#define MP2_BASE__INST1_SEG3 0 > > +#define MP2_BASE__INST1_SEG4 0 > > + > > +#define MP2_BASE__INST2_SEG0 0 > > +#define MP2_BASE__INST2_SEG1 0 > > +#define MP2_BASE__INST2_SEG2 0 > > +#define MP2_BASE__INST2_SEG3 0 > > +#define MP2_BASE__INST2_SEG4 0 > > + > > +#define MP2_BASE__INST3_SEG0 0 > > +#define MP2_BASE__INST3_SEG1 0 > > +#define MP2_BASE__INST3_SEG2 0 > > +#define MP2_BASE__INST3_SEG3 0 > > +#define MP2_BASE__INST3_SEG4 0 > > + > > +#define MP2_BASE__INST4_SEG0 0 > > +#define MP2_BASE__INST4_SEG1 0 > > +#define MP2_BASE__INST4_SEG2 0 > > +#define MP2_BASE__INST4_SEG3 0 > > +#define MP2_BASE__INST4_SEG4 0 > > + > > +#define DF_BASE__INST0_SEG0 0x00007000 > > +#define DF_BASE__INST0_SEG1 0 > > +#define DF_BASE__INST0_SEG2 0 > > +#define DF_BASE__INST0_SEG3 0 > > +#define DF_BASE__INST0_SEG4 0 > > + > > +#define DF_BASE__INST1_SEG0 0 > > +#define DF_BASE__INST1_SEG1 0 > > +#define DF_BASE__INST1_SEG2 0 > > +#define DF_BASE__INST1_SEG3 0 > > +#define DF_BASE__INST1_SEG4 0 > > + > > +#define DF_BASE__INST2_SEG0 0 > > +#define DF_BASE__INST2_SEG1 0 > > +#define DF_BASE__INST2_SEG2 0 > > +#define DF_BASE__INST2_SEG3 0 > > +#define DF_BASE__INST2_SEG4 0 > > + > > +#define DF_BASE__INST3_SEG0 0 > > +#define DF_BASE__INST3_SEG1 0 > > +#define DF_BASE__INST3_SEG2 0 > > +#define DF_BASE__INST3_SEG3 0 > > +#define DF_BASE__INST3_SEG4 0 > > + > > +#define DF_BASE__INST4_SEG0 0 > > +#define DF_BASE__INST4_SEG1 0 > > +#define DF_BASE__INST4_SEG2 0 > > +#define DF_BASE__INST4_SEG3 0 > > +#define DF_BASE__INST4_SEG4 0 > > + > > +#define UVD_BASE__INST0_SEG0 0x00007800 > > +#define UVD_BASE__INST0_SEG1 0x00007E00 > > +#define UVD_BASE__INST0_SEG2 0 > > +#define UVD_BASE__INST0_SEG3 0 > > +#define UVD_BASE__INST0_SEG4 0 > > + > > +#define UVD_BASE__INST1_SEG0 0 > > +#define UVD_BASE__INST1_SEG1 0 > > +#define UVD_BASE__INST1_SEG2 0 > > +#define UVD_BASE__INST1_SEG3 0 > > +#define UVD_BASE__INST1_SEG4 0 > > + > > +#define UVD_BASE__INST2_SEG0 0 > > +#define UVD_BASE__INST2_SEG1 0 > > +#define UVD_BASE__INST2_SEG2 0 > > +#define UVD_BASE__INST2_SEG3 0 > > +#define UVD_BASE__INST2_SEG4 0 > > + > > +#define UVD_BASE__INST3_SEG0 0 > > +#define UVD_BASE__INST3_SEG1 0 > > +#define UVD_BASE__INST3_SEG2 0 > > +#define UVD_BASE__INST3_SEG3 0 > > +#define UVD_BASE__INST3_SEG4 0 > > + > > +#define UVD_BASE__INST4_SEG0 0 > > +#define UVD_BASE__INST4_SEG1 0 > > +#define UVD_BASE__INST4_SEG2 0 > > +#define UVD_BASE__INST4_SEG3 0 > > +#define UVD_BASE__INST4_SEG4 0 > > + > > +#define VCN_BASE__INST0_SEG0 0x00007800 > > +#define VCN_BASE__INST0_SEG1 0x00007E00 > > +#define VCN_BASE__INST0_SEG2 0 > > +#define VCN_BASE__INST0_SEG3 0 > > +#define VCN_BASE__INST0_SEG4 0 > > + > > +#define VCN_BASE__INST1_SEG0 0 > > +#define VCN_BASE__INST1_SEG1 0 > > +#define VCN_BASE__INST1_SEG2 0 > > +#define VCN_BASE__INST1_SEG3 0 > > +#define VCN_BASE__INST1_SEG4 0 > > + > > +#define VCN_BASE__INST2_SEG0 0 > > +#define VCN_BASE__INST2_SEG1 0 > > +#define VCN_BASE__INST2_SEG2 0 > > +#define VCN_BASE__INST2_SEG3 0 > > +#define VCN_BASE__INST2_SEG4 0 > > + > > +#define VCN_BASE__INST3_SEG0 0 > > +#define VCN_BASE__INST3_SEG1 0 > > +#define VCN_BASE__INST3_SEG2 0 > > +#define VCN_BASE__INST3_SEG3 0 > > +#define VCN_BASE__INST3_SEG4 0 > > + > > +#define VCN_BASE__INST4_SEG0 0 > > +#define VCN_BASE__INST4_SEG1 0 > > +#define VCN_BASE__INST4_SEG2 0 > > +#define VCN_BASE__INST4_SEG3 0 > > +#define VCN_BASE__INST4_SEG4 0 > > + > > +#define DBGU_BASE__INST0_SEG0 0x00000180 > > +#define DBGU_BASE__INST0_SEG1 0x000001A0 > > +#define DBGU_BASE__INST0_SEG2 0 > > +#define DBGU_BASE__INST0_SEG3 0 > > +#define DBGU_BASE__INST0_SEG4 0 > > + > > +#define DBGU_BASE__INST1_SEG0 0 > > +#define DBGU_BASE__INST1_SEG1 0 > > +#define DBGU_BASE__INST1_SEG2 0 > > +#define DBGU_BASE__INST1_SEG3 0 > > +#define DBGU_BASE__INST1_SEG4 0 > > + > > +#define DBGU_BASE__INST2_SEG0 0 > > +#define DBGU_BASE__INST2_SEG1 0 > > +#define DBGU_BASE__INST2_SEG2 0 > > +#define DBGU_BASE__INST2_SEG3 0 > > +#define DBGU_BASE__INST2_SEG4 0 > > + > > +#define DBGU_BASE__INST3_SEG0 0 > > +#define DBGU_BASE__INST3_SEG1 0 > > +#define DBGU_BASE__INST3_SEG2 0 > > +#define DBGU_BASE__INST3_SEG3 0 > > +#define DBGU_BASE__INST3_SEG4 0 > > + > > +#define DBGU_BASE__INST4_SEG0 0 > > +#define DBGU_BASE__INST4_SEG1 0 > > +#define DBGU_BASE__INST4_SEG2 0 > > +#define DBGU_BASE__INST4_SEG3 0 > > +#define DBGU_BASE__INST4_SEG4 0 > > + > > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 > > +#define DBGU_NBIO_BASE__INST0_SEG1 0 > > +#define DBGU_NBIO_BASE__INST0_SEG2 0 > > +#define DBGU_NBIO_BASE__INST0_SEG3 0 > > +#define DBGU_NBIO_BASE__INST0_SEG4 0 > > + > > +#define DBGU_NBIO_BASE__INST1_SEG0 0 > > +#define DBGU_NBIO_BASE__INST1_SEG1 0 > > +#define DBGU_NBIO_BASE__INST1_SEG2 0 > > +#define DBGU_NBIO_BASE__INST1_SEG3 0 > > +#define DBGU_NBIO_BASE__INST1_SEG4 0 > > + > > +#define DBGU_NBIO_BASE__INST2_SEG0 0 > > +#define DBGU_NBIO_BASE__INST2_SEG1 0 > > +#define DBGU_NBIO_BASE__INST2_SEG2 0 > > +#define DBGU_NBIO_BASE__INST2_SEG3 0 > > +#define DBGU_NBIO_BASE__INST2_SEG4 0 > > + > > +#define DBGU_NBIO_BASE__INST3_SEG0 0 > > +#define DBGU_NBIO_BASE__INST3_SEG1 0 > > +#define DBGU_NBIO_BASE__INST3_SEG2 0 > > +#define DBGU_NBIO_BASE__INST3_SEG3 0 > > +#define DBGU_NBIO_BASE__INST3_SEG4 0 > > + > > +#define DBGU_NBIO_BASE__INST4_SEG0 0 > > +#define DBGU_NBIO_BASE__INST4_SEG1 0 > > +#define DBGU_NBIO_BASE__INST4_SEG2 0 > > +#define DBGU_NBIO_BASE__INST4_SEG3 0 > > +#define DBGU_NBIO_BASE__INST4_SEG4 0 > > + > > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 > > +#define DBGU_IO_BASE__INST0_SEG1 0 > > +#define DBGU_IO_BASE__INST0_SEG2 0 > > +#define DBGU_IO_BASE__INST0_SEG3 0 > > +#define DBGU_IO_BASE__INST0_SEG4 0 > > + > > +#define DBGU_IO_BASE__INST1_SEG0 0 > > +#define DBGU_IO_BASE__INST1_SEG1 0 > > +#define DBGU_IO_BASE__INST1_SEG2 0 > > +#define DBGU_IO_BASE__INST1_SEG3 0 > > +#define DBGU_IO_BASE__INST1_SEG4 0 > > + > > +#define DBGU_IO_BASE__INST2_SEG0 0 > > +#define DBGU_IO_BASE__INST2_SEG1 0 > > +#define DBGU_IO_BASE__INST2_SEG2 0 > > +#define DBGU_IO_BASE__INST2_SEG3 0 > > +#define DBGU_IO_BASE__INST2_SEG4 0 > > + > > +#define DBGU_IO_BASE__INST3_SEG0 0 > > +#define DBGU_IO_BASE__INST3_SEG1 0 > > +#define DBGU_IO_BASE__INST3_SEG2 0 > > +#define DBGU_IO_BASE__INST3_SEG3 0 > > +#define DBGU_IO_BASE__INST3_SEG4 0 > > + > > +#define DBGU_IO_BASE__INST4_SEG0 0 > > +#define DBGU_IO_BASE__INST4_SEG1 0 > > +#define DBGU_IO_BASE__INST4_SEG2 0 > > +#define DBGU_IO_BASE__INST4_SEG3 0 > > +#define DBGU_IO_BASE__INST4_SEG4 0 > > + > > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 > > +#define DFX_DAP_BASE__INST0_SEG1 0 > > +#define DFX_DAP_BASE__INST0_SEG2 0 > > +#define DFX_DAP_BASE__INST0_SEG3 0 > > +#define DFX_DAP_BASE__INST0_SEG4 0 > > + > > +#define DFX_DAP_BASE__INST1_SEG0 0 > > +#define DFX_DAP_BASE__INST1_SEG1 0 > > +#define DFX_DAP_BASE__INST1_SEG2 0 > > +#define DFX_DAP_BASE__INST1_SEG3 0 > > +#define DFX_DAP_BASE__INST1_SEG4 0 > > + > > +#define DFX_DAP_BASE__INST2_SEG0 0 > > +#define DFX_DAP_BASE__INST2_SEG1 0 > > +#define DFX_DAP_BASE__INST2_SEG2 0 > > +#define DFX_DAP_BASE__INST2_SEG3 0 > > +#define DFX_DAP_BASE__INST2_SEG4 0 > > + > > +#define DFX_DAP_BASE__INST3_SEG0 0 > > +#define DFX_DAP_BASE__INST3_SEG1 0 > > +#define DFX_DAP_BASE__INST3_SEG2 0 > > +#define DFX_DAP_BASE__INST3_SEG3 0 > > +#define DFX_DAP_BASE__INST3_SEG4 0 > > + > > +#define DFX_DAP_BASE__INST4_SEG0 0 > > +#define DFX_DAP_BASE__INST4_SEG1 0 > > +#define DFX_DAP_BASE__INST4_SEG2 0 > > +#define DFX_DAP_BASE__INST4_SEG3 0 > > +#define DFX_DAP_BASE__INST4_SEG4 0 > > + > > +#define DFX_BASE__INST0_SEG0 0x00000580 > > +#define DFX_BASE__INST0_SEG1 0 > > +#define DFX_BASE__INST0_SEG2 0 > > +#define DFX_BASE__INST0_SEG3 0 > > +#define DFX_BASE__INST0_SEG4 0 > > + > > +#define DFX_BASE__INST1_SEG0 0 > > +#define DFX_BASE__INST1_SEG1 0 > > +#define DFX_BASE__INST1_SEG2 0 > > +#define DFX_BASE__INST1_SEG3 0 > > +#define DFX_BASE__INST1_SEG4 0 > > + > > +#define DFX_BASE__INST2_SEG0 0 > > +#define DFX_BASE__INST2_SEG1 0 > > +#define DFX_BASE__INST2_SEG2 0 > > +#define DFX_BASE__INST2_SEG3 0 > > +#define DFX_BASE__INST2_SEG4 0 > > + > > +#define DFX_BASE__INST3_SEG0 0 > > +#define DFX_BASE__INST3_SEG1 0 > > +#define DFX_BASE__INST3_SEG2 0 > > +#define DFX_BASE__INST3_SEG3 0 > > +#define DFX_BASE__INST3_SEG4 0 > > + > > +#define DFX_BASE__INST4_SEG0 0 > > +#define DFX_BASE__INST4_SEG1 0 > > +#define DFX_BASE__INST4_SEG2 0 > > +#define DFX_BASE__INST4_SEG3 0 > > +#define DFX_BASE__INST4_SEG4 0 > > + > > +#define ISP_BASE__INST0_SEG0 0x00018000 > > +#define ISP_BASE__INST0_SEG1 0 > > +#define ISP_BASE__INST0_SEG2 0 > > +#define ISP_BASE__INST0_SEG3 0 > > +#define ISP_BASE__INST0_SEG4 0 > > + > > +#define ISP_BASE__INST1_SEG0 0 > > +#define ISP_BASE__INST1_SEG1 0 > > +#define ISP_BASE__INST1_SEG2 0 > > +#define ISP_BASE__INST1_SEG3 0 > > +#define ISP_BASE__INST1_SEG4 0 > > + > > +#define ISP_BASE__INST2_SEG0 0 > > +#define ISP_BASE__INST2_SEG1 0 > > +#define ISP_BASE__INST2_SEG2 0 > > +#define ISP_BASE__INST2_SEG3 0 > > +#define ISP_BASE__INST2_SEG4 0 > > + > > +#define ISP_BASE__INST3_SEG0 0 > > +#define ISP_BASE__INST3_SEG1 0 > > +#define ISP_BASE__INST3_SEG2 0 > > +#define ISP_BASE__INST3_SEG3 0 > > +#define ISP_BASE__INST3_SEG4 0 > > + > > +#define ISP_BASE__INST4_SEG0 0 > > +#define ISP_BASE__INST4_SEG1 0 > > +#define ISP_BASE__INST4_SEG2 0 > > +#define ISP_BASE__INST4_SEG3 0 > > +#define ISP_BASE__INST4_SEG4 0 > > + > > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 > > +#define SYSTEMHUB_BASE__INST0_SEG1 0 > > +#define SYSTEMHUB_BASE__INST0_SEG2 0 > > +#define SYSTEMHUB_BASE__INST0_SEG3 0 > > +#define SYSTEMHUB_BASE__INST0_SEG4 0 > > + > > +#define SYSTEMHUB_BASE__INST1_SEG0 0 > > +#define SYSTEMHUB_BASE__INST1_SEG1 0 > > +#define SYSTEMHUB_BASE__INST1_SEG2 0 > > +#define SYSTEMHUB_BASE__INST1_SEG3 0 > > +#define SYSTEMHUB_BASE__INST1_SEG4 0 > > + > > +#define SYSTEMHUB_BASE__INST2_SEG0 0 > > +#define SYSTEMHUB_BASE__INST2_SEG1 0 > > +#define SYSTEMHUB_BASE__INST2_SEG2 0 > > +#define SYSTEMHUB_BASE__INST2_SEG3 0 > > +#define SYSTEMHUB_BASE__INST2_SEG4 0 > > + > > +#define SYSTEMHUB_BASE__INST3_SEG0 0 > > +#define SYSTEMHUB_BASE__INST3_SEG1 0 > > +#define SYSTEMHUB_BASE__INST3_SEG2 0 > > +#define SYSTEMHUB_BASE__INST3_SEG3 0 > > +#define SYSTEMHUB_BASE__INST3_SEG4 0 > > + > > +#define SYSTEMHUB_BASE__INST4_SEG0 0 > > +#define SYSTEMHUB_BASE__INST4_SEG1 0 > > +#define SYSTEMHUB_BASE__INST4_SEG2 0 > > +#define SYSTEMHUB_BASE__INST4_SEG3 0 > > +#define SYSTEMHUB_BASE__INST4_SEG4 0 > > + > > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 > > +#define L2IMU_BASE__INST0_SEG1 0 > > +#define L2IMU_BASE__INST0_SEG2 0 > > +#define L2IMU_BASE__INST0_SEG3 0 > > +#define L2IMU_BASE__INST0_SEG4 0 > > + > > +#define L2IMU_BASE__INST1_SEG0 0 > > +#define L2IMU_BASE__INST1_SEG1 0 > > +#define L2IMU_BASE__INST1_SEG2 0 > > +#define L2IMU_BASE__INST1_SEG3 0 > > +#define L2IMU_BASE__INST1_SEG4 0 > > + > > +#define L2IMU_BASE__INST2_SEG0 0 > > +#define L2IMU_BASE__INST2_SEG1 0 > > +#define L2IMU_BASE__INST2_SEG2 0 > > +#define L2IMU_BASE__INST2_SEG3 0 > > +#define L2IMU_BASE__INST2_SEG4 0 > > + > > +#define L2IMU_BASE__INST3_SEG0 0 > > +#define L2IMU_BASE__INST3_SEG1 0 > > +#define L2IMU_BASE__INST3_SEG2 0 > > +#define L2IMU_BASE__INST3_SEG3 0 > > +#define L2IMU_BASE__INST3_SEG4 0 > > + > > +#define L2IMU_BASE__INST4_SEG0 0 > > +#define L2IMU_BASE__INST4_SEG1 0 > > +#define L2IMU_BASE__INST4_SEG2 0 > > +#define L2IMU_BASE__INST4_SEG3 0 > > +#define L2IMU_BASE__INST4_SEG4 0 > > + > > +#define IOHC_BASE__INST0_SEG0 0x00010000 > > +#define IOHC_BASE__INST0_SEG1 0 > > +#define IOHC_BASE__INST0_SEG2 0 > > +#define IOHC_BASE__INST0_SEG3 0 > > +#define IOHC_BASE__INST0_SEG4 0 > > + > > +#define IOHC_BASE__INST1_SEG0 0 > > +#define IOHC_BASE__INST1_SEG1 0 > > +#define IOHC_BASE__INST1_SEG2 0 > > +#define IOHC_BASE__INST1_SEG3 0 > > +#define IOHC_BASE__INST1_SEG4 0 > > + > > +#define IOHC_BASE__INST2_SEG0 0 > > +#define IOHC_BASE__INST2_SEG1 0 > > +#define IOHC_BASE__INST2_SEG2 0 > > +#define IOHC_BASE__INST2_SEG3 0 > > +#define IOHC_BASE__INST2_SEG4 0 > > + > > +#define IOHC_BASE__INST3_SEG0 0 > > +#define IOHC_BASE__INST3_SEG1 0 > > +#define IOHC_BASE__INST3_SEG2 0 > > +#define IOHC_BASE__INST3_SEG3 0 > > +#define IOHC_BASE__INST3_SEG4 0 > > + > > +#define IOHC_BASE__INST4_SEG0 0 > > +#define IOHC_BASE__INST4_SEG1 0 > > +#define IOHC_BASE__INST4_SEG2 0 > > +#define IOHC_BASE__INST4_SEG3 0 > > +#define IOHC_BASE__INST4_SEG4 0 > > + > > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 > > +#define ATHUB_BASE__INST0_SEG1 0 > > +#define ATHUB_BASE__INST0_SEG2 0 > > +#define ATHUB_BASE__INST0_SEG3 0 > > +#define ATHUB_BASE__INST0_SEG4 0 > > + > > +#define ATHUB_BASE__INST1_SEG0 0 > > +#define ATHUB_BASE__INST1_SEG1 0 > > +#define ATHUB_BASE__INST1_SEG2 0 > > +#define ATHUB_BASE__INST1_SEG3 0 > > +#define ATHUB_BASE__INST1_SEG4 0 > > + > > +#define ATHUB_BASE__INST2_SEG0 0 > > +#define ATHUB_BASE__INST2_SEG1 0 > > +#define ATHUB_BASE__INST2_SEG2 0 > > +#define ATHUB_BASE__INST2_SEG3 0 > > +#define ATHUB_BASE__INST2_SEG4 0 > > + > > +#define ATHUB_BASE__INST3_SEG0 0 > > +#define ATHUB_BASE__INST3_SEG1 0 > > +#define ATHUB_BASE__INST3_SEG2 0 > > +#define ATHUB_BASE__INST3_SEG3 0 > > +#define ATHUB_BASE__INST3_SEG4 0 > > + > > +#define ATHUB_BASE__INST4_SEG0 0 > > +#define ATHUB_BASE__INST4_SEG1 0 > > +#define ATHUB_BASE__INST4_SEG2 0 > > +#define ATHUB_BASE__INST4_SEG3 0 > > +#define ATHUB_BASE__INST4_SEG4 0 > > + > > +#define VCE_BASE__INST0_SEG0 0x00007E00 > > +#define VCE_BASE__INST0_SEG1 0x00048800 > > +#define VCE_BASE__INST0_SEG2 0 > > +#define VCE_BASE__INST0_SEG3 0 > > +#define VCE_BASE__INST0_SEG4 0 > > + > > +#define VCE_BASE__INST1_SEG0 0 > > +#define VCE_BASE__INST1_SEG1 0 > > +#define VCE_BASE__INST1_SEG2 0 > > +#define VCE_BASE__INST1_SEG3 0 > > +#define VCE_BASE__INST1_SEG4 0 > > + > > +#define VCE_BASE__INST2_SEG0 0 > > +#define VCE_BASE__INST2_SEG1 0 > > +#define VCE_BASE__INST2_SEG2 0 > > +#define VCE_BASE__INST2_SEG3 0 > > +#define VCE_BASE__INST2_SEG4 0 > > + > > +#define VCE_BASE__INST3_SEG0 0 > > +#define VCE_BASE__INST3_SEG1 0 > > +#define VCE_BASE__INST3_SEG2 0 > > +#define VCE_BASE__INST3_SEG3 0 > > +#define VCE_BASE__INST3_SEG4 0 > > + > > +#define VCE_BASE__INST4_SEG0 0 > > +#define VCE_BASE__INST4_SEG1 0 > > +#define VCE_BASE__INST4_SEG2 0 > > +#define VCE_BASE__INST4_SEG3 0 > > +#define VCE_BASE__INST4_SEG4 0 > > + > > +#define GC_BASE__INST0_SEG0 0x00002000 > > +#define GC_BASE__INST0_SEG1 0x0000A000 > > +#define GC_BASE__INST0_SEG2 0 > > +#define GC_BASE__INST0_SEG3 0 > > +#define GC_BASE__INST0_SEG4 0 > > + > > +#define GC_BASE__INST1_SEG0 0 > > +#define GC_BASE__INST1_SEG1 0 > > +#define GC_BASE__INST1_SEG2 0 > > +#define GC_BASE__INST1_SEG3 0 > > +#define GC_BASE__INST1_SEG4 0 > > + > > +#define GC_BASE__INST2_SEG0 0 > > +#define GC_BASE__INST2_SEG1 0 > > +#define GC_BASE__INST2_SEG2 0 > > +#define GC_BASE__INST2_SEG3 0 > > +#define GC_BASE__INST2_SEG4 0 > > + > > +#define GC_BASE__INST3_SEG0 0 > > +#define GC_BASE__INST3_SEG1 0 > > +#define GC_BASE__INST3_SEG2 0 > > +#define GC_BASE__INST3_SEG3 0 > > +#define GC_BASE__INST3_SEG4 0 > > + > > +#define GC_BASE__INST4_SEG0 0 > > +#define GC_BASE__INST4_SEG1 0 > > +#define GC_BASE__INST4_SEG2 0 > > +#define GC_BASE__INST4_SEG3 0 > > +#define GC_BASE__INST4_SEG4 0 > > + > > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 > > +#define MMHUB_BASE__INST0_SEG1 0 > > +#define MMHUB_BASE__INST0_SEG2 0 > > +#define MMHUB_BASE__INST0_SEG3 0 > > +#define MMHUB_BASE__INST0_SEG4 0 > > + > > +#define MMHUB_BASE__INST1_SEG0 0 > > +#define MMHUB_BASE__INST1_SEG1 0 > > +#define MMHUB_BASE__INST1_SEG2 0 > > +#define MMHUB_BASE__INST1_SEG3 0 > > +#define MMHUB_BASE__INST1_SEG4 0 > > + > > +#define MMHUB_BASE__INST2_SEG0 0 > > +#define MMHUB_BASE__INST2_SEG1 0 > > +#define MMHUB_BASE__INST2_SEG2 0 > > +#define MMHUB_BASE__INST2_SEG3 0 > > +#define MMHUB_BASE__INST2_SEG4 0 > > + > > +#define MMHUB_BASE__INST3_SEG0 0 > > +#define MMHUB_BASE__INST3_SEG1 0 > > +#define MMHUB_BASE__INST3_SEG2 0 > > +#define MMHUB_BASE__INST3_SEG3 0 > > +#define MMHUB_BASE__INST3_SEG4 0 > > + > > +#define MMHUB_BASE__INST4_SEG0 0 > > +#define MMHUB_BASE__INST4_SEG1 0 > > +#define MMHUB_BASE__INST4_SEG2 0 > > +#define MMHUB_BASE__INST4_SEG3 0 > > +#define MMHUB_BASE__INST4_SEG4 0 > > + > > +#define RSMU_BASE__INST0_SEG0 0x00012000 > > +#define RSMU_BASE__INST0_SEG1 0 > > +#define RSMU_BASE__INST0_SEG2 0 > > +#define RSMU_BASE__INST0_SEG3 0 > > +#define RSMU_BASE__INST0_SEG4 0 > > + > > +#define RSMU_BASE__INST1_SEG0 0 > > +#define RSMU_BASE__INST1_SEG1 0 > > +#define RSMU_BASE__INST1_SEG2 0 > > +#define RSMU_BASE__INST1_SEG3 0 > > +#define RSMU_BASE__INST1_SEG4 0 > > + > > +#define RSMU_BASE__INST2_SEG0 0 > > +#define RSMU_BASE__INST2_SEG1 0 > > +#define RSMU_BASE__INST2_SEG2 0 > > +#define RSMU_BASE__INST2_SEG3 0 > > +#define RSMU_BASE__INST2_SEG4 0 > > + > > +#define RSMU_BASE__INST3_SEG0 0 > > +#define RSMU_BASE__INST3_SEG1 0 > > +#define RSMU_BASE__INST3_SEG2 0 > > +#define RSMU_BASE__INST3_SEG3 0 > > +#define RSMU_BASE__INST3_SEG4 0 > > + > > +#define RSMU_BASE__INST4_SEG0 0 > > +#define RSMU_BASE__INST4_SEG1 0 > > +#define RSMU_BASE__INST4_SEG2 0 > > +#define RSMU_BASE__INST4_SEG3 0 > > +#define RSMU_BASE__INST4_SEG4 0 > > + > > +#define HDP_BASE__INST0_SEG0 0x00000F20 > > +#define HDP_BASE__INST0_SEG1 0 > > +#define HDP_BASE__INST0_SEG2 0 > > +#define HDP_BASE__INST0_SEG3 0 > > +#define HDP_BASE__INST0_SEG4 0 > > + > > +#define HDP_BASE__INST1_SEG0 0 > > +#define HDP_BASE__INST1_SEG1 0 > > +#define HDP_BASE__INST1_SEG2 0 > > +#define HDP_BASE__INST1_SEG3 0 > > +#define HDP_BASE__INST1_SEG4 0 > > + > > +#define HDP_BASE__INST2_SEG0 0 > > +#define HDP_BASE__INST2_SEG1 0 > > +#define HDP_BASE__INST2_SEG2 0 > > +#define HDP_BASE__INST2_SEG3 0 > > +#define HDP_BASE__INST2_SEG4 0 > > + > > +#define HDP_BASE__INST3_SEG0 0 > > +#define HDP_BASE__INST3_SEG1 0 > > +#define HDP_BASE__INST3_SEG2 0 > > +#define HDP_BASE__INST3_SEG3 0 > > +#define HDP_BASE__INST3_SEG4 0 > > + > > +#define HDP_BASE__INST4_SEG0 0 > > +#define HDP_BASE__INST4_SEG1 0 > > +#define HDP_BASE__INST4_SEG2 0 > > +#define HDP_BASE__INST4_SEG3 0 > > +#define HDP_BASE__INST4_SEG4 0 > > + > > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 > > +#define OSSSYS_BASE__INST0_SEG1 0 > > +#define OSSSYS_BASE__INST0_SEG2 0 > > +#define OSSSYS_BASE__INST0_SEG3 0 > > +#define OSSSYS_BASE__INST0_SEG4 0 > > + > > +#define OSSSYS_BASE__INST1_SEG0 0 > > +#define OSSSYS_BASE__INST1_SEG1 0 > > +#define OSSSYS_BASE__INST1_SEG2 0 > > +#define OSSSYS_BASE__INST1_SEG3 0 > > +#define OSSSYS_BASE__INST1_SEG4 0 > > + > > +#define OSSSYS_BASE__INST2_SEG0 0 > > +#define OSSSYS_BASE__INST2_SEG1 0 > > +#define OSSSYS_BASE__INST2_SEG2 0 > > +#define OSSSYS_BASE__INST2_SEG3 0 > > +#define OSSSYS_BASE__INST2_SEG4 0 > > + > > +#define OSSSYS_BASE__INST3_SEG0 0 > > +#define OSSSYS_BASE__INST3_SEG1 0 > > +#define OSSSYS_BASE__INST3_SEG2 0 > > +#define OSSSYS_BASE__INST3_SEG3 0 > > +#define OSSSYS_BASE__INST3_SEG4 0 > > + > > +#define OSSSYS_BASE__INST4_SEG0 0 > > +#define OSSSYS_BASE__INST4_SEG1 0 > > +#define OSSSYS_BASE__INST4_SEG2 0 > > +#define OSSSYS_BASE__INST4_SEG3 0 > > +#define OSSSYS_BASE__INST4_SEG4 0 > > + > > +#define SDMA0_BASE__INST0_SEG0 0x00001260 > > +#define SDMA0_BASE__INST0_SEG1 0 > > +#define SDMA0_BASE__INST0_SEG2 0 > > +#define SDMA0_BASE__INST0_SEG3 0 > > +#define SDMA0_BASE__INST0_SEG4 0 > > + > > +#define SDMA0_BASE__INST1_SEG0 0 > > +#define SDMA0_BASE__INST1_SEG1 0 > > +#define SDMA0_BASE__INST1_SEG2 0 > > +#define SDMA0_BASE__INST1_SEG3 0 > > +#define SDMA0_BASE__INST1_SEG4 0 > > + > > +#define SDMA0_BASE__INST2_SEG0 0 > > +#define SDMA0_BASE__INST2_SEG1 0 > > +#define SDMA0_BASE__INST2_SEG2 0 > > +#define SDMA0_BASE__INST2_SEG3 0 > > +#define SDMA0_BASE__INST2_SEG4 0 > > + > > +#define SDMA0_BASE__INST3_SEG0 0 > > +#define SDMA0_BASE__INST3_SEG1 0 > > +#define SDMA0_BASE__INST3_SEG2 0 > > +#define SDMA0_BASE__INST3_SEG3 0 > > +#define SDMA0_BASE__INST3_SEG4 0 > > + > > +#define SDMA0_BASE__INST4_SEG0 0 > > +#define SDMA0_BASE__INST4_SEG1 0 > > +#define SDMA0_BASE__INST4_SEG2 0 > > +#define SDMA0_BASE__INST4_SEG3 0 > > +#define SDMA0_BASE__INST4_SEG4 0 > > + > > +#define SDMA1_BASE__INST0_SEG0 0x00001460 > > +#define SDMA1_BASE__INST0_SEG1 0 > > +#define SDMA1_BASE__INST0_SEG2 0 > > +#define SDMA1_BASE__INST0_SEG3 0 > > +#define SDMA1_BASE__INST0_SEG4 0 > > + > > +#define SDMA1_BASE__INST1_SEG0 0 > > +#define SDMA1_BASE__INST1_SEG1 0 > > +#define SDMA1_BASE__INST1_SEG2 0 > > +#define SDMA1_BASE__INST1_SEG3 0 > > +#define SDMA1_BASE__INST1_SEG4 0 > > + > > +#define SDMA1_BASE__INST2_SEG0 0 > > +#define SDMA1_BASE__INST2_SEG1 0 > > +#define SDMA1_BASE__INST2_SEG2 0 > > +#define SDMA1_BASE__INST2_SEG3 0 > > +#define SDMA1_BASE__INST2_SEG4 0 > > + > > +#define SDMA1_BASE__INST3_SEG0 0 > > +#define SDMA1_BASE__INST3_SEG1 0 > > +#define SDMA1_BASE__INST3_SEG2 0 > > +#define SDMA1_BASE__INST3_SEG3 0 > > +#define SDMA1_BASE__INST3_SEG4 0 > > + > > +#define SDMA1_BASE__INST4_SEG0 0 > > +#define SDMA1_BASE__INST4_SEG1 0 > > +#define SDMA1_BASE__INST4_SEG2 0 > > +#define SDMA1_BASE__INST4_SEG3 0 > > +#define SDMA1_BASE__INST4_SEG4 0 > > + > > +#define XDMA_BASE__INST0_SEG0 0x00003400 > > +#define XDMA_BASE__INST0_SEG1 0 > > +#define XDMA_BASE__INST0_SEG2 0 > > +#define XDMA_BASE__INST0_SEG3 0 > > +#define XDMA_BASE__INST0_SEG4 0 > > + > > +#define XDMA_BASE__INST1_SEG0 0 > > +#define XDMA_BASE__INST1_SEG1 0 > > +#define XDMA_BASE__INST1_SEG2 0 > > +#define XDMA_BASE__INST1_SEG3 0 > > > > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <702bfce6-78ef-0284-6306-f4b3366d34f7-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <702bfce6-78ef-0284-6306-f4b3366d34f7-5C7GfCeVMHo@public.gmane.org> @ 2017-11-27 20:44 ` Christian König [not found] ` <ec783d5b-74a5-07e8-6bb4-5c930e56a718-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: Christian König @ 2017-11-27 20:44 UTC (permalink / raw) To: Felix Kuehling, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 27.11.2017 um 21:01 schrieb Felix Kuehling: > On 2017-11-27 02:37 PM, Koenig, Christian wrote: >> And that is a clear NAK to this approach. > Hi Christian, > > Do you have other objections than the style issues? If so, please explain. No, the technical aspect actually looks rather reasonable. > Please clarify, why this file needs to be treated differently from other > files under include/asic_reg? All those files are auto-generated by HW > teams. Fixing the coding style adds no value and makes future updates > more complicated. We already got complains about that and most likely will need to fix the rest as well. Nicolai looked into using a different auto generator for the header files, but not sure how far that already got along. The point is that the structures added with this won't be used by soc15 alone, but rather be the base of the new register definition for future hardware generations as well. > Like Shaoyun pointed out for example, the existing file > include/asic_reg/vega10/soc15ip.h has the same style issues. That file actually doesn't exists any more. Please see the work from Feifei about that as well. Regards, Christian. > > Regards, > Felix > >> Please start by fixing at least the obvious style problems before >> resending. >> >> Thanks, >> Christian. >> >> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: >> >> I agree that this HW engineer generated file doesn't match the >> coding style from linux software engineer point of view , but >> since we already import other similar " HW engineer style" files >> under include/asic_reg/vega10/, I don't see a reason to specially >> change this file without touch else . This file is actually almost >> identical as soc15ip.h . I think it's easier for us to import >> other offset file in the future if we keep them un-touched . >> >> Regards >> Shaoyun.liu >> >> >> -----Original Message----- >> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] >> Sent: Monday, November 27, 2017 2:17 PM >> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org >> Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file >> >> First of let us fix the obvious style problems. >> >> Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: >> > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c >> > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> >> > --- >> > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 >> ++++++++++++++++++++ >> > 1 file changed, 1248 insertions(+) >> > create mode 100644 >> drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >> > >> > diff --git >> a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >> b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >> > new file mode 100644 >> > index 0000000..76cb748 >> > --- /dev/null >> > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >> > @@ -0,0 +1,1248 @@ >> > +#ifndef _ip_offset_1_HEADER >> > +#define _ip_offset_1_HEADER >> Names for preprocessor defines should be capitable. >> >> > + >> > +#define MAX_INSTANCE 5 >> > +#define MAX_SEGMENT 5 >> > + >> > + >> > +struct IP_BASE_INSTANCE >> >> Structure names should be lower case. And we need an amdgpu_ or at >> least >> amd_ prefix here. >> >> Regards, >> Christian. >> >> > +{ >> > + unsigned int segment[MAX_SEGMENT]; >> > +}; >> > + >> > +struct IP_BASE >> > +{ >> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >> > +}; >> > + >> > + >> > +static const struct IP_BASE NBIF_BASE = >> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE NBIO_BASE = >> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE DCE_BASE = { { { { >> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE DCN_BASE = { { { { >> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE MP0_BASE = { { { { >> 0x00016000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE MP1_BASE = { { { { >> 0x00016000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE MP2_BASE = { { { { >> 0x00016000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE DF_BASE = { { { { >> 0x00007000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE UVD_BASE = { { { { >> 0x00007800, 0x00007E00, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment >> >> No "//" in kernel code please. >> >> > +static const struct IP_BASE VCN_BASE = { { { { >> 0x00007800, 0x00007E00, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment >> > +static const struct IP_BASE DBGU_BASE = >> { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { >> 0x000001C0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE DBGU_IO_BASE = { { { { >> 0x000001E0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE DFX_DAP_BASE = { { { { >> 0x000005A0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE DFX_BASE = { { { { >> 0x00000580, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers >> > +static const struct IP_BASE ISP_BASE = { { { { >> 0x00018000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { >> 0x00000EA0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; // not exist >> > +static const struct IP_BASE L2IMU_BASE = >> { { { { 0x00007DC0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE IOHC_BASE = >> { { { { 0x00010000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE ATHUB_BASE = >> { { { { 0x00000C20, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE VCE_BASE = { { { { >> 0x00007E00, 0x00048800, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE GC_BASE = { { { { >> 0x00002000, 0x0000A000, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE MMHUB_BASE = >> { { { { 0x0001A000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE RSMU_BASE = >> { { { { 0x00012000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE HDP_BASE = { { { { >> 0x00000F20, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE OSSSYS_BASE = { { { { >> 0x000010A0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE SDMA0_BASE = >> { { { { 0x00001260, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE SDMA1_BASE = >> { { { { 0x00001460, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE XDMA_BASE = >> { { { { 0x00003400, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE UMC_BASE = { { { { >> 0x00014000, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE THM_BASE = { { { { >> 0x00016600, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE SMUIO_BASE = >> { { { { 0x00016800, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE PWR_BASE = { { { { >> 0x00016A00, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE CLK_BASE = { { { { >> 0x00016C00, 0, 0, 0, 0 } }, >> > >> + >> { { 0x00016E00, 0, 0, 0, 0 } }, >> > >> + >> { { 0x00017000, 0, 0, 0, 0 } }, >> > + { { 0x00017200, 0, 0, >> 0, 0 } }, >> > + { >> { 0x00017E00, 0, 0, 0, 0 } } } }; >> > +static const struct IP_BASE FUSE_BASE = >> { { { { 0x00017400, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } }, >> > >> + >> { { 0, 0, 0, 0, 0 } } } }; >> > + >> > + >> > +#define NBIF_BASE__INST0_SEG0 0x00000000 >> > +#define NBIF_BASE__INST0_SEG1 0x00000014 >> > +#define NBIF_BASE__INST0_SEG2 0x00000D20 >> > +#define NBIF_BASE__INST0_SEG3 0x00010400 >> > +#define NBIF_BASE__INST0_SEG4 0 >> > + >> > +#define NBIF_BASE__INST1_SEG0 0 >> > +#define NBIF_BASE__INST1_SEG1 0 >> > +#define NBIF_BASE__INST1_SEG2 0 >> > +#define NBIF_BASE__INST1_SEG3 0 >> > +#define NBIF_BASE__INST1_SEG4 0 >> > + >> > +#define NBIF_BASE__INST2_SEG0 0 >> > +#define NBIF_BASE__INST2_SEG1 0 >> > +#define NBIF_BASE__INST2_SEG2 0 >> > +#define NBIF_BASE__INST2_SEG3 0 >> > +#define NBIF_BASE__INST2_SEG4 0 >> > + >> > +#define NBIF_BASE__INST3_SEG0 0 >> > +#define NBIF_BASE__INST3_SEG1 0 >> > +#define NBIF_BASE__INST3_SEG2 0 >> > +#define NBIF_BASE__INST3_SEG3 0 >> > +#define NBIF_BASE__INST3_SEG4 0 >> > + >> > +#define NBIF_BASE__INST4_SEG0 0 >> > +#define NBIF_BASE__INST4_SEG1 0 >> > +#define NBIF_BASE__INST4_SEG2 0 >> > +#define NBIF_BASE__INST4_SEG3 0 >> > +#define NBIF_BASE__INST4_SEG4 0 >> > + >> > +#define NBIO_BASE__INST0_SEG0 0x00000000 >> > +#define NBIO_BASE__INST0_SEG1 0x00000014 >> > +#define NBIO_BASE__INST0_SEG2 0x00000D20 >> > +#define NBIO_BASE__INST0_SEG3 0x00010400 >> > +#define NBIO_BASE__INST0_SEG4 0 >> > + >> > +#define NBIO_BASE__INST1_SEG0 0 >> > +#define NBIO_BASE__INST1_SEG1 0 >> > +#define NBIO_BASE__INST1_SEG2 0 >> > +#define NBIO_BASE__INST1_SEG3 0 >> > +#define NBIO_BASE__INST1_SEG4 0 >> > + >> > +#define NBIO_BASE__INST2_SEG0 0 >> > +#define NBIO_BASE__INST2_SEG1 0 >> > +#define NBIO_BASE__INST2_SEG2 0 >> > +#define NBIO_BASE__INST2_SEG3 0 >> > +#define NBIO_BASE__INST2_SEG4 0 >> > + >> > +#define NBIO_BASE__INST3_SEG0 0 >> > +#define NBIO_BASE__INST3_SEG1 0 >> > +#define NBIO_BASE__INST3_SEG2 0 >> > +#define NBIO_BASE__INST3_SEG3 0 >> > +#define NBIO_BASE__INST3_SEG4 0 >> > + >> > +#define NBIO_BASE__INST4_SEG0 0 >> > +#define NBIO_BASE__INST4_SEG1 0 >> > +#define NBIO_BASE__INST4_SEG2 0 >> > +#define NBIO_BASE__INST4_SEG3 0 >> > +#define NBIO_BASE__INST4_SEG4 0 >> > + >> > +#define DCE_BASE__INST0_SEG0 0x00000012 >> > +#define DCE_BASE__INST0_SEG1 0x000000C0 >> > +#define DCE_BASE__INST0_SEG2 0x000034C0 >> > +#define DCE_BASE__INST0_SEG3 0 >> > +#define DCE_BASE__INST0_SEG4 0 >> > + >> > +#define DCE_BASE__INST1_SEG0 0 >> > +#define DCE_BASE__INST1_SEG1 0 >> > +#define DCE_BASE__INST1_SEG2 0 >> > +#define DCE_BASE__INST1_SEG3 0 >> > +#define DCE_BASE__INST1_SEG4 0 >> > + >> > +#define DCE_BASE__INST2_SEG0 0 >> > +#define DCE_BASE__INST2_SEG1 0 >> > +#define DCE_BASE__INST2_SEG2 0 >> > +#define DCE_BASE__INST2_SEG3 0 >> > +#define DCE_BASE__INST2_SEG4 0 >> > + >> > +#define DCE_BASE__INST3_SEG0 0 >> > +#define DCE_BASE__INST3_SEG1 0 >> > +#define DCE_BASE__INST3_SEG2 0 >> > +#define DCE_BASE__INST3_SEG3 0 >> > +#define DCE_BASE__INST3_SEG4 0 >> > + >> > +#define DCE_BASE__INST4_SEG0 0 >> > +#define DCE_BASE__INST4_SEG1 0 >> > +#define DCE_BASE__INST4_SEG2 0 >> > +#define DCE_BASE__INST4_SEG3 0 >> > +#define DCE_BASE__INST4_SEG4 0 >> > + >> > +#define DCN_BASE__INST0_SEG0 0x00000012 >> > +#define DCN_BASE__INST0_SEG1 0x000000C0 >> > +#define DCN_BASE__INST0_SEG2 0x000034C0 >> > +#define DCN_BASE__INST0_SEG3 0 >> > +#define DCN_BASE__INST0_SEG4 0 >> > + >> > +#define DCN_BASE__INST1_SEG0 0 >> > +#define DCN_BASE__INST1_SEG1 0 >> > +#define DCN_BASE__INST1_SEG2 0 >> > +#define DCN_BASE__INST1_SEG3 0 >> > +#define DCN_BASE__INST1_SEG4 0 >> > + >> > +#define DCN_BASE__INST2_SEG0 0 >> > +#define DCN_BASE__INST2_SEG1 0 >> > +#define DCN_BASE__INST2_SEG2 0 >> > +#define DCN_BASE__INST2_SEG3 0 >> > +#define DCN_BASE__INST2_SEG4 0 >> > + >> > +#define DCN_BASE__INST3_SEG0 0 >> > +#define DCN_BASE__INST3_SEG1 0 >> > +#define DCN_BASE__INST3_SEG2 0 >> > +#define DCN_BASE__INST3_SEG3 0 >> > +#define DCN_BASE__INST3_SEG4 0 >> > + >> > +#define DCN_BASE__INST4_SEG0 0 >> > +#define DCN_BASE__INST4_SEG1 0 >> > +#define DCN_BASE__INST4_SEG2 0 >> > +#define DCN_BASE__INST4_SEG3 0 >> > +#define DCN_BASE__INST4_SEG4 0 >> > + >> > +#define MP0_BASE__INST0_SEG0 0x00016000 >> > +#define MP0_BASE__INST0_SEG1 0 >> > +#define MP0_BASE__INST0_SEG2 0 >> > +#define MP0_BASE__INST0_SEG3 0 >> > +#define MP0_BASE__INST0_SEG4 0 >> > + >> > +#define MP0_BASE__INST1_SEG0 0 >> > +#define MP0_BASE__INST1_SEG1 0 >> > +#define MP0_BASE__INST1_SEG2 0 >> > +#define MP0_BASE__INST1_SEG3 0 >> > +#define MP0_BASE__INST1_SEG4 0 >> > + >> > +#define MP0_BASE__INST2_SEG0 0 >> > +#define MP0_BASE__INST2_SEG1 0 >> > +#define MP0_BASE__INST2_SEG2 0 >> > +#define MP0_BASE__INST2_SEG3 0 >> > +#define MP0_BASE__INST2_SEG4 0 >> > + >> > +#define MP0_BASE__INST3_SEG0 0 >> > +#define MP0_BASE__INST3_SEG1 0 >> > +#define MP0_BASE__INST3_SEG2 0 >> > +#define MP0_BASE__INST3_SEG3 0 >> > +#define MP0_BASE__INST3_SEG4 0 >> > + >> > +#define MP0_BASE__INST4_SEG0 0 >> > +#define MP0_BASE__INST4_SEG1 0 >> > +#define MP0_BASE__INST4_SEG2 0 >> > +#define MP0_BASE__INST4_SEG3 0 >> > +#define MP0_BASE__INST4_SEG4 0 >> > + >> > +#define MP1_BASE__INST0_SEG0 0x00016000 >> > +#define MP1_BASE__INST0_SEG1 0 >> > +#define MP1_BASE__INST0_SEG2 0 >> > +#define MP1_BASE__INST0_SEG3 0 >> > +#define MP1_BASE__INST0_SEG4 0 >> > + >> > +#define MP1_BASE__INST1_SEG0 0 >> > +#define MP1_BASE__INST1_SEG1 0 >> > +#define MP1_BASE__INST1_SEG2 0 >> > +#define MP1_BASE__INST1_SEG3 0 >> > +#define MP1_BASE__INST1_SEG4 0 >> > + >> > +#define MP1_BASE__INST2_SEG0 0 >> > +#define MP1_BASE__INST2_SEG1 0 >> > +#define MP1_BASE__INST2_SEG2 0 >> > +#define MP1_BASE__INST2_SEG3 0 >> > +#define MP1_BASE__INST2_SEG4 0 >> > + >> > +#define MP1_BASE__INST3_SEG0 0 >> > +#define MP1_BASE__INST3_SEG1 0 >> > +#define MP1_BASE__INST3_SEG2 0 >> > +#define MP1_BASE__INST3_SEG3 0 >> > +#define MP1_BASE__INST3_SEG4 0 >> > + >> > +#define MP1_BASE__INST4_SEG0 0 >> > +#define MP1_BASE__INST4_SEG1 0 >> > +#define MP1_BASE__INST4_SEG2 0 >> > +#define MP1_BASE__INST4_SEG3 0 >> > +#define MP1_BASE__INST4_SEG4 0 >> > + >> > +#define MP2_BASE__INST0_SEG0 0x00016000 >> > +#define MP2_BASE__INST0_SEG1 0 >> > +#define MP2_BASE__INST0_SEG2 0 >> > +#define MP2_BASE__INST0_SEG3 0 >> > +#define MP2_BASE__INST0_SEG4 0 >> > + >> > +#define MP2_BASE__INST1_SEG0 0 >> > +#define MP2_BASE__INST1_SEG1 0 >> > +#define MP2_BASE__INST1_SEG2 0 >> > +#define MP2_BASE__INST1_SEG3 0 >> > +#define MP2_BASE__INST1_SEG4 0 >> > + >> > +#define MP2_BASE__INST2_SEG0 0 >> > +#define MP2_BASE__INST2_SEG1 0 >> > +#define MP2_BASE__INST2_SEG2 0 >> > +#define MP2_BASE__INST2_SEG3 0 >> > +#define MP2_BASE__INST2_SEG4 0 >> > + >> > +#define MP2_BASE__INST3_SEG0 0 >> > +#define MP2_BASE__INST3_SEG1 0 >> > +#define MP2_BASE__INST3_SEG2 0 >> > +#define MP2_BASE__INST3_SEG3 0 >> > +#define MP2_BASE__INST3_SEG4 0 >> > + >> > +#define MP2_BASE__INST4_SEG0 0 >> > +#define MP2_BASE__INST4_SEG1 0 >> > +#define MP2_BASE__INST4_SEG2 0 >> > +#define MP2_BASE__INST4_SEG3 0 >> > +#define MP2_BASE__INST4_SEG4 0 >> > + >> > +#define DF_BASE__INST0_SEG0 0x00007000 >> > +#define DF_BASE__INST0_SEG1 0 >> > +#define DF_BASE__INST0_SEG2 0 >> > +#define DF_BASE__INST0_SEG3 0 >> > +#define DF_BASE__INST0_SEG4 0 >> > + >> > +#define DF_BASE__INST1_SEG0 0 >> > +#define DF_BASE__INST1_SEG1 0 >> > +#define DF_BASE__INST1_SEG2 0 >> > +#define DF_BASE__INST1_SEG3 0 >> > +#define DF_BASE__INST1_SEG4 0 >> > + >> > +#define DF_BASE__INST2_SEG0 0 >> > +#define DF_BASE__INST2_SEG1 0 >> > +#define DF_BASE__INST2_SEG2 0 >> > +#define DF_BASE__INST2_SEG3 0 >> > +#define DF_BASE__INST2_SEG4 0 >> > + >> > +#define DF_BASE__INST3_SEG0 0 >> > +#define DF_BASE__INST3_SEG1 0 >> > +#define DF_BASE__INST3_SEG2 0 >> > +#define DF_BASE__INST3_SEG3 0 >> > +#define DF_BASE__INST3_SEG4 0 >> > + >> > +#define DF_BASE__INST4_SEG0 0 >> > +#define DF_BASE__INST4_SEG1 0 >> > +#define DF_BASE__INST4_SEG2 0 >> > +#define DF_BASE__INST4_SEG3 0 >> > +#define DF_BASE__INST4_SEG4 0 >> > + >> > +#define UVD_BASE__INST0_SEG0 0x00007800 >> > +#define UVD_BASE__INST0_SEG1 0x00007E00 >> > +#define UVD_BASE__INST0_SEG2 0 >> > +#define UVD_BASE__INST0_SEG3 0 >> > +#define UVD_BASE__INST0_SEG4 0 >> > + >> > +#define UVD_BASE__INST1_SEG0 0 >> > +#define UVD_BASE__INST1_SEG1 0 >> > +#define UVD_BASE__INST1_SEG2 0 >> > +#define UVD_BASE__INST1_SEG3 0 >> > +#define UVD_BASE__INST1_SEG4 0 >> > + >> > +#define UVD_BASE__INST2_SEG0 0 >> > +#define UVD_BASE__INST2_SEG1 0 >> > +#define UVD_BASE__INST2_SEG2 0 >> > +#define UVD_BASE__INST2_SEG3 0 >> > +#define UVD_BASE__INST2_SEG4 0 >> > + >> > +#define UVD_BASE__INST3_SEG0 0 >> > +#define UVD_BASE__INST3_SEG1 0 >> > +#define UVD_BASE__INST3_SEG2 0 >> > +#define UVD_BASE__INST3_SEG3 0 >> > +#define UVD_BASE__INST3_SEG4 0 >> > + >> > +#define UVD_BASE__INST4_SEG0 0 >> > +#define UVD_BASE__INST4_SEG1 0 >> > +#define UVD_BASE__INST4_SEG2 0 >> > +#define UVD_BASE__INST4_SEG3 0 >> > +#define UVD_BASE__INST4_SEG4 0 >> > + >> > +#define VCN_BASE__INST0_SEG0 0x00007800 >> > +#define VCN_BASE__INST0_SEG1 0x00007E00 >> > +#define VCN_BASE__INST0_SEG2 0 >> > +#define VCN_BASE__INST0_SEG3 0 >> > +#define VCN_BASE__INST0_SEG4 0 >> > + >> > +#define VCN_BASE__INST1_SEG0 0 >> > +#define VCN_BASE__INST1_SEG1 0 >> > +#define VCN_BASE__INST1_SEG2 0 >> > +#define VCN_BASE__INST1_SEG3 0 >> > +#define VCN_BASE__INST1_SEG4 0 >> > + >> > +#define VCN_BASE__INST2_SEG0 0 >> > +#define VCN_BASE__INST2_SEG1 0 >> > +#define VCN_BASE__INST2_SEG2 0 >> > +#define VCN_BASE__INST2_SEG3 0 >> > +#define VCN_BASE__INST2_SEG4 0 >> > + >> > +#define VCN_BASE__INST3_SEG0 0 >> > +#define VCN_BASE__INST3_SEG1 0 >> > +#define VCN_BASE__INST3_SEG2 0 >> > +#define VCN_BASE__INST3_SEG3 0 >> > +#define VCN_BASE__INST3_SEG4 0 >> > + >> > +#define VCN_BASE__INST4_SEG0 0 >> > +#define VCN_BASE__INST4_SEG1 0 >> > +#define VCN_BASE__INST4_SEG2 0 >> > +#define VCN_BASE__INST4_SEG3 0 >> > +#define VCN_BASE__INST4_SEG4 0 >> > + >> > +#define DBGU_BASE__INST0_SEG0 0x00000180 >> > +#define DBGU_BASE__INST0_SEG1 0x000001A0 >> > +#define DBGU_BASE__INST0_SEG2 0 >> > +#define DBGU_BASE__INST0_SEG3 0 >> > +#define DBGU_BASE__INST0_SEG4 0 >> > + >> > +#define DBGU_BASE__INST1_SEG0 0 >> > +#define DBGU_BASE__INST1_SEG1 0 >> > +#define DBGU_BASE__INST1_SEG2 0 >> > +#define DBGU_BASE__INST1_SEG3 0 >> > +#define DBGU_BASE__INST1_SEG4 0 >> > + >> > +#define DBGU_BASE__INST2_SEG0 0 >> > +#define DBGU_BASE__INST2_SEG1 0 >> > +#define DBGU_BASE__INST2_SEG2 0 >> > +#define DBGU_BASE__INST2_SEG3 0 >> > +#define DBGU_BASE__INST2_SEG4 0 >> > + >> > +#define DBGU_BASE__INST3_SEG0 0 >> > +#define DBGU_BASE__INST3_SEG1 0 >> > +#define DBGU_BASE__INST3_SEG2 0 >> > +#define DBGU_BASE__INST3_SEG3 0 >> > +#define DBGU_BASE__INST3_SEG4 0 >> > + >> > +#define DBGU_BASE__INST4_SEG0 0 >> > +#define DBGU_BASE__INST4_SEG1 0 >> > +#define DBGU_BASE__INST4_SEG2 0 >> > +#define DBGU_BASE__INST4_SEG3 0 >> > +#define DBGU_BASE__INST4_SEG4 0 >> > + >> > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 >> > +#define DBGU_NBIO_BASE__INST0_SEG1 0 >> > +#define DBGU_NBIO_BASE__INST0_SEG2 0 >> > +#define DBGU_NBIO_BASE__INST0_SEG3 0 >> > +#define DBGU_NBIO_BASE__INST0_SEG4 0 >> > + >> > +#define DBGU_NBIO_BASE__INST1_SEG0 0 >> > +#define DBGU_NBIO_BASE__INST1_SEG1 0 >> > +#define DBGU_NBIO_BASE__INST1_SEG2 0 >> > +#define DBGU_NBIO_BASE__INST1_SEG3 0 >> > +#define DBGU_NBIO_BASE__INST1_SEG4 0 >> > + >> > +#define DBGU_NBIO_BASE__INST2_SEG0 0 >> > +#define DBGU_NBIO_BASE__INST2_SEG1 0 >> > +#define DBGU_NBIO_BASE__INST2_SEG2 0 >> > +#define DBGU_NBIO_BASE__INST2_SEG3 0 >> > +#define DBGU_NBIO_BASE__INST2_SEG4 0 >> > + >> > +#define DBGU_NBIO_BASE__INST3_SEG0 0 >> > +#define DBGU_NBIO_BASE__INST3_SEG1 0 >> > +#define DBGU_NBIO_BASE__INST3_SEG2 0 >> > +#define DBGU_NBIO_BASE__INST3_SEG3 0 >> > +#define DBGU_NBIO_BASE__INST3_SEG4 0 >> > + >> > +#define DBGU_NBIO_BASE__INST4_SEG0 0 >> > +#define DBGU_NBIO_BASE__INST4_SEG1 0 >> > +#define DBGU_NBIO_BASE__INST4_SEG2 0 >> > +#define DBGU_NBIO_BASE__INST4_SEG3 0 >> > +#define DBGU_NBIO_BASE__INST4_SEG4 0 >> > + >> > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >> > +#define DBGU_IO_BASE__INST0_SEG1 0 >> > +#define DBGU_IO_BASE__INST0_SEG2 0 >> > +#define DBGU_IO_BASE__INST0_SEG3 0 >> > +#define DBGU_IO_BASE__INST0_SEG4 0 >> > + >> > +#define DBGU_IO_BASE__INST1_SEG0 0 >> > +#define DBGU_IO_BASE__INST1_SEG1 0 >> > +#define DBGU_IO_BASE__INST1_SEG2 0 >> > +#define DBGU_IO_BASE__INST1_SEG3 0 >> > +#define DBGU_IO_BASE__INST1_SEG4 0 >> > + >> > +#define DBGU_IO_BASE__INST2_SEG0 0 >> > +#define DBGU_IO_BASE__INST2_SEG1 0 >> > +#define DBGU_IO_BASE__INST2_SEG2 0 >> > +#define DBGU_IO_BASE__INST2_SEG3 0 >> > +#define DBGU_IO_BASE__INST2_SEG4 0 >> > + >> > +#define DBGU_IO_BASE__INST3_SEG0 0 >> > +#define DBGU_IO_BASE__INST3_SEG1 0 >> > +#define DBGU_IO_BASE__INST3_SEG2 0 >> > +#define DBGU_IO_BASE__INST3_SEG3 0 >> > +#define DBGU_IO_BASE__INST3_SEG4 0 >> > + >> > +#define DBGU_IO_BASE__INST4_SEG0 0 >> > +#define DBGU_IO_BASE__INST4_SEG1 0 >> > +#define DBGU_IO_BASE__INST4_SEG2 0 >> > +#define DBGU_IO_BASE__INST4_SEG3 0 >> > +#define DBGU_IO_BASE__INST4_SEG4 0 >> > + >> > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 >> > +#define DFX_DAP_BASE__INST0_SEG1 0 >> > +#define DFX_DAP_BASE__INST0_SEG2 0 >> > +#define DFX_DAP_BASE__INST0_SEG3 0 >> > +#define DFX_DAP_BASE__INST0_SEG4 0 >> > + >> > +#define DFX_DAP_BASE__INST1_SEG0 0 >> > +#define DFX_DAP_BASE__INST1_SEG1 0 >> > +#define DFX_DAP_BASE__INST1_SEG2 0 >> > +#define DFX_DAP_BASE__INST1_SEG3 0 >> > +#define DFX_DAP_BASE__INST1_SEG4 0 >> > + >> > +#define DFX_DAP_BASE__INST2_SEG0 0 >> > +#define DFX_DAP_BASE__INST2_SEG1 0 >> > +#define DFX_DAP_BASE__INST2_SEG2 0 >> > +#define DFX_DAP_BASE__INST2_SEG3 0 >> > +#define DFX_DAP_BASE__INST2_SEG4 0 >> > + >> > +#define DFX_DAP_BASE__INST3_SEG0 0 >> > +#define DFX_DAP_BASE__INST3_SEG1 0 >> > +#define DFX_DAP_BASE__INST3_SEG2 0 >> > +#define DFX_DAP_BASE__INST3_SEG3 0 >> > +#define DFX_DAP_BASE__INST3_SEG4 0 >> > + >> > +#define DFX_DAP_BASE__INST4_SEG0 0 >> > +#define DFX_DAP_BASE__INST4_SEG1 0 >> > +#define DFX_DAP_BASE__INST4_SEG2 0 >> > +#define DFX_DAP_BASE__INST4_SEG3 0 >> > +#define DFX_DAP_BASE__INST4_SEG4 0 >> > + >> > +#define DFX_BASE__INST0_SEG0 0x00000580 >> > +#define DFX_BASE__INST0_SEG1 0 >> > +#define DFX_BASE__INST0_SEG2 0 >> > +#define DFX_BASE__INST0_SEG3 0 >> > +#define DFX_BASE__INST0_SEG4 0 >> > + >> > +#define DFX_BASE__INST1_SEG0 0 >> > +#define DFX_BASE__INST1_SEG1 0 >> > +#define DFX_BASE__INST1_SEG2 0 >> > +#define DFX_BASE__INST1_SEG3 0 >> > +#define DFX_BASE__INST1_SEG4 0 >> > + >> > +#define DFX_BASE__INST2_SEG0 0 >> > +#define DFX_BASE__INST2_SEG1 0 >> > +#define DFX_BASE__INST2_SEG2 0 >> > +#define DFX_BASE__INST2_SEG3 0 >> > +#define DFX_BASE__INST2_SEG4 0 >> > + >> > +#define DFX_BASE__INST3_SEG0 0 >> > +#define DFX_BASE__INST3_SEG1 0 >> > +#define DFX_BASE__INST3_SEG2 0 >> > +#define DFX_BASE__INST3_SEG3 0 >> > +#define DFX_BASE__INST3_SEG4 0 >> > + >> > +#define DFX_BASE__INST4_SEG0 0 >> > +#define DFX_BASE__INST4_SEG1 0 >> > +#define DFX_BASE__INST4_SEG2 0 >> > +#define DFX_BASE__INST4_SEG3 0 >> > +#define DFX_BASE__INST4_SEG4 0 >> > + >> > +#define ISP_BASE__INST0_SEG0 0x00018000 >> > +#define ISP_BASE__INST0_SEG1 0 >> > +#define ISP_BASE__INST0_SEG2 0 >> > +#define ISP_BASE__INST0_SEG3 0 >> > +#define ISP_BASE__INST0_SEG4 0 >> > + >> > +#define ISP_BASE__INST1_SEG0 0 >> > +#define ISP_BASE__INST1_SEG1 0 >> > +#define ISP_BASE__INST1_SEG2 0 >> > +#define ISP_BASE__INST1_SEG3 0 >> > +#define ISP_BASE__INST1_SEG4 0 >> > + >> > +#define ISP_BASE__INST2_SEG0 0 >> > +#define ISP_BASE__INST2_SEG1 0 >> > +#define ISP_BASE__INST2_SEG2 0 >> > +#define ISP_BASE__INST2_SEG3 0 >> > +#define ISP_BASE__INST2_SEG4 0 >> > + >> > +#define ISP_BASE__INST3_SEG0 0 >> > +#define ISP_BASE__INST3_SEG1 0 >> > +#define ISP_BASE__INST3_SEG2 0 >> > +#define ISP_BASE__INST3_SEG3 0 >> > +#define ISP_BASE__INST3_SEG4 0 >> > + >> > +#define ISP_BASE__INST4_SEG0 0 >> > +#define ISP_BASE__INST4_SEG1 0 >> > +#define ISP_BASE__INST4_SEG2 0 >> > +#define ISP_BASE__INST4_SEG3 0 >> > +#define ISP_BASE__INST4_SEG4 0 >> > + >> > +#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0 >> > +#define SYSTEMHUB_BASE__INST0_SEG1 0 >> > +#define SYSTEMHUB_BASE__INST0_SEG2 0 >> > +#define SYSTEMHUB_BASE__INST0_SEG3 0 >> > +#define SYSTEMHUB_BASE__INST0_SEG4 0 >> > + >> > +#define SYSTEMHUB_BASE__INST1_SEG0 0 >> > +#define SYSTEMHUB_BASE__INST1_SEG1 0 >> > +#define SYSTEMHUB_BASE__INST1_SEG2 0 >> > +#define SYSTEMHUB_BASE__INST1_SEG3 0 >> > +#define SYSTEMHUB_BASE__INST1_SEG4 0 >> > + >> > +#define SYSTEMHUB_BASE__INST2_SEG0 0 >> > +#define SYSTEMHUB_BASE__INST2_SEG1 0 >> > +#define SYSTEMHUB_BASE__INST2_SEG2 0 >> > +#define SYSTEMHUB_BASE__INST2_SEG3 0 >> > +#define SYSTEMHUB_BASE__INST2_SEG4 0 >> > + >> > +#define SYSTEMHUB_BASE__INST3_SEG0 0 >> > +#define SYSTEMHUB_BASE__INST3_SEG1 0 >> > +#define SYSTEMHUB_BASE__INST3_SEG2 0 >> > +#define SYSTEMHUB_BASE__INST3_SEG3 0 >> > +#define SYSTEMHUB_BASE__INST3_SEG4 0 >> > + >> > +#define SYSTEMHUB_BASE__INST4_SEG0 0 >> > +#define SYSTEMHUB_BASE__INST4_SEG1 0 >> > +#define SYSTEMHUB_BASE__INST4_SEG2 0 >> > +#define SYSTEMHUB_BASE__INST4_SEG3 0 >> > +#define SYSTEMHUB_BASE__INST4_SEG4 0 >> > + >> > +#define L2IMU_BASE__INST0_SEG0 0x00007DC0 >> > +#define L2IMU_BASE__INST0_SEG1 0 >> > +#define L2IMU_BASE__INST0_SEG2 0 >> > +#define L2IMU_BASE__INST0_SEG3 0 >> > +#define L2IMU_BASE__INST0_SEG4 0 >> > + >> > +#define L2IMU_BASE__INST1_SEG0 0 >> > +#define L2IMU_BASE__INST1_SEG1 0 >> > +#define L2IMU_BASE__INST1_SEG2 0 >> > +#define L2IMU_BASE__INST1_SEG3 0 >> > +#define L2IMU_BASE__INST1_SEG4 0 >> > + >> > +#define L2IMU_BASE__INST2_SEG0 0 >> > +#define L2IMU_BASE__INST2_SEG1 0 >> > +#define L2IMU_BASE__INST2_SEG2 0 >> > +#define L2IMU_BASE__INST2_SEG3 0 >> > +#define L2IMU_BASE__INST2_SEG4 0 >> > + >> > +#define L2IMU_BASE__INST3_SEG0 0 >> > +#define L2IMU_BASE__INST3_SEG1 0 >> > +#define L2IMU_BASE__INST3_SEG2 0 >> > +#define L2IMU_BASE__INST3_SEG3 0 >> > +#define L2IMU_BASE__INST3_SEG4 0 >> > + >> > +#define L2IMU_BASE__INST4_SEG0 0 >> > +#define L2IMU_BASE__INST4_SEG1 0 >> > +#define L2IMU_BASE__INST4_SEG2 0 >> > +#define L2IMU_BASE__INST4_SEG3 0 >> > +#define L2IMU_BASE__INST4_SEG4 0 >> > + >> > +#define IOHC_BASE__INST0_SEG0 0x00010000 >> > +#define IOHC_BASE__INST0_SEG1 0 >> > +#define IOHC_BASE__INST0_SEG2 0 >> > +#define IOHC_BASE__INST0_SEG3 0 >> > +#define IOHC_BASE__INST0_SEG4 0 >> > + >> > +#define IOHC_BASE__INST1_SEG0 0 >> > +#define IOHC_BASE__INST1_SEG1 0 >> > +#define IOHC_BASE__INST1_SEG2 0 >> > +#define IOHC_BASE__INST1_SEG3 0 >> > +#define IOHC_BASE__INST1_SEG4 0 >> > + >> > +#define IOHC_BASE__INST2_SEG0 0 >> > +#define IOHC_BASE__INST2_SEG1 0 >> > +#define IOHC_BASE__INST2_SEG2 0 >> > +#define IOHC_BASE__INST2_SEG3 0 >> > +#define IOHC_BASE__INST2_SEG4 0 >> > + >> > +#define IOHC_BASE__INST3_SEG0 0 >> > +#define IOHC_BASE__INST3_SEG1 0 >> > +#define IOHC_BASE__INST3_SEG2 0 >> > +#define IOHC_BASE__INST3_SEG3 0 >> > +#define IOHC_BASE__INST3_SEG4 0 >> > + >> > +#define IOHC_BASE__INST4_SEG0 0 >> > +#define IOHC_BASE__INST4_SEG1 0 >> > +#define IOHC_BASE__INST4_SEG2 0 >> > +#define IOHC_BASE__INST4_SEG3 0 >> > +#define IOHC_BASE__INST4_SEG4 0 >> > + >> > +#define ATHUB_BASE__INST0_SEG0 0x00000C20 >> > +#define ATHUB_BASE__INST0_SEG1 0 >> > +#define ATHUB_BASE__INST0_SEG2 0 >> > +#define ATHUB_BASE__INST0_SEG3 0 >> > +#define ATHUB_BASE__INST0_SEG4 0 >> > + >> > +#define ATHUB_BASE__INST1_SEG0 0 >> > +#define ATHUB_BASE__INST1_SEG1 0 >> > +#define ATHUB_BASE__INST1_SEG2 0 >> > +#define ATHUB_BASE__INST1_SEG3 0 >> > +#define ATHUB_BASE__INST1_SEG4 0 >> > + >> > +#define ATHUB_BASE__INST2_SEG0 0 >> > +#define ATHUB_BASE__INST2_SEG1 0 >> > +#define ATHUB_BASE__INST2_SEG2 0 >> > +#define ATHUB_BASE__INST2_SEG3 0 >> > +#define ATHUB_BASE__INST2_SEG4 0 >> > + >> > +#define ATHUB_BASE__INST3_SEG0 0 >> > +#define ATHUB_BASE__INST3_SEG1 0 >> > +#define ATHUB_BASE__INST3_SEG2 0 >> > +#define ATHUB_BASE__INST3_SEG3 0 >> > +#define ATHUB_BASE__INST3_SEG4 0 >> > + >> > +#define ATHUB_BASE__INST4_SEG0 0 >> > +#define ATHUB_BASE__INST4_SEG1 0 >> > +#define ATHUB_BASE__INST4_SEG2 0 >> > +#define ATHUB_BASE__INST4_SEG3 0 >> > +#define ATHUB_BASE__INST4_SEG4 0 >> > + >> > +#define VCE_BASE__INST0_SEG0 0x00007E00 >> > +#define VCE_BASE__INST0_SEG1 0x00048800 >> > +#define VCE_BASE__INST0_SEG2 0 >> > +#define VCE_BASE__INST0_SEG3 0 >> > +#define VCE_BASE__INST0_SEG4 0 >> > + >> > +#define VCE_BASE__INST1_SEG0 0 >> > +#define VCE_BASE__INST1_SEG1 0 >> > +#define VCE_BASE__INST1_SEG2 0 >> > +#define VCE_BASE__INST1_SEG3 0 >> > +#define VCE_BASE__INST1_SEG4 0 >> > + >> > +#define VCE_BASE__INST2_SEG0 0 >> > +#define VCE_BASE__INST2_SEG1 0 >> > +#define VCE_BASE__INST2_SEG2 0 >> > +#define VCE_BASE__INST2_SEG3 0 >> > +#define VCE_BASE__INST2_SEG4 0 >> > + >> > +#define VCE_BASE__INST3_SEG0 0 >> > +#define VCE_BASE__INST3_SEG1 0 >> > +#define VCE_BASE__INST3_SEG2 0 >> > +#define VCE_BASE__INST3_SEG3 0 >> > +#define VCE_BASE__INST3_SEG4 0 >> > + >> > +#define VCE_BASE__INST4_SEG0 0 >> > +#define VCE_BASE__INST4_SEG1 0 >> > +#define VCE_BASE__INST4_SEG2 0 >> > +#define VCE_BASE__INST4_SEG3 0 >> > +#define VCE_BASE__INST4_SEG4 0 >> > + >> > +#define GC_BASE__INST0_SEG0 0x00002000 >> > +#define GC_BASE__INST0_SEG1 0x0000A000 >> > +#define GC_BASE__INST0_SEG2 0 >> > +#define GC_BASE__INST0_SEG3 0 >> > +#define GC_BASE__INST0_SEG4 0 >> > + >> > +#define GC_BASE__INST1_SEG0 0 >> > +#define GC_BASE__INST1_SEG1 0 >> > +#define GC_BASE__INST1_SEG2 0 >> > +#define GC_BASE__INST1_SEG3 0 >> > +#define GC_BASE__INST1_SEG4 0 >> > + >> > +#define GC_BASE__INST2_SEG0 0 >> > +#define GC_BASE__INST2_SEG1 0 >> > +#define GC_BASE__INST2_SEG2 0 >> > +#define GC_BASE__INST2_SEG3 0 >> > +#define GC_BASE__INST2_SEG4 0 >> > + >> > +#define GC_BASE__INST3_SEG0 0 >> > +#define GC_BASE__INST3_SEG1 0 >> > +#define GC_BASE__INST3_SEG2 0 >> > +#define GC_BASE__INST3_SEG3 0 >> > +#define GC_BASE__INST3_SEG4 0 >> > + >> > +#define GC_BASE__INST4_SEG0 0 >> > +#define GC_BASE__INST4_SEG1 0 >> > +#define GC_BASE__INST4_SEG2 0 >> > +#define GC_BASE__INST4_SEG3 0 >> > +#define GC_BASE__INST4_SEG4 0 >> > + >> > +#define MMHUB_BASE__INST0_SEG0 0x0001A000 >> > +#define MMHUB_BASE__INST0_SEG1 0 >> > +#define MMHUB_BASE__INST0_SEG2 0 >> > +#define MMHUB_BASE__INST0_SEG3 0 >> > +#define MMHUB_BASE__INST0_SEG4 0 >> > + >> > +#define MMHUB_BASE__INST1_SEG0 0 >> > +#define MMHUB_BASE__INST1_SEG1 0 >> > +#define MMHUB_BASE__INST1_SEG2 0 >> > +#define MMHUB_BASE__INST1_SEG3 0 >> > +#define MMHUB_BASE__INST1_SEG4 0 >> > + >> > +#define MMHUB_BASE__INST2_SEG0 0 >> > +#define MMHUB_BASE__INST2_SEG1 0 >> > +#define MMHUB_BASE__INST2_SEG2 0 >> > +#define MMHUB_BASE__INST2_SEG3 0 >> > +#define MMHUB_BASE__INST2_SEG4 0 >> > + >> > +#define MMHUB_BASE__INST3_SEG0 0 >> > +#define MMHUB_BASE__INST3_SEG1 0 >> > +#define MMHUB_BASE__INST3_SEG2 0 >> > +#define MMHUB_BASE__INST3_SEG3 0 >> > +#define MMHUB_BASE__INST3_SEG4 0 >> > + >> > +#define MMHUB_BASE__INST4_SEG0 0 >> > +#define MMHUB_BASE__INST4_SEG1 0 >> > +#define MMHUB_BASE__INST4_SEG2 0 >> > +#define MMHUB_BASE__INST4_SEG3 0 >> > +#define MMHUB_BASE__INST4_SEG4 0 >> > + >> > +#define RSMU_BASE__INST0_SEG0 0x00012000 >> > +#define RSMU_BASE__INST0_SEG1 0 >> > +#define RSMU_BASE__INST0_SEG2 0 >> > +#define RSMU_BASE__INST0_SEG3 0 >> > +#define RSMU_BASE__INST0_SEG4 0 >> > + >> > +#define RSMU_BASE__INST1_SEG0 0 >> > +#define RSMU_BASE__INST1_SEG1 0 >> > +#define RSMU_BASE__INST1_SEG2 0 >> > +#define RSMU_BASE__INST1_SEG3 0 >> > +#define RSMU_BASE__INST1_SEG4 0 >> > + >> > +#define RSMU_BASE__INST2_SEG0 0 >> > +#define RSMU_BASE__INST2_SEG1 0 >> > +#define RSMU_BASE__INST2_SEG2 0 >> > +#define RSMU_BASE__INST2_SEG3 0 >> > +#define RSMU_BASE__INST2_SEG4 0 >> > + >> > +#define RSMU_BASE__INST3_SEG0 0 >> > +#define RSMU_BASE__INST3_SEG1 0 >> > +#define RSMU_BASE__INST3_SEG2 0 >> > +#define RSMU_BASE__INST3_SEG3 0 >> > +#define RSMU_BASE__INST3_SEG4 0 >> > + >> > +#define RSMU_BASE__INST4_SEG0 0 >> > +#define RSMU_BASE__INST4_SEG1 0 >> > +#define RSMU_BASE__INST4_SEG2 0 >> > +#define RSMU_BASE__INST4_SEG3 0 >> > +#define RSMU_BASE__INST4_SEG4 0 >> > + >> > +#define HDP_BASE__INST0_SEG0 0x00000F20 >> > +#define HDP_BASE__INST0_SEG1 0 >> > +#define HDP_BASE__INST0_SEG2 0 >> > +#define HDP_BASE__INST0_SEG3 0 >> > +#define HDP_BASE__INST0_SEG4 0 >> > + >> > +#define HDP_BASE__INST1_SEG0 0 >> > +#define HDP_BASE__INST1_SEG1 0 >> > +#define HDP_BASE__INST1_SEG2 0 >> > +#define HDP_BASE__INST1_SEG3 0 >> > +#define HDP_BASE__INST1_SEG4 0 >> > + >> > +#define HDP_BASE__INST2_SEG0 0 >> > +#define HDP_BASE__INST2_SEG1 0 >> > +#define HDP_BASE__INST2_SEG2 0 >> > +#define HDP_BASE__INST2_SEG3 0 >> > +#define HDP_BASE__INST2_SEG4 0 >> > + >> > +#define HDP_BASE__INST3_SEG0 0 >> > +#define HDP_BASE__INST3_SEG1 0 >> > +#define HDP_BASE__INST3_SEG2 0 >> > +#define HDP_BASE__INST3_SEG3 0 >> > +#define HDP_BASE__INST3_SEG4 0 >> > + >> > +#define HDP_BASE__INST4_SEG0 0 >> > +#define HDP_BASE__INST4_SEG1 0 >> > +#define HDP_BASE__INST4_SEG2 0 >> > +#define HDP_BASE__INST4_SEG3 0 >> > +#define HDP_BASE__INST4_SEG4 0 >> > + >> > +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 >> > +#define OSSSYS_BASE__INST0_SEG1 0 >> > +#define OSSSYS_BASE__INST0_SEG2 0 >> > +#define OSSSYS_BASE__INST0_SEG3 0 >> > +#define OSSSYS_BASE__INST0_SEG4 0 >> > + >> > +#define OSSSYS_BASE__INST1_SEG0 0 >> > +#define OSSSYS_BASE__INST1_SEG1 0 >> > +#define OSSSYS_BASE__INST1_SEG2 0 >> > +#define OSSSYS_BASE__INST1_SEG3 0 >> > +#define OSSSYS_BASE__INST1_SEG4 0 >> > + >> > +#define OSSSYS_BASE__INST2_SEG0 0 >> > +#define OSSSYS_BASE__INST2_SEG1 0 >> > +#define OSSSYS_BASE__INST2_SEG2 0 >> > +#define OSSSYS_BASE__INST2_SEG3 0 >> > +#define OSSSYS_BASE__INST2_SEG4 0 >> > + >> > +#define OSSSYS_BASE__INST3_SEG0 0 >> > +#define OSSSYS_BASE__INST3_SEG1 0 >> > +#define OSSSYS_BASE__INST3_SEG2 0 >> > +#define OSSSYS_BASE__INST3_SEG3 0 >> > +#define OSSSYS_BASE__INST3_SEG4 0 >> > + >> > +#define OSSSYS_BASE__INST4_SEG0 0 >> > +#define OSSSYS_BASE__INST4_SEG1 0 >> > +#define OSSSYS_BASE__INST4_SEG2 0 >> > +#define OSSSYS_BASE__INST4_SEG3 0 >> > +#define OSSSYS_BASE__INST4_SEG4 0 >> > + >> > +#define SDMA0_BASE__INST0_SEG0 0x00001260 >> > +#define SDMA0_BASE__INST0_SEG1 0 >> > +#define SDMA0_BASE__INST0_SEG2 0 >> > +#define SDMA0_BASE__INST0_SEG3 0 >> > +#define SDMA0_BASE__INST0_SEG4 0 >> > + >> > +#define SDMA0_BASE__INST1_SEG0 0 >> > +#define SDMA0_BASE__INST1_SEG1 0 >> > +#define SDMA0_BASE__INST1_SEG2 0 >> > +#define SDMA0_BASE__INST1_SEG3 0 >> > +#define SDMA0_BASE__INST1_SEG4 0 >> > + >> > +#define SDMA0_BASE__INST2_SEG0 0 >> > +#define SDMA0_BASE__INST2_SEG1 0 >> > +#define SDMA0_BASE__INST2_SEG2 0 >> > +#define SDMA0_BASE__INST2_SEG3 0 >> > +#define SDMA0_BASE__INST2_SEG4 0 >> > + >> > +#define SDMA0_BASE__INST3_SEG0 0 >> > +#define SDMA0_BASE__INST3_SEG1 0 >> > +#define SDMA0_BASE__INST3_SEG2 0 >> > +#define SDMA0_BASE__INST3_SEG3 0 >> > +#define SDMA0_BASE__INST3_SEG4 0 >> > + >> > +#define SDMA0_BASE__INST4_SEG0 0 >> > +#define SDMA0_BASE__INST4_SEG1 0 >> > +#define SDMA0_BASE__INST4_SEG2 0 >> > +#define SDMA0_BASE__INST4_SEG3 0 >> > +#define SDMA0_BASE__INST4_SEG4 0 >> > + >> > +#define SDMA1_BASE__INST0_SEG0 0x00001460 >> > +#define SDMA1_BASE__INST0_SEG1 0 >> > +#define SDMA1_BASE__INST0_SEG2 0 >> > +#define SDMA1_BASE__INST0_SEG3 0 >> > +#define SDMA1_BASE__INST0_SEG4 0 >> > + >> > +#define SDMA1_BASE__INST1_SEG0 0 >> > +#define SDMA1_BASE__INST1_SEG1 0 >> > +#define SDMA1_BASE__INST1_SEG2 0 >> > +#define SDMA1_BASE__INST1_SEG3 0 >> > +#define SDMA1_BASE__INST1_SEG4 0 >> > + >> > +#define SDMA1_BASE__INST2_SEG0 0 >> > +#define SDMA1_BASE__INST2_SEG1 0 >> > +#define SDMA1_BASE__INST2_SEG2 0 >> > +#define SDMA1_BASE__INST2_SEG3 0 >> > +#define SDMA1_BASE__INST2_SEG4 0 >> > + >> > +#define SDMA1_BASE__INST3_SEG0 0 >> > +#define SDMA1_BASE__INST3_SEG1 0 >> > +#define SDMA1_BASE__INST3_SEG2 0 >> > +#define SDMA1_BASE__INST3_SEG3 0 >> > +#define SDMA1_BASE__INST3_SEG4 0 >> > + >> > +#define SDMA1_BASE__INST4_SEG0 0 >> > +#define SDMA1_BASE__INST4_SEG1 0 >> > +#define SDMA1_BASE__INST4_SEG2 0 >> > +#define SDMA1_BASE__INST4_SEG3 0 >> > +#define SDMA1_BASE__INST4_SEG4 0 >> > + >> > +#define XDMA_BASE__INST0_SEG0 0x00003400 >> > +#define XDMA_BASE__INST0_SEG1 0 >> > +#define XDMA_BASE__INST0_SEG2 0 >> > +#define XDMA_BASE__INST0_SEG3 0 >> > +#define XDMA_BASE__INST0_SEG4 0 >> > + >> > +#define XDMA_BASE__INST1_SEG0 0 >> > +#define XDMA_BASE__INST1_SEG1 0 >> > +#define XDMA_BASE__INST1_SEG2 0 >> > +#define XDMA_BASE__INST1_SEG3 0 >> > >> >> >> >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <ec783d5b-74a5-07e8-6bb4-5c930e56a718-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <ec783d5b-74a5-07e8-6bb4-5c930e56a718-5C7GfCeVMHo@public.gmane.org> @ 2017-11-27 20:56 ` Alex Deucher [not found] ` <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: Alex Deucher @ 2017-11-27 20:56 UTC (permalink / raw) To: Christian König; +Cc: Felix Kuehling, amd-gfx list On Mon, Nov 27, 2017 at 3:44 PM, Christian König <christian.koenig@amd.com> wrote: > Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >> >> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>> >>> And that is a clear NAK to this approach. >> >> Hi Christian, >> >> Do you have other objections than the style issues? If so, please explain. > > > No, the technical aspect actually looks rather reasonable. > >> Please clarify, why this file needs to be treated differently from other >> files under include/asic_reg? All those files are auto-generated by HW >> teams. Fixing the coding style adds no value and makes future updates >> more complicated. > > > We already got complains about that and most likely will need to fix the > rest as well. I'd like to stay as close as possible to the headers formats we are using internally across teams for consistency. Rather than rewriting these now, how about we just rename soc15ip.h to vg10ip.h and use that or even just drop patch 1 and use soc15ip.h as is for now. Alex > > Nicolai looked into using a different auto generator for the header files, > but not sure how far that already got along. > > The point is that the structures added with this won't be used by soc15 > alone, but rather be the base of the new register definition for future > hardware generations as well. > >> Like Shaoyun pointed out for example, the existing file >> include/asic_reg/vega10/soc15ip.h has the same style issues. > > > That file actually doesn't exists any more. Please see the work from Feifei > about that as well. > > Regards, > Christian. > >> >> Regards, >> Felix >> >>> Please start by fixing at least the obvious style problems before >>> resending. >>> >>> Thanks, >>> Christian. >>> >>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: >>> >>> I agree that this HW engineer generated file doesn't match the >>> coding style from linux software engineer point of view , but >>> since we already import other similar " HW engineer style" files >>> under include/asic_reg/vega10/, I don't see a reason to specially >>> change this file without touch else . This file is actually almost >>> identical as soc15ip.h . I think it's easier for us to import >>> other offset file in the future if we keep them un-touched . >>> >>> Regards >>> Shaoyun.liu >>> >>> >>> -----Original Message----- >>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] >>> Sent: Monday, November 27, 2017 2:17 PM >>> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org >>> Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file >>> >>> First of let us fix the obvious style problems. >>> >>> Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: >>> > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c >>> > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> >>> > --- >>> > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 >>> ++++++++++++++++++++ >>> > 1 file changed, 1248 insertions(+) >>> > create mode 100644 >>> drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > >>> > diff --git >>> a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > new file mode 100644 >>> > index 0000000..76cb748 >>> > --- /dev/null >>> > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > @@ -0,0 +1,1248 @@ >>> > +#ifndef _ip_offset_1_HEADER >>> > +#define _ip_offset_1_HEADER >>> Names for preprocessor defines should be capitable. >>> >>> > + >>> > +#define MAX_INSTANCE 5 >>> > +#define MAX_SEGMENT 5 >>> > + >>> > + >>> > +struct IP_BASE_INSTANCE >>> >>> Structure names should be lower case. And we need an amdgpu_ or at >>> least >>> amd_ prefix here. >>> >>> Regards, >>> Christian. >>> >>> > +{ >>> > + unsigned int segment[MAX_SEGMENT]; >>> > +}; >>> > + >>> > +struct IP_BASE >>> > +{ >>> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >>> > +}; >>> > + >>> > + >>> > +static const struct IP_BASE NBIF_BASE = >>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE NBIO_BASE = >>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DCE_BASE = { { { { >>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DCN_BASE = { { { { >>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP0_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP1_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP2_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DF_BASE = { { { { >>> 0x00007000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE UVD_BASE = { { { { >>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>> segment >>> >>> No "//" in kernel code please. >>> >>> > +static const struct IP_BASE VCN_BASE = { { { { >>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>> segment >>> > +static const struct IP_BASE DBGU_BASE = >>> { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { >>> 0x000001C0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DBGU_IO_BASE = { { { { >>> 0x000001E0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DFX_DAP_BASE = { { { { >>> 0x000005A0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DFX_BASE = { { { { >>> 0x00000580, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers >>> > +static const struct IP_BASE ISP_BASE = { { { { >>> 0x00018000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { >>> 0x00000EA0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE L2IMU_BASE = >>> { { { { 0x00007DC0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE IOHC_BASE = >>> { { { { 0x00010000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE ATHUB_BASE = >>> { { { { 0x00000C20, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE VCE_BASE = { { { { >>> 0x00007E00, 0x00048800, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE GC_BASE = { { { { >>> 0x00002000, 0x0000A000, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MMHUB_BASE = >>> { { { { 0x0001A000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE RSMU_BASE = >>> { { { { 0x00012000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE HDP_BASE = { { { { >>> 0x00000F20, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE OSSSYS_BASE = { { { { >>> 0x000010A0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SDMA0_BASE = >>> { { { { 0x00001260, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SDMA1_BASE = >>> { { { { 0x00001460, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE XDMA_BASE = >>> { { { { 0x00003400, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE UMC_BASE = { { { { >>> 0x00014000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE THM_BASE = { { { { >>> 0x00016600, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SMUIO_BASE = >>> { { { { 0x00016800, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE PWR_BASE = { { { { >>> 0x00016A00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE CLK_BASE = { { { { >>> 0x00016C00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0x00016E00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0x00017000, 0, 0, 0, 0 } }, >>> > + { { 0x00017200, 0, 0, >>> 0, 0 } }, >>> > + { >>> { 0x00017E00, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE FUSE_BASE = >>> { { { { 0x00017400, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > + >>> > + >>> > +#define NBIF_BASE__INST0_SEG0 0x00000000 >>> > +#define NBIF_BASE__INST0_SEG1 0x00000014 >>> > +#define NBIF_BASE__INST0_SEG2 0x00000D20 >>> > +#define NBIF_BASE__INST0_SEG3 0x00010400 >>> > +#define NBIF_BASE__INST0_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST1_SEG0 0 >>> > +#define NBIF_BASE__INST1_SEG1 0 >>> > +#define NBIF_BASE__INST1_SEG2 0 >>> > +#define NBIF_BASE__INST1_SEG3 0 >>> > +#define NBIF_BASE__INST1_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST2_SEG0 0 >>> > +#define NBIF_BASE__INST2_SEG1 0 >>> > +#define NBIF_BASE__INST2_SEG2 0 >>> > +#define NBIF_BASE__INST2_SEG3 0 >>> > +#define NBIF_BASE__INST2_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST3_SEG0 0 >>> > +#define NBIF_BASE__INST3_SEG1 0 >>> > +#define NBIF_BASE__INST3_SEG2 0 >>> > +#define NBIF_BASE__INST3_SEG3 0 >>> > +#define NBIF_BASE__INST3_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST4_SEG0 0 >>> > +#define NBIF_BASE__INST4_SEG1 0 >>> > +#define NBIF_BASE__INST4_SEG2 0 >>> > +#define NBIF_BASE__INST4_SEG3 0 >>> > +#define NBIF_BASE__INST4_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST0_SEG0 0x00000000 >>> > +#define NBIO_BASE__INST0_SEG1 0x00000014 >>> > +#define NBIO_BASE__INST0_SEG2 0x00000D20 >>> > +#define NBIO_BASE__INST0_SEG3 0x00010400 >>> > +#define NBIO_BASE__INST0_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST1_SEG0 0 >>> > +#define NBIO_BASE__INST1_SEG1 0 >>> > +#define NBIO_BASE__INST1_SEG2 0 >>> > +#define NBIO_BASE__INST1_SEG3 0 >>> > +#define NBIO_BASE__INST1_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST2_SEG0 0 >>> > +#define NBIO_BASE__INST2_SEG1 0 >>> > +#define NBIO_BASE__INST2_SEG2 0 >>> > +#define NBIO_BASE__INST2_SEG3 0 >>> > +#define NBIO_BASE__INST2_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST3_SEG0 0 >>> > +#define NBIO_BASE__INST3_SEG1 0 >>> > +#define NBIO_BASE__INST3_SEG2 0 >>> > +#define NBIO_BASE__INST3_SEG3 0 >>> > +#define NBIO_BASE__INST3_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST4_SEG0 0 >>> > +#define NBIO_BASE__INST4_SEG1 0 >>> > +#define NBIO_BASE__INST4_SEG2 0 >>> > +#define NBIO_BASE__INST4_SEG3 0 >>> > +#define NBIO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST0_SEG0 0x00000012 >>> > +#define DCE_BASE__INST0_SEG1 0x000000C0 >>> > +#define DCE_BASE__INST0_SEG2 0x000034C0 >>> > +#define DCE_BASE__INST0_SEG3 0 >>> > +#define DCE_BASE__INST0_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST1_SEG0 0 >>> > +#define DCE_BASE__INST1_SEG1 0 >>> > +#define DCE_BASE__INST1_SEG2 0 >>> > +#define DCE_BASE__INST1_SEG3 0 >>> > +#define DCE_BASE__INST1_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST2_SEG0 0 >>> > +#define DCE_BASE__INST2_SEG1 0 >>> > +#define DCE_BASE__INST2_SEG2 0 >>> > +#define DCE_BASE__INST2_SEG3 0 >>> > +#define DCE_BASE__INST2_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST3_SEG0 0 >>> > +#define DCE_BASE__INST3_SEG1 0 >>> > +#define DCE_BASE__INST3_SEG2 0 >>> > +#define DCE_BASE__INST3_SEG3 0 >>> > +#define DCE_BASE__INST3_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST4_SEG0 0 >>> > +#define DCE_BASE__INST4_SEG1 0 >>> > +#define DCE_BASE__INST4_SEG2 0 >>> > +#define DCE_BASE__INST4_SEG3 0 >>> > +#define DCE_BASE__INST4_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST0_SEG0 0x00000012 >>> > +#define DCN_BASE__INST0_SEG1 0x000000C0 >>> > +#define DCN_BASE__INST0_SEG2 0x000034C0 >>> > +#define DCN_BASE__INST0_SEG3 0 >>> > +#define DCN_BASE__INST0_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST1_SEG0 0 >>> > +#define DCN_BASE__INST1_SEG1 0 >>> > +#define DCN_BASE__INST1_SEG2 0 >>> > +#define DCN_BASE__INST1_SEG3 0 >>> > +#define DCN_BASE__INST1_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST2_SEG0 0 >>> > +#define DCN_BASE__INST2_SEG1 0 >>> > +#define DCN_BASE__INST2_SEG2 0 >>> > +#define DCN_BASE__INST2_SEG3 0 >>> > +#define DCN_BASE__INST2_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST3_SEG0 0 >>> > +#define DCN_BASE__INST3_SEG1 0 >>> > +#define DCN_BASE__INST3_SEG2 0 >>> > +#define DCN_BASE__INST3_SEG3 0 >>> > +#define DCN_BASE__INST3_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST4_SEG0 0 >>> > +#define DCN_BASE__INST4_SEG1 0 >>> > +#define DCN_BASE__INST4_SEG2 0 >>> > +#define DCN_BASE__INST4_SEG3 0 >>> > +#define DCN_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST0_SEG0 0x00016000 >>> > +#define MP0_BASE__INST0_SEG1 0 >>> > +#define MP0_BASE__INST0_SEG2 0 >>> > +#define MP0_BASE__INST0_SEG3 0 >>> > +#define MP0_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST1_SEG0 0 >>> > +#define MP0_BASE__INST1_SEG1 0 >>> > +#define MP0_BASE__INST1_SEG2 0 >>> > +#define MP0_BASE__INST1_SEG3 0 >>> > +#define MP0_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST2_SEG0 0 >>> > +#define MP0_BASE__INST2_SEG1 0 >>> > +#define MP0_BASE__INST2_SEG2 0 >>> > +#define MP0_BASE__INST2_SEG3 0 >>> > +#define MP0_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST3_SEG0 0 >>> > +#define MP0_BASE__INST3_SEG1 0 >>> > +#define MP0_BASE__INST3_SEG2 0 >>> > +#define MP0_BASE__INST3_SEG3 0 >>> > +#define MP0_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST4_SEG0 0 >>> > +#define MP0_BASE__INST4_SEG1 0 >>> > +#define MP0_BASE__INST4_SEG2 0 >>> > +#define MP0_BASE__INST4_SEG3 0 >>> > +#define MP0_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST0_SEG0 0x00016000 >>> > +#define MP1_BASE__INST0_SEG1 0 >>> > +#define MP1_BASE__INST0_SEG2 0 >>> > +#define MP1_BASE__INST0_SEG3 0 >>> > +#define MP1_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST1_SEG0 0 >>> > +#define MP1_BASE__INST1_SEG1 0 >>> > +#define MP1_BASE__INST1_SEG2 0 >>> > +#define MP1_BASE__INST1_SEG3 0 >>> > +#define MP1_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST2_SEG0 0 >>> > +#define MP1_BASE__INST2_SEG1 0 >>> > +#define MP1_BASE__INST2_SEG2 0 >>> > +#define MP1_BASE__INST2_SEG3 0 >>> > +#define MP1_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST3_SEG0 0 >>> > +#define MP1_BASE__INST3_SEG1 0 >>> > +#define MP1_BASE__INST3_SEG2 0 >>> > +#define MP1_BASE__INST3_SEG3 0 >>> > +#define MP1_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST4_SEG0 0 >>> > +#define MP1_BASE__INST4_SEG1 0 >>> > +#define MP1_BASE__INST4_SEG2 0 >>> > +#define MP1_BASE__INST4_SEG3 0 >>> > +#define MP1_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST0_SEG0 0x00016000 >>> > +#define MP2_BASE__INST0_SEG1 0 >>> > +#define MP2_BASE__INST0_SEG2 0 >>> > +#define MP2_BASE__INST0_SEG3 0 >>> > +#define MP2_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST1_SEG0 0 >>> > +#define MP2_BASE__INST1_SEG1 0 >>> > +#define MP2_BASE__INST1_SEG2 0 >>> > +#define MP2_BASE__INST1_SEG3 0 >>> > +#define MP2_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST2_SEG0 0 >>> > +#define MP2_BASE__INST2_SEG1 0 >>> > +#define MP2_BASE__INST2_SEG2 0 >>> > +#define MP2_BASE__INST2_SEG3 0 >>> > +#define MP2_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST3_SEG0 0 >>> > +#define MP2_BASE__INST3_SEG1 0 >>> > +#define MP2_BASE__INST3_SEG2 0 >>> > +#define MP2_BASE__INST3_SEG3 0 >>> > +#define MP2_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST4_SEG0 0 >>> > +#define MP2_BASE__INST4_SEG1 0 >>> > +#define MP2_BASE__INST4_SEG2 0 >>> > +#define MP2_BASE__INST4_SEG3 0 >>> > +#define MP2_BASE__INST4_SEG4 0 >>> > + >>> > +#define DF_BASE__INST0_SEG0 0x00007000 >>> > +#define DF_BASE__INST0_SEG1 0 >>> > +#define DF_BASE__INST0_SEG2 0 >>> > +#define DF_BASE__INST0_SEG3 0 >>> > +#define DF_BASE__INST0_SEG4 0 >>> > + >>> > +#define DF_BASE__INST1_SEG0 0 >>> > +#define DF_BASE__INST1_SEG1 0 >>> > +#define DF_BASE__INST1_SEG2 0 >>> > +#define DF_BASE__INST1_SEG3 0 >>> > +#define DF_BASE__INST1_SEG4 0 >>> > + >>> > +#define DF_BASE__INST2_SEG0 0 >>> > +#define DF_BASE__INST2_SEG1 0 >>> > +#define DF_BASE__INST2_SEG2 0 >>> > +#define DF_BASE__INST2_SEG3 0 >>> > +#define DF_BASE__INST2_SEG4 0 >>> > + >>> > +#define DF_BASE__INST3_SEG0 0 >>> > +#define DF_BASE__INST3_SEG1 0 >>> > +#define DF_BASE__INST3_SEG2 0 >>> > +#define DF_BASE__INST3_SEG3 0 >>> > +#define DF_BASE__INST3_SEG4 0 >>> > + >>> > +#define DF_BASE__INST4_SEG0 0 >>> > +#define DF_BASE__INST4_SEG1 0 >>> > +#define DF_BASE__INST4_SEG2 0 >>> > +#define DF_BASE__INST4_SEG3 0 >>> > +#define DF_BASE__INST4_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST0_SEG0 0x00007800 >>> > +#define UVD_BASE__INST0_SEG1 0x00007E00 >>> > +#define UVD_BASE__INST0_SEG2 0 >>> > +#define UVD_BASE__INST0_SEG3 0 >>> > +#define UVD_BASE__INST0_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST1_SEG0 0 >>> > +#define UVD_BASE__INST1_SEG1 0 >>> > +#define UVD_BASE__INST1_SEG2 0 >>> > +#define UVD_BASE__INST1_SEG3 0 >>> > +#define UVD_BASE__INST1_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST2_SEG0 0 >>> > +#define UVD_BASE__INST2_SEG1 0 >>> > +#define UVD_BASE__INST2_SEG2 0 >>> > +#define UVD_BASE__INST2_SEG3 0 >>> > +#define UVD_BASE__INST2_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST3_SEG0 0 >>> > +#define UVD_BASE__INST3_SEG1 0 >>> > +#define UVD_BASE__INST3_SEG2 0 >>> > +#define UVD_BASE__INST3_SEG3 0 >>> > +#define UVD_BASE__INST3_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST4_SEG0 0 >>> > +#define UVD_BASE__INST4_SEG1 0 >>> > +#define UVD_BASE__INST4_SEG2 0 >>> > +#define UVD_BASE__INST4_SEG3 0 >>> > +#define UVD_BASE__INST4_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST0_SEG0 0x00007800 >>> > +#define VCN_BASE__INST0_SEG1 0x00007E00 >>> > +#define VCN_BASE__INST0_SEG2 0 >>> > +#define VCN_BASE__INST0_SEG3 0 >>> > +#define VCN_BASE__INST0_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST1_SEG0 0 >>> > +#define VCN_BASE__INST1_SEG1 0 >>> > +#define VCN_BASE__INST1_SEG2 0 >>> > +#define VCN_BASE__INST1_SEG3 0 >>> > +#define VCN_BASE__INST1_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST2_SEG0 0 >>> > +#define VCN_BASE__INST2_SEG1 0 >>> > +#define VCN_BASE__INST2_SEG2 0 >>> > +#define VCN_BASE__INST2_SEG3 0 >>> > +#define VCN_BASE__INST2_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST3_SEG0 0 >>> > +#define VCN_BASE__INST3_SEG1 0 >>> > +#define VCN_BASE__INST3_SEG2 0 >>> > +#define VCN_BASE__INST3_SEG3 0 >>> > +#define VCN_BASE__INST3_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST4_SEG0 0 >>> > +#define VCN_BASE__INST4_SEG1 0 >>> > +#define VCN_BASE__INST4_SEG2 0 >>> > +#define VCN_BASE__INST4_SEG3 0 >>> > +#define VCN_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST0_SEG0 0x00000180 >>> > +#define DBGU_BASE__INST0_SEG1 0x000001A0 >>> > +#define DBGU_BASE__INST0_SEG2 0 >>> > +#define DBGU_BASE__INST0_SEG3 0 >>> > +#define DBGU_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST1_SEG0 0 >>> > +#define DBGU_BASE__INST1_SEG1 0 >>> > +#define DBGU_BASE__INST1_SEG2 0 >>> > +#define DBGU_BASE__INST1_SEG3 0 >>> > +#define DBGU_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST2_SEG0 0 >>> > +#define DBGU_BASE__INST2_SEG1 0 >>> > +#define DBGU_BASE__INST2_SEG2 0 >>> > +#define DBGU_BASE__INST2_SEG3 0 >>> > +#define DBGU_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST3_SEG0 0 >>> > +#define DBGU_BASE__INST3_SEG1 0 >>> > +#define DBGU_BASE__INST3_SEG2 0 >>> > +#define DBGU_BASE__INST3_SEG3 0 >>> > +#define DBGU_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST4_SEG0 0 >>> > +#define DBGU_BASE__INST4_SEG1 0 >>> > +#define DBGU_BASE__INST4_SEG2 0 >>> > +#define DBGU_BASE__INST4_SEG3 0 >>> > +#define DBGU_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST1_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST2_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST3_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST4_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >>> > +#define DBGU_IO_BASE__INST0_SEG1 0 >>> > +#define DBGU_IO_BASE__INST0_SEG2 0 >>> > +#define DBGU_IO_BASE__INST0_SEG3 0 >>> > +#define DBGU_IO_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST1_SEG0 0 >>> > +#define DBGU_IO_BASE__INST1_SEG1 0 >>> > +#define DBGU_IO_BASE__INST1_SEG2 0 >>> > +#define DBGU_IO_BASE__INST1_SEG3 0 >>> > +#define DBGU_IO_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST2_SEG0 0 >>> > +#define DBGU_IO_BASE__INST2_SEG1 0 >>> > +#define DBGU_IO_BASE__INST2_SEG2 0 >>> > +#define DBGU_IO_BASE__INST2_SEG3 0 >>> > +#define DBGU_IO_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST3_SEG0 0 >>> > +#define DBGU_IO_BASE__INST3_SEG1 0 >>> > +#define DBGU_IO_BASE__INST3_SEG2 0 >>> > +#define DBGU_IO_BASE__INST3_SEG3 0 >>> > +#define DBGU_IO_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST4_SEG0 0 >>> > +#define DBGU_IO_BASE__INST4_SEG1 0 >>> > +#define DBGU_IO_BASE__INST4_SEG2 0 >>> > +#define DBGU_IO_BASE__INST4_SEG3 0 >>> > +#define DBGU_IO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 >>> > +#define DFX_DAP_BASE__INST0_SEG1 0 >>> > +#define DFX_DAP_BASE__INST0_SEG2 0 >>> > +#define DFX_DAP_BASE__INST0_SEG3 0 >>> > +#define DFX_DAP_BASE__INST0_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST1_SEG0 0 >>> > +#define DFX_DAP_BASE__INST1_SEG1 0 >>> > +#define DFX_DAP_BASE__INST1_SEG2 0 >>> > +#define DFX_DAP_BASE__INST1_SEG3 0 >>> > +#define DFX_DAP_BASE__INST1_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST2_SEG0 0 >>> > +#define DFX_DAP_BASE__INST2_SEG1 0 >>> > +#define DFX_DAP_BASE__INST2_SEG2 0 >>> > +#define DFX_DAP_BASE__INST2_SEG3 0 >>> > +#define DFX_DAP_BASE__INST2_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST3_SEG0 0 >>> > +#define DFX_DAP_BASE__INST3_SEG1 0 >>> > +#define DFX_DAP_BASE__INST3_SEG2 0 >>> > +#define DFX_DAP_BASE__INST3_SEG3 0 >>> > +#define DFX_DAP_BASE__INST3_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST4_SEG0 0 >>> > +#define DFX_DAP_BASE__INST4_SEG1 0 >>> > +#define DFX_DAP_BASE__INST4_SEG2 0 >>> > +#define DFX_DAP_BASE__INST4_SEG3 0 >>> > +#define DFX_DAP_BASE__INST4_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST0_SEG0 0x00000580 >>> > +#define DFX_BASE__INST0_SEG1 0 >>> > +#define DFX_BASE__INST0_SEG2 0 >>> > +#define DFX_BASE__INST0_SEG3 0 >>> > +#define DFX_BASE__INST0_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST1_SEG0 0 >>> > +#define DFX_BASE__INST1_SEG1 0 >>> > +#define DFX_BASE__INST1_SEG2 0 >>> > +#define DFX_BASE__INST1_SEG3 0 >>> > +#define DFX_BASE__INST1_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST2_SEG0 0 >>> > +#define DFX_BASE__INST2_SEG1 0 >>> > +#define DFX_BASE__INST2_SEG2 0 >>> > +#define DFX_BASE__INST2_SEG3 0 >>> > +#define DFX_BASE__INST2_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST3_SEG0 0 >>> > +#define DFX_BASE__INST3_SEG1 0 >>> > +#define DFX_BASE__INST3_SEG2 0 >>> > +#define DFX_BASE__INST3_SEG3 0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* RE: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2017-11-27 21:24 ` Liu, Shaoyun 2017-11-27 21:28 ` Christian König 1 sibling, 0 replies; 14+ messages in thread From: Liu, Shaoyun @ 2017-11-27 21:24 UTC (permalink / raw) To: Alex Deucher, Koenig, Christian; +Cc: Kuehling, Felix, amd-gfx list Ok , that works for me , I can use the soc15ip.h for now . Regards Shaoyun.liu -----Original Message----- From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Alex Deucher Sent: Monday, November 27, 2017 3:56 PM To: Koenig, Christian Cc: Kuehling, Felix; amd-gfx list Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file On Mon, Nov 27, 2017 at 3:44 PM, Christian König <christian.koenig@amd.com> wrote: > Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >> >> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>> >>> And that is a clear NAK to this approach. >> >> Hi Christian, >> >> Do you have other objections than the style issues? If so, please explain. > > > No, the technical aspect actually looks rather reasonable. > >> Please clarify, why this file needs to be treated differently from >> other files under include/asic_reg? All those files are >> auto-generated by HW teams. Fixing the coding style adds no value and >> makes future updates more complicated. > > > We already got complains about that and most likely will need to fix > the rest as well. I'd like to stay as close as possible to the headers formats we are using internally across teams for consistency. Rather than rewriting these now, how about we just rename soc15ip.h to vg10ip.h and use that or even just drop patch 1 and use soc15ip.h as is for now. Alex > > Nicolai looked into using a different auto generator for the header > files, but not sure how far that already got along. > > The point is that the structures added with this won't be used by > soc15 alone, but rather be the base of the new register definition for > future hardware generations as well. > >> Like Shaoyun pointed out for example, the existing file >> include/asic_reg/vega10/soc15ip.h has the same style issues. > > > That file actually doesn't exists any more. Please see the work from > Feifei about that as well. > > Regards, > Christian. > >> >> Regards, >> Felix >> >>> Please start by fixing at least the obvious style problems before >>> resending. >>> >>> Thanks, >>> Christian. >>> >>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: >>> >>> I agree that this HW engineer generated file doesn't match the >>> coding style from linux software engineer point of view , but >>> since we already import other similar " HW engineer style" files >>> under include/asic_reg/vega10/, I don't see a reason to specially >>> change this file without touch else . This file is actually almost >>> identical as soc15ip.h . I think it's easier for us to import >>> other offset file in the future if we keep them un-touched . >>> >>> Regards >>> Shaoyun.liu >>> >>> >>> -----Original Message----- >>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] >>> Sent: Monday, November 27, 2017 2:17 PM >>> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org >>> Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define >>> file >>> >>> First of let us fix the obvious style problems. >>> >>> Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: >>> > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c >>> > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> >>> > --- >>> > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 >>> ++++++++++++++++++++ >>> > 1 file changed, 1248 insertions(+) >>> > create mode 100644 >>> drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > >>> > diff --git >>> a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > new file mode 100644 >>> > index 0000000..76cb748 >>> > --- /dev/null >>> > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>> > @@ -0,0 +1,1248 @@ >>> > +#ifndef _ip_offset_1_HEADER >>> > +#define _ip_offset_1_HEADER >>> Names for preprocessor defines should be capitable. >>> >>> > + >>> > +#define MAX_INSTANCE 5 >>> > +#define MAX_SEGMENT 5 >>> > + >>> > + >>> > +struct IP_BASE_INSTANCE >>> >>> Structure names should be lower case. And we need an amdgpu_ or at >>> least >>> amd_ prefix here. >>> >>> Regards, >>> Christian. >>> >>> > +{ >>> > + unsigned int segment[MAX_SEGMENT]; >>> > +}; >>> > + >>> > +struct IP_BASE >>> > +{ >>> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >>> > +}; >>> > + >>> > + >>> > +static const struct IP_BASE NBIF_BASE = >>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE NBIO_BASE = >>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DCE_BASE = { { { { >>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DCN_BASE = { { { { >>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP0_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP1_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MP2_BASE = { { { { >>> 0x00016000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE DF_BASE = { { { { >>> 0x00007000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE UVD_BASE = { { { { >>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>> segment >>> >>> No "//" in kernel code please. >>> >>> > +static const struct IP_BASE VCN_BASE = { { { { >>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>> segment >>> > +static const struct IP_BASE DBGU_BASE = >>> { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { >>> 0x000001C0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DBGU_IO_BASE = { { { { >>> 0x000001E0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DFX_DAP_BASE = { { { { >>> 0x000005A0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE DFX_BASE = { { { { >>> 0x00000580, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers >>> > +static const struct IP_BASE ISP_BASE = { { { { >>> 0x00018000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { >>> 0x00000EA0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>> > +static const struct IP_BASE L2IMU_BASE = >>> { { { { 0x00007DC0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE IOHC_BASE = >>> { { { { 0x00010000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE ATHUB_BASE = >>> { { { { 0x00000C20, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE VCE_BASE = { { { { >>> 0x00007E00, 0x00048800, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE GC_BASE = { { { { >>> 0x00002000, 0x0000A000, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE MMHUB_BASE = >>> { { { { 0x0001A000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE RSMU_BASE = >>> { { { { 0x00012000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE HDP_BASE = { { { { >>> 0x00000F20, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE OSSSYS_BASE = { { { { >>> 0x000010A0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SDMA0_BASE = >>> { { { { 0x00001260, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SDMA1_BASE = >>> { { { { 0x00001460, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE XDMA_BASE = >>> { { { { 0x00003400, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE UMC_BASE = { { { { >>> 0x00014000, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE THM_BASE = { { { { >>> 0x00016600, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE SMUIO_BASE = >>> { { { { 0x00016800, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE PWR_BASE = { { { { >>> 0x00016A00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE CLK_BASE = { { { { >>> 0x00016C00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0x00016E00, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0x00017000, 0, 0, 0, 0 } }, >>> > + { { 0x00017200, 0, 0, >>> 0, 0 } }, >>> > + { >>> { 0x00017E00, 0, 0, 0, 0 } } } }; >>> > +static const struct IP_BASE FUSE_BASE = >>> { { { { 0x00017400, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } }, >>> > >>> + >>> { { 0, 0, 0, 0, 0 } } } }; >>> > + >>> > + >>> > +#define NBIF_BASE__INST0_SEG0 0x00000000 >>> > +#define NBIF_BASE__INST0_SEG1 0x00000014 >>> > +#define NBIF_BASE__INST0_SEG2 0x00000D20 >>> > +#define NBIF_BASE__INST0_SEG3 0x00010400 >>> > +#define NBIF_BASE__INST0_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST1_SEG0 0 >>> > +#define NBIF_BASE__INST1_SEG1 0 >>> > +#define NBIF_BASE__INST1_SEG2 0 >>> > +#define NBIF_BASE__INST1_SEG3 0 >>> > +#define NBIF_BASE__INST1_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST2_SEG0 0 >>> > +#define NBIF_BASE__INST2_SEG1 0 >>> > +#define NBIF_BASE__INST2_SEG2 0 >>> > +#define NBIF_BASE__INST2_SEG3 0 >>> > +#define NBIF_BASE__INST2_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST3_SEG0 0 >>> > +#define NBIF_BASE__INST3_SEG1 0 >>> > +#define NBIF_BASE__INST3_SEG2 0 >>> > +#define NBIF_BASE__INST3_SEG3 0 >>> > +#define NBIF_BASE__INST3_SEG4 0 >>> > + >>> > +#define NBIF_BASE__INST4_SEG0 0 >>> > +#define NBIF_BASE__INST4_SEG1 0 >>> > +#define NBIF_BASE__INST4_SEG2 0 >>> > +#define NBIF_BASE__INST4_SEG3 0 >>> > +#define NBIF_BASE__INST4_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST0_SEG0 0x00000000 >>> > +#define NBIO_BASE__INST0_SEG1 0x00000014 >>> > +#define NBIO_BASE__INST0_SEG2 0x00000D20 >>> > +#define NBIO_BASE__INST0_SEG3 0x00010400 >>> > +#define NBIO_BASE__INST0_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST1_SEG0 0 >>> > +#define NBIO_BASE__INST1_SEG1 0 >>> > +#define NBIO_BASE__INST1_SEG2 0 >>> > +#define NBIO_BASE__INST1_SEG3 0 >>> > +#define NBIO_BASE__INST1_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST2_SEG0 0 >>> > +#define NBIO_BASE__INST2_SEG1 0 >>> > +#define NBIO_BASE__INST2_SEG2 0 >>> > +#define NBIO_BASE__INST2_SEG3 0 >>> > +#define NBIO_BASE__INST2_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST3_SEG0 0 >>> > +#define NBIO_BASE__INST3_SEG1 0 >>> > +#define NBIO_BASE__INST3_SEG2 0 >>> > +#define NBIO_BASE__INST3_SEG3 0 >>> > +#define NBIO_BASE__INST3_SEG4 0 >>> > + >>> > +#define NBIO_BASE__INST4_SEG0 0 >>> > +#define NBIO_BASE__INST4_SEG1 0 >>> > +#define NBIO_BASE__INST4_SEG2 0 >>> > +#define NBIO_BASE__INST4_SEG3 0 >>> > +#define NBIO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST0_SEG0 0x00000012 >>> > +#define DCE_BASE__INST0_SEG1 0x000000C0 >>> > +#define DCE_BASE__INST0_SEG2 0x000034C0 >>> > +#define DCE_BASE__INST0_SEG3 0 >>> > +#define DCE_BASE__INST0_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST1_SEG0 0 >>> > +#define DCE_BASE__INST1_SEG1 0 >>> > +#define DCE_BASE__INST1_SEG2 0 >>> > +#define DCE_BASE__INST1_SEG3 0 >>> > +#define DCE_BASE__INST1_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST2_SEG0 0 >>> > +#define DCE_BASE__INST2_SEG1 0 >>> > +#define DCE_BASE__INST2_SEG2 0 >>> > +#define DCE_BASE__INST2_SEG3 0 >>> > +#define DCE_BASE__INST2_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST3_SEG0 0 >>> > +#define DCE_BASE__INST3_SEG1 0 >>> > +#define DCE_BASE__INST3_SEG2 0 >>> > +#define DCE_BASE__INST3_SEG3 0 >>> > +#define DCE_BASE__INST3_SEG4 0 >>> > + >>> > +#define DCE_BASE__INST4_SEG0 0 >>> > +#define DCE_BASE__INST4_SEG1 0 >>> > +#define DCE_BASE__INST4_SEG2 0 >>> > +#define DCE_BASE__INST4_SEG3 0 >>> > +#define DCE_BASE__INST4_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST0_SEG0 0x00000012 >>> > +#define DCN_BASE__INST0_SEG1 0x000000C0 >>> > +#define DCN_BASE__INST0_SEG2 0x000034C0 >>> > +#define DCN_BASE__INST0_SEG3 0 >>> > +#define DCN_BASE__INST0_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST1_SEG0 0 >>> > +#define DCN_BASE__INST1_SEG1 0 >>> > +#define DCN_BASE__INST1_SEG2 0 >>> > +#define DCN_BASE__INST1_SEG3 0 >>> > +#define DCN_BASE__INST1_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST2_SEG0 0 >>> > +#define DCN_BASE__INST2_SEG1 0 >>> > +#define DCN_BASE__INST2_SEG2 0 >>> > +#define DCN_BASE__INST2_SEG3 0 >>> > +#define DCN_BASE__INST2_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST3_SEG0 0 >>> > +#define DCN_BASE__INST3_SEG1 0 >>> > +#define DCN_BASE__INST3_SEG2 0 >>> > +#define DCN_BASE__INST3_SEG3 0 >>> > +#define DCN_BASE__INST3_SEG4 0 >>> > + >>> > +#define DCN_BASE__INST4_SEG0 0 >>> > +#define DCN_BASE__INST4_SEG1 0 >>> > +#define DCN_BASE__INST4_SEG2 0 >>> > +#define DCN_BASE__INST4_SEG3 0 >>> > +#define DCN_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST0_SEG0 0x00016000 >>> > +#define MP0_BASE__INST0_SEG1 0 >>> > +#define MP0_BASE__INST0_SEG2 0 >>> > +#define MP0_BASE__INST0_SEG3 0 >>> > +#define MP0_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST1_SEG0 0 >>> > +#define MP0_BASE__INST1_SEG1 0 >>> > +#define MP0_BASE__INST1_SEG2 0 >>> > +#define MP0_BASE__INST1_SEG3 0 >>> > +#define MP0_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST2_SEG0 0 >>> > +#define MP0_BASE__INST2_SEG1 0 >>> > +#define MP0_BASE__INST2_SEG2 0 >>> > +#define MP0_BASE__INST2_SEG3 0 >>> > +#define MP0_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST3_SEG0 0 >>> > +#define MP0_BASE__INST3_SEG1 0 >>> > +#define MP0_BASE__INST3_SEG2 0 >>> > +#define MP0_BASE__INST3_SEG3 0 >>> > +#define MP0_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP0_BASE__INST4_SEG0 0 >>> > +#define MP0_BASE__INST4_SEG1 0 >>> > +#define MP0_BASE__INST4_SEG2 0 >>> > +#define MP0_BASE__INST4_SEG3 0 >>> > +#define MP0_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST0_SEG0 0x00016000 >>> > +#define MP1_BASE__INST0_SEG1 0 >>> > +#define MP1_BASE__INST0_SEG2 0 >>> > +#define MP1_BASE__INST0_SEG3 0 >>> > +#define MP1_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST1_SEG0 0 >>> > +#define MP1_BASE__INST1_SEG1 0 >>> > +#define MP1_BASE__INST1_SEG2 0 >>> > +#define MP1_BASE__INST1_SEG3 0 >>> > +#define MP1_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST2_SEG0 0 >>> > +#define MP1_BASE__INST2_SEG1 0 >>> > +#define MP1_BASE__INST2_SEG2 0 >>> > +#define MP1_BASE__INST2_SEG3 0 >>> > +#define MP1_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST3_SEG0 0 >>> > +#define MP1_BASE__INST3_SEG1 0 >>> > +#define MP1_BASE__INST3_SEG2 0 >>> > +#define MP1_BASE__INST3_SEG3 0 >>> > +#define MP1_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP1_BASE__INST4_SEG0 0 >>> > +#define MP1_BASE__INST4_SEG1 0 >>> > +#define MP1_BASE__INST4_SEG2 0 >>> > +#define MP1_BASE__INST4_SEG3 0 >>> > +#define MP1_BASE__INST4_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST0_SEG0 0x00016000 >>> > +#define MP2_BASE__INST0_SEG1 0 >>> > +#define MP2_BASE__INST0_SEG2 0 >>> > +#define MP2_BASE__INST0_SEG3 0 >>> > +#define MP2_BASE__INST0_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST1_SEG0 0 >>> > +#define MP2_BASE__INST1_SEG1 0 >>> > +#define MP2_BASE__INST1_SEG2 0 >>> > +#define MP2_BASE__INST1_SEG3 0 >>> > +#define MP2_BASE__INST1_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST2_SEG0 0 >>> > +#define MP2_BASE__INST2_SEG1 0 >>> > +#define MP2_BASE__INST2_SEG2 0 >>> > +#define MP2_BASE__INST2_SEG3 0 >>> > +#define MP2_BASE__INST2_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST3_SEG0 0 >>> > +#define MP2_BASE__INST3_SEG1 0 >>> > +#define MP2_BASE__INST3_SEG2 0 >>> > +#define MP2_BASE__INST3_SEG3 0 >>> > +#define MP2_BASE__INST3_SEG4 0 >>> > + >>> > +#define MP2_BASE__INST4_SEG0 0 >>> > +#define MP2_BASE__INST4_SEG1 0 >>> > +#define MP2_BASE__INST4_SEG2 0 >>> > +#define MP2_BASE__INST4_SEG3 0 >>> > +#define MP2_BASE__INST4_SEG4 0 >>> > + >>> > +#define DF_BASE__INST0_SEG0 0x00007000 >>> > +#define DF_BASE__INST0_SEG1 0 >>> > +#define DF_BASE__INST0_SEG2 0 >>> > +#define DF_BASE__INST0_SEG3 0 >>> > +#define DF_BASE__INST0_SEG4 0 >>> > + >>> > +#define DF_BASE__INST1_SEG0 0 >>> > +#define DF_BASE__INST1_SEG1 0 >>> > +#define DF_BASE__INST1_SEG2 0 >>> > +#define DF_BASE__INST1_SEG3 0 >>> > +#define DF_BASE__INST1_SEG4 0 >>> > + >>> > +#define DF_BASE__INST2_SEG0 0 >>> > +#define DF_BASE__INST2_SEG1 0 >>> > +#define DF_BASE__INST2_SEG2 0 >>> > +#define DF_BASE__INST2_SEG3 0 >>> > +#define DF_BASE__INST2_SEG4 0 >>> > + >>> > +#define DF_BASE__INST3_SEG0 0 >>> > +#define DF_BASE__INST3_SEG1 0 >>> > +#define DF_BASE__INST3_SEG2 0 >>> > +#define DF_BASE__INST3_SEG3 0 >>> > +#define DF_BASE__INST3_SEG4 0 >>> > + >>> > +#define DF_BASE__INST4_SEG0 0 >>> > +#define DF_BASE__INST4_SEG1 0 >>> > +#define DF_BASE__INST4_SEG2 0 >>> > +#define DF_BASE__INST4_SEG3 0 >>> > +#define DF_BASE__INST4_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST0_SEG0 0x00007800 >>> > +#define UVD_BASE__INST0_SEG1 0x00007E00 >>> > +#define UVD_BASE__INST0_SEG2 0 >>> > +#define UVD_BASE__INST0_SEG3 0 >>> > +#define UVD_BASE__INST0_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST1_SEG0 0 >>> > +#define UVD_BASE__INST1_SEG1 0 >>> > +#define UVD_BASE__INST1_SEG2 0 >>> > +#define UVD_BASE__INST1_SEG3 0 >>> > +#define UVD_BASE__INST1_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST2_SEG0 0 >>> > +#define UVD_BASE__INST2_SEG1 0 >>> > +#define UVD_BASE__INST2_SEG2 0 >>> > +#define UVD_BASE__INST2_SEG3 0 >>> > +#define UVD_BASE__INST2_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST3_SEG0 0 >>> > +#define UVD_BASE__INST3_SEG1 0 >>> > +#define UVD_BASE__INST3_SEG2 0 >>> > +#define UVD_BASE__INST3_SEG3 0 >>> > +#define UVD_BASE__INST3_SEG4 0 >>> > + >>> > +#define UVD_BASE__INST4_SEG0 0 >>> > +#define UVD_BASE__INST4_SEG1 0 >>> > +#define UVD_BASE__INST4_SEG2 0 >>> > +#define UVD_BASE__INST4_SEG3 0 >>> > +#define UVD_BASE__INST4_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST0_SEG0 0x00007800 >>> > +#define VCN_BASE__INST0_SEG1 0x00007E00 >>> > +#define VCN_BASE__INST0_SEG2 0 >>> > +#define VCN_BASE__INST0_SEG3 0 >>> > +#define VCN_BASE__INST0_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST1_SEG0 0 >>> > +#define VCN_BASE__INST1_SEG1 0 >>> > +#define VCN_BASE__INST1_SEG2 0 >>> > +#define VCN_BASE__INST1_SEG3 0 >>> > +#define VCN_BASE__INST1_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST2_SEG0 0 >>> > +#define VCN_BASE__INST2_SEG1 0 >>> > +#define VCN_BASE__INST2_SEG2 0 >>> > +#define VCN_BASE__INST2_SEG3 0 >>> > +#define VCN_BASE__INST2_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST3_SEG0 0 >>> > +#define VCN_BASE__INST3_SEG1 0 >>> > +#define VCN_BASE__INST3_SEG2 0 >>> > +#define VCN_BASE__INST3_SEG3 0 >>> > +#define VCN_BASE__INST3_SEG4 0 >>> > + >>> > +#define VCN_BASE__INST4_SEG0 0 >>> > +#define VCN_BASE__INST4_SEG1 0 >>> > +#define VCN_BASE__INST4_SEG2 0 >>> > +#define VCN_BASE__INST4_SEG3 0 >>> > +#define VCN_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST0_SEG0 0x00000180 >>> > +#define DBGU_BASE__INST0_SEG1 0x000001A0 >>> > +#define DBGU_BASE__INST0_SEG2 0 >>> > +#define DBGU_BASE__INST0_SEG3 0 >>> > +#define DBGU_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST1_SEG0 0 >>> > +#define DBGU_BASE__INST1_SEG1 0 >>> > +#define DBGU_BASE__INST1_SEG2 0 >>> > +#define DBGU_BASE__INST1_SEG3 0 >>> > +#define DBGU_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST2_SEG0 0 >>> > +#define DBGU_BASE__INST2_SEG1 0 >>> > +#define DBGU_BASE__INST2_SEG2 0 >>> > +#define DBGU_BASE__INST2_SEG3 0 >>> > +#define DBGU_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST3_SEG0 0 >>> > +#define DBGU_BASE__INST3_SEG1 0 >>> > +#define DBGU_BASE__INST3_SEG2 0 >>> > +#define DBGU_BASE__INST3_SEG3 0 >>> > +#define DBGU_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_BASE__INST4_SEG0 0 >>> > +#define DBGU_BASE__INST4_SEG1 0 >>> > +#define DBGU_BASE__INST4_SEG2 0 >>> > +#define DBGU_BASE__INST4_SEG3 0 >>> > +#define DBGU_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST1_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST2_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST3_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_NBIO_BASE__INST4_SEG0 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG1 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG2 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG3 0 >>> > +#define DBGU_NBIO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >>> > +#define DBGU_IO_BASE__INST0_SEG1 0 >>> > +#define DBGU_IO_BASE__INST0_SEG2 0 >>> > +#define DBGU_IO_BASE__INST0_SEG3 0 >>> > +#define DBGU_IO_BASE__INST0_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST1_SEG0 0 >>> > +#define DBGU_IO_BASE__INST1_SEG1 0 >>> > +#define DBGU_IO_BASE__INST1_SEG2 0 >>> > +#define DBGU_IO_BASE__INST1_SEG3 0 >>> > +#define DBGU_IO_BASE__INST1_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST2_SEG0 0 >>> > +#define DBGU_IO_BASE__INST2_SEG1 0 >>> > +#define DBGU_IO_BASE__INST2_SEG2 0 >>> > +#define DBGU_IO_BASE__INST2_SEG3 0 >>> > +#define DBGU_IO_BASE__INST2_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST3_SEG0 0 >>> > +#define DBGU_IO_BASE__INST3_SEG1 0 >>> > +#define DBGU_IO_BASE__INST3_SEG2 0 >>> > +#define DBGU_IO_BASE__INST3_SEG3 0 >>> > +#define DBGU_IO_BASE__INST3_SEG4 0 >>> > + >>> > +#define DBGU_IO_BASE__INST4_SEG0 0 >>> > +#define DBGU_IO_BASE__INST4_SEG1 0 >>> > +#define DBGU_IO_BASE__INST4_SEG2 0 >>> > +#define DBGU_IO_BASE__INST4_SEG3 0 >>> > +#define DBGU_IO_BASE__INST4_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 >>> > +#define DFX_DAP_BASE__INST0_SEG1 0 >>> > +#define DFX_DAP_BASE__INST0_SEG2 0 >>> > +#define DFX_DAP_BASE__INST0_SEG3 0 >>> > +#define DFX_DAP_BASE__INST0_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST1_SEG0 0 >>> > +#define DFX_DAP_BASE__INST1_SEG1 0 >>> > +#define DFX_DAP_BASE__INST1_SEG2 0 >>> > +#define DFX_DAP_BASE__INST1_SEG3 0 >>> > +#define DFX_DAP_BASE__INST1_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST2_SEG0 0 >>> > +#define DFX_DAP_BASE__INST2_SEG1 0 >>> > +#define DFX_DAP_BASE__INST2_SEG2 0 >>> > +#define DFX_DAP_BASE__INST2_SEG3 0 >>> > +#define DFX_DAP_BASE__INST2_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST3_SEG0 0 >>> > +#define DFX_DAP_BASE__INST3_SEG1 0 >>> > +#define DFX_DAP_BASE__INST3_SEG2 0 >>> > +#define DFX_DAP_BASE__INST3_SEG3 0 >>> > +#define DFX_DAP_BASE__INST3_SEG4 0 >>> > + >>> > +#define DFX_DAP_BASE__INST4_SEG0 0 >>> > +#define DFX_DAP_BASE__INST4_SEG1 0 >>> > +#define DFX_DAP_BASE__INST4_SEG2 0 >>> > +#define DFX_DAP_BASE__INST4_SEG3 0 >>> > +#define DFX_DAP_BASE__INST4_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST0_SEG0 0x00000580 >>> > +#define DFX_BASE__INST0_SEG1 0 >>> > +#define DFX_BASE__INST0_SEG2 0 >>> > +#define DFX_BASE__INST0_SEG3 0 >>> > +#define DFX_BASE__INST0_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST1_SEG0 0 >>> > +#define DFX_BASE__INST1_SEG1 0 >>> > +#define DFX_BASE__INST1_SEG2 0 >>> > +#define DFX_BASE__INST1_SEG3 0 >>> > +#define DFX_BASE__INST1_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST2_SEG0 0 >>> > +#define DFX_BASE__INST2_SEG1 0 >>> > +#define DFX_BASE__INST2_SEG2 0 >>> > +#define DFX_BASE__INST2_SEG3 0 >>> > +#define DFX_BASE__INST2_SEG4 0 >>> > + >>> > +#define DFX_BASE__INST3_SEG0 0 >>> > +#define DFX_BASE__INST3_SEG1 0 >>> > +#define DFX_BASE__INST3_SEG2 0 >>> > +#define DFX_BASE__INST3_SEG3 0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2017-11-27 21:24 ` Liu, Shaoyun @ 2017-11-27 21:28 ` Christian König [not found] ` <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org> 1 sibling, 1 reply; 14+ messages in thread From: Christian König @ 2017-11-27 21:28 UTC (permalink / raw) To: Alex Deucher; +Cc: Felix Kuehling, amd-gfx list Am 27.11.2017 um 21:56 schrieb Alex Deucher: > On Mon, Nov 27, 2017 at 3:44 PM, Christian König > <christian.koenig@amd.com> wrote: >> Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >>> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>>> And that is a clear NAK to this approach. >>> Hi Christian, >>> >>> Do you have other objections than the style issues? If so, please explain. >> >> No, the technical aspect actually looks rather reasonable. >> >>> Please clarify, why this file needs to be treated differently from other >>> files under include/asic_reg? All those files are auto-generated by HW >>> teams. Fixing the coding style adds no value and makes future updates >>> more complicated. >> >> We already got complains about that and most likely will need to fix the >> rest as well. > I'd like to stay as close as possible to the headers formats we are > using internally across teams for consistency. To be honest I strongly disagree on that. The bad quality of the internal AMD headers is the reason we had to basically have the VMHUB code for Vega10 twice for example. We should either massively push back on that (already done and with the next hardware generation a bunch of things will be fixed, but unfortunately not for Vega10 any more). Or we start to cleanup and/or generate the headers ourself. Or at least do the manual cleanup for Vega10 and hope that the next chunk will be better. > Rather than rewriting these now, how about we just rename soc15ip.h to vg10ip.h and use that That sounds like a good idea to me, but the structure defines still need to be asic independent and applicable for all hardware generations, not just Vega10. Otherwise we will need to create translation functions for each ASIC generation to our internal format which is neither clean nor looks very good. Christian. > or even just drop patch 1 and use soc15ip.h as is for now. > > Alex > >> Nicolai looked into using a different auto generator for the header files, >> but not sure how far that already got along. >> >> The point is that the structures added with this won't be used by soc15 >> alone, but rather be the base of the new register definition for future >> hardware generations as well. >> >>> Like Shaoyun pointed out for example, the existing file >>> include/asic_reg/vega10/soc15ip.h has the same style issues. >> >> That file actually doesn't exists any more. Please see the work from Feifei >> about that as well. >> >> Regards, >> Christian. >> >>> Regards, >>> Felix >>> >>>> Please start by fixing at least the obvious style problems before >>>> resending. >>>> >>>> Thanks, >>>> Christian. >>>> >>>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: >>>> >>>> I agree that this HW engineer generated file doesn't match the >>>> coding style from linux software engineer point of view , but >>>> since we already import other similar " HW engineer style" files >>>> under include/asic_reg/vega10/, I don't see a reason to specially >>>> change this file without touch else . This file is actually almost >>>> identical as soc15ip.h . I think it's easier for us to import >>>> other offset file in the future if we keep them un-touched . >>>> >>>> Regards >>>> Shaoyun.liu >>>> >>>> >>>> -----Original Message----- >>>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] >>>> Sent: Monday, November 27, 2017 2:17 PM >>>> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org >>>> Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file >>>> >>>> First of let us fix the obvious style problems. >>>> >>>> Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: >>>> > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c >>>> > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> >>>> > --- >>>> > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 >>>> ++++++++++++++++++++ >>>> > 1 file changed, 1248 insertions(+) >>>> > create mode 100644 >>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>> > >>>> > diff --git >>>> a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>> b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>> > new file mode 100644 >>>> > index 0000000..76cb748 >>>> > --- /dev/null >>>> > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>> > @@ -0,0 +1,1248 @@ >>>> > +#ifndef _ip_offset_1_HEADER >>>> > +#define _ip_offset_1_HEADER >>>> Names for preprocessor defines should be capitable. >>>> >>>> > + >>>> > +#define MAX_INSTANCE 5 >>>> > +#define MAX_SEGMENT 5 >>>> > + >>>> > + >>>> > +struct IP_BASE_INSTANCE >>>> >>>> Structure names should be lower case. And we need an amdgpu_ or at >>>> least >>>> amd_ prefix here. >>>> >>>> Regards, >>>> Christian. >>>> >>>> > +{ >>>> > + unsigned int segment[MAX_SEGMENT]; >>>> > +}; >>>> > + >>>> > +struct IP_BASE >>>> > +{ >>>> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >>>> > +}; >>>> > + >>>> > + >>>> > +static const struct IP_BASE NBIF_BASE = >>>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE NBIO_BASE = >>>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE DCE_BASE = { { { { >>>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE DCN_BASE = { { { { >>>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE MP0_BASE = { { { { >>>> 0x00016000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE MP1_BASE = { { { { >>>> 0x00016000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE MP2_BASE = { { { { >>>> 0x00016000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE DF_BASE = { { { { >>>> 0x00007000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE UVD_BASE = { { { { >>>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>>> segment >>>> >>>> No "//" in kernel code please. >>>> >>>> > +static const struct IP_BASE VCN_BASE = { { { { >>>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>>> segment >>>> > +static const struct IP_BASE DBGU_BASE = >>>> { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { >>>> 0x000001C0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE DBGU_IO_BASE = { { { { >>>> 0x000001E0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE DFX_DAP_BASE = { { { { >>>> 0x000005A0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE DFX_BASE = { { { { >>>> 0x00000580, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers >>>> > +static const struct IP_BASE ISP_BASE = { { { { >>>> 0x00018000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { >>>> 0x00000EA0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>> > +static const struct IP_BASE L2IMU_BASE = >>>> { { { { 0x00007DC0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE IOHC_BASE = >>>> { { { { 0x00010000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE ATHUB_BASE = >>>> { { { { 0x00000C20, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE VCE_BASE = { { { { >>>> 0x00007E00, 0x00048800, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE GC_BASE = { { { { >>>> 0x00002000, 0x0000A000, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE MMHUB_BASE = >>>> { { { { 0x0001A000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE RSMU_BASE = >>>> { { { { 0x00012000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE HDP_BASE = { { { { >>>> 0x00000F20, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE OSSSYS_BASE = { { { { >>>> 0x000010A0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE SDMA0_BASE = >>>> { { { { 0x00001260, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE SDMA1_BASE = >>>> { { { { 0x00001460, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE XDMA_BASE = >>>> { { { { 0x00003400, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE UMC_BASE = { { { { >>>> 0x00014000, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE THM_BASE = { { { { >>>> 0x00016600, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE SMUIO_BASE = >>>> { { { { 0x00016800, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE PWR_BASE = { { { { >>>> 0x00016A00, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE CLK_BASE = { { { { >>>> 0x00016C00, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0x00016E00, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0x00017000, 0, 0, 0, 0 } }, >>>> > + { { 0x00017200, 0, 0, >>>> 0, 0 } }, >>>> > + { >>>> { 0x00017E00, 0, 0, 0, 0 } } } }; >>>> > +static const struct IP_BASE FUSE_BASE = >>>> { { { { 0x00017400, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } }, >>>> > >>>> + >>>> { { 0, 0, 0, 0, 0 } } } }; >>>> > + >>>> > + >>>> > +#define NBIF_BASE__INST0_SEG0 0x00000000 >>>> > +#define NBIF_BASE__INST0_SEG1 0x00000014 >>>> > +#define NBIF_BASE__INST0_SEG2 0x00000D20 >>>> > +#define NBIF_BASE__INST0_SEG3 0x00010400 >>>> > +#define NBIF_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define NBIF_BASE__INST1_SEG0 0 >>>> > +#define NBIF_BASE__INST1_SEG1 0 >>>> > +#define NBIF_BASE__INST1_SEG2 0 >>>> > +#define NBIF_BASE__INST1_SEG3 0 >>>> > +#define NBIF_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define NBIF_BASE__INST2_SEG0 0 >>>> > +#define NBIF_BASE__INST2_SEG1 0 >>>> > +#define NBIF_BASE__INST2_SEG2 0 >>>> > +#define NBIF_BASE__INST2_SEG3 0 >>>> > +#define NBIF_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define NBIF_BASE__INST3_SEG0 0 >>>> > +#define NBIF_BASE__INST3_SEG1 0 >>>> > +#define NBIF_BASE__INST3_SEG2 0 >>>> > +#define NBIF_BASE__INST3_SEG3 0 >>>> > +#define NBIF_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define NBIF_BASE__INST4_SEG0 0 >>>> > +#define NBIF_BASE__INST4_SEG1 0 >>>> > +#define NBIF_BASE__INST4_SEG2 0 >>>> > +#define NBIF_BASE__INST4_SEG3 0 >>>> > +#define NBIF_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define NBIO_BASE__INST0_SEG0 0x00000000 >>>> > +#define NBIO_BASE__INST0_SEG1 0x00000014 >>>> > +#define NBIO_BASE__INST0_SEG2 0x00000D20 >>>> > +#define NBIO_BASE__INST0_SEG3 0x00010400 >>>> > +#define NBIO_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define NBIO_BASE__INST1_SEG0 0 >>>> > +#define NBIO_BASE__INST1_SEG1 0 >>>> > +#define NBIO_BASE__INST1_SEG2 0 >>>> > +#define NBIO_BASE__INST1_SEG3 0 >>>> > +#define NBIO_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define NBIO_BASE__INST2_SEG0 0 >>>> > +#define NBIO_BASE__INST2_SEG1 0 >>>> > +#define NBIO_BASE__INST2_SEG2 0 >>>> > +#define NBIO_BASE__INST2_SEG3 0 >>>> > +#define NBIO_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define NBIO_BASE__INST3_SEG0 0 >>>> > +#define NBIO_BASE__INST3_SEG1 0 >>>> > +#define NBIO_BASE__INST3_SEG2 0 >>>> > +#define NBIO_BASE__INST3_SEG3 0 >>>> > +#define NBIO_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define NBIO_BASE__INST4_SEG0 0 >>>> > +#define NBIO_BASE__INST4_SEG1 0 >>>> > +#define NBIO_BASE__INST4_SEG2 0 >>>> > +#define NBIO_BASE__INST4_SEG3 0 >>>> > +#define NBIO_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DCE_BASE__INST0_SEG0 0x00000012 >>>> > +#define DCE_BASE__INST0_SEG1 0x000000C0 >>>> > +#define DCE_BASE__INST0_SEG2 0x000034C0 >>>> > +#define DCE_BASE__INST0_SEG3 0 >>>> > +#define DCE_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DCE_BASE__INST1_SEG0 0 >>>> > +#define DCE_BASE__INST1_SEG1 0 >>>> > +#define DCE_BASE__INST1_SEG2 0 >>>> > +#define DCE_BASE__INST1_SEG3 0 >>>> > +#define DCE_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DCE_BASE__INST2_SEG0 0 >>>> > +#define DCE_BASE__INST2_SEG1 0 >>>> > +#define DCE_BASE__INST2_SEG2 0 >>>> > +#define DCE_BASE__INST2_SEG3 0 >>>> > +#define DCE_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DCE_BASE__INST3_SEG0 0 >>>> > +#define DCE_BASE__INST3_SEG1 0 >>>> > +#define DCE_BASE__INST3_SEG2 0 >>>> > +#define DCE_BASE__INST3_SEG3 0 >>>> > +#define DCE_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DCE_BASE__INST4_SEG0 0 >>>> > +#define DCE_BASE__INST4_SEG1 0 >>>> > +#define DCE_BASE__INST4_SEG2 0 >>>> > +#define DCE_BASE__INST4_SEG3 0 >>>> > +#define DCE_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DCN_BASE__INST0_SEG0 0x00000012 >>>> > +#define DCN_BASE__INST0_SEG1 0x000000C0 >>>> > +#define DCN_BASE__INST0_SEG2 0x000034C0 >>>> > +#define DCN_BASE__INST0_SEG3 0 >>>> > +#define DCN_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DCN_BASE__INST1_SEG0 0 >>>> > +#define DCN_BASE__INST1_SEG1 0 >>>> > +#define DCN_BASE__INST1_SEG2 0 >>>> > +#define DCN_BASE__INST1_SEG3 0 >>>> > +#define DCN_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DCN_BASE__INST2_SEG0 0 >>>> > +#define DCN_BASE__INST2_SEG1 0 >>>> > +#define DCN_BASE__INST2_SEG2 0 >>>> > +#define DCN_BASE__INST2_SEG3 0 >>>> > +#define DCN_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DCN_BASE__INST3_SEG0 0 >>>> > +#define DCN_BASE__INST3_SEG1 0 >>>> > +#define DCN_BASE__INST3_SEG2 0 >>>> > +#define DCN_BASE__INST3_SEG3 0 >>>> > +#define DCN_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DCN_BASE__INST4_SEG0 0 >>>> > +#define DCN_BASE__INST4_SEG1 0 >>>> > +#define DCN_BASE__INST4_SEG2 0 >>>> > +#define DCN_BASE__INST4_SEG3 0 >>>> > +#define DCN_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define MP0_BASE__INST0_SEG0 0x00016000 >>>> > +#define MP0_BASE__INST0_SEG1 0 >>>> > +#define MP0_BASE__INST0_SEG2 0 >>>> > +#define MP0_BASE__INST0_SEG3 0 >>>> > +#define MP0_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define MP0_BASE__INST1_SEG0 0 >>>> > +#define MP0_BASE__INST1_SEG1 0 >>>> > +#define MP0_BASE__INST1_SEG2 0 >>>> > +#define MP0_BASE__INST1_SEG3 0 >>>> > +#define MP0_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define MP0_BASE__INST2_SEG0 0 >>>> > +#define MP0_BASE__INST2_SEG1 0 >>>> > +#define MP0_BASE__INST2_SEG2 0 >>>> > +#define MP0_BASE__INST2_SEG3 0 >>>> > +#define MP0_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define MP0_BASE__INST3_SEG0 0 >>>> > +#define MP0_BASE__INST3_SEG1 0 >>>> > +#define MP0_BASE__INST3_SEG2 0 >>>> > +#define MP0_BASE__INST3_SEG3 0 >>>> > +#define MP0_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define MP0_BASE__INST4_SEG0 0 >>>> > +#define MP0_BASE__INST4_SEG1 0 >>>> > +#define MP0_BASE__INST4_SEG2 0 >>>> > +#define MP0_BASE__INST4_SEG3 0 >>>> > +#define MP0_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define MP1_BASE__INST0_SEG0 0x00016000 >>>> > +#define MP1_BASE__INST0_SEG1 0 >>>> > +#define MP1_BASE__INST0_SEG2 0 >>>> > +#define MP1_BASE__INST0_SEG3 0 >>>> > +#define MP1_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define MP1_BASE__INST1_SEG0 0 >>>> > +#define MP1_BASE__INST1_SEG1 0 >>>> > +#define MP1_BASE__INST1_SEG2 0 >>>> > +#define MP1_BASE__INST1_SEG3 0 >>>> > +#define MP1_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define MP1_BASE__INST2_SEG0 0 >>>> > +#define MP1_BASE__INST2_SEG1 0 >>>> > +#define MP1_BASE__INST2_SEG2 0 >>>> > +#define MP1_BASE__INST2_SEG3 0 >>>> > +#define MP1_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define MP1_BASE__INST3_SEG0 0 >>>> > +#define MP1_BASE__INST3_SEG1 0 >>>> > +#define MP1_BASE__INST3_SEG2 0 >>>> > +#define MP1_BASE__INST3_SEG3 0 >>>> > +#define MP1_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define MP1_BASE__INST4_SEG0 0 >>>> > +#define MP1_BASE__INST4_SEG1 0 >>>> > +#define MP1_BASE__INST4_SEG2 0 >>>> > +#define MP1_BASE__INST4_SEG3 0 >>>> > +#define MP1_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define MP2_BASE__INST0_SEG0 0x00016000 >>>> > +#define MP2_BASE__INST0_SEG1 0 >>>> > +#define MP2_BASE__INST0_SEG2 0 >>>> > +#define MP2_BASE__INST0_SEG3 0 >>>> > +#define MP2_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define MP2_BASE__INST1_SEG0 0 >>>> > +#define MP2_BASE__INST1_SEG1 0 >>>> > +#define MP2_BASE__INST1_SEG2 0 >>>> > +#define MP2_BASE__INST1_SEG3 0 >>>> > +#define MP2_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define MP2_BASE__INST2_SEG0 0 >>>> > +#define MP2_BASE__INST2_SEG1 0 >>>> > +#define MP2_BASE__INST2_SEG2 0 >>>> > +#define MP2_BASE__INST2_SEG3 0 >>>> > +#define MP2_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define MP2_BASE__INST3_SEG0 0 >>>> > +#define MP2_BASE__INST3_SEG1 0 >>>> > +#define MP2_BASE__INST3_SEG2 0 >>>> > +#define MP2_BASE__INST3_SEG3 0 >>>> > +#define MP2_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define MP2_BASE__INST4_SEG0 0 >>>> > +#define MP2_BASE__INST4_SEG1 0 >>>> > +#define MP2_BASE__INST4_SEG2 0 >>>> > +#define MP2_BASE__INST4_SEG3 0 >>>> > +#define MP2_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DF_BASE__INST0_SEG0 0x00007000 >>>> > +#define DF_BASE__INST0_SEG1 0 >>>> > +#define DF_BASE__INST0_SEG2 0 >>>> > +#define DF_BASE__INST0_SEG3 0 >>>> > +#define DF_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DF_BASE__INST1_SEG0 0 >>>> > +#define DF_BASE__INST1_SEG1 0 >>>> > +#define DF_BASE__INST1_SEG2 0 >>>> > +#define DF_BASE__INST1_SEG3 0 >>>> > +#define DF_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DF_BASE__INST2_SEG0 0 >>>> > +#define DF_BASE__INST2_SEG1 0 >>>> > +#define DF_BASE__INST2_SEG2 0 >>>> > +#define DF_BASE__INST2_SEG3 0 >>>> > +#define DF_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DF_BASE__INST3_SEG0 0 >>>> > +#define DF_BASE__INST3_SEG1 0 >>>> > +#define DF_BASE__INST3_SEG2 0 >>>> > +#define DF_BASE__INST3_SEG3 0 >>>> > +#define DF_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DF_BASE__INST4_SEG0 0 >>>> > +#define DF_BASE__INST4_SEG1 0 >>>> > +#define DF_BASE__INST4_SEG2 0 >>>> > +#define DF_BASE__INST4_SEG3 0 >>>> > +#define DF_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define UVD_BASE__INST0_SEG0 0x00007800 >>>> > +#define UVD_BASE__INST0_SEG1 0x00007E00 >>>> > +#define UVD_BASE__INST0_SEG2 0 >>>> > +#define UVD_BASE__INST0_SEG3 0 >>>> > +#define UVD_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define UVD_BASE__INST1_SEG0 0 >>>> > +#define UVD_BASE__INST1_SEG1 0 >>>> > +#define UVD_BASE__INST1_SEG2 0 >>>> > +#define UVD_BASE__INST1_SEG3 0 >>>> > +#define UVD_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define UVD_BASE__INST2_SEG0 0 >>>> > +#define UVD_BASE__INST2_SEG1 0 >>>> > +#define UVD_BASE__INST2_SEG2 0 >>>> > +#define UVD_BASE__INST2_SEG3 0 >>>> > +#define UVD_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define UVD_BASE__INST3_SEG0 0 >>>> > +#define UVD_BASE__INST3_SEG1 0 >>>> > +#define UVD_BASE__INST3_SEG2 0 >>>> > +#define UVD_BASE__INST3_SEG3 0 >>>> > +#define UVD_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define UVD_BASE__INST4_SEG0 0 >>>> > +#define UVD_BASE__INST4_SEG1 0 >>>> > +#define UVD_BASE__INST4_SEG2 0 >>>> > +#define UVD_BASE__INST4_SEG3 0 >>>> > +#define UVD_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define VCN_BASE__INST0_SEG0 0x00007800 >>>> > +#define VCN_BASE__INST0_SEG1 0x00007E00 >>>> > +#define VCN_BASE__INST0_SEG2 0 >>>> > +#define VCN_BASE__INST0_SEG3 0 >>>> > +#define VCN_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define VCN_BASE__INST1_SEG0 0 >>>> > +#define VCN_BASE__INST1_SEG1 0 >>>> > +#define VCN_BASE__INST1_SEG2 0 >>>> > +#define VCN_BASE__INST1_SEG3 0 >>>> > +#define VCN_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define VCN_BASE__INST2_SEG0 0 >>>> > +#define VCN_BASE__INST2_SEG1 0 >>>> > +#define VCN_BASE__INST2_SEG2 0 >>>> > +#define VCN_BASE__INST2_SEG3 0 >>>> > +#define VCN_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define VCN_BASE__INST3_SEG0 0 >>>> > +#define VCN_BASE__INST3_SEG1 0 >>>> > +#define VCN_BASE__INST3_SEG2 0 >>>> > +#define VCN_BASE__INST3_SEG3 0 >>>> > +#define VCN_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define VCN_BASE__INST4_SEG0 0 >>>> > +#define VCN_BASE__INST4_SEG1 0 >>>> > +#define VCN_BASE__INST4_SEG2 0 >>>> > +#define VCN_BASE__INST4_SEG3 0 >>>> > +#define VCN_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DBGU_BASE__INST0_SEG0 0x00000180 >>>> > +#define DBGU_BASE__INST0_SEG1 0x000001A0 >>>> > +#define DBGU_BASE__INST0_SEG2 0 >>>> > +#define DBGU_BASE__INST0_SEG3 0 >>>> > +#define DBGU_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DBGU_BASE__INST1_SEG0 0 >>>> > +#define DBGU_BASE__INST1_SEG1 0 >>>> > +#define DBGU_BASE__INST1_SEG2 0 >>>> > +#define DBGU_BASE__INST1_SEG3 0 >>>> > +#define DBGU_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DBGU_BASE__INST2_SEG0 0 >>>> > +#define DBGU_BASE__INST2_SEG1 0 >>>> > +#define DBGU_BASE__INST2_SEG2 0 >>>> > +#define DBGU_BASE__INST2_SEG3 0 >>>> > +#define DBGU_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DBGU_BASE__INST3_SEG0 0 >>>> > +#define DBGU_BASE__INST3_SEG1 0 >>>> > +#define DBGU_BASE__INST3_SEG2 0 >>>> > +#define DBGU_BASE__INST3_SEG3 0 >>>> > +#define DBGU_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DBGU_BASE__INST4_SEG0 0 >>>> > +#define DBGU_BASE__INST4_SEG1 0 >>>> > +#define DBGU_BASE__INST4_SEG2 0 >>>> > +#define DBGU_BASE__INST4_SEG3 0 >>>> > +#define DBGU_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 >>>> > +#define DBGU_NBIO_BASE__INST0_SEG1 0 >>>> > +#define DBGU_NBIO_BASE__INST0_SEG2 0 >>>> > +#define DBGU_NBIO_BASE__INST0_SEG3 0 >>>> > +#define DBGU_NBIO_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DBGU_NBIO_BASE__INST1_SEG0 0 >>>> > +#define DBGU_NBIO_BASE__INST1_SEG1 0 >>>> > +#define DBGU_NBIO_BASE__INST1_SEG2 0 >>>> > +#define DBGU_NBIO_BASE__INST1_SEG3 0 >>>> > +#define DBGU_NBIO_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DBGU_NBIO_BASE__INST2_SEG0 0 >>>> > +#define DBGU_NBIO_BASE__INST2_SEG1 0 >>>> > +#define DBGU_NBIO_BASE__INST2_SEG2 0 >>>> > +#define DBGU_NBIO_BASE__INST2_SEG3 0 >>>> > +#define DBGU_NBIO_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DBGU_NBIO_BASE__INST3_SEG0 0 >>>> > +#define DBGU_NBIO_BASE__INST3_SEG1 0 >>>> > +#define DBGU_NBIO_BASE__INST3_SEG2 0 >>>> > +#define DBGU_NBIO_BASE__INST3_SEG3 0 >>>> > +#define DBGU_NBIO_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DBGU_NBIO_BASE__INST4_SEG0 0 >>>> > +#define DBGU_NBIO_BASE__INST4_SEG1 0 >>>> > +#define DBGU_NBIO_BASE__INST4_SEG2 0 >>>> > +#define DBGU_NBIO_BASE__INST4_SEG3 0 >>>> > +#define DBGU_NBIO_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >>>> > +#define DBGU_IO_BASE__INST0_SEG1 0 >>>> > +#define DBGU_IO_BASE__INST0_SEG2 0 >>>> > +#define DBGU_IO_BASE__INST0_SEG3 0 >>>> > +#define DBGU_IO_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DBGU_IO_BASE__INST1_SEG0 0 >>>> > +#define DBGU_IO_BASE__INST1_SEG1 0 >>>> > +#define DBGU_IO_BASE__INST1_SEG2 0 >>>> > +#define DBGU_IO_BASE__INST1_SEG3 0 >>>> > +#define DBGU_IO_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DBGU_IO_BASE__INST2_SEG0 0 >>>> > +#define DBGU_IO_BASE__INST2_SEG1 0 >>>> > +#define DBGU_IO_BASE__INST2_SEG2 0 >>>> > +#define DBGU_IO_BASE__INST2_SEG3 0 >>>> > +#define DBGU_IO_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DBGU_IO_BASE__INST3_SEG0 0 >>>> > +#define DBGU_IO_BASE__INST3_SEG1 0 >>>> > +#define DBGU_IO_BASE__INST3_SEG2 0 >>>> > +#define DBGU_IO_BASE__INST3_SEG3 0 >>>> > +#define DBGU_IO_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DBGU_IO_BASE__INST4_SEG0 0 >>>> > +#define DBGU_IO_BASE__INST4_SEG1 0 >>>> > +#define DBGU_IO_BASE__INST4_SEG2 0 >>>> > +#define DBGU_IO_BASE__INST4_SEG3 0 >>>> > +#define DBGU_IO_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 >>>> > +#define DFX_DAP_BASE__INST0_SEG1 0 >>>> > +#define DFX_DAP_BASE__INST0_SEG2 0 >>>> > +#define DFX_DAP_BASE__INST0_SEG3 0 >>>> > +#define DFX_DAP_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DFX_DAP_BASE__INST1_SEG0 0 >>>> > +#define DFX_DAP_BASE__INST1_SEG1 0 >>>> > +#define DFX_DAP_BASE__INST1_SEG2 0 >>>> > +#define DFX_DAP_BASE__INST1_SEG3 0 >>>> > +#define DFX_DAP_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DFX_DAP_BASE__INST2_SEG0 0 >>>> > +#define DFX_DAP_BASE__INST2_SEG1 0 >>>> > +#define DFX_DAP_BASE__INST2_SEG2 0 >>>> > +#define DFX_DAP_BASE__INST2_SEG3 0 >>>> > +#define DFX_DAP_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DFX_DAP_BASE__INST3_SEG0 0 >>>> > +#define DFX_DAP_BASE__INST3_SEG1 0 >>>> > +#define DFX_DAP_BASE__INST3_SEG2 0 >>>> > +#define DFX_DAP_BASE__INST3_SEG3 0 >>>> > +#define DFX_DAP_BASE__INST3_SEG4 0 >>>> > + >>>> > +#define DFX_DAP_BASE__INST4_SEG0 0 >>>> > +#define DFX_DAP_BASE__INST4_SEG1 0 >>>> > +#define DFX_DAP_BASE__INST4_SEG2 0 >>>> > +#define DFX_DAP_BASE__INST4_SEG3 0 >>>> > +#define DFX_DAP_BASE__INST4_SEG4 0 >>>> > + >>>> > +#define DFX_BASE__INST0_SEG0 0x00000580 >>>> > +#define DFX_BASE__INST0_SEG1 0 >>>> > +#define DFX_BASE__INST0_SEG2 0 >>>> > +#define DFX_BASE__INST0_SEG3 0 >>>> > +#define DFX_BASE__INST0_SEG4 0 >>>> > + >>>> > +#define DFX_BASE__INST1_SEG0 0 >>>> > +#define DFX_BASE__INST1_SEG1 0 >>>> > +#define DFX_BASE__INST1_SEG2 0 >>>> > +#define DFX_BASE__INST1_SEG3 0 >>>> > +#define DFX_BASE__INST1_SEG4 0 >>>> > + >>>> > +#define DFX_BASE__INST2_SEG0 0 >>>> > +#define DFX_BASE__INST2_SEG1 0 >>>> > +#define DFX_BASE__INST2_SEG2 0 >>>> > +#define DFX_BASE__INST2_SEG3 0 >>>> > +#define DFX_BASE__INST2_SEG4 0 >>>> > + >>>> > +#define DFX_BASE__INST3_SEG0 0 >>>> > +#define DFX_BASE__INST3_SEG1 0 >>>> > +#define DFX_BASE__INST3_SEG2 0 >>>> > +#define DFX_BASE__INST3_SEG3 0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org> @ 2017-11-27 22:30 ` Tom St Denis [not found] ` <fefe3e0b-91d8-39dc-2d34-9a795cf61274-5C7GfCeVMHo@public.gmane.org> 2017-11-27 22:40 ` Alex Deucher 1 sibling, 1 reply; 14+ messages in thread From: Tom St Denis @ 2017-11-27 22:30 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW On 27/11/17 04:28 PM, Christian König wrote: > Am 27.11.2017 um 21:56 schrieb Alex Deucher: >> On Mon, Nov 27, 2017 at 3:44 PM, Christian König >> <christian.koenig@amd.com> wrote: >>> Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >>>> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>>>> And that is a clear NAK to this approach. >>>> Hi Christian, >>>> >>>> Do you have other objections than the style issues? If so, please >>>> explain. >>> >>> No, the technical aspect actually looks rather reasonable. >>> >>>> Please clarify, why this file needs to be treated differently from >>>> other >>>> files under include/asic_reg? All those files are auto-generated by HW >>>> teams. Fixing the coding style adds no value and makes future updates >>>> more complicated. >>> >>> We already got complains about that and most likely will need to fix the >>> rest as well. >> I'd like to stay as close as possible to the headers formats we are >> using internally across teams for consistency. > > To be honest I strongly disagree on that. The bad quality of the > internal AMD headers is the reason we had to basically have the VMHUB > code for Vega10 twice for example. At the very least the globals we use per ip block should be version specific. That way if you cscope/ctags around you can find the actual references and not collisions. Tom _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <fefe3e0b-91d8-39dc-2d34-9a795cf61274-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <fefe3e0b-91d8-39dc-2d34-9a795cf61274-5C7GfCeVMHo@public.gmane.org> @ 2017-11-28 9:40 ` Christian König 0 siblings, 0 replies; 14+ messages in thread From: Christian König @ 2017-11-28 9:40 UTC (permalink / raw) To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 27.11.2017 um 23:30 schrieb Tom St Denis: > On 27/11/17 04:28 PM, Christian König wrote: >> Am 27.11.2017 um 21:56 schrieb Alex Deucher: >>> On Mon, Nov 27, 2017 at 3:44 PM, Christian König >>> <christian.koenig@amd.com> wrote: >>>> Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >>>>> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>>>>> And that is a clear NAK to this approach. >>>>> Hi Christian, >>>>> >>>>> Do you have other objections than the style issues? If so, please >>>>> explain. >>>> >>>> No, the technical aspect actually looks rather reasonable. >>>> >>>>> Please clarify, why this file needs to be treated differently from >>>>> other >>>>> files under include/asic_reg? All those files are auto-generated >>>>> by HW >>>>> teams. Fixing the coding style adds no value and makes future updates >>>>> more complicated. >>>> >>>> We already got complains about that and most likely will need to >>>> fix the >>>> rest as well. >>> I'd like to stay as close as possible to the headers formats we are >>> using internally across teams for consistency. >> >> To be honest I strongly disagree on that. The bad quality of the >> internal AMD headers is the reason we had to basically have the VMHUB >> code for Vega10 twice for example. > > At the very least the globals we use per ip block should be version > specific. That way if you cscope/ctags around you can find the actual > references and not collisions. Yeah, completely agree on that. Regards, Christian. > > Tom > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file [not found] ` <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org> 2017-11-27 22:30 ` Tom St Denis @ 2017-11-27 22:40 ` Alex Deucher 1 sibling, 0 replies; 14+ messages in thread From: Alex Deucher @ 2017-11-27 22:40 UTC (permalink / raw) To: Christian König; +Cc: Felix Kuehling, amd-gfx list On Mon, Nov 27, 2017 at 4:28 PM, Christian König <christian.koenig@amd.com> wrote: > Am 27.11.2017 um 21:56 schrieb Alex Deucher: >> >> On Mon, Nov 27, 2017 at 3:44 PM, Christian König >> <christian.koenig@amd.com> wrote: >>> >>> Am 27.11.2017 um 21:01 schrieb Felix Kuehling: >>>> >>>> On 2017-11-27 02:37 PM, Koenig, Christian wrote: >>>>> >>>>> And that is a clear NAK to this approach. >>>> >>>> Hi Christian, >>>> >>>> Do you have other objections than the style issues? If so, please >>>> explain. >>> >>> >>> No, the technical aspect actually looks rather reasonable. >>> >>>> Please clarify, why this file needs to be treated differently from other >>>> files under include/asic_reg? All those files are auto-generated by HW >>>> teams. Fixing the coding style adds no value and makes future updates >>>> more complicated. >>> >>> >>> We already got complains about that and most likely will need to fix the >>> rest as well. >> >> I'd like to stay as close as possible to the headers formats we are >> using internally across teams for consistency. > > > To be honest I strongly disagree on that. The bad quality of the internal > AMD headers is the reason we had to basically have the VMHUB code for Vega10 > twice for example. > > We should either massively push back on that (already done and with the next > hardware generation a bunch of things will be fixed, but unfortunately not > for Vega10 any more). > > Or we start to cleanup and/or generate the headers ourself. > > Or at least do the manual cleanup for Vega10 and hope that the next chunk > will be better. I don't disagree, but I'd rather we talk to the other teams and try and get some consensus and figure out what teams will use or maintain the tools going forward and have a plan in place rather than just going off on our own in the short term. Alex > >> Rather than rewriting these now, how about we just rename soc15ip.h to >> vg10ip.h and use that > > > That sounds like a good idea to me, but the structure defines still need to > be asic independent and applicable for all hardware generations, not just > Vega10. > > Otherwise we will need to create translation functions for each ASIC > generation to our internal format which is neither clean nor looks very > good. > > Christian. > > >> or even just drop patch 1 and use soc15ip.h as is for now. >> >> Alex >> >>> Nicolai looked into using a different auto generator for the header >>> files, >>> but not sure how far that already got along. >>> >>> The point is that the structures added with this won't be used by soc15 >>> alone, but rather be the base of the new register definition for future >>> hardware generations as well. >>> >>>> Like Shaoyun pointed out for example, the existing file >>>> include/asic_reg/vega10/soc15ip.h has the same style issues. >>> >>> >>> That file actually doesn't exists any more. Please see the work from >>> Feifei >>> about that as well. >>> >>> Regards, >>> Christian. >>> >>>> Regards, >>>> Felix >>>> >>>>> Please start by fixing at least the obvious style problems before >>>>> resending. >>>>> >>>>> Thanks, >>>>> Christian. >>>>> >>>>> Am 27.11.2017 20:29 schrieb "Liu, Shaoyun" <Shaoyun.Liu@amd.com>: >>>>> >>>>> I agree that this HW engineer generated file doesn't match the >>>>> coding style from linux software engineer point of view , but >>>>> since we already import other similar " HW engineer style" files >>>>> under include/asic_reg/vega10/, I don't see a reason to specially >>>>> change this file without touch else . This file is actually >>>>> almost >>>>> identical as soc15ip.h . I think it's easier for us to import >>>>> other offset file in the future if we keep them un-touched . >>>>> >>>>> Regards >>>>> Shaoyun.liu >>>>> >>>>> >>>>> -----Original Message----- >>>>> From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] >>>>> Sent: Monday, November 27, 2017 2:17 PM >>>>> To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org >>>>> Subject: Re: [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define >>>>> file >>>>> >>>>> First of let us fix the obvious style problems. >>>>> >>>>> Am 27.11.2017 um 19:30 schrieb Shaoyun Liu: >>>>> > Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c >>>>> > Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> >>>>> > --- >>>>> > .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 >>>>> ++++++++++++++++++++ >>>>> > 1 file changed, 1248 insertions(+) >>>>> > create mode 100644 >>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>>> > >>>>> > diff --git >>>>> a/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>>> b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>>> > new file mode 100644 >>>>> > index 0000000..76cb748 >>>>> > --- /dev/null >>>>> > +++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/ip_offset_1.h >>>>> > @@ -0,0 +1,1248 @@ >>>>> > +#ifndef _ip_offset_1_HEADER >>>>> > +#define _ip_offset_1_HEADER >>>>> Names for preprocessor defines should be capitable. >>>>> >>>>> > + >>>>> > +#define MAX_INSTANCE 5 >>>>> > +#define MAX_SEGMENT 5 >>>>> > + >>>>> > + >>>>> > +struct IP_BASE_INSTANCE >>>>> >>>>> Structure names should be lower case. And we need an amdgpu_ or >>>>> at >>>>> least >>>>> amd_ prefix here. >>>>> >>>>> Regards, >>>>> Christian. >>>>> >>>>> > +{ >>>>> > + unsigned int segment[MAX_SEGMENT]; >>>>> > +}; >>>>> > + >>>>> > +struct IP_BASE >>>>> > +{ >>>>> > + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; >>>>> > +}; >>>>> > + >>>>> > + >>>>> > +static const struct IP_BASE NBIF_BASE = >>>>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE NBIO_BASE = >>>>> { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE DCE_BASE = { { { { >>>>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE DCN_BASE = { { { { >>>>> 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE MP0_BASE = { { { { >>>>> 0x00016000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE MP1_BASE = { { { { >>>>> 0x00016000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE MP2_BASE = { { { { >>>>> 0x00016000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE DF_BASE = { { { { >>>>> 0x00007000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE UVD_BASE = { { { { >>>>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>>>> segment >>>>> >>>>> No "//" in kernel code please. >>>>> >>>>> > +static const struct IP_BASE VCN_BASE = { { { { >>>>> 0x00007800, 0x00007E00, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first >>>>> segment >>>>> > +static const struct IP_BASE DBGU_BASE = >>>>> { { { { 0x00000180, 0x000001A0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE DBGU_NBIO_BASE = { { { { >>>>> 0x000001C0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE DBGU_IO_BASE = { { { { >>>>> 0x000001E0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE DFX_DAP_BASE = { { { { >>>>> 0x000005A0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE DFX_BASE = { { { { >>>>> 0x00000580, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // this file does not contain >>>>> registers >>>>> > +static const struct IP_BASE ISP_BASE = { { { { >>>>> 0x00018000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE SYSTEMHUB_BASE = { { { { >>>>> 0x00000EA0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; // not exist >>>>> > +static const struct IP_BASE L2IMU_BASE = >>>>> { { { { 0x00007DC0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE IOHC_BASE = >>>>> { { { { 0x00010000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE ATHUB_BASE = >>>>> { { { { 0x00000C20, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE VCE_BASE = { { { { >>>>> 0x00007E00, 0x00048800, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE GC_BASE = { { { { >>>>> 0x00002000, 0x0000A000, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE MMHUB_BASE = >>>>> { { { { 0x0001A000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE RSMU_BASE = >>>>> { { { { 0x00012000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE HDP_BASE = { { { { >>>>> 0x00000F20, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE OSSSYS_BASE = { { { { >>>>> 0x000010A0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE SDMA0_BASE = >>>>> { { { { 0x00001260, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE SDMA1_BASE = >>>>> { { { { 0x00001460, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE XDMA_BASE = >>>>> { { { { 0x00003400, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE UMC_BASE = { { { { >>>>> 0x00014000, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE THM_BASE = { { { { >>>>> 0x00016600, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE SMUIO_BASE = >>>>> { { { { 0x00016800, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE PWR_BASE = { { { { >>>>> 0x00016A00, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE CLK_BASE = { { { { >>>>> 0x00016C00, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0x00016E00, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0x00017000, 0, 0, 0, 0 } }, >>>>> > + { { 0x00017200, 0, 0, >>>>> 0, 0 } }, >>>>> > + { >>>>> { 0x00017E00, 0, 0, 0, 0 } } } }; >>>>> > +static const struct IP_BASE FUSE_BASE = >>>>> { { { { 0x00017400, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } }, >>>>> > >>>>> + >>>>> { { 0, 0, 0, 0, 0 } } } }; >>>>> > + >>>>> > + >>>>> > +#define NBIF_BASE__INST0_SEG0 0x00000000 >>>>> > +#define NBIF_BASE__INST0_SEG1 0x00000014 >>>>> > +#define NBIF_BASE__INST0_SEG2 0x00000D20 >>>>> > +#define NBIF_BASE__INST0_SEG3 0x00010400 >>>>> > +#define NBIF_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define NBIF_BASE__INST1_SEG0 0 >>>>> > +#define NBIF_BASE__INST1_SEG1 0 >>>>> > +#define NBIF_BASE__INST1_SEG2 0 >>>>> > +#define NBIF_BASE__INST1_SEG3 0 >>>>> > +#define NBIF_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define NBIF_BASE__INST2_SEG0 0 >>>>> > +#define NBIF_BASE__INST2_SEG1 0 >>>>> > +#define NBIF_BASE__INST2_SEG2 0 >>>>> > +#define NBIF_BASE__INST2_SEG3 0 >>>>> > +#define NBIF_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define NBIF_BASE__INST3_SEG0 0 >>>>> > +#define NBIF_BASE__INST3_SEG1 0 >>>>> > +#define NBIF_BASE__INST3_SEG2 0 >>>>> > +#define NBIF_BASE__INST3_SEG3 0 >>>>> > +#define NBIF_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define NBIF_BASE__INST4_SEG0 0 >>>>> > +#define NBIF_BASE__INST4_SEG1 0 >>>>> > +#define NBIF_BASE__INST4_SEG2 0 >>>>> > +#define NBIF_BASE__INST4_SEG3 0 >>>>> > +#define NBIF_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define NBIO_BASE__INST0_SEG0 0x00000000 >>>>> > +#define NBIO_BASE__INST0_SEG1 0x00000014 >>>>> > +#define NBIO_BASE__INST0_SEG2 0x00000D20 >>>>> > +#define NBIO_BASE__INST0_SEG3 0x00010400 >>>>> > +#define NBIO_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define NBIO_BASE__INST1_SEG0 0 >>>>> > +#define NBIO_BASE__INST1_SEG1 0 >>>>> > +#define NBIO_BASE__INST1_SEG2 0 >>>>> > +#define NBIO_BASE__INST1_SEG3 0 >>>>> > +#define NBIO_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define NBIO_BASE__INST2_SEG0 0 >>>>> > +#define NBIO_BASE__INST2_SEG1 0 >>>>> > +#define NBIO_BASE__INST2_SEG2 0 >>>>> > +#define NBIO_BASE__INST2_SEG3 0 >>>>> > +#define NBIO_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define NBIO_BASE__INST3_SEG0 0 >>>>> > +#define NBIO_BASE__INST3_SEG1 0 >>>>> > +#define NBIO_BASE__INST3_SEG2 0 >>>>> > +#define NBIO_BASE__INST3_SEG3 0 >>>>> > +#define NBIO_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define NBIO_BASE__INST4_SEG0 0 >>>>> > +#define NBIO_BASE__INST4_SEG1 0 >>>>> > +#define NBIO_BASE__INST4_SEG2 0 >>>>> > +#define NBIO_BASE__INST4_SEG3 0 >>>>> > +#define NBIO_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DCE_BASE__INST0_SEG0 0x00000012 >>>>> > +#define DCE_BASE__INST0_SEG1 0x000000C0 >>>>> > +#define DCE_BASE__INST0_SEG2 0x000034C0 >>>>> > +#define DCE_BASE__INST0_SEG3 0 >>>>> > +#define DCE_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DCE_BASE__INST1_SEG0 0 >>>>> > +#define DCE_BASE__INST1_SEG1 0 >>>>> > +#define DCE_BASE__INST1_SEG2 0 >>>>> > +#define DCE_BASE__INST1_SEG3 0 >>>>> > +#define DCE_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DCE_BASE__INST2_SEG0 0 >>>>> > +#define DCE_BASE__INST2_SEG1 0 >>>>> > +#define DCE_BASE__INST2_SEG2 0 >>>>> > +#define DCE_BASE__INST2_SEG3 0 >>>>> > +#define DCE_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DCE_BASE__INST3_SEG0 0 >>>>> > +#define DCE_BASE__INST3_SEG1 0 >>>>> > +#define DCE_BASE__INST3_SEG2 0 >>>>> > +#define DCE_BASE__INST3_SEG3 0 >>>>> > +#define DCE_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DCE_BASE__INST4_SEG0 0 >>>>> > +#define DCE_BASE__INST4_SEG1 0 >>>>> > +#define DCE_BASE__INST4_SEG2 0 >>>>> > +#define DCE_BASE__INST4_SEG3 0 >>>>> > +#define DCE_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DCN_BASE__INST0_SEG0 0x00000012 >>>>> > +#define DCN_BASE__INST0_SEG1 0x000000C0 >>>>> > +#define DCN_BASE__INST0_SEG2 0x000034C0 >>>>> > +#define DCN_BASE__INST0_SEG3 0 >>>>> > +#define DCN_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DCN_BASE__INST1_SEG0 0 >>>>> > +#define DCN_BASE__INST1_SEG1 0 >>>>> > +#define DCN_BASE__INST1_SEG2 0 >>>>> > +#define DCN_BASE__INST1_SEG3 0 >>>>> > +#define DCN_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DCN_BASE__INST2_SEG0 0 >>>>> > +#define DCN_BASE__INST2_SEG1 0 >>>>> > +#define DCN_BASE__INST2_SEG2 0 >>>>> > +#define DCN_BASE__INST2_SEG3 0 >>>>> > +#define DCN_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DCN_BASE__INST3_SEG0 0 >>>>> > +#define DCN_BASE__INST3_SEG1 0 >>>>> > +#define DCN_BASE__INST3_SEG2 0 >>>>> > +#define DCN_BASE__INST3_SEG3 0 >>>>> > +#define DCN_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DCN_BASE__INST4_SEG0 0 >>>>> > +#define DCN_BASE__INST4_SEG1 0 >>>>> > +#define DCN_BASE__INST4_SEG2 0 >>>>> > +#define DCN_BASE__INST4_SEG3 0 >>>>> > +#define DCN_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define MP0_BASE__INST0_SEG0 0x00016000 >>>>> > +#define MP0_BASE__INST0_SEG1 0 >>>>> > +#define MP0_BASE__INST0_SEG2 0 >>>>> > +#define MP0_BASE__INST0_SEG3 0 >>>>> > +#define MP0_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define MP0_BASE__INST1_SEG0 0 >>>>> > +#define MP0_BASE__INST1_SEG1 0 >>>>> > +#define MP0_BASE__INST1_SEG2 0 >>>>> > +#define MP0_BASE__INST1_SEG3 0 >>>>> > +#define MP0_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define MP0_BASE__INST2_SEG0 0 >>>>> > +#define MP0_BASE__INST2_SEG1 0 >>>>> > +#define MP0_BASE__INST2_SEG2 0 >>>>> > +#define MP0_BASE__INST2_SEG3 0 >>>>> > +#define MP0_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define MP0_BASE__INST3_SEG0 0 >>>>> > +#define MP0_BASE__INST3_SEG1 0 >>>>> > +#define MP0_BASE__INST3_SEG2 0 >>>>> > +#define MP0_BASE__INST3_SEG3 0 >>>>> > +#define MP0_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define MP0_BASE__INST4_SEG0 0 >>>>> > +#define MP0_BASE__INST4_SEG1 0 >>>>> > +#define MP0_BASE__INST4_SEG2 0 >>>>> > +#define MP0_BASE__INST4_SEG3 0 >>>>> > +#define MP0_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define MP1_BASE__INST0_SEG0 0x00016000 >>>>> > +#define MP1_BASE__INST0_SEG1 0 >>>>> > +#define MP1_BASE__INST0_SEG2 0 >>>>> > +#define MP1_BASE__INST0_SEG3 0 >>>>> > +#define MP1_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define MP1_BASE__INST1_SEG0 0 >>>>> > +#define MP1_BASE__INST1_SEG1 0 >>>>> > +#define MP1_BASE__INST1_SEG2 0 >>>>> > +#define MP1_BASE__INST1_SEG3 0 >>>>> > +#define MP1_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define MP1_BASE__INST2_SEG0 0 >>>>> > +#define MP1_BASE__INST2_SEG1 0 >>>>> > +#define MP1_BASE__INST2_SEG2 0 >>>>> > +#define MP1_BASE__INST2_SEG3 0 >>>>> > +#define MP1_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define MP1_BASE__INST3_SEG0 0 >>>>> > +#define MP1_BASE__INST3_SEG1 0 >>>>> > +#define MP1_BASE__INST3_SEG2 0 >>>>> > +#define MP1_BASE__INST3_SEG3 0 >>>>> > +#define MP1_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define MP1_BASE__INST4_SEG0 0 >>>>> > +#define MP1_BASE__INST4_SEG1 0 >>>>> > +#define MP1_BASE__INST4_SEG2 0 >>>>> > +#define MP1_BASE__INST4_SEG3 0 >>>>> > +#define MP1_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define MP2_BASE__INST0_SEG0 0x00016000 >>>>> > +#define MP2_BASE__INST0_SEG1 0 >>>>> > +#define MP2_BASE__INST0_SEG2 0 >>>>> > +#define MP2_BASE__INST0_SEG3 0 >>>>> > +#define MP2_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define MP2_BASE__INST1_SEG0 0 >>>>> > +#define MP2_BASE__INST1_SEG1 0 >>>>> > +#define MP2_BASE__INST1_SEG2 0 >>>>> > +#define MP2_BASE__INST1_SEG3 0 >>>>> > +#define MP2_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define MP2_BASE__INST2_SEG0 0 >>>>> > +#define MP2_BASE__INST2_SEG1 0 >>>>> > +#define MP2_BASE__INST2_SEG2 0 >>>>> > +#define MP2_BASE__INST2_SEG3 0 >>>>> > +#define MP2_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define MP2_BASE__INST3_SEG0 0 >>>>> > +#define MP2_BASE__INST3_SEG1 0 >>>>> > +#define MP2_BASE__INST3_SEG2 0 >>>>> > +#define MP2_BASE__INST3_SEG3 0 >>>>> > +#define MP2_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define MP2_BASE__INST4_SEG0 0 >>>>> > +#define MP2_BASE__INST4_SEG1 0 >>>>> > +#define MP2_BASE__INST4_SEG2 0 >>>>> > +#define MP2_BASE__INST4_SEG3 0 >>>>> > +#define MP2_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DF_BASE__INST0_SEG0 0x00007000 >>>>> > +#define DF_BASE__INST0_SEG1 0 >>>>> > +#define DF_BASE__INST0_SEG2 0 >>>>> > +#define DF_BASE__INST0_SEG3 0 >>>>> > +#define DF_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DF_BASE__INST1_SEG0 0 >>>>> > +#define DF_BASE__INST1_SEG1 0 >>>>> > +#define DF_BASE__INST1_SEG2 0 >>>>> > +#define DF_BASE__INST1_SEG3 0 >>>>> > +#define DF_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DF_BASE__INST2_SEG0 0 >>>>> > +#define DF_BASE__INST2_SEG1 0 >>>>> > +#define DF_BASE__INST2_SEG2 0 >>>>> > +#define DF_BASE__INST2_SEG3 0 >>>>> > +#define DF_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DF_BASE__INST3_SEG0 0 >>>>> > +#define DF_BASE__INST3_SEG1 0 >>>>> > +#define DF_BASE__INST3_SEG2 0 >>>>> > +#define DF_BASE__INST3_SEG3 0 >>>>> > +#define DF_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DF_BASE__INST4_SEG0 0 >>>>> > +#define DF_BASE__INST4_SEG1 0 >>>>> > +#define DF_BASE__INST4_SEG2 0 >>>>> > +#define DF_BASE__INST4_SEG3 0 >>>>> > +#define DF_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define UVD_BASE__INST0_SEG0 0x00007800 >>>>> > +#define UVD_BASE__INST0_SEG1 0x00007E00 >>>>> > +#define UVD_BASE__INST0_SEG2 0 >>>>> > +#define UVD_BASE__INST0_SEG3 0 >>>>> > +#define UVD_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define UVD_BASE__INST1_SEG0 0 >>>>> > +#define UVD_BASE__INST1_SEG1 0 >>>>> > +#define UVD_BASE__INST1_SEG2 0 >>>>> > +#define UVD_BASE__INST1_SEG3 0 >>>>> > +#define UVD_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define UVD_BASE__INST2_SEG0 0 >>>>> > +#define UVD_BASE__INST2_SEG1 0 >>>>> > +#define UVD_BASE__INST2_SEG2 0 >>>>> > +#define UVD_BASE__INST2_SEG3 0 >>>>> > +#define UVD_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define UVD_BASE__INST3_SEG0 0 >>>>> > +#define UVD_BASE__INST3_SEG1 0 >>>>> > +#define UVD_BASE__INST3_SEG2 0 >>>>> > +#define UVD_BASE__INST3_SEG3 0 >>>>> > +#define UVD_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define UVD_BASE__INST4_SEG0 0 >>>>> > +#define UVD_BASE__INST4_SEG1 0 >>>>> > +#define UVD_BASE__INST4_SEG2 0 >>>>> > +#define UVD_BASE__INST4_SEG3 0 >>>>> > +#define UVD_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define VCN_BASE__INST0_SEG0 0x00007800 >>>>> > +#define VCN_BASE__INST0_SEG1 0x00007E00 >>>>> > +#define VCN_BASE__INST0_SEG2 0 >>>>> > +#define VCN_BASE__INST0_SEG3 0 >>>>> > +#define VCN_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define VCN_BASE__INST1_SEG0 0 >>>>> > +#define VCN_BASE__INST1_SEG1 0 >>>>> > +#define VCN_BASE__INST1_SEG2 0 >>>>> > +#define VCN_BASE__INST1_SEG3 0 >>>>> > +#define VCN_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define VCN_BASE__INST2_SEG0 0 >>>>> > +#define VCN_BASE__INST2_SEG1 0 >>>>> > +#define VCN_BASE__INST2_SEG2 0 >>>>> > +#define VCN_BASE__INST2_SEG3 0 >>>>> > +#define VCN_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define VCN_BASE__INST3_SEG0 0 >>>>> > +#define VCN_BASE__INST3_SEG1 0 >>>>> > +#define VCN_BASE__INST3_SEG2 0 >>>>> > +#define VCN_BASE__INST3_SEG3 0 >>>>> > +#define VCN_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define VCN_BASE__INST4_SEG0 0 >>>>> > +#define VCN_BASE__INST4_SEG1 0 >>>>> > +#define VCN_BASE__INST4_SEG2 0 >>>>> > +#define VCN_BASE__INST4_SEG3 0 >>>>> > +#define VCN_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DBGU_BASE__INST0_SEG0 0x00000180 >>>>> > +#define DBGU_BASE__INST0_SEG1 0x000001A0 >>>>> > +#define DBGU_BASE__INST0_SEG2 0 >>>>> > +#define DBGU_BASE__INST0_SEG3 0 >>>>> > +#define DBGU_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DBGU_BASE__INST1_SEG0 0 >>>>> > +#define DBGU_BASE__INST1_SEG1 0 >>>>> > +#define DBGU_BASE__INST1_SEG2 0 >>>>> > +#define DBGU_BASE__INST1_SEG3 0 >>>>> > +#define DBGU_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DBGU_BASE__INST2_SEG0 0 >>>>> > +#define DBGU_BASE__INST2_SEG1 0 >>>>> > +#define DBGU_BASE__INST2_SEG2 0 >>>>> > +#define DBGU_BASE__INST2_SEG3 0 >>>>> > +#define DBGU_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DBGU_BASE__INST3_SEG0 0 >>>>> > +#define DBGU_BASE__INST3_SEG1 0 >>>>> > +#define DBGU_BASE__INST3_SEG2 0 >>>>> > +#define DBGU_BASE__INST3_SEG3 0 >>>>> > +#define DBGU_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DBGU_BASE__INST4_SEG0 0 >>>>> > +#define DBGU_BASE__INST4_SEG1 0 >>>>> > +#define DBGU_BASE__INST4_SEG2 0 >>>>> > +#define DBGU_BASE__INST4_SEG3 0 >>>>> > +#define DBGU_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0 >>>>> > +#define DBGU_NBIO_BASE__INST0_SEG1 0 >>>>> > +#define DBGU_NBIO_BASE__INST0_SEG2 0 >>>>> > +#define DBGU_NBIO_BASE__INST0_SEG3 0 >>>>> > +#define DBGU_NBIO_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DBGU_NBIO_BASE__INST1_SEG0 0 >>>>> > +#define DBGU_NBIO_BASE__INST1_SEG1 0 >>>>> > +#define DBGU_NBIO_BASE__INST1_SEG2 0 >>>>> > +#define DBGU_NBIO_BASE__INST1_SEG3 0 >>>>> > +#define DBGU_NBIO_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DBGU_NBIO_BASE__INST2_SEG0 0 >>>>> > +#define DBGU_NBIO_BASE__INST2_SEG1 0 >>>>> > +#define DBGU_NBIO_BASE__INST2_SEG2 0 >>>>> > +#define DBGU_NBIO_BASE__INST2_SEG3 0 >>>>> > +#define DBGU_NBIO_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DBGU_NBIO_BASE__INST3_SEG0 0 >>>>> > +#define DBGU_NBIO_BASE__INST3_SEG1 0 >>>>> > +#define DBGU_NBIO_BASE__INST3_SEG2 0 >>>>> > +#define DBGU_NBIO_BASE__INST3_SEG3 0 >>>>> > +#define DBGU_NBIO_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DBGU_NBIO_BASE__INST4_SEG0 0 >>>>> > +#define DBGU_NBIO_BASE__INST4_SEG1 0 >>>>> > +#define DBGU_NBIO_BASE__INST4_SEG2 0 >>>>> > +#define DBGU_NBIO_BASE__INST4_SEG3 0 >>>>> > +#define DBGU_NBIO_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 >>>>> > +#define DBGU_IO_BASE__INST0_SEG1 0 >>>>> > +#define DBGU_IO_BASE__INST0_SEG2 0 >>>>> > +#define DBGU_IO_BASE__INST0_SEG3 0 >>>>> > +#define DBGU_IO_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DBGU_IO_BASE__INST1_SEG0 0 >>>>> > +#define DBGU_IO_BASE__INST1_SEG1 0 >>>>> > +#define DBGU_IO_BASE__INST1_SEG2 0 >>>>> > +#define DBGU_IO_BASE__INST1_SEG3 0 >>>>> > +#define DBGU_IO_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DBGU_IO_BASE__INST2_SEG0 0 >>>>> > +#define DBGU_IO_BASE__INST2_SEG1 0 >>>>> > +#define DBGU_IO_BASE__INST2_SEG2 0 >>>>> > +#define DBGU_IO_BASE__INST2_SEG3 0 >>>>> > +#define DBGU_IO_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DBGU_IO_BASE__INST3_SEG0 0 >>>>> > +#define DBGU_IO_BASE__INST3_SEG1 0 >>>>> > +#define DBGU_IO_BASE__INST3_SEG2 0 >>>>> > +#define DBGU_IO_BASE__INST3_SEG3 0 >>>>> > +#define DBGU_IO_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DBGU_IO_BASE__INST4_SEG0 0 >>>>> > +#define DBGU_IO_BASE__INST4_SEG1 0 >>>>> > +#define DBGU_IO_BASE__INST4_SEG2 0 >>>>> > +#define DBGU_IO_BASE__INST4_SEG3 0 >>>>> > +#define DBGU_IO_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DFX_DAP_BASE__INST0_SEG0 0x000005A0 >>>>> > +#define DFX_DAP_BASE__INST0_SEG1 0 >>>>> > +#define DFX_DAP_BASE__INST0_SEG2 0 >>>>> > +#define DFX_DAP_BASE__INST0_SEG3 0 >>>>> > +#define DFX_DAP_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DFX_DAP_BASE__INST1_SEG0 0 >>>>> > +#define DFX_DAP_BASE__INST1_SEG1 0 >>>>> > +#define DFX_DAP_BASE__INST1_SEG2 0 >>>>> > +#define DFX_DAP_BASE__INST1_SEG3 0 >>>>> > +#define DFX_DAP_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DFX_DAP_BASE__INST2_SEG0 0 >>>>> > +#define DFX_DAP_BASE__INST2_SEG1 0 >>>>> > +#define DFX_DAP_BASE__INST2_SEG2 0 >>>>> > +#define DFX_DAP_BASE__INST2_SEG3 0 >>>>> > +#define DFX_DAP_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DFX_DAP_BASE__INST3_SEG0 0 >>>>> > +#define DFX_DAP_BASE__INST3_SEG1 0 >>>>> > +#define DFX_DAP_BASE__INST3_SEG2 0 >>>>> > +#define DFX_DAP_BASE__INST3_SEG3 0 >>>>> > +#define DFX_DAP_BASE__INST3_SEG4 0 >>>>> > + >>>>> > +#define DFX_DAP_BASE__INST4_SEG0 0 >>>>> > +#define DFX_DAP_BASE__INST4_SEG1 0 >>>>> > +#define DFX_DAP_BASE__INST4_SEG2 0 >>>>> > +#define DFX_DAP_BASE__INST4_SEG3 0 >>>>> > +#define DFX_DAP_BASE__INST4_SEG4 0 >>>>> > + >>>>> > +#define DFX_BASE__INST0_SEG0 0x00000580 >>>>> > +#define DFX_BASE__INST0_SEG1 0 >>>>> > +#define DFX_BASE__INST0_SEG2 0 >>>>> > +#define DFX_BASE__INST0_SEG3 0 >>>>> > +#define DFX_BASE__INST0_SEG4 0 >>>>> > + >>>>> > +#define DFX_BASE__INST1_SEG0 0 >>>>> > +#define DFX_BASE__INST1_SEG1 0 >>>>> > +#define DFX_BASE__INST1_SEG2 0 >>>>> > +#define DFX_BASE__INST1_SEG3 0 >>>>> > +#define DFX_BASE__INST1_SEG4 0 >>>>> > + >>>>> > +#define DFX_BASE__INST2_SEG0 0 >>>>> > +#define DFX_BASE__INST2_SEG1 0 >>>>> > +#define DFX_BASE__INST2_SEG2 0 >>>>> > +#define DFX_BASE__INST2_SEG3 0 >>>>> > +#define DFX_BASE__INST2_SEG4 0 >>>>> > + >>>>> > +#define DFX_BASE__INST3_SEG0 0 >>>>> > +#define DFX_BASE__INST3_SEG1 0 >>>>> > +#define DFX_BASE__INST3_SEG2 0 >>>>> > +#define DFX_BASE__INST3_SEG3 0 > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-11-28 9:40 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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2017-11-27 18:30 [PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file Shaoyun Liu
[not found] ` <1511807458-27102-1-git-send-email-Shaoyun.Liu-5C7GfCeVMHo@public.gmane.org>
2017-11-27 18:54 ` Tom St Denis
[not found] ` <a831909b-4381-1a63-fba3-0eb816fa5e61-5C7GfCeVMHo@public.gmane.org>
2017-11-27 19:04 ` Liu, Shaoyun
2017-11-27 19:17 ` Christian König
[not found] ` <2db922e4-fe49-7499-38f1-a3b2c8e07cf5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-11-27 19:29 ` Liu, Shaoyun
2017-11-27 19:37 Koenig, Christian
[not found] ` <2a0a3687-0207-4ea0-bb2c-20750a1d2bb3-2ueSQiBKiTY7tOexoI0I+QC/G2K4zDHf@public.gmane.org>
2017-11-27 20:01 ` Felix Kuehling
[not found] ` <702bfce6-78ef-0284-6306-f4b3366d34f7-5C7GfCeVMHo@public.gmane.org>
2017-11-27 20:44 ` Christian König
[not found] ` <ec783d5b-74a5-07e8-6bb4-5c930e56a718-5C7GfCeVMHo@public.gmane.org>
2017-11-27 20:56 ` Alex Deucher
[not found] ` <CADnq5_M55-qJEwfVGvkxpajePPxK1fePzG57ZTjCLVBQuddf6w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-11-27 21:24 ` Liu, Shaoyun
2017-11-27 21:28 ` Christian König
[not found] ` <cca23fad-52d4-8c49-d2b1-e7ed1bde7b39-5C7GfCeVMHo@public.gmane.org>
2017-11-27 22:30 ` Tom St Denis
[not found] ` <fefe3e0b-91d8-39dc-2d34-9a795cf61274-5C7GfCeVMHo@public.gmane.org>
2017-11-28 9:40 ` Christian König
2017-11-27 22:40 ` Alex Deucher
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