[PATCH 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

[PATCH 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

[Evan Quan]

As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to
be incomplete. Another fix(see link below) has been sent out.
Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/

Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c       |  5 +---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 26 +------------------
 2 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..09ee34312268 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2176,10 +2176,7 @@ static int psp_load_smu_fw(struct psp_context *psp)
 	if ((amdgpu_in_reset(adev) &&
 	     ras && adev->ras_enabled &&
 	     (adev->asic_type == CHIP_ARCTURUS ||
-	      adev->asic_type == CHIP_VEGA20)) ||
-	     (adev->in_runpm &&
-	      adev->asic_type >= CHIP_NAVI10 &&
-	      adev->asic_type <= CHIP_NAVI12)) {
+	      adev->asic_type == CHIP_VEGA20))) {
 		ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
 		if (ret) {
 			DRM_WARN("Failed to set MP1 state prepare for reload\n");
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d28236ba0018..32a52c1bea07 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -431,30 +431,6 @@ static int navi10_store_powerplay_table(struct smu_context *smu)
 	return 0;
 }
 
-static int navi10_set_mp1_state(struct smu_context *smu,
-				enum pp_mp1_state mp1_state)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t mp1_fw_flags;
-	int ret = 0;
-
-	ret = smu_cmn_set_mp1_state(smu, mp1_state);
-	if (ret)
-		return ret;
-
-	if (mp1_state == PP_MP1_STATE_UNLOAD) {
-		mp1_fw_flags = RREG32_PCIE(MP1_Public |
-					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
-
-		mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK;
-
-		WREG32_PCIE(MP1_Public |
-			    (smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags);
-	}
-
-	return 0;
-}
-
 static int navi10_setup_pptable(struct smu_context *smu)
 {
 	int ret = 0;
@@ -3119,7 +3095,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.get_fan_parameters = navi10_get_fan_parameters,
 	.post_init = navi10_post_smu_init,
 	.interrupt_work = smu_v11_0_interrupt_work,
-	.set_mp1_state = navi10_set_mp1_state,
+	.set_mp1_state = smu_cmn_set_mp1_state,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
-- 
2.29.0

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[PATCH 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC

[Evan Quan]

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the
Dstate change. Driver involvement for determining the timing for
BACO enter/exit is not needed.

Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c    | 20 ++++++++++---------
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3de1accb060e..3fad67c32098 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1574,6 +1574,8 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
 		 */
 		pci_set_master(pdev);
 	} else if (amdgpu_device_supports_baco(drm_dev)) {
+		/* Wait for PMFW handling for the Dstate change */
+		msleep(10);
 		amdgpu_device_baco_exit(drm_dev);
 	}
 	ret = amdgpu_device_resume(drm_dev, false);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 362696208fd8..61d00b989e49 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1581,25 +1581,27 @@ int smu_v11_0_baco_enter(struct smu_context *smu)
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
 
-	/* Arcturus does not need this audio workaround */
-	if (adev->asic_type != CHIP_ARCTURUS) {
+	if (adev->in_runpm) {
 		ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+	} else {
+		ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
 		if (ret)
 			return ret;
-	}
-
-	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
-	if (ret)
-		return ret;
 
-	msleep(10);
+		msleep(10);
+	}
 
 	return ret;
 }
 
 int smu_v11_0_baco_exit(struct smu_context *smu)
 {
-	return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
+	struct amdgpu_device *adev = smu->adev;
+
+	if (adev->in_runpm)
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+	else
+		return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
 }
 
 int smu_v11_0_mode1_reset(struct smu_context *smu)
-- 
2.29.0

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[PATCH 3/5] drm/amdgpu: correct the audio function initial Dstate

[Evan Quan]

On driver loading, the ASIC is in D0 state. The bundled
audio function should be in the same state also.

Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index c354ffa62483..9d497b4f8e34 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -137,6 +137,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 	struct drm_device *dev;
 	struct pci_dev *parent;
 	int r, acpi_status;
+	struct pci_dev *p = NULL;
 
 	dev = adev_to_drm(adev);
 
@@ -212,9 +213,22 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 						DPM_FLAG_MAY_SKIP_RESUME);
 		pm_runtime_use_autosuspend(dev->dev);
 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
+
 		pm_runtime_allow(dev->dev);
+
 		pm_runtime_mark_last_busy(dev->dev);
 		pm_runtime_put_autosuspend(dev->dev);
+
+		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
+				adev->pdev->bus->number, 1);
+		if (p) {
+			pm_runtime_get_sync(&p->dev);
+
+			pm_runtime_mark_last_busy(&p->dev);
+			pm_runtime_put_autosuspend(&p->dev);
+
+			pci_dev_put(p);
+		}
 	}
 
 	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
-- 
2.29.0

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Re: [PATCH 3/5] drm/amdgpu: correct the audio function initial Dstate

[Lazar, Lijo]

On 6/3/2021 10:26 AM, Evan Quan wrote:
> On driver loading, the ASIC is in D0 state. The bundled
> audio function should be in the same state also.
> 
> Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index c354ffa62483..9d497b4f8e34 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -137,6 +137,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
>   	struct drm_device *dev;
>   	struct pci_dev *parent;
>   	int r, acpi_status;
> +	struct pci_dev *p = NULL;
>   
>   	dev = adev_to_drm(adev);
>   
> @@ -212,9 +213,22 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
>   						DPM_FLAG_MAY_SKIP_RESUME);
>   		pm_runtime_use_autosuspend(dev->dev);
>   		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> +
>   		pm_runtime_allow(dev->dev);
> +
>   		pm_runtime_mark_last_busy(dev->dev);
>   		pm_runtime_put_autosuspend(dev->dev);
> +
> +		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
> +				adev->pdev->bus->number, 1);

For the sake of readability, it's better to wrap this as get_audio_dev 
or similar.

Thanks,
Lijo

> +		if (p) {
> +			pm_runtime_get_sync(&p->dev);
> +
> +			pm_runtime_mark_last_busy(&p->dev);
> +			pm_runtime_put_autosuspend(&p->dev);
> +
> +			pci_dev_put(p);
> +		}
>   	}
>   
>   	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
> 
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RE: [PATCH 3/5] drm/amdgpu: correct the audio function initial Dstate

[Quan, Evan]

[AMD Official Use Only]



> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@amd.com>
> Sent: Thursday, June 3, 2021 7:09 PM
> To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH 3/5] drm/amdgpu: correct the audio function initial
> Dstate
> 
> 
> 
> On 6/3/2021 10:26 AM, Evan Quan wrote:
> > On driver loading, the ASIC is in D0 state. The bundled audio function
> > should be in the same state also.
> >
> > Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++++++++++++++
> >   1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index c354ffa62483..9d497b4f8e34 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -137,6 +137,7 @@ int amdgpu_driver_load_kms(struct
> amdgpu_device *adev, unsigned long flags)
> >   	struct drm_device *dev;
> >   	struct pci_dev *parent;
> >   	int r, acpi_status;
> > +	struct pci_dev *p = NULL;
> >
> >   	dev = adev_to_drm(adev);
> >
> > @@ -212,9 +213,22 @@ int amdgpu_driver_load_kms(struct
> amdgpu_device *adev, unsigned long flags)
> >
> 	DPM_FLAG_MAY_SKIP_RESUME);
> >   		pm_runtime_use_autosuspend(dev->dev);
> >   		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
> > +
> >   		pm_runtime_allow(dev->dev);
> > +
> >   		pm_runtime_mark_last_busy(dev->dev);
> >   		pm_runtime_put_autosuspend(dev->dev);
> > +
> > +		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev-
> >pdev->bus),
> > +				adev->pdev->bus->number, 1);
> 
> For the sake of readability, it's better to wrap this as get_audio_dev or similar.
[Quan, Evan] Sounds good to me. Will update it in V2.
BR
Evan
> 
> Thanks,
> Lijo
> 
> > +		if (p) {
> > +			pm_runtime_get_sync(&p->dev);
> > +
> > +			pm_runtime_mark_last_busy(&p->dev);
> > +			pm_runtime_put_autosuspend(&p->dev);
> > +
> > +			pci_dev_put(p);
> > +		}
> >   	}
> >
> >   	if (amdgpu_acpi_smart_shift_update(dev,
> AMDGPU_SS_DRV_LOAD))
> >
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[PATCH 4/5] drm/amd/pm: clear the cached dpm feature status

[Evan Quan]

For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be cleared to pair that.

Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index c9a31556e077..fd7b1b8edeb7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
 	return 0;
 }
 
+static void smu_reset_cached_dpm_feature_status(struct smu_context *smu)
+{
+	struct smu_feature *feature = &smu->smu_feature;
+
+	mutex_lock(&feature->mutex);
+	bitmap_zero(feature->enabled, feature->feature_num);
+	bitmap_zero(feature->supported, feature->feature_num);
+	mutex_unlock(&feature->mutex);
+}
+
 static int smu_disable_dpms(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
@@ -1374,16 +1384,20 @@ static int smu_disable_dpms(struct smu_context *smu)
 	 */
 	if (smu->uploading_custom_pp_table &&
 	    (adev->asic_type >= CHIP_NAVI10) &&
-	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
+	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
+		smu_reset_cached_dpm_feature_status(smu);
 		return 0;
+	}
 
 	/*
 	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
 	 * on BACO in. Driver involvement is unnecessary.
 	 */
 	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
-	     use_baco)
+	     use_baco) {
+		smu_reset_cached_dpm_feature_status(smu);
 		return 0;
+	}
 
 	/*
 	 * For gpu reset, runpm and hibernation through BACO,
-- 
2.29.0

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Re: [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status

[Lazar, Lijo]

On 6/3/2021 10:26 AM, Evan Quan wrote:
> For some ASICs, the real dpm feature disablement job is handled by
> PMFW during baco reset and custom pptable loading. Cached dpm feature
> status need to be cleared to pair that.
> 
> Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 ++++++++++++++++--
>   1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index c9a31556e077..fd7b1b8edeb7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
>   	return 0;
>   }
>   
> +static void smu_reset_cached_dpm_feature_status(struct smu_context *smu)
> +{
> +	struct smu_feature *feature = &smu->smu_feature;
> +
> +	mutex_lock(&feature->mutex);
> +	bitmap_zero(feature->enabled, feature->feature_num);
> +	bitmap_zero(feature->supported, feature->feature_num);

This will clear also clear the BACO feature status. Won't that affect 
using baco exit for runtime pm resume?

Thanks,
Lijo

> +	mutex_unlock(&feature->mutex);
> +}
> +
>   static int smu_disable_dpms(struct smu_context *smu)
>   {
>   	struct amdgpu_device *adev = smu->adev;
> @@ -1374,16 +1384,20 @@ static int smu_disable_dpms(struct smu_context *smu)
>   	 */
>   	if (smu->uploading_custom_pp_table &&
>   	    (adev->asic_type >= CHIP_NAVI10) &&
> -	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> +	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
> +		smu_reset_cached_dpm_feature_status(smu);
>   		return 0;
> +	}
>   
>   	/*
>   	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
>   	 * on BACO in. Driver involvement is unnecessary.
>   	 */
>   	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
> -	     use_baco)
> +	     use_baco) {
> +		smu_reset_cached_dpm_feature_status(smu);
>   		return 0;
> +	}
>   
>   	/*
>   	 * For gpu reset, runpm and hibernation through BACO,
> 
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RE: [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status

[Quan, Evan]

[AMD Official Use Only]



> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@amd.com>
> Sent: Thursday, June 3, 2021 7:04 PM
> To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status
> 
> 
> 
> On 6/3/2021 10:26 AM, Evan Quan wrote:
> > For some ASICs, the real dpm feature disablement job is handled by
> > PMFW during baco reset and custom pptable loading. Cached dpm feature
> > status need to be cleared to pair that.
> >
> > Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18
> ++++++++++++++++--
> >   1 file changed, 16 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index c9a31556e077..fd7b1b8edeb7 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
> >   	return 0;
> >   }
> >
> > +static void smu_reset_cached_dpm_feature_status(struct smu_context
> > +*smu) {
> > +	struct smu_feature *feature = &smu->smu_feature;
> > +
> > +	mutex_lock(&feature->mutex);
> > +	bitmap_zero(feature->enabled, feature->feature_num);
> > +	bitmap_zero(feature->supported, feature->feature_num);
> 
> This will clear also clear the BACO feature status. Won't that affect using baco
> exit for runtime pm resume?
[Quan, Evan] Yes, you are right. Will update it.
Regards,
Evan
> 
> Thanks,
> Lijo
> 
> > +	mutex_unlock(&feature->mutex);
> > +}
> > +
> >   static int smu_disable_dpms(struct smu_context *smu)
> >   {
> >   	struct amdgpu_device *adev = smu->adev; @@ -1374,16 +1384,20
> @@
> > static int smu_disable_dpms(struct smu_context *smu)
> >   	 */
> >   	if (smu->uploading_custom_pp_table &&
> >   	    (adev->asic_type >= CHIP_NAVI10) &&
> > -	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> > +	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
> > +		smu_reset_cached_dpm_feature_status(smu);
> >   		return 0;
> > +	}
> >
> >   	/*
> >   	 * For Sienna_Cichlid, PMFW will handle the features disablement
> properly
> >   	 * on BACO in. Driver involvement is unnecessary.
> >   	 */
> >   	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
> > -	     use_baco)
> > +	     use_baco) {
> > +		smu_reset_cached_dpm_feature_status(smu);
> >   		return 0;
> > +	}
> >
> >   	/*
> >   	 * For gpu reset, runpm and hibernation through BACO,
> >
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[PATCH 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x

[Evan Quan]

For BACO scenario, PMFW will handle the dpm features disablement
and interaction with RLC properly. Driver involvement is unnecessary
and error prone.

Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fd7b1b8edeb7..e3e309bb086d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1393,7 +1393,8 @@ static int smu_disable_dpms(struct smu_context *smu)
 	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
 	 * on BACO in. Driver involvement is unnecessary.
 	 */
-	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+	if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+	     ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
 	     use_baco) {
 		smu_reset_cached_dpm_feature_status(smu);
 		return 0;
-- 
2.29.0

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