* [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
@ 2019-03-20 10:08 Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Vandita Kulkarni @ 2019-03-20 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at the later point in
the enable sequence.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index beb30d9..f02504d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ /* make sure that the ddi clocks are not gated */
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ }
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
POSTING_READ(DPCLKA_CFGCR0_ICL);
mutex_unlock(&dev_priv->dpll_lock);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
@ 2019-03-20 10:08 ` Vandita Kulkarni
2019-03-20 11:07 ` Imre Deak
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Vandita Kulkarni @ 2019-03-20 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Re-enable clock gating of DDI clocks.
Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f02504d..716be38 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
DRM_ERROR("DDI port:%c buffer not idle\n",
port_name(port));
}
- gen11_dsi_ungate_clocks(encoder);
+ gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
@ 2019-03-20 11:07 ` Imre Deak
2019-03-20 12:02 ` Shankar, Uma
2019-03-21 13:56 ` Kulkarni, Vandita
0 siblings, 2 replies; 12+ messages in thread
From: Imre Deak @ 2019-03-20 11:07 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: jani.nikula, intel-gfx
On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> Re-enable clock gating of DDI clocks.
>
> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index f02504d..716be38 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
> DRM_ERROR("DDI port:%c buffer not idle\n",
> port_name(port));
> }
> - gen11_dsi_ungate_clocks(encoder);
> + gen11_dsi_gate_clocks(encoder);
This also requires updating icl_sanitize_encoder_pll_mapping().
Currently it assumes that the DDI clock needs to be ungated if the
corresponding DSI port is disabled and gated if the port is enabled.
The changes in this patchset mean that the DDI clock should be gated for
DSI ports regardless of whether the port is enabled or not.
> }
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
@ 2019-03-20 11:49 ` Shankar, Uma
2019-03-21 13:53 ` Kulkarni, Vandita
2019-03-20 14:28 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-03-20 19:01 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 12+ messages in thread
From: Shankar, Uma @ 2019-03-20 11:49 UTC (permalink / raw)
To: Kulkarni, Vandita, intel-gfx; +Cc: Nikula, Jani
>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Wednesday, March 20, 2019 3:39 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>Chauhan, Madhav <madhav.chauhan@intel.com>; Kulkarni, Vandita
><vandita.kulkarni@intel.com>
>Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
You can drop dsi from commit header. Just drm/i915/icl/ should be good.
Also update header as Ungate ddi clocks if gated
>
>IO enable sequencing needs ddi clocks enabled.
>These clocks will be gated at the later point in the enable sequence.
>
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>---
> drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index
>beb30d9..f02504d 100644
>--- a/drivers/gpu/drm/i915/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/icl_dsi.c
>@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
>*encoder,
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
>+ /* make sure that the ddi clocks are not gated */
>+ val = I915_READ(DPCLKA_CFGCR0_ICL);
>+ for_each_dsi_port(port, intel_dsi->ports) {
>+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>+ }
>+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
> POSTING_READ(DPCLKA_CFGCR0_ICL);
I think you can reuse the val from top and avoid an extra write to the same register.
Otherwise change looks ok to me. With above comments fixed,
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> mutex_unlock(&dev_priv->dpll_lock);
>--
>1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
2019-03-20 11:07 ` Imre Deak
@ 2019-03-20 12:02 ` Shankar, Uma
2019-03-21 13:57 ` Kulkarni, Vandita
2019-03-21 13:56 ` Kulkarni, Vandita
1 sibling, 1 reply; 12+ messages in thread
From: Shankar, Uma @ 2019-03-20 12:02 UTC (permalink / raw)
To: Deak, Imre, Kulkarni, Vandita; +Cc: Nikula, Jani, intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Imre
>Deak
>Sent: Wednesday, March 20, 2019 4:38 PM
>To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
>Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
You can drop the dsi from drm/i915/icl/. Add at description or commit header. Like
drm/i915/icl: Fix DSI port disable sequence
>
>On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
>> Re-enable clock gating of DDI clocks.
>>
>> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> b/drivers/gpu/drm/i915/icl_dsi.c index f02504d..716be38 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
>*encoder)
>> DRM_ERROR("DDI port:%c buffer not idle\n",
>> port_name(port));
>> }
>> - gen11_dsi_ungate_clocks(encoder);
>> + gen11_dsi_gate_clocks(encoder);
>
>This also requires updating icl_sanitize_encoder_pll_mapping().
>Currently it assumes that the DDI clock needs to be ungated if the corresponding DSI
>port is disabled and gated if the port is enabled.
>
>The changes in this patchset mean that the DDI clock should be gated for DSI ports
>regardless of whether the port is enabled or not.
I agree. This change look fine, but there is an issue there with
icl_sanitize_encoder_pll_mapping.
>> }
>>
>> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
@ 2019-03-20 14:28 ` Patchwork
2019-03-20 19:01 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-03-20 14:28 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12529
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58241/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12529 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-bsd2:
- fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182]
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841]
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (48 -> 42)
------------------------------
Additional (1): fi-kbl-7500u
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
Build changes
-------------
* Linux: CI_DRM_5780 -> Patchwork_12529
CI_DRM_5780: 774f8c588542dda6d73161429cbf1e027789d6ef @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12529: c02cf03dcc1a2a611ac8dcbda219882e1215f91f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c02cf03dcc1a drm/i915/icl/dsi: Fix port disable sequence
4aec4839ddd9 drm/i915/icl/dsi: Ungate clocks if gated
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12529/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
` (2 preceding siblings ...)
2019-03-20 14:28 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
@ 2019-03-20 19:01 ` Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-03-20 19:01 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12529_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12529_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@preempt-other-bsd2:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +22
* igt@gem_pwrite@big-cpu-fbr:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +135
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> FAIL [fdo#108686]
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@gem-mmap-cpu:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@i915_selftest@live_workarounds:
- shard-iclb: PASS -> DMESG-FAIL [fdo#108954]
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-f:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16
* igt@kms_busy@extended-pageflip-hang-newfb-render-e:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
- shard-skl: PASS -> FAIL [fdo#107791] / [fdo#108145]
* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_frontbuffer_tracking@basic:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: PASS -> INCOMPLETE [fdo#106978]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#109247] +14
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] +1
* igt@kms_psr@cursor_mmap_gtt:
- shard-iclb: PASS -> FAIL [fdo#107383] +2
* igt@kms_psr@cursor_plane_onoff:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +27
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: PASS -> SKIP [fdo#109441]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
* igt@perf_pmu@rc6-runtime-pm:
- shard-apl: PASS -> FAIL [fdo#105010]
* igt@prime_vgem@wait-bsd1:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +33
#### Possible fixes ####
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@modeset-lpsp:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +1
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-iclb: FAIL [fdo#103355] -> PASS
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: FAIL [fdo#105682] / [fdo#108040] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +7
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: FAIL [fdo#109247] -> PASS +11
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: SKIP [fdo#109441] -> PASS +4
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] -> PASS +3
#### Warnings ####
* igt@kms_concurrent@pipe-d:
- shard-apl: SKIP [fdo#109271] / [fdo#109278] -> INCOMPLETE [fdo#103927]
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: INCOMPLETE [fdo#103665] -> DMESG-FAIL [fdo#105763]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#110207]: https://bugs.freedesktop.org/show_bug.cgi?id=110207
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5780 -> Patchwork_12529
CI_DRM_5780: 774f8c588542dda6d73161429cbf1e027789d6ef @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12529: c02cf03dcc1a2a611ac8dcbda219882e1215f91f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12529/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
@ 2019-03-21 13:53 ` Kulkarni, Vandita
2019-03-22 7:48 ` Kulkarni, Vandita
0 siblings, 1 reply; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-03-21 13:53 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Shankar, Uma
> Sent: Wednesday, March 20, 2019 5:19 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>
>
>
> >-----Original Message-----
> >From: Kulkarni, Vandita
> >Sent: Wednesday, March 20, 2019 3:39 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> ><uma.shankar@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>;
> >Kulkarni, Vandita <vandita.kulkarni@intel.com>
> >Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>
> You can drop dsi from commit header. Just drm/i915/icl/ should be good.
> Also update header as Ungate ddi clocks if gated
Okay.
>
> >
> >IO enable sequencing needs ddi clocks enabled.
> >These clocks will be gated at the later point in the enable sequence.
> >
> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >---
> > drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> >b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..f02504d 100644
> >--- a/drivers/gpu/drm/i915/icl_dsi.c
> >+++ b/drivers/gpu/drm/i915/icl_dsi.c
> >@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
> >*encoder,
> > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> > }
> > I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> >+
> >+ /* make sure that the ddi clocks are not gated */
> >+ val = I915_READ(DPCLKA_CFGCR0_ICL);
> >+ for_each_dsi_port(port, intel_dsi->ports) {
> >+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> >+ }
> >+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> >+
> > POSTING_READ(DPCLKA_CFGCR0_ICL);
>
> I think you can reuse the val from top and avoid an extra write to the same
> register.
At this point we ideally have the clocks gated and we need to ungate it. We must write to this register.
Accordingly, will fix the commit header too.
Thanks.
Vandita
>
> Otherwise change looks ok to me. With above comments fixed,
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> >
> > mutex_unlock(&dev_priv->dpll_lock);
> >--
> >1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
2019-03-20 11:07 ` Imre Deak
2019-03-20 12:02 ` Shankar, Uma
@ 2019-03-21 13:56 ` Kulkarni, Vandita
1 sibling, 0 replies; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-03-21 13:56 UTC (permalink / raw)
To: Deak, Imre; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Deak, Imre
> Sent: Wednesday, March 20, 2019 4:38 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
>
> On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> > Re-enable clock gating of DDI clocks.
> >
> > Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > b/drivers/gpu/drm/i915/icl_dsi.c index f02504d..716be38 100644
> > --- a/drivers/gpu/drm/i915/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/icl_dsi.c
> > @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct
> intel_encoder *encoder)
> > DRM_ERROR("DDI port:%c buffer not idle\n",
> > port_name(port));
> > }
> > - gen11_dsi_ungate_clocks(encoder);
> > + gen11_dsi_gate_clocks(encoder);
>
> This also requires updating icl_sanitize_encoder_pll_mapping().
Thank you. Will send the fix in v2.
-Vandita
> Currently it assumes that the DDI clock needs to be ungated if the corresponding
> DSI port is disabled and gated if the port is enabled.
>
> The changes in this patchset mean that the DDI clock should be gated for DSI
> ports regardless of whether the port is enabled or not.
>
> > }
> >
> > static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
2019-03-20 12:02 ` Shankar, Uma
@ 2019-03-21 13:57 ` Kulkarni, Vandita
0 siblings, 0 replies; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-03-21 13:57 UTC (permalink / raw)
To: Shankar, Uma, Deak, Imre; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Shankar, Uma
> Sent: Wednesday, March 20, 2019 5:32 PM
> To: Deak, Imre <imre.deak@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
>
>
>
> >-----Original Message-----
> >From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
> >Behalf Of Imre Deak
> >Sent: Wednesday, March 20, 2019 4:38 PM
> >To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> >Cc: Nikula, Jani <jani.nikula@intel.com>;
> >intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable
> >sequence
>
> You can drop the dsi from drm/i915/icl/. Add at description or commit header.
> Like
> drm/i915/icl: Fix DSI port disable sequence
Okay.
>
> >
> >On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> >> Re-enable clock gating of DDI clocks.
> >>
> >> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> >> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> >> b/drivers/gpu/drm/i915/icl_dsi.c index f02504d..716be38 100644
> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> >> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct
> >> intel_encoder
> >*encoder)
> >> DRM_ERROR("DDI port:%c buffer not idle\n",
> >> port_name(port));
> >> }
> >> - gen11_dsi_ungate_clocks(encoder);
> >> + gen11_dsi_gate_clocks(encoder);
> >
> >This also requires updating icl_sanitize_encoder_pll_mapping().
> >Currently it assumes that the DDI clock needs to be ungated if the
> >corresponding DSI port is disabled and gated if the port is enabled.
> >
> >The changes in this patchset mean that the DDI clock should be gated
> >for DSI ports regardless of whether the port is enabled or not.
>
> I agree. This change look fine, but there is an issue there with
> icl_sanitize_encoder_pll_mapping.
Thank you. Will send the fix in V2.
-Vandita
>
> >> }
> >>
> >> static void gen11_dsi_disable_io_power(struct intel_encoder
> >> *encoder)
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-21 13:53 ` Kulkarni, Vandita
@ 2019-03-22 7:48 ` Kulkarni, Vandita
2019-03-22 8:18 ` Shankar, Uma
0 siblings, 1 reply; 12+ messages in thread
From: Kulkarni, Vandita @ 2019-03-22 7:48 UTC (permalink / raw)
To: Shankar, Uma, 'intel-gfx@lists.freedesktop.org'; +Cc: Nikula, Jani
> -----Original Message-----
> From: Kulkarni, Vandita
> Sent: Thursday, March 21, 2019 7:23 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>
>
> > -----Original Message-----
> > From: Shankar, Uma
> > Sent: Wednesday, March 20, 2019 5:19 PM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> > <madhav.chauhan@intel.com>
> > Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
> >
> >
> >
> > >-----Original Message-----
> > >From: Kulkarni, Vandita
> > >Sent: Wednesday, March 20, 2019 3:39 PM
> > >To: intel-gfx@lists.freedesktop.org
> > >Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> > ><uma.shankar@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>;
> > >Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > >Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
> >
> > You can drop dsi from commit header. Just drm/i915/icl/ should be good.
> > Also update header as Ungate ddi clocks if gated
> Okay.
> >
> > >
> > >IO enable sequencing needs ddi clocks enabled.
> > >These clocks will be gated at the later point in the enable sequence.
> > >
> > >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > >---
> > > drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > >diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> > >b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..f02504d 100644
> > >--- a/drivers/gpu/drm/i915/icl_dsi.c
> > >+++ b/drivers/gpu/drm/i915/icl_dsi.c
> > >@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct
> > >intel_encoder *encoder,
> > > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> > > }
> > > I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> > >+
> > >+ /* make sure that the ddi clocks are not gated */
> > >+ val = I915_READ(DPCLKA_CFGCR0_ICL);
> > >+ for_each_dsi_port(port, intel_dsi->ports) {
> > >+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> > >+ }
> > >+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> > >+
> > > POSTING_READ(DPCLKA_CFGCR0_ICL);
> >
> > I think you can reuse the val from top and avoid an extra write to the
> > same register.
> At this point we ideally have the clocks gated and we need to ungate it. We must
> write to this register.
> Accordingly, will fix the commit header too.
As per the spec, 2 different writes are needed for mapping and turning on the clocks.
Thanks,
Vandita
>
> Thanks.
> Vandita
> >
> > Otherwise change looks ok to me. With above comments fixed,
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> >
> > >
> > > mutex_unlock(&dev_priv->dpll_lock);
> > >--
> > >1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
2019-03-22 7:48 ` Kulkarni, Vandita
@ 2019-03-22 8:18 ` Shankar, Uma
0 siblings, 0 replies; 12+ messages in thread
From: Shankar, Uma @ 2019-03-22 8:18 UTC (permalink / raw)
To: Kulkarni, Vandita, 'intel-gfx@lists.freedesktop.org'; +Cc: Nikula, Jani
>> -----Original Message-----
>> From: Kulkarni, Vandita
>> Sent: Thursday, March 21, 2019 7:23 PM
>> To: Shankar, Uma <uma.shankar@intel.com>;
>> intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
>> <madhav.chauhan@intel.com>
>> Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>>
>>
>> > -----Original Message-----
>> > From: Shankar, Uma
>> > Sent: Wednesday, March 20, 2019 5:19 PM
>> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> > gfx@lists.freedesktop.org
>> > Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
>> > <madhav.chauhan@intel.com>
>> > Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>> >
>> >
>> >
>> > >-----Original Message-----
>> > >From: Kulkarni, Vandita
>> > >Sent: Wednesday, March 20, 2019 3:39 PM
>> > >To: intel-gfx@lists.freedesktop.org
>> > >Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
>> > ><uma.shankar@intel.com>; Chauhan, Madhav
>> <madhav.chauhan@intel.com>;
>> > >Kulkarni, Vandita <vandita.kulkarni@intel.com>
>> > >Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>> >
>> > You can drop dsi from commit header. Just drm/i915/icl/ should be good.
>> > Also update header as Ungate ddi clocks if gated
>> Okay.
>> >
>> > >
>> > >IO enable sequencing needs ddi clocks enabled.
>> > >These clocks will be gated at the later point in the enable sequence.
>> > >
>> > >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > >---
>> > > drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
>> > > 1 file changed, 8 insertions(+)
>> > >
>> > >diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> > >b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..f02504d 100644
>> > >--- a/drivers/gpu/drm/i915/icl_dsi.c
>> > >+++ b/drivers/gpu/drm/i915/icl_dsi.c
>> > >@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct
>> > >intel_encoder *encoder,
>> > > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>> > > }
>> > > I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>> > >+
>> > >+ /* make sure that the ddi clocks are not gated */
>> > >+ val = I915_READ(DPCLKA_CFGCR0_ICL);
>> > >+ for_each_dsi_port(port, intel_dsi->ports) {
>> > >+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>> > >+ }
>> > >+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>> > >+
>> > > POSTING_READ(DPCLKA_CFGCR0_ICL);
>> >
>> > I think you can reuse the val from top and avoid an extra write to
>> > the same register.
>> At this point we ideally have the clocks gated and we need to ungate
>> it. We must write to this register.
>> Accordingly, will fix the commit header too.
>As per the spec, 2 different writes are needed for mapping and turning on the clocks.
Oh ok, yes seems like indeed spec expects separate write for individual steps.
Thanks for the pointing out. You can keep the current change and my RB.
Regards,
Uma Shankar
>Thanks,
>Vandita
>
>>
>> Thanks.
>> Vandita
>> >
>> > Otherwise change looks ok to me. With above comments fixed,
>> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> >
>> > >
>> > > mutex_unlock(&dev_priv->dpll_lock);
>> > >--
>> > >1.9.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-03-22 8:18 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
2019-03-20 11:07 ` Imre Deak
2019-03-20 12:02 ` Shankar, Uma
2019-03-21 13:57 ` Kulkarni, Vandita
2019-03-21 13:56 ` Kulkarni, Vandita
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
2019-03-21 13:53 ` Kulkarni, Vandita
2019-03-22 7:48 ` Kulkarni, Vandita
2019-03-22 8:18 ` Shankar, Uma
2019-03-20 14:28 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-03-20 19:01 ` ✓ Fi.CI.IGT: " Patchwork
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