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* [PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block
@ 2020-01-24 20:02 ` Ville Syrjala
  0 siblings, 0 replies; 67+ messages in thread
From: Ville Syrjala @ 2020-01-24 20:02 UTC (permalink / raw)
  To: dri-devel; +Cc: Allen Chen, intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CEA-861 says :
"d = offset for the byte following the reserved data block.
 If no data is provided in the reserved data block, then d=4.
 If no DTDs are provided, then d=0."

So let's not look for DTDs when d==0. In fact let's just make that
<4 since those values would just mean that he DTDs overlap the block
header. And let's also check that d isn't so big as to declare
the descriptors to live past the block end, although the code
does already survive that case as we'd just end up with a negative
number of descriptors and the loop would not do anything.

Cc: Allen Chen <allen.chen@ite.com.tw>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_edid.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 99769d6c9f84..1b6e544cf5c7 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2201,10 +2201,13 @@ typedef void detailed_cb(struct detailed_timing *timing, void *closure);
 static void
 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
 {
-	int i, n = 0;
+	int i, n;
 	u8 d = ext[0x02];
 	u8 *det_base = ext + d;
 
+	if (d < 4 || d > 127)
+		return;
+
 	n = (127 - d) / 18;
 	for (i = 0; i < n; i++)
 		cb((struct detailed_timing *)(det_base + 18 * i), closure);
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 67+ messages in thread

end of thread, other threads:[~2020-02-04 14:57 UTC | newest]

Thread overview: 67+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-24 20:02 [PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block Ville Syrjala
2020-01-24 20:02 ` [Intel-gfx] " Ville Syrjala
2020-01-24 20:02 ` [PATCH 2/8] drm/edid: Don't accept any old garbage as a display descriptor Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:35   ` Alex Deucher
2020-01-27 22:35     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:44     ` Shankar, Uma
2020-02-03 19:44       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 3/8] drm/edid: Introduce is_detailed_timing_descritor() Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:36   ` Alex Deucher
2020-01-27 22:36     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:49     ` Shankar, Uma
2020-02-03 19:49       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 4/8] drm/i915: Clear out spurious whitespace Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:28   ` Alex Deucher
2020-01-27 22:28     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:51     ` Shankar, Uma
2020-02-03 19:51       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:30   ` Alex Deucher
2020-01-27 22:30     ` [Intel-gfx] " Alex Deucher
2020-01-28 11:44     ` Ville Syrjälä
2020-01-28 11:44       ` [Intel-gfx] " Ville Syrjälä
2020-02-03 19:58       ` Shankar, Uma
2020-02-03 19:58         ` [Intel-gfx] " Shankar, Uma
2020-01-24 20:02 ` [PATCH 6/8] drm/edid: Add a FIXME about DispID CEA data block revision Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:32   ` Alex Deucher
2020-01-27 22:32     ` [Intel-gfx] " Alex Deucher
2020-02-03 20:15   ` Shankar, Uma
2020-02-03 20:15     ` Shankar, Uma
2020-02-04 13:32     ` Ville Syrjälä
2020-02-04 13:32       ` Ville Syrjälä
2020-02-04 14:57       ` Shankar, Uma
2020-02-04 14:57         ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 7/8] drm/edid: Constify lots of things Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:38   ` Alex Deucher
2020-01-27 22:38     ` [Intel-gfx] " Alex Deucher
2020-01-28 11:49     ` Ville Syrjälä
2020-01-28 11:49       ` [Intel-gfx] " Ville Syrjälä
2020-02-03 20:34       ` Shankar, Uma
2020-02-03 20:34         ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 8/8] drm/edid: Dump bogus 18 byte descriptors Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:38   ` Alex Deucher
2020-01-27 22:38     ` [Intel-gfx] " Alex Deucher
2020-02-03 20:38     ` Shankar, Uma
2020-02-03 20:38       ` Shankar, Uma
2020-01-24 22:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block Patchwork
2020-01-24 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-27 13:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-27 22:34 ` [PATCH 1/8] " Alex Deucher
2020-01-27 22:34   ` [Intel-gfx] " Alex Deucher
2020-02-03 19:15   ` Shankar, Uma
2020-02-03 19:15     ` [Intel-gfx] " Shankar, Uma
2020-01-28 15:17 ` Daniel Vetter
2020-01-28 15:17   ` [Intel-gfx] " Daniel Vetter
2020-01-28 16:15   ` Ville Syrjälä
2020-01-28 16:15     ` [Intel-gfx] " Ville Syrjälä
2020-01-28 16:18     ` Daniel Vetter
2020-01-28 16:18       ` [Intel-gfx] " Daniel Vetter
2020-01-28 16:28       ` Ville Syrjälä
2020-01-28 16:28         ` [Intel-gfx] " Ville Syrjälä

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