[PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We already handle the color encoding mode properly. Remove the broken
NV12 special case.

Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f5c078c9d0d2..42c1f4a56556 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3643,11 +3643,6 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
 
 	if (intel_format_is_yuv(fb->format->format)) {
-		if (fb->format->format == DRM_FORMAT_NV12) {
-			plane_color_ctl |=
-				PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
-			goto out;
-		}
 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 		else
@@ -3656,7 +3651,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 	}
-out:
+
 	return plane_color_ctl;
 }
 
-- 
2.16.1

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[PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Set up the SKL+ scaler initial phase registers correctly. Otherwise
we start fetching the data from the center of the first pixel instead
of the top-left corner, which obviously then leads to right/bottom edges
replicating data excessively as the data runs out half a pixel too soon.

Cc: Vidya Srinivas <vidya.srinivas@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
 drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++++++++++++++++++--
 4 files changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb79272..094527403ede 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6774,6 +6774,10 @@ enum {
 #define _PS_VPHASE_1B       0x68988
 #define _PS_VPHASE_2B       0x68A88
 #define _PS_VPHASE_1C       0x69188
+#define  PS_Y_PHASE(x)		((x) << 16)
+#define  PS_UV_RGB_PHASE(x)	((x) << 0)
+#define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
+#define   PS_PHASE_TRIP	(1 << 0)
 
 #define _PS_HPHASE_1A       0x68194
 #define _PS_HPHASE_2A       0x68294
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42c1f4a56556..07185644a88a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4729,6 +4729,39 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 	}
 }
 
+/*
+ * The hardware phase 0.0 refers to the center of the pixel.
+ * We want to start from the top/left edge which is phase
+ * -0.5. That matches how the hardware calculates the scaling
+ * factors (from top-left of the first pixel to bottom-right
+ * of the last pixel, as opposed to the pixel centers).
+ *
+ * For 4:2:0 subsampled chroma planes we obviously have to
+ * adjust that so that the chroma sample position lands in
+ * the right spot.
+ *
+ * Note that for packed YCbCr 4:2:2 formats there is no way to
+ * control chroma siting. The hardware simply replicates the
+ * chroma samples for both of the luma samples, and thus we don't
+ * actually get the expected MPEG2 chroma siting convention :(
+ * The same behaviour is observed on pre-SKL platforms as well.
+ */
+u16 skl_scaler_calc_phase(int sub, bool chroma_cosited)
+{
+	int phase = -0x8000;
+	u16 trip = 0;
+
+	if (chroma_cosited)
+		phase += (sub - 1) * 0x8000 / sub;
+
+	if (phase < 0)
+		phase = 0x10000 + phase;
+	else
+		trip = PS_PHASE_TRIP;
+
+	return ((phase >> 2) & PS_PHASE_MASK) | trip;
+}
+
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		  unsigned int scaler_user, int *scaler_id,
@@ -4928,14 +4961,22 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
 		&crtc->config->scaler_state;
 
 	if (crtc->config->pch_pfit.enabled) {
+		u16 uv_rgb_hphase, uv_rgb_vphase;
 		int id;
 
 		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
 			return;
 
+		uv_rgb_hphase = skl_scaler_calc_phase(1, false);
+		uv_rgb_vphase = skl_scaler_calc_phase(1, false);
+
 		id = scaler_state->scaler_id;
 		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
 			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+		I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
+			      PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+		I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
+			      PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 42a59b7fd736..0f1dbfcf8538 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1621,6 +1621,7 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 				  struct intel_crtc_state *crtc_state);
 
+u16 skl_scaler_calc_phase(int sub, bool chroma_center);
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 		  uint32_t pixel_format);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 214cc730642c..58522441253d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -284,13 +284,35 @@ skl_update_plane(struct intel_plane *plane,
 	/* program plane scaler */
 	if (plane_state->scaler_id >= 0) {
 		int scaler_id = plane_state->scaler_id;
-		const struct intel_scaler *scaler;
+		const struct intel_scaler *scaler =
+			&crtc_state->scaler_state.scalers[scaler_id];
+		u16 y_hphase, uv_rgb_hphase;
+		u16 y_vphase, uv_rgb_vphase;
+
+		/* TODO: handle sub-pixel coordinates */
+		if (fb->format->format == DRM_FORMAT_NV12) {
+			y_hphase = skl_scaler_calc_phase(1, false);
+			y_vphase = skl_scaler_calc_phase(1, false);
+
+			/* MPEG2 chroma siting convention */
+			uv_rgb_hphase = skl_scaler_calc_phase(2, true);
+			uv_rgb_vphase = skl_scaler_calc_phase(2, false);
+		} else {
+			/* not used */
+			y_hphase = 0;
+			y_vphase = 0;
 
-		scaler = &crtc_state->scaler_state.scalers[scaler_id];
+			uv_rgb_hphase = skl_scaler_calc_phase(1, false);
+			uv_rgb_vphase = skl_scaler_calc_phase(1, false);
+		}
 
 		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
 			      PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
+		I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
+			      PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+		I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
+			      PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
 		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
 			      ((crtc_w + 1) << 16)|(crtc_h + 1));
-- 
2.16.1

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup
URL   : https://patchwork.freedesktop.org/series/43531/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4213 -> Patchwork_9072 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9072 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9072, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43531/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9072:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9072 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cfl-s3:          PASS -> FAIL (fdo#100368)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       PASS -> DMESG-FAIL (fdo#106103, fdo#102614)

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 38) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-cnl-y3 fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4213 -> Patchwork_9072

  CI_DRM_4213: d7671eea834c4e06f9b86e2248581d23ad98ec73 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9072: dfe6bfb2ba8e010dfbeee4c62c857e5d344123f5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit


== Linux commits ==

dfe6bfb2ba8e drm/i915: Configure SKL+ scaler initial phase correctly
add70e8c7fbe drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9072/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup
URL   : https://patchwork.freedesktop.org/series/43531/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4213_full -> Patchwork_9072_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9072_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9072_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43531/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9072_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd1:
      shard-kbl:          SKIP -> PASS

    igt@gem_exec_schedule@deep-vebox:
      shard-kbl:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9072_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-glk:          PASS -> FAIL (fdo#105703)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          PASS -> FAIL (fdo#106509, fdo#105454)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#105363)

    igt@kms_setmode@basic:
      shard-hsw:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          DMESG-FAIL (fdo#106560) -> PASS

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          FAIL (fdo#105703) -> PASS

    igt@kms_flip@2x-blocking-wf_vblank:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-hsw:          FAIL (fdo#102887) -> PASS

    igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_flip@dpms-vs-vblank-race:
      shard-hsw:          FAIL (fdo#103060) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
      shard-snb:          FAIL (fdo#104724, fdo#103167) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4213 -> Patchwork_9072

  CI_DRM_4213: d7671eea834c4e06f9b86e2248581d23ad98ec73 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9072: dfe6bfb2ba8e010dfbeee4c62c857e5d344123f5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9072/shards.html
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Re: [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Jani Nikula]

On Mon, 21 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already handle the color encoding mode properly. Remove the broken
> NV12 special case.
>
> Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

For both patches, Fixes: ?

The deadline for v4.18 just passed, so this won't follow the nv12
enabling without it.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f5c078c9d0d2..42c1f4a56556 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3643,11 +3643,6 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
>  
>  	if (intel_format_is_yuv(fb->format->format)) {
> -		if (fb->format->format == DRM_FORMAT_NV12) {
> -			plane_color_ctl |=
> -				PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> -			goto out;
> -		}
>  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
>  			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>  		else
> @@ -3656,7 +3651,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
>  		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
>  			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>  	}
> -out:
> +
>  	return plane_color_ctl;
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Ville Syrjälä]

On Tue, May 22, 2018 at 01:16:59PM +0300, Jani Nikula wrote:
> On Mon, 21 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We already handle the color encoding mode properly. Remove the broken
> > NV12 special case.
> >
> > Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For both patches, Fixes: ?
> 
> The deadline for v4.18 just passed, so this won't follow the nv12
> enabling without it.

Yeah, I suppose we want the nv12 fix in asap. The initial phase thing
might event want cc:stable, although no one has actually complained
about the problem afaik.

> 
> BR,
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 7 +------
> >  1 file changed, 1 insertion(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f5c078c9d0d2..42c1f4a56556 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3643,11 +3643,6 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >  	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> >  
> >  	if (intel_format_is_yuv(fb->format->format)) {
> > -		if (fb->format->format == DRM_FORMAT_NV12) {
> > -			plane_color_ctl |=
> > -				PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> > -			goto out;
> > -		}
> >  		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> >  			plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> >  		else
> > @@ -3656,7 +3651,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> >  		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> >  			plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> >  	}
> > -out:
> > +
> >  	return plane_color_ctl;
> >  }
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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Re: [PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly

[Srinivas, Vidya]

Thank you.
Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>

> -----Original Message-----
> From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> Sent: Tuesday, May 22, 2018 12:26 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srinivas, Vidya <vidya.srinivas@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: [PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Set up the SKL+ scaler initial phase registers correctly. Otherwise we start
> fetching the data from the center of the first pixel instead of the top-left
> corner, which obviously then leads to right/bottom edges replicating data
> excessively as the data runs out half a pixel too soon.
> 
> Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
>  drivers/gpu/drm/i915/intel_display.c | 41
> ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |  1 +
>  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++++++++++++++++++--
>  4 files changed, 70 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 196a0eb79272..094527403ede
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6774,6 +6774,10 @@ enum {
>  #define _PS_VPHASE_1B       0x68988
>  #define _PS_VPHASE_2B       0x68A88
>  #define _PS_VPHASE_1C       0x69188
> +#define  PS_Y_PHASE(x)		((x) << 16)
> +#define  PS_UV_RGB_PHASE(x)	((x) << 0)
> +#define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
> +#define   PS_PHASE_TRIP	(1 << 0)
> 
>  #define _PS_HPHASE_1A       0x68194
>  #define _PS_HPHASE_2A       0x68294
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 42c1f4a56556..07185644a88a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4729,6 +4729,39 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
>  	}
>  }
> 
> +/*
> + * The hardware phase 0.0 refers to the center of the pixel.
> + * We want to start from the top/left edge which is phase
> + * -0.5. That matches how the hardware calculates the scaling
> + * factors (from top-left of the first pixel to bottom-right
> + * of the last pixel, as opposed to the pixel centers).
> + *
> + * For 4:2:0 subsampled chroma planes we obviously have to
> + * adjust that so that the chroma sample position lands in
> + * the right spot.
> + *
> + * Note that for packed YCbCr 4:2:2 formats there is no way to
> + * control chroma siting. The hardware simply replicates the
> + * chroma samples for both of the luma samples, and thus we don't
> + * actually get the expected MPEG2 chroma siting convention :(
> + * The same behaviour is observed on pre-SKL platforms as well.
> + */
> +u16 skl_scaler_calc_phase(int sub, bool chroma_cosited) {
> +	int phase = -0x8000;
> +	u16 trip = 0;
> +
> +	if (chroma_cosited)
> +		phase += (sub - 1) * 0x8000 / sub;
> +
> +	if (phase < 0)
> +		phase = 0x10000 + phase;
> +	else
> +		trip = PS_PHASE_TRIP;
> +
> +	return ((phase >> 2) & PS_PHASE_MASK) | trip; }
> +
>  static int
>  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  		  unsigned int scaler_user, int *scaler_id, @@ -4928,14
> +4961,22 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
>  		&crtc->config->scaler_state;
> 
>  	if (crtc->config->pch_pfit.enabled) {
> +		u16 uv_rgb_hphase, uv_rgb_vphase;
>  		int id;
> 
>  		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
>  			return;
> 
> +		uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> +		uv_rgb_vphase = skl_scaler_calc_phase(1, false);
> +
>  		id = scaler_state->scaler_id;
>  		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
>  			PS_FILTER_MEDIUM | scaler_state-
> >scalers[id].mode);
> +		I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
> +			      PS_Y_PHASE(0) |
> PS_UV_RGB_PHASE(uv_rgb_vphase));
> +		I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
> +			      PS_Y_PHASE(0) |
> PS_UV_RGB_PHASE(uv_rgb_hphase));
>  		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config-
> >pch_pfit.pos);
>  		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config-
> >pch_pfit.size);
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 42a59b7fd736..0f1dbfcf8538 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1621,6 +1621,7 @@ void intel_mode_from_pipe_config(struct
> drm_display_mode *mode,  void intel_crtc_arm_fifo_underrun(struct
> intel_crtc *crtc,
>  				  struct intel_crtc_state *crtc_state);
> 
> +u16 skl_scaler_calc_phase(int sub, bool chroma_center);
>  int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);  int
> skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  		  uint32_t pixel_format);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 214cc730642c..58522441253d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -284,13 +284,35 @@ skl_update_plane(struct intel_plane *plane,
>  	/* program plane scaler */
>  	if (plane_state->scaler_id >= 0) {
>  		int scaler_id = plane_state->scaler_id;
> -		const struct intel_scaler *scaler;
> +		const struct intel_scaler *scaler =
> +			&crtc_state->scaler_state.scalers[scaler_id];
> +		u16 y_hphase, uv_rgb_hphase;
> +		u16 y_vphase, uv_rgb_vphase;
> +
> +		/* TODO: handle sub-pixel coordinates */
> +		if (fb->format->format == DRM_FORMAT_NV12) {
> +			y_hphase = skl_scaler_calc_phase(1, false);
> +			y_vphase = skl_scaler_calc_phase(1, false);
> +
> +			/* MPEG2 chroma siting convention */
> +			uv_rgb_hphase = skl_scaler_calc_phase(2, true);
> +			uv_rgb_vphase = skl_scaler_calc_phase(2, false);
> +		} else {
> +			/* not used */
> +			y_hphase = 0;
> +			y_vphase = 0;
> 
> -		scaler = &crtc_state->scaler_state.scalers[scaler_id];
> +			uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> +			uv_rgb_vphase = skl_scaler_calc_phase(1, false);
> +		}
> 
>  		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
>  			      PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
> scaler->mode);
>  		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
> +		I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
> +			      PS_Y_PHASE(y_vphase) |
> PS_UV_RGB_PHASE(uv_rgb_vphase));
> +		I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
> +			      PS_Y_PHASE(y_hphase) |
> PS_UV_RGB_PHASE(uv_rgb_hphase));
>  		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x
> << 16) | crtc_y);
>  		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
>  			      ((crtc_w + 1) << 16)|(crtc_h + 1));
> --
> 2.16.1

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Re: [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL setup

[Srinivas, Vidya]

Thank you.
Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>

> -----Original Message-----
> From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> Sent: Tuesday, May 22, 2018 12:26 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srinivas, Vidya <vidya.srinivas@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: [PATCH 1/2] drm/i915: Remove bogus NV12 PLANE_COLOR_CTL
> setup
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We already handle the color encoding mode properly. Remove the broken
> NV12 special case.
> 
> Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index f5c078c9d0d2..42c1f4a56556 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3643,11 +3643,6 @@ u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
>  	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> 
>  	if (intel_format_is_yuv(fb->format->format)) {
> -		if (fb->format->format == DRM_FORMAT_NV12) {
> -			plane_color_ctl |=
> -
> 	PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> -			goto out;
> -		}
>  		if (plane_state->base.color_encoding ==
> DRM_COLOR_YCBCR_BT709)
>  			plane_color_ctl |=
> PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>  		else
> @@ -3656,7 +3651,7 @@ u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
>  		if (plane_state->base.color_range ==
> DRM_COLOR_YCBCR_FULL_RANGE)
>  			plane_color_ctl |=
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
>  	}
> -out:
> +
>  	return plane_color_ctl;
>  }
> 
> --
> 2.16.1

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Re: [PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly

[Ville Syrjälä]

On Thu, May 31, 2018 at 04:20:24AM +0000, Srinivas, Vidya wrote:
> Thank you.
> Reviewed-By: Vidya Srinivas <vidya.srinivas@intel.com>

Thanks. Series pushed to dinq.

> 
> > -----Original Message-----
> > From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> > Sent: Tuesday, May 22, 2018 12:26 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Srinivas, Vidya <vidya.srinivas@intel.com>; Maarten Lankhorst
> > <maarten.lankhorst@linux.intel.com>
> > Subject: [PATCH 2/2] drm/i915: Configure SKL+ scaler initial phase correctly
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Set up the SKL+ scaler initial phase registers correctly. Otherwise we start
> > fetching the data from the center of the first pixel instead of the top-left
> > corner, which obviously then leads to right/bottom edges replicating data
> > excessively as the data runs out half a pixel too soon.
> > 
> > Cc: Vidya Srinivas <vidya.srinivas@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
> >  drivers/gpu/drm/i915/intel_display.c | 41
> > ++++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h     |  1 +
> >  drivers/gpu/drm/i915/intel_sprite.c  | 26 +++++++++++++++++++++--
> >  4 files changed, 70 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 196a0eb79272..094527403ede
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6774,6 +6774,10 @@ enum {
> >  #define _PS_VPHASE_1B       0x68988
> >  #define _PS_VPHASE_2B       0x68A88
> >  #define _PS_VPHASE_1C       0x69188
> > +#define  PS_Y_PHASE(x)		((x) << 16)
> > +#define  PS_UV_RGB_PHASE(x)	((x) << 0)
> > +#define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
> > +#define   PS_PHASE_TRIP	(1 << 0)
> > 
> >  #define _PS_HPHASE_1A       0x68194
> >  #define _PS_HPHASE_2A       0x68294
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 42c1f4a56556..07185644a88a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4729,6 +4729,39 @@ static void cpt_verify_modeset(struct
> > drm_device *dev, int pipe)
> >  	}
> >  }
> > 
> > +/*
> > + * The hardware phase 0.0 refers to the center of the pixel.
> > + * We want to start from the top/left edge which is phase
> > + * -0.5. That matches how the hardware calculates the scaling
> > + * factors (from top-left of the first pixel to bottom-right
> > + * of the last pixel, as opposed to the pixel centers).
> > + *
> > + * For 4:2:0 subsampled chroma planes we obviously have to
> > + * adjust that so that the chroma sample position lands in
> > + * the right spot.
> > + *
> > + * Note that for packed YCbCr 4:2:2 formats there is no way to
> > + * control chroma siting. The hardware simply replicates the
> > + * chroma samples for both of the luma samples, and thus we don't
> > + * actually get the expected MPEG2 chroma siting convention :(
> > + * The same behaviour is observed on pre-SKL platforms as well.
> > + */
> > +u16 skl_scaler_calc_phase(int sub, bool chroma_cosited) {
> > +	int phase = -0x8000;
> > +	u16 trip = 0;
> > +
> > +	if (chroma_cosited)
> > +		phase += (sub - 1) * 0x8000 / sub;
> > +
> > +	if (phase < 0)
> > +		phase = 0x10000 + phase;
> > +	else
> > +		trip = PS_PHASE_TRIP;
> > +
> > +	return ((phase >> 2) & PS_PHASE_MASK) | trip; }
> > +
> >  static int
> >  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> >  		  unsigned int scaler_user, int *scaler_id, @@ -4928,14
> > +4961,22 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
> >  		&crtc->config->scaler_state;
> > 
> >  	if (crtc->config->pch_pfit.enabled) {
> > +		u16 uv_rgb_hphase, uv_rgb_vphase;
> >  		int id;
> > 
> >  		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
> >  			return;
> > 
> > +		uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> > +		uv_rgb_vphase = skl_scaler_calc_phase(1, false);
> > +
> >  		id = scaler_state->scaler_id;
> >  		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> >  			PS_FILTER_MEDIUM | scaler_state-
> > >scalers[id].mode);
> > +		I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
> > +			      PS_Y_PHASE(0) |
> > PS_UV_RGB_PHASE(uv_rgb_vphase));
> > +		I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
> > +			      PS_Y_PHASE(0) |
> > PS_UV_RGB_PHASE(uv_rgb_hphase));
> >  		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config-
> > >pch_pfit.pos);
> >  		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config-
> > >pch_pfit.size);
> >  	}
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 42a59b7fd736..0f1dbfcf8538 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1621,6 +1621,7 @@ void intel_mode_from_pipe_config(struct
> > drm_display_mode *mode,  void intel_crtc_arm_fifo_underrun(struct
> > intel_crtc *crtc,
> >  				  struct intel_crtc_state *crtc_state);
> > 
> > +u16 skl_scaler_calc_phase(int sub, bool chroma_center);
> >  int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);  int
> > skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> >  		  uint32_t pixel_format);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 214cc730642c..58522441253d 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -284,13 +284,35 @@ skl_update_plane(struct intel_plane *plane,
> >  	/* program plane scaler */
> >  	if (plane_state->scaler_id >= 0) {
> >  		int scaler_id = plane_state->scaler_id;
> > -		const struct intel_scaler *scaler;
> > +		const struct intel_scaler *scaler =
> > +			&crtc_state->scaler_state.scalers[scaler_id];
> > +		u16 y_hphase, uv_rgb_hphase;
> > +		u16 y_vphase, uv_rgb_vphase;
> > +
> > +		/* TODO: handle sub-pixel coordinates */
> > +		if (fb->format->format == DRM_FORMAT_NV12) {
> > +			y_hphase = skl_scaler_calc_phase(1, false);
> > +			y_vphase = skl_scaler_calc_phase(1, false);
> > +
> > +			/* MPEG2 chroma siting convention */
> > +			uv_rgb_hphase = skl_scaler_calc_phase(2, true);
> > +			uv_rgb_vphase = skl_scaler_calc_phase(2, false);
> > +		} else {
> > +			/* not used */
> > +			y_hphase = 0;
> > +			y_vphase = 0;
> > 
> > -		scaler = &crtc_state->scaler_state.scalers[scaler_id];
> > +			uv_rgb_hphase = skl_scaler_calc_phase(1, false);
> > +			uv_rgb_vphase = skl_scaler_calc_phase(1, false);
> > +		}
> > 
> >  		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
> >  			      PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
> > scaler->mode);
> >  		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
> > +		I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
> > +			      PS_Y_PHASE(y_vphase) |
> > PS_UV_RGB_PHASE(uv_rgb_vphase));
> > +		I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
> > +			      PS_Y_PHASE(y_hphase) |
> > PS_UV_RGB_PHASE(uv_rgb_hphase));
> >  		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x
> > << 16) | crtc_y);
> >  		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
> >  			      ((crtc_w + 1) << 16)|(crtc_h + 1));
> > --
> > 2.16.1
> 

-- 
Ville Syrjälä
Intel
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