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From: Yassine Oudjana <y.oudjana@protonmail.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Android Kernel Team <kernel-team@android.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Vincent Whitchurch <vincent.whitchurch@axis.com>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
Date: Wed, 07 Jul 2021 08:24:16 +0000	[thread overview]
Message-ID: <M0wGhzKTDUUYQPjRdiabG3xuKLx8p19uB1iqdkwfa8Op45i4zBGm4mpcHIxpYzWkJLiUM6JtQIDuBVyLlXtPhrlPyycbhZ2GO1ldLymA40g=@protonmail.com> (raw)
In-Reply-To: <CAK8P3a1rtXTtGQ_Q7eg2SOrYa_OhSWPWFiS8m=oSb_GU1uUNXQ@mail.gmail.com>

On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@protonmail.com wrote:
> > ...
>
> This is still somewhat inconclusive, but it does give some hope. The data that
>
> I found on random web sites was
>
> -   32KB L1, 2MB/1MB L2 [1][2]
> -   16KB L1, 1.5MB L2 [3]
> -   32KB L1, 1MB/512KB L2 [4]
>
>     so none of the sizes really line up. My best guess is that the actual hierarchy
>     1MB per-core L2 cache on the two big CPU, 512KB per-core L2 cache on
>     the two little ones, but no shared L2 or L3. The older Krait had a 4KB L0
>     cache, which could explain the 512-byte L1 output.
>
>     Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64
>     byte L1 line size that the 'cache' test reported?
>
>     Arnd
>
>     [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_processors#Snapdragon_820_and_821_(2016)
>     [2] https://en.wikipedia.org/wiki/Kryo
>     [3] https://www.geektopia.es/es/product/qualcomm/snapdragon-820/
>     [4] https://www.anandtech.com/show/9837/snapdragon-820-preview/2

$ numactl -C 0 line -M 128K
64
$ numactl -C 3 line -M 128K
64


WARNING: multiple messages have this Message-ID (diff)
From: Yassine Oudjana <y.oudjana@protonmail.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Android Kernel Team <kernel-team@android.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Vincent Whitchurch <vincent.whitchurch@axis.com>,
	linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
Date: Wed, 07 Jul 2021 08:24:16 +0000	[thread overview]
Message-ID: <M0wGhzKTDUUYQPjRdiabG3xuKLx8p19uB1iqdkwfa8Op45i4zBGm4mpcHIxpYzWkJLiUM6JtQIDuBVyLlXtPhrlPyycbhZ2GO1ldLymA40g=@protonmail.com> (raw)
In-Reply-To: <CAK8P3a1rtXTtGQ_Q7eg2SOrYa_OhSWPWFiS8m=oSb_GU1uUNXQ@mail.gmail.com>

On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@protonmail.com wrote:
> > ...
>
> This is still somewhat inconclusive, but it does give some hope. The data that
>
> I found on random web sites was
>
> -   32KB L1, 2MB/1MB L2 [1][2]
> -   16KB L1, 1.5MB L2 [3]
> -   32KB L1, 1MB/512KB L2 [4]
>
>     so none of the sizes really line up. My best guess is that the actual hierarchy
>     1MB per-core L2 cache on the two big CPU, 512KB per-core L2 cache on
>     the two little ones, but no shared L2 or L3. The older Krait had a 4KB L0
>     cache, which could explain the 512-byte L1 output.
>
>     Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64
>     byte L1 line size that the 'cache' test reported?
>
>     Arnd
>
>     [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_processors#Snapdragon_820_and_821_(2016)
>     [2] https://en.wikipedia.org/wiki/Kryo
>     [3] https://www.geektopia.es/es/product/qualcomm/snapdragon-820/
>     [4] https://www.anandtech.com/show/9837/snapdragon-820-preview/2

$ numactl -C 0 line -M 128K
64
$ numactl -C 3 line -M 128K
64


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  parent reply	other threads:[~2021-07-07  8:24 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-27 12:43 [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) Will Deacon
2021-05-27 13:11 ` Catalin Marinas
2021-05-27 13:19 ` Mark Rutland
2021-05-28  9:35   ` Arnd Bergmann
2021-06-01 10:14     ` Catalin Marinas
2021-05-31  5:38 ` Ard Biesheuvel
2021-06-01 18:21 ` Will Deacon
     [not found] ` <CGME20210602132541eucas1p17127696041c26c00d1d2f50bef9cfaf0@eucas1p1.samsung.com>
2021-06-02 13:25   ` Marek Szyprowski
2021-06-02 13:51     ` Mark Rutland
2021-06-02 14:09       ` Marek Szyprowski
2021-06-02 14:14         ` Arnd Bergmann
2021-06-02 14:28           ` Marek Szyprowski
2021-06-02 14:52             ` Arnd Bergmann
2021-06-07 12:17               ` Arnd Bergmann
2021-06-04 10:01         ` Mark Rutland
2021-06-07  9:58           ` Marek Szyprowski
2021-06-07 12:01             ` Mark Rutland
2021-06-07 13:08               ` Mark Rutland
2021-06-07 13:39                 ` Will Deacon
2021-06-07 13:39                   ` Will Deacon
2021-06-07 13:56                   ` Mark Rutland
2021-06-07 13:56                     ` Mark Rutland
2021-06-07 13:57                   ` Arnd Bergmann
2021-06-07 13:57                     ` Arnd Bergmann
2021-06-07 15:17                     ` Maxime Ripard
2021-06-07 15:17                       ` Maxime Ripard
2021-06-07 15:50                       ` Arnd Bergmann
2021-06-07 15:50                         ` Arnd Bergmann
2021-06-08  8:57                         ` Mark Rutland
2021-06-08  8:57                           ` Mark Rutland
2021-06-07 15:32                     ` Mark Rutland
2021-06-07 15:32                       ` Mark Rutland
2021-06-02 14:11       ` Arnd Bergmann
2021-06-02 14:15         ` Marek Szyprowski
2021-07-06  9:26 ` Yassine Oudjana
2021-07-06 10:26   ` Catalin Marinas
2021-07-06 10:26     ` Catalin Marinas
2021-07-06 13:29     ` Robin Murphy
2021-07-06 13:29       ` Robin Murphy
2021-07-06 13:33       ` Will Deacon
2021-07-06 13:33         ` Will Deacon
2021-07-06 13:44         ` Marc Zyngier
2021-07-06 13:44           ` Marc Zyngier
2021-07-06 14:21           ` Robin Murphy
2021-07-06 14:21             ` Robin Murphy
2021-07-06 14:30           ` Arnd Bergmann
2021-07-06 14:30             ` Arnd Bergmann
2021-07-06 14:46             ` Marc Zyngier
2021-07-06 14:46               ` Marc Zyngier
2021-07-06 15:43               ` Arnd Bergmann
2021-07-06 15:43                 ` Arnd Bergmann
2021-07-06 17:15                 ` Yassine Oudjana
2021-07-06 17:15                   ` Yassine Oudjana
2021-07-06 20:33                   ` Arnd Bergmann
2021-07-06 20:33                     ` Arnd Bergmann
2021-07-06 22:27                     ` Bjorn Andersson
2021-07-06 22:27                       ` Bjorn Andersson
2021-07-07  9:27                       ` Will Deacon
2021-07-07  9:27                         ` Will Deacon
2021-07-07  8:24                     ` Yassine Oudjana [this message]
2021-07-07  8:24                       ` Yassine Oudjana
2021-07-07  9:29                       ` Arnd Bergmann
2021-07-07  9:29                         ` Arnd Bergmann
2021-07-07 14:41                         ` Jeffrey Hugo
2021-07-07 14:41                           ` Jeffrey Hugo
2021-07-08 20:59                           ` Jeffrey Hugo
2021-07-08 20:59                             ` Jeffrey Hugo
2021-07-09  8:48                             ` Will Deacon
2021-07-09  8:48                               ` Will Deacon
2021-07-09 17:10                               ` Catalin Marinas
2021-07-09 17:10                                 ` Catalin Marinas
2021-07-06 16:20             ` Will Deacon
2021-07-06 16:20               ` Will Deacon

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