From: Chen Wang <unicorn_wang@outlook.com> To: Inochi Amaoto <inochiama@outlook.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Chao Wei <chao.wei@sophgo.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Jisheng Zhang <jszhang@kernel.org>, Liu Gui <kenneth.liu@sophgo.com>, Jingbao Qiu <qiujingbao.dlmu@gmail.com>, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v6 3/4] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Date: Wed, 31 Jan 2024 11:44:37 +0800 [thread overview] Message-ID: <MA0P287MB2822C383EA3F6763705AAE28FE7C2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM> (raw) In-Reply-To: <IA1PR20MB4953355805F79ABDD7FE9129BB6D2@IA1PR20MB4953.namprd20.prod.outlook.com> On 2024/1/14 12:17, Inochi Amaoto wrote: > Add clock generator node for CV1800B and CV1812H. > > Until now, It uses DT override to minimize duplication. This may > change in the future. See the last link for the discussion on > maintaining DT of CV1800 series. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf > Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reviewed-by: Chen Wang <unicorn_wang@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++ > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 ++++ > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 6 ++++++ > 3 files changed, 14 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index 165e9e320a8c..baf641829e72 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -16,3 +16,7 @@ &plic { > &clint { > compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > }; > + > +&clk { > + compatible = "sophgo,cv1800-clk"; > +}; > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > index 3e7a942f5c1a..7fa4c1e2d1da 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -22,3 +22,7 @@ &plic { > &clint { > compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > }; > + > +&clk { > + compatible = "sophgo,cv1810-clk"; > +}; > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > index 2d6f4a4b1e58..6ea1b2784db9 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -53,6 +53,12 @@ soc { > dma-noncoherent; > ranges; > > + clk: clock-controller@3002000 { > + reg = <0x03002000 0x1000>; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > + > gpio0: gpio@3020000 { > compatible = "snps,dw-apb-gpio"; > reg = <0x3020000 0x1000>; > -- > 2.43.0 >
WARNING: multiple messages have this Message-ID (diff)
From: Chen Wang <unicorn_wang@outlook.com> To: Inochi Amaoto <inochiama@outlook.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Chao Wei <chao.wei@sophgo.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: Jisheng Zhang <jszhang@kernel.org>, Liu Gui <kenneth.liu@sophgo.com>, Jingbao Qiu <qiujingbao.dlmu@gmail.com>, dlan@gentoo.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v6 3/4] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Date: Wed, 31 Jan 2024 11:44:37 +0800 [thread overview] Message-ID: <MA0P287MB2822C383EA3F6763705AAE28FE7C2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM> (raw) In-Reply-To: <IA1PR20MB4953355805F79ABDD7FE9129BB6D2@IA1PR20MB4953.namprd20.prod.outlook.com> On 2024/1/14 12:17, Inochi Amaoto wrote: > Add clock generator node for CV1800B and CV1812H. > > Until now, It uses DT override to minimize duplication. This may > change in the future. See the last link for the discussion on > maintaining DT of CV1800 series. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf > Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reviewed-by: Chen Wang <unicorn_wang@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++ > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 ++++ > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 6 ++++++ > 3 files changed, 14 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > index 165e9e320a8c..baf641829e72 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -16,3 +16,7 @@ &plic { > &clint { > compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; > }; > + > +&clk { > + compatible = "sophgo,cv1800-clk"; > +}; > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > index 3e7a942f5c1a..7fa4c1e2d1da 100644 > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > @@ -22,3 +22,7 @@ &plic { > &clint { > compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; > }; > + > +&clk { > + compatible = "sophgo,cv1810-clk"; > +}; > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > index 2d6f4a4b1e58..6ea1b2784db9 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -53,6 +53,12 @@ soc { > dma-noncoherent; > ranges; > > + clk: clock-controller@3002000 { > + reg = <0x03002000 0x1000>; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > + > gpio0: gpio@3020000 { > compatible = "snps,dw-apb-gpio"; > reg = <0x3020000 0x1000>; > -- > 2.43.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-01-31 3:44 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-01-14 4:15 [PATCH v6 0/4] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Inochi Amaoto 2024-01-14 4:15 ` Inochi Amaoto 2024-01-14 4:16 ` [PATCH v6 1/4] dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC Inochi Amaoto 2024-01-14 4:16 ` Inochi Amaoto 2024-01-15 7:31 ` Krzysztof Kozlowski 2024-01-15 7:31 ` Krzysztof Kozlowski 2024-01-15 16:35 ` Conor Dooley 2024-01-15 16:35 ` Conor Dooley 2024-01-16 0:27 ` Inochi Amaoto 2024-01-16 0:27 ` Inochi Amaoto 2024-01-16 7:36 ` Conor Dooley 2024-01-16 7:36 ` Conor Dooley 2024-01-16 8:00 ` Inochi Amaoto 2024-01-16 8:00 ` Inochi Amaoto 2024-01-16 17:24 ` Conor Dooley 2024-01-16 17:24 ` Conor Dooley 2024-01-14 4:16 ` [PATCH v6 2/4] clk: sophgo: Add CV1800/SG2000 series clock controller driver Inochi Amaoto 2024-01-14 4:16 ` Inochi Amaoto 2024-01-31 4:27 ` Inochi Amaoto 2024-01-31 4:27 ` Inochi Amaoto 2024-01-14 4:17 ` [PATCH v6 3/4] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Inochi Amaoto 2024-01-14 4:17 ` Inochi Amaoto 2024-01-31 3:44 ` Chen Wang [this message] 2024-01-31 3:44 ` Chen Wang 2024-01-14 4:17 ` [PATCH v6 4/4] riscv: dts: sophgo: add uart clock " Inochi Amaoto 2024-01-14 4:17 ` Inochi Amaoto 2024-01-31 3:46 ` Chen Wang 2024-01-31 3:46 ` Chen Wang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=MA0P287MB2822C383EA3F6763705AAE28FE7C2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM \ --to=unicorn_wang@outlook.com \ --cc=aou@eecs.berkeley.edu \ --cc=chao.wei@sophgo.com \ --cc=conor+dt@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=dlan@gentoo.org \ --cc=inochiama@outlook.com \ --cc=jszhang@kernel.org \ --cc=kenneth.liu@sophgo.com \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mturquette@baylibre.com \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=qiujingbao.dlmu@gmail.com \ --cc=robh+dt@kernel.org \ --cc=sboyd@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.