From: Anup Patel <Anup.Patel@wdc.com>
To: Guo Ren <guoren@kernel.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Mike Rapoport <rppt@linux.ibm.com>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <Atish.Patra@wdc.com>, Gary Guo <gary@garyguo.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: RE: [PATCH v2] RISC-V: Implement ASID allocator
Date: Tue, 9 Apr 2019 03:36:03 +0000 [thread overview]
Message-ID: <MN2PR04MB6061824812AF1E83BA2434408D2D0@MN2PR04MB6061.namprd04.prod.outlook.com> (raw)
In-Reply-To: <20190409030231.GA14861@guoren-Inspiron-7460>
> -----Original Message-----
> From: Guo Ren <guoren@kernel.org>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <Anup.Patel@wdc.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>; Albert Ou
> <aou@eecs.berkeley.edu>; linux-kernel@vger.kernel.org; Mike Rapoport
> <rppt@linux.ibm.com>; Christoph Hellwig <hch@infradead.org>; Atish Patra
> <Atish.Patra@wdc.com>; Gary Guo <gary@garyguo.net>; Paul Walmsley
> <paul.walmsley@sifive.com>; linux-riscv@lists.infradead.org
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
>
> Hi Anup,
>
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?
I am testing this using hackbench.
Regards,
Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <Anup.Patel@wdc.com>
To: Guo Ren <guoren@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Mike Rapoport <rppt@linux.ibm.com>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <Atish.Patra@wdc.com>, Gary Guo <gary@garyguo.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: RE: [PATCH v2] RISC-V: Implement ASID allocator
Date: Tue, 9 Apr 2019 03:36:03 +0000 [thread overview]
Message-ID: <MN2PR04MB6061824812AF1E83BA2434408D2D0@MN2PR04MB6061.namprd04.prod.outlook.com> (raw)
In-Reply-To: <20190409030231.GA14861@guoren-Inspiron-7460>
> -----Original Message-----
> From: Guo Ren <guoren@kernel.org>
> Sent: Tuesday, April 9, 2019 8:33 AM
> To: Anup Patel <Anup.Patel@wdc.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>; Albert Ou
> <aou@eecs.berkeley.edu>; linux-kernel@vger.kernel.org; Mike Rapoport
> <rppt@linux.ibm.com>; Christoph Hellwig <hch@infradead.org>; Atish Patra
> <Atish.Patra@wdc.com>; Gary Guo <gary@garyguo.net>; Paul Walmsley
> <paul.walmsley@sifive.com>; linux-riscv@lists.infradead.org
> Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator
>
> Hi Anup,
>
> On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote:
> > This patch is tested on QEMU/virt machine and SiFive Unleashed board.
> > On QEMU/virt machine, we see 10% (approx) performance improvement
> with
> > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP
> > CSR are not implemented on SiFive Unleashed board so we don't see any
> > change in performance.
> Can you tell me what is the test case ?
I am testing this using hackbench.
Regards,
Anup
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next prev parent reply other threads:[~2019-04-09 3:36 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-28 6:32 [PATCH v2] RISC-V: Implement ASID allocator Anup Patel
2019-03-28 6:32 ` Anup Patel
2019-03-28 13:37 ` Gary Guo
2019-03-28 13:37 ` Gary Guo
2019-03-28 14:09 ` Anup Patel
2019-03-28 14:09 ` Anup Patel
2019-03-28 14:30 ` Gary Guo
2019-03-28 14:30 ` Gary Guo
2019-03-29 4:43 ` Anup Patel
2019-03-29 4:43 ` Anup Patel
2019-03-28 14:13 ` Anup Patel
2019-03-28 14:13 ` Anup Patel
2019-03-28 14:33 ` Gary Guo
2019-03-28 14:33 ` Gary Guo
2019-03-29 4:49 ` Anup Patel
2019-03-29 4:49 ` Anup Patel
2019-03-29 5:04 ` Paul Walmsley
2019-03-29 5:04 ` Paul Walmsley
2019-03-29 5:12 ` Anup Patel
2019-03-29 5:12 ` Anup Patel
2019-04-09 3:02 ` Guo Ren
2019-04-09 3:02 ` Guo Ren
2019-04-09 3:36 ` Anup Patel [this message]
2019-04-09 3:36 ` Anup Patel
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