[PATCH v3 0/5] add DM based reset driver for SiFive SoC's

[PATCH v3 0/5] add DM based reset driver for SiFive SoC's

[Sagar Shrikant Kadam]

The FU540-C000 support in U-Boot is missing DM based reset driver,
and is handling reset's to sub-system within the prci driver itself.
The series here adds a generic DM reset driver for SiFive SoC's so as 
to leverage the U-Boot's reset framework and binds the reset driver with
prci driver.
The PRCI driver takes care of triggering the consumers reset signals
appropriately.

Patch 1: Add necessary dt indexes for device reset register.
Patch 2: Update macro's to use common dt indexes from binding header. 
Patch 3: Add reset producer and consumer entries within the device tree.
Patch 4: Add reset dm driver and bind it within prci module.
Patch 5: Add Kconfig, Makefile entries and enable the driver

This series is based on mainline U-Boot commit 2f5fbb5b39f7 ("Prepare
v2020.07")

History:
==========================
V3:
-Add reset indexes in separate dt binding header instead of
 updating the clock dt binding header which is synced from Linux

V2:
-Removed extra character in commit log of 2nd patch 

V1:
-Base version.

Sagar Shrikant Kadam (5):
  dt-bindings: prci: add indexes for reset signals available in prci
  fu540: prci: use common reset indexes defined in binding header
  fu540: dtsi: add reset producer and consumer entries
  sifive: reset: add DM based reset driver for SiFive SoC's
  configs: reset: fu540: enable dm reset framework for SiFive SoC

 arch/riscv/dts/fu540-c000-u-boot.dtsi         |  12 +++
 arch/riscv/include/asm/arch-fu540/reset.h     |  13 +++
 configs/sifive_fu540_defconfig                |   2 +
 drivers/clk/sifive/fu540-prci.c               |  90 ++++++++++++++------
 drivers/reset/Kconfig                         |   9 ++
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sifive.c                  | 118 ++++++++++++++++++++++++++
 include/dt-bindings/reset/sifive-fu540-prci.h |  19 +++++
 8 files changed, 239 insertions(+), 25 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h
 create mode 100644 drivers/reset/reset-sifive.c
 create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h

-- 
2.7.4

[PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals available in prci

[Sagar Shrikant Kadam]

Add bit indexes for reset signals within the PRCI module
on FU540-C000 SoC.
The DDR and ethernet sub-system's have reset signals
indicated by these reset indexes.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h

diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h
new file mode 100644
index 0000000..89aa5b6
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu540-prci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Sifive, Inc.
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define PRCI_RST_DDR_CTRL_N	0
+#define PRCI_RST_DDR_AXI_N	1
+#define PRCI_RST_DDR_AHB_N	2
+#define PRCI_RST_DDR_PHY_N	3
+/* bit 4 is reserved bit */
+#define PRCI_RST_RSVD_N		4
+#define PRCI_RST_GEMGXL_N	5
+
+#endif
-- 
2.7.4

[PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals available in prci

[Pragnesh Patel]

>-----Original Message-----
>From: Sagar Kadam <sagar.kadam@sifive.com>
>Sent: 10 July 2020 14:08
>To: u-boot at lists.denx.de
>Cc: rick at andestech.com; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; palmer at dabbelt.com; anup.patel at wdc.com;
>atish.patra at wdc.com; lukma at denx.de; Pragnesh Patel
><pragnesh.patel@sifive.com>; bin.meng at windriver.com;
>jagan at amarulasolutions.com; sjg at chromium.org; twoerner at gmail.com;
>abrodkin at synopsys.com; Eugeniy.Paltsev at synopsys.com; patrick at blueri.se;
>weijie.gao at mediatek.com; festevam at gmail.com; Sagar Kadam
><sagar.kadam@sifive.com>
>Subject: [PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals
>available in prci
>
>Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC.
>The DDR and ethernet sub-system's have reset signals indicated by these
>reset indexes.
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
>---
> include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
>

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

[PATCH v3 1/5] dt-bindings: prci: add indexes for reset signals available in prci

[Bin Meng]

On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>
> Add bit indexes for reset signals within the PRCI module
> on FU540-C000 SoC.
> The DDR and ethernet sub-system's have reset signals
> indicated by these reset indexes.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> ---
>  include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
>

Reviewed-by: Bin Meng <bin.meng@windriver.com>

[PATCH v3 2/5] fu540: prci: use common reset indexes defined in binding header

[Sagar Shrikant Kadam]

Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 drivers/clk/sifive/fu540-prci.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index fe6e0d4..00c31fc 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -41,6 +41,7 @@
 #include <linux/math64.h>
 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
 #include <dt-bindings/clock/sifive-fu540-prci.h>
+#include <dt-bindings/reset/sifive-fu540-prci.h>
 
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
@@ -131,21 +132,17 @@
 
 /* DEVICESRESETREG */
 #define PRCI_DEVICESRESETREG_OFFSET	0x28
-#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
+
 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
+			(0x1 << PRCI_RST_DDR_CTRL_N)
 #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
+			(0x1 << PRCI_RST_DDR_AXI_N)
 #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
+			(0x1 << PRCI_RST_DDR_AHB_N)
 #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
-#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
+			(0x1 << PRCI_RST_DDR_PHY_N)
 #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
-			(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
+			(0x1 << PRCI_RST_GEMGXL_N)
 
 /* CLKMUXSTATUSREG */
 #define PRCI_CLKMUXSTATUSREG_OFFSET	0x2c
-- 
2.7.4

[PATCH v3 2/5] fu540: prci: use common reset indexes defined in binding header

[Pragnesh Patel]

>-----Original Message-----
>From: Sagar Kadam <sagar.kadam@sifive.com>
>Sent: 10 July 2020 14:08
>To: u-boot at lists.denx.de
>Cc: rick at andestech.com; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; palmer at dabbelt.com; anup.patel at wdc.com;
>atish.patra at wdc.com; lukma at denx.de; Pragnesh Patel
><pragnesh.patel@sifive.com>; bin.meng at windriver.com;
>jagan at amarulasolutions.com; sjg at chromium.org; twoerner at gmail.com;
>abrodkin at synopsys.com; Eugeniy.Paltsev at synopsys.com; patrick at blueri.se;
>weijie.gao at mediatek.com; festevam at gmail.com; Sagar Kadam
><sagar.kadam@sifive.com>
>Subject: [PATCH v3 2/5] fu540: prci: use common reset indexes defined in
>binding header
>
>Indexes of reset signals available in PRCI driver are also defined in include/dt-
>bindings/reset/sifive-fu540-prci.h.
>So use those instead of defining new ones again within the fu540-prci driver.
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
>---
> drivers/clk/sifive/fu540-prci.c | 17 +++++++----------
> 1 file changed, 7 insertions(+), 10 deletions(-)
>

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

[PATCH v3 2/5] fu540: prci: use common reset indexes defined in binding header

[Bin Meng]

On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>
> Indexes of reset signals available in PRCI driver are also
> defined in include/dt-bindings/reset/sifive-fu540-prci.h.
> So use those instead of defining new ones again within the
> fu540-prci driver.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> ---
>  drivers/clk/sifive/fu540-prci.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
>

Reviewed-by: Bin Meng <bin.meng@windriver.com>

[PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries

[Sagar Shrikant Kadam]

The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index afdb4f4..5302677 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -3,6 +3,8 @@
  * (C) Copyright 2019 SiFive, Inc
  */
 
+#include <dt-bindings/reset/sifive-fu540-prci.h>
+
 / {
 	cpus {
 		assigned-clocks = <&prci PRCI_CLK_COREPLL>;
@@ -59,6 +61,16 @@
 			reg = <0x0 0x2000000 0x0 0xc0000>;
 			u-boot,dm-spl;
 		};
+		prci: clock-controller at 10000000 {
+			#reset-cells = <1>;
+			resets = <&prci PRCI_RST_DDR_CTRL_N>,
+				 <&prci PRCI_RST_DDR_AXI_N>,
+				 <&prci PRCI_RST_DDR_AHB_N>,
+				 <&prci PRCI_RST_DDR_PHY_N>,
+				 <&prci PRCI_RST_GEMGXL_N>;
+			reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+					"ddr_phy", "gemgxl_reset";
+		};
 		dmc: dmc at 100b0000 {
 			compatible = "sifive,fu540-c000-ddr";
 			reg = <0x0 0x100b0000 0x0 0x0800
-- 
2.7.4

[PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries

[Pragnesh Patel]

>-----Original Message-----
>From: Sagar Kadam <sagar.kadam@sifive.com>
>Sent: 10 July 2020 14:08
>To: u-boot at lists.denx.de
>Cc: rick at andestech.com; Paul Walmsley ( Sifive)
><paul.walmsley@sifive.com>; palmer at dabbelt.com; anup.patel at wdc.com;
>atish.patra at wdc.com; lukma at denx.de; Pragnesh Patel
><pragnesh.patel@sifive.com>; bin.meng at windriver.com;
>jagan at amarulasolutions.com; sjg at chromium.org; twoerner at gmail.com;
>abrodkin at synopsys.com; Eugeniy.Paltsev at synopsys.com; patrick at blueri.se;
>weijie.gao at mediatek.com; festevam at gmail.com; Sagar Kadam
><sagar.kadam@sifive.com>
>Subject: [PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries
>
>The resets to DDR and ethernet sub-system are connected to PRCI device
>reset control register, these reset signals are active low and are held low at
>power-up. Add these reset producer and consumer details needed by the
>reset driver.
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
>---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

[PATCH v3 3/5] fu540: dtsi: add reset producer and consumer entries

[Bin Meng]

On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>
> The resets to DDR and ethernet sub-system are connected to
> PRCI device reset control register, these reset signals
> are active low and are held low at power-up. Add these reset
> producer and consumer details needed by the reset driver.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> ---
>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>

Reviewed-by: Bin Meng <bin.meng@windriver.com>

[PATCH v3 4/5] sifive: reset: add DM based reset driver for SiFive SoC's

[Sagar Shrikant Kadam]

PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
 arch/riscv/include/asm/arch-fu540/reset.h |  13 ++++
 drivers/clk/sifive/fu540-prci.c           |  73 ++++++++++++++----
 drivers/reset/reset-sifive.c              | 118 ++++++++++++++++++++++++++++++
 3 files changed, 189 insertions(+), 15 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h
 create mode 100644 drivers/reset/reset-sifive.c

diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h
new file mode 100644
index 0000000..e42797a
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 00c31fc..c5148e9 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -30,11 +30,15 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/reset.h>
 #include <clk-uclass.h>
 #include <clk.h>
 #include <div64.h>
 #include <dm.h>
 #include <errno.h>
+#include <reset-uclass.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
@@ -132,6 +136,7 @@
 
 /* DEVICESRESETREG */
 #define PRCI_DEVICESRESETREG_OFFSET	0x28
+#define PRCI_DEVICERESETCNT 5
 
 #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
 			(0x1 << PRCI_RST_DDR_CTRL_N)
@@ -525,6 +530,41 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
 	.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
 };
 
+static int __prci_consumer_reset(const char *rst_name, bool trigger)
+{
+	struct udevice *dev;
+	struct reset_ctl rst_sig;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_RESET,
+					  DM_GET_DRIVER(sifive_reset),
+					  &dev);
+	if (ret) {
+		dev_err(dev, "Reset driver not found: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_get_by_name(dev, rst_name, &rst_sig);
+	if (ret) {
+		dev_err(dev, "failed to get %s reset\n", rst_name);
+		return ret;
+	}
+
+	if (reset_valid(&rst_sig)) {
+		if (trigger)
+			ret = reset_deassert(&rst_sig);
+		else
+			ret = reset_assert(&rst_sig);
+		if (ret) {
+			dev_err(dev, "failed to trigger reset id = %ld\n",
+				rst_sig.id);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
 /**
  * __prci_ddr_release_reset() - Release DDR reset
  * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
@@ -532,19 +572,20 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
  */
 static void __prci_ddr_release_reset(struct __prci_data *pd)
 {
-	u32 v;
-
-	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
-	v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
-	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+	/* Release DDR ctrl reset */
+	__prci_consumer_reset("ddr_ctrl", true);
 
 	/* HACK to get the '1 full controller clock cycle'. */
 	asm volatile ("fence");
-	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
-	v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
-			PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
-			PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
-	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+	/* Release DDR AXI reset */
+	__prci_consumer_reset("ddr_axi", true);
+
+	/* Release DDR AHB reset */
+	__prci_consumer_reset("ddr_ahb", true);
+
+	/* Release DDR PHY reset */
+	__prci_consumer_reset("ddr_phy", true);
 
 	/* HACK to get the '1 full controller clock cycle'. */
 	asm volatile ("fence");
@@ -564,12 +605,8 @@ static void __prci_ddr_release_reset(struct __prci_data *pd)
  */
 static void __prci_ethernet_release_reset(struct __prci_data *pd)
 {
-	u32 v;
-
 	/* Release GEMGXL reset */
-	v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
-	v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
-	__prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+	__prci_consumer_reset("gemgxl_reset", true);
 
 	/* Procmon => core clock */
 	__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
@@ -754,6 +791,11 @@ static struct clk_ops sifive_fu540_prci_ops = {
 	.disable = sifive_fu540_prci_disable,
 };
 
+static int sifive_fu540_clk_bind(struct udevice *dev)
+{
+	return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
+}
+
 static const struct udevice_id sifive_fu540_prci_ids[] = {
 	{ .compatible = "sifive,fu540-c000-prci" },
 	{ }
@@ -766,4 +808,5 @@ U_BOOT_DRIVER(sifive_fu540_prci) = {
 	.probe = sifive_fu540_prci_probe,
 	.ops = &sifive_fu540_prci_ops,
 	.priv_auto_alloc_size = sizeof(struct __prci_data),
+	.bind = sifive_fu540_clk_bind,
 };
diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c
new file mode 100644
index 0000000..527757f
--- /dev/null
+++ b/drivers/reset/reset-sifive.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sifive, Inc.
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitops.h>
+
+#define PRCI_RESETREG_OFFSET 0x28
+
+struct sifive_reset_priv {
+	void *base;
+	/* number of reset signals */
+	int nr_reset;
+};
+
+static int sifive_rst_trigger(struct reset_ctl *rst, bool level)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+	int id = rst->id;
+	int regval = readl(priv->base + PRCI_RESETREG_OFFSET);
+
+	/* Derive bitposition from rst id */
+	if (level)
+		/* Reset deassert */
+		regval |= BIT(id);
+	else
+		/* Reset assert */
+		regval &= ~BIT(id);
+
+	writel(regval, priv->base + PRCI_RESETREG_OFFSET);
+
+	return 0;
+}
+
+static int sifive_reset_assert(struct reset_ctl *rst)
+{
+	return sifive_rst_trigger(rst, false);
+}
+
+static int sifive_reset_deassert(struct reset_ctl *rst)
+{
+	return sifive_rst_trigger(rst, true);
+}
+
+static int sifive_reset_request(struct reset_ctl *rst)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+
+	debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
+	      rst, rst->dev, rst->id, priv->nr_reset);
+
+	if (rst->id > priv->nr_reset)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sifive_reset_free(struct reset_ctl *rst)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
+
+	debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
+	      rst, rst->dev, rst->id, priv->nr_reset);
+
+	return 0;
+}
+
+static int sifive_reset_probe(struct udevice *dev)
+{
+	struct sifive_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	return 0;
+}
+
+int sifive_reset_bind(struct udevice *dev, ulong count)
+{
+	struct udevice *rst_dev;
+	struct sifive_reset_priv *priv;
+	int ret;
+
+	ret = device_bind_driver_to_node(dev, "sifive-reset", "reset",
+					 dev_ofnode(dev), &rst_dev);
+	if (ret) {
+		dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret);
+		return ret;
+	}
+	priv = malloc(sizeof(struct sifive_reset_priv));
+	priv->nr_reset = count;
+	rst_dev->priv = priv;
+
+	return 0;
+}
+
+const struct reset_ops sifive_reset_ops = {
+	.request = sifive_reset_request,
+	.rfree = sifive_reset_free,
+	.rst_assert = sifive_reset_assert,
+	.rst_deassert = sifive_reset_deassert,
+};
+
+U_BOOT_DRIVER(sifive_reset) = {
+	.name		= "sifive-reset",
+	.id		= UCLASS_RESET,
+	.ops		= &sifive_reset_ops,
+	.probe		= sifive_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct sifive_reset_priv),
+};
-- 
2.7.4

[PATCH v3 5/5] configs: reset: fu540: enable dm reset framework for SiFive SoC

[Sagar Shrikant Kadam]

Add necessary defconfig and Kconfig entries to enable SiFive SoC's
reset driver so as to utilise U-Boot's reset framework.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
---
 configs/sifive_fu540_defconfig | 2 ++
 drivers/reset/Kconfig          | 9 +++++++++
 drivers/reset/Makefile         | 1 +
 3 files changed, 12 insertions(+)

diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
index 32347c2..12f2469 100644
--- a/configs/sifive_fu540_defconfig
+++ b/configs/sifive_fu540_defconfig
@@ -20,3 +20,5 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SPL_CLK=y
 CONFIG_DM_MTD=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_DM_RESET=y
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 88d3be1..627f8e8 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -148,4 +148,13 @@ config RESET_IMX7
 	help
 	  Support for reset controller on i.MX7/8 SoCs.
 
+config RESET_SIFIVE
+	bool "Reset Driver for SiFive SoC's"
+	depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
+	default y
+	help
+	  PRCI module within SiFive SoC's provides mechanism to reset
+	  different hw blocks like DDR, gemgxl. With this driver we leverage
+	  U-Boot's reset framework to reset these hardware blocks.
+
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 0a044d5..e3c27c4 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
-- 
2.7.4

[PATCH v3 5/5] configs: reset: fu540: enable dm reset framework for SiFive SoC

[Rick Chen]

Hi Sagar

> From: Sagar Shrikant Kadam [mailto:sagar.kadam at sifive.com]
> Sent: Friday, July 10, 2020 4:38 PM
> To: u-boot at lists.denx.de
> Cc: Rick Jian-Zhi Chen(???); paul.walmsley at sifive.com; palmer at dabbelt.com; anup.patel at wdc.com; atish.patra at wdc.com; lukma at denx.de; pragnesh.patel at sifive.com; bin.meng at windriver.com; jagan at amarulasolutions.com; sjg at chromium.org; twoerner at gmail.com; abrodkin at synopsys.com; Eugeniy.Paltsev at synopsys.com; patrick at blueri.se; weijie.gao at mediatek.com; festevam at gmail.com; Sagar Shrikant Kadam
> Subject: [PATCH v3 5/5] configs: reset: fu540: enable dm reset framework for SiFive SoC
>
> Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Tested-by: Bin Meng <bin.meng@windriver.com>
> ---
>  configs/sifive_fu540_defconfig | 2 ++
>  drivers/reset/Kconfig          | 9 +++++++++
>  drivers/reset/Makefile         | 1 +
>  3 files changed, 12 insertions(+)
>
> diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 32347c2..12f2469 100644
> --- a/configs/sifive_fu540_defconfig
> +++ b/configs/sifive_fu540_defconfig
> @@ -20,3 +20,5 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>  CONFIG_SPL_CLK=y
>  CONFIG_DM_MTD=y
> +CONFIG_SPL_DM_RESET=y
> +CONFIG_DM_RESET=y
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 88d3be1..627f8e8 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -148,4 +148,13 @@ config RESET_IMX7
>         help
>           Support for reset controller on i.MX7/8 SoCs.
>
> +config RESET_SIFIVE
> +       bool "Reset Driver for SiFive SoC's"
> +       depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
> +       default y
> +       help
> +         PRCI module within SiFive SoC's provides mechanism to reset
> +         different hw blocks like DDR, gemgxl. With this driver we leverage
> +         U-Boot's reset framework to reset these hardware blocks.
> +
>  endmenu
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0a044d5..e3c27c4 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
>  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
>  obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
>  obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> +obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o

This patch conflicts with u-boot/master, please rebase.

Applying: dt-bindings: prci: add indexes for reset signals available in prci
Applying: fu540: prci: use common reset indexes defined in binding header
Applying: fu540: dtsi: add reset producer and consumer entries
Applying: sifive: reset: add DM based reset driver for SiFive SoC's
Applying: configs: reset: fu540: enable dm reset framework for SiFive SoC
error: patch failed: drivers/reset/Kconfig:148
error: drivers/reset/Kconfig: patch does not apply
error: patch failed: drivers/reset/Makefile:23
error: drivers/reset/Makefile: patch does not apply
Patch failed at 0005 configs: reset: fu540: enable dm reset framework
for SiFive SoC

Thanks,
Rick

[PATCH v3 5/5] configs: reset: fu540: enable dm reset framework for SiFive SoC

[Sagar Kadam]

Hi Rick,

> -----Original Message-----
> From: Rick Chen <rickchen36@gmail.com>
> Sent: Thursday, July 23, 2020 7:56 AM
> To: Sagar Kadam <sagar.kadam@sifive.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Anup
> Patel <anup.patel@wdc.com>; Atish Patra <atish.patra@wdc.com>; Lukasz
> Majewski <lukma@denx.de>; Pragnesh Patel <pragnesh.patel@sifive.com>; Bin
> Meng <bmeng.cn@gmail.com>; Jagan Teki <jagan@amarulasolutions.com>;
> Simon Glass <sjg@chromium.org>; Trevor Woerner <twoerner@gmail.com>;
> rick <rick@andestech.com>; Alan Kao <alankao@andestech.com>
> Subject: Re: [PATCH v3 5/5] configs: reset: fu540: enable dm reset framework
> for SiFive SoC
> 
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
> 
> Hi Sagar
> 
> > From: Sagar Shrikant Kadam [mailto:sagar.kadam at sifive.com]
> > Sent: Friday, July 10, 2020 4:38 PM
> > To: u-boot at lists.denx.de
> > Cc: Rick Jian-Zhi Chen(???); paul.walmsley at sifive.com;
> > palmer at dabbelt.com; anup.patel at wdc.com; atish.patra at wdc.com;
> > lukma at denx.de; pragnesh.patel at sifive.com; bin.meng at windriver.com;
> > jagan at amarulasolutions.com; sjg at chromium.org; twoerner at gmail.com;
> > abrodkin at synopsys.com; Eugeniy.Paltsev at synopsys.com;
> > patrick at blueri.se; weijie.gao at mediatek.com; festevam at gmail.com; Sagar
> > Shrikant Kadam
> > Subject: [PATCH v3 5/5] configs: reset: fu540: enable dm reset
> > framework for SiFive SoC
> >
> > Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset
> driver so as to utilise U-Boot's reset framework.
> >
> > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> > Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
> > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> > Tested-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >  configs/sifive_fu540_defconfig | 2 ++
> >  drivers/reset/Kconfig          | 9 +++++++++
> >  drivers/reset/Makefile         | 1 +
> >  3 files changed, 12 insertions(+)
> >
> > diff --git a/configs/sifive_fu540_defconfig
> > b/configs/sifive_fu540_defconfig index 32347c2..12f2469 100644
> > --- a/configs/sifive_fu540_defconfig
> > +++ b/configs/sifive_fu540_defconfig
> > @@ -20,3 +20,5 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-
> a00"
> >  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> >  CONFIG_SPL_CLK=y
> >  CONFIG_DM_MTD=y
> > +CONFIG_SPL_DM_RESET=y
> > +CONFIG_DM_RESET=y
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> > 88d3be1..627f8e8 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -148,4 +148,13 @@ config RESET_IMX7
> >         help
> >           Support for reset controller on i.MX7/8 SoCs.
> >
> > +config RESET_SIFIVE
> > +       bool "Reset Driver for SiFive SoC's"
> > +       depends on DM_RESET && CLK_SIFIVE_FU540_PRCI &&
> TARGET_SIFIVE_FU540
> > +       default y
> > +       help
> > +         PRCI module within SiFive SoC's provides mechanism to reset
> > +         different hw blocks like DDR, gemgxl. With this driver we leverage
> > +         U-Boot's reset framework to reset these hardware blocks.
> > +
> >  endmenu
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index
> > 0a044d5..e3c27c4 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
> >  obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
> >  obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
> >  obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> > +obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
> 
> This patch conflicts with u-boot/master, please rebase.
> 
Ok, I will rebase the series on u-boot/master and send it.

Thanks & BR,
Sagar

> Applying: dt-bindings: prci: add indexes for reset signals available in prci
> Applying: fu540: prci: use common reset indexes defined in binding header
> Applying: fu540: dtsi: add reset producer and consumer entries
> Applying: sifive: reset: add DM based reset driver for SiFive SoC's
> Applying: configs: reset: fu540: enable dm reset framework for SiFive SoC
> error: patch failed: drivers/reset/Kconfig:148
> error: drivers/reset/Kconfig: patch does not apply
> error: patch failed: drivers/reset/Makefile:23
> error: drivers/reset/Makefile: patch does not apply Patch failed at 0005 configs:
> reset: fu540: enable dm reset framework for SiFive SoC
> 
> Thanks,
> Rick