RE: [PATCH 5/5] misc: zynqmp: Add afi config driver

[Nava kishore Manne <navam@xilinx.com>]

Hi Greg,

	Please find my response inline.

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Tuesday, April 20, 2021 2:18 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: robh+dt@kernel.org; Michal Simek <michals@xilinx.com>; Derek Kiernan
> <dkiernan@xilinx.com>; Dragan Cvetic <draganc@xilinx.com>;
> arnd@arndb.de; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>; Amit Sunil
> Dhamne <amitsuni@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore369@gmail.com; git <git@xilinx.com>
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
> 
> On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > This patch adds zynqmp afi config driver.This is useful for the
> > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> 
> Again, please spell out what those terms mean, as I have no idea :(
> 

Will fix in v2

> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> >  drivers/misc/Kconfig      | 11 ++++++
> >  drivers/misc/Makefile     |  1 +
> >  drivers/misc/zynqmp-afi.c | 83
> > +++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 95 insertions(+)
> >  create mode 100644 drivers/misc/zynqmp-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 877b43b3377d..d1ea1eeb3ac1 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> >  	  between PS and PL, the AXI port data path should be configured
> >  	  with the proper Bus-width values
> >
> > +config ZYNQMP_AFI
> > +        tristate "Xilinx ZYNQMP AFI support"
> > +        help
> > +	  ZynqMP AFI driver support for writing to the AFI registers for
> > +	  configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > +	  PS to the programmable logic (PL) through the AXI port. This AXI
> > +	  port helps to establish the data path between the PS and PL.
> > +	  In-order to establish the proper communication path between
> > +	  PS and PL, the AXI port data path should be configured with
> > +	  the proper Bus-width values
> 
> Please use tabs properly, you mix them above, checkpatch should have
> caught that.
> 
Yes, Ideally check patch should report this issue but it's failed to report.
Will fix this issue in v2.

Regards,
Navakishore.