[Intel-gfx] [PATCH v9 0/7] Enable YCbCr420 for VDSC

[Intel-gfx] [PATCH v9 0/7] Enable YCbCr420 for VDSC

[Suraj Kandpal]

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]

---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-add display version check before writing in new pps register

---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only

--v6
-add patch to check dsc slice design requirement [Vandita]

--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]

--v8
-fix slice width and height 2's multiple check
-fix minimum pixel requirement in slice check

--v9 
-Add debugfs entry to validate output format

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

Swati Sharma (1):
  drm/i915/dsc: Add debugfs entry to validate DSC output formats

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |  77 ++++++++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  44 ++++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 106 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   7 +
 11 files changed, 438 insertions(+), 24 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check if the sink supports given format with DSC

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Add helper function to check if the DP sink supports DSC with the given
output format.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp_helper.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..d529d0254b68 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -194,6 +194,13 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
 }
 
+/* Check if sink supports DSC with given output format */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
+{
+	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
+}
+
 /* Forward Error Correction Support on DP 1.4 */
 static inline bool
 drm_dp_sink_supports_fec(const u8 fec_capable)
-- 
2.25.1

Re: [Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check if the sink supports given format with DSC

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Tuesday, February 7, 2023 1:14 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check if the sink
> supports given format with DSC
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Add helper function to check if the DP sink supports DSC with the given output
> format.

Nit: You can drop "function" and "the" to truncate it, add o/p format to be clear.
Also I feel this can be squashed with 2nd patch. This seems to be a static function,
so scope is limited.

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp_helper.h | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index ab55453f2d2c..d529d0254b68 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -194,6 +194,13 @@ drm_dp_dsc_sink_max_slice_width(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>  		DP_DSC_SLICE_WIDTH_MULTIPLIER;
>  }
> 
> +/* Check if sink supports DSC with given output format */

To stay consistent with rest of the file, please elaborate the function's purpose
and explain input parameters.

static inline
> +bool drm_dp_dsc_sink_supports_format(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) {
> +	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT]
> &
> +output_format; }
> +
>  /* Forward Error Correction Support on DP 1.4 */  static inline bool
> drm_dp_sink_supports_fec(const u8 fec_capable)
> --
> 2.25.1

Re: [Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check if the sink supports given format with DSC

[Shankar, Uma]

> -----Original Message-----
> From: Shankar, Uma
> Sent: Tuesday, February 21, 2023 2:08 AM
> To: Suraj Kandpal <suraj.kandpal@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check if the sink
> supports given format with DSC
> 
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: Tuesday, February 7, 2023 1:14 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v9 1/7] drm/dp_helper: Add helper to check
> > if the sink supports given format with DSC
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > Add helper function to check if the DP sink supports DSC with the
> > given output format.
> 
> Nit: You can drop "function" and "the" to truncate it, add o/p format to be clear.
> Also I feel this can be squashed with 2nd patch. This seems to be a static function, so
> scope is limited.

Skip the squashing comment, it's a drm core change. Its good to keep it separate.

> 
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  include/drm/display/drm_dp_helper.h | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/include/drm/display/drm_dp_helper.h
> > b/include/drm/display/drm_dp_helper.h
> > index ab55453f2d2c..d529d0254b68 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -194,6 +194,13 @@ drm_dp_dsc_sink_max_slice_width(const u8
> > dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> >  		DP_DSC_SLICE_WIDTH_MULTIPLIER;
> >  }
> >
> > +/* Check if sink supports DSC with given output format */
> 
> To stay consistent with rest of the file, please elaborate the function's purpose and
> explain input parameters.
> 
> static inline
> > +bool drm_dp_dsc_sink_supports_format(const u8
> > +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) {
> > +	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT]
> > &
> > +output_format; }
> > +
> >  /* Forward Error Correction Support on DP 1.4 */  static inline bool
> > drm_dp_sink_supports_fec(const u8 fec_capable)
> > --
> > 2.25.1

[Intel-gfx] [PATCH v9 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Go with DSC only if the given output_format is supported.

v2: Use drm helper to get DSC format support for sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cb4fbcd935db..73a7baccd7d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1494,6 +1494,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+					 enum intel_output_format output_format)
+{
+	u8 sink_dsc_format;
+
+	switch (output_format) {
+	case INTEL_OUTPUT_FORMAT_RGB:
+		sink_dsc_format = DP_DSC_RGB;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		sink_dsc_format = DP_DSC_YCbCr444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		if (min(intel_dp_source_dsc_version_minor(intel_dp),
+			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+			return false;
+		sink_dsc_format = DP_DSC_YCbCr420_Native;
+		break;
+	default:
+		return false;
+	}
+
+	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -1514,11 +1539,16 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
+	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+		return -EINVAL;
+
 	if (compute_pipe_bpp)
 		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
 	else
 		pipe_bpp = pipe_config->pipe_bpp;
 
+	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+
 	if (intel_dp->force_dsc_bpc) {
 		pipe_bpp = intel_dp->force_dsc_bpc * 3;
 		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
-- 
2.25.1

Re: [Intel-gfx] [PATCH v9 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Tuesday, February 7, 2023 1:14 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v9 2/7] drm/i915/dp: Check if DSC supports the given
> output_format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Go with DSC only if the given output_format is supported.
> 
> v2: Use drm helper to get DSC format support for sink.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cb4fbcd935db..73a7baccd7d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1494,6 +1494,31 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
> 
> +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> +					 enum intel_output_format output_format)
> {
> +	u8 sink_dsc_format;
> +
> +	switch (output_format) {
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +		sink_dsc_format = DP_DSC_RGB;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		sink_dsc_format = DP_DSC_YCbCr444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		if (min(intel_dp_source_dsc_version_minor(intel_dp),
> +			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
> +			return false;
> +		sink_dsc_format = DP_DSC_YCbCr420_Native;
> +		break;
> +	default:
> +		return false;
> +	}
> +
> +	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +sink_dsc_format); }
> +
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config,
>  				struct drm_connector_state *conn_state, @@ -
> 1514,11 +1539,16 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
> 
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	if (compute_pipe_bpp)
>  		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> >max_requested_bpc);
>  	else
>  		pipe_bpp = pipe_config->pipe_bpp;
> 
> +	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> +conn_state->max_requested_bpc);

This seems to be  wrong as it unconditionally overwrites the non-compress case.

> +
>  	if (intel_dp->force_dsc_bpc) {
>  		pipe_bpp = intel_dp->force_dsc_bpc * 3;
>  		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d",
> pipe_bpp);
> --
> 2.25.1

[Intel-gfx] [PATCH v9 3/7] drm/i915: Adding the new registers for DSC

[Suraj Kandpal]

Adding new DSC register which are introducted MTL onwards

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 596efc940ee7..9e25e21d37e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7715,6 +7715,8 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define  DSC_NATIVE_422_ENABLE		BIT(23)
+#define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
 #define  DSC_VBR_ENABLE			(1 << 19)
 #define  DSC_422_ENABLE			(1 << 18)
@@ -7959,6 +7961,32 @@ enum skl_power_gate {
 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
 
+/* MTL Display Stream Compression registers */
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
+#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
+#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
+
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
+#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
+#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
+#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
-- 
2.25.1

[Intel-gfx] [PATCH v9 4/7] drm/i915: Enable YCbCr420 for VDSC

[Suraj Kandpal]

Implementation of VDSC for YCbCr420.
Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c
(Derived from C-Model, which is given along with DSC1.2a Spec from Vesa)
intel_lookup_range_min/max_qp functons need to take into account the
output format. Based on that appropriate qp table need to be chosen.
Other rc_parameters need to be set where currently values for 444 format
is hardcoded in calculate_rc_parameters( ).
vdsc_cfg struct needs to be filled with output format information, where
these are hardcoded for 444 format.
Bspec: 49259

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 3 files changed, 180 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..6e86c0971d24 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -17,6 +17,15 @@
 /* from BPP 6 to 36 in steps of 0.5 */
 #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
 
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP		17
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP	23
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP	29
+
 /*
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
@@ -283,26 +292,182 @@ static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
 	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
 };
 
-#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
-	if (bpc == (_bpc)) \
-		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 }
+};
+
+static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
+	{ 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
+	{ 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
+	{ 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
+	{ 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
+	{ 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
+	{ 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
+	{ 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
+	  2, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
+	  5, 4, 4 }
+};
+
+static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
+	  0 },
+	{ 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+	  0 },
+	{ 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
+	  1 },
+	{ 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
+	  1 },
+	{ 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
+	  2, 1 },
+	{ 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
+	  2, 2 },
+	{ 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
+	  2, 2 },
+	{ 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
+	  3, 3, 2 },
+	{ 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
+	  4, 3, 3 },
+	{ 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
+	  6, 6, 5, 5 }
+};
+
+static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
+	  0, 0, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
+	  2, 1, 1, 1, 1, 1, 0 },
+	{ 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
+	  3, 2, 2, 1, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
+	  5, 4, 4, 2, 2, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
+	  5, 4, 4, 3, 2, 2, 1, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
+	  6, 5, 4, 3, 3, 2, 2, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
+	{ 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
+	  8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
+	  10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
+	  0, 0, 0, 0, 0, 0 },
+	{ 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
+	  1, 1, 1, 0, 0, 0, 0 },
+	{ 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
+	  4, 3, 2, 2, 1, 1, 0, 0, 0 },
+	{ 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
+	  4, 4, 3, 2, 2, 2, 1, 1, 0 },
+	{ 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
+	  5, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
+	  6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
+	{ 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
+	{ 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
+	  8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
+	{ 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
+	{ 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
+	  9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
+	{ 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
+	  11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 }
+};
+
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(min, 8, buf_i, bpp_i);
-	PARAM_TABLE(min, 10, buf_i, bpp_i);
-	PARAM_TABLE(min, 12, buf_i, bpp_i);
+	PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
 }
 
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(max, 8, buf_i, bpp_i);
-	PARAM_TABLE(max, 10, buf_i, bpp_i);
-	PARAM_TABLE(max, 12, buf_i, bpp_i);
+	PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
index 9fb3c36bd7c6..a9ff9ca29938 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed16f63d6355 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
 	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 		/* Read range_minqp and range_max_qp from qp tables */
 		rc->rc_range_params[buf_i].range_min_qp =
-			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 		rc->rc_range_params[buf_i].range_max_qp =
-			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 
 		/* Calculate range_bgp_offset */
 		if (bpp <= 6) {
-- 
2.25.1

[Intel-gfx] [PATCH v9 5/7] drm/i915: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c | 72 ++++++++++++++++++++++-
 3 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 003cac918228..f8c999fa3242 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 73a7baccd7d0..250d9cdd14b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1470,9 +1470,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
 
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
-
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
 		drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..13ad853e24eb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = !(pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+				  pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444);
+
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
+	/* Gen 11 does not support YCbCr422 */
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	/*
+	 * According to DSC 1.2 specs if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +627,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +944,34 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		if (is_pipe_dsc(crtc, cpu_transcoder)) {
+			intel_de_write(dev_priv,
+				       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+			if (crtc_state->dsc.dsc_split)
+				intel_de_write(dev_priv,
+					       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+					       pps_val);
+		}
+	}
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
-- 
2.25.1

Re: [Intel-gfx] [PATCH v9 5/7] drm/i915: Fill in native_420 field

[Jani Nikula]

On Tue, 07 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Now that we have laid the groundwork for YUV420 Enablement
> we fill up native_420 field in vdsc_cfg and add appropriate
> checks wherever required.
>
> ---v2
> -adding native_422 field as 0 [Vandita]
> -filling in second_line_bpg_offset, second_line_offset_adj
> and nsl_bpg_offset in vds_cfg when native_420 is true
>
> ---v3
> -adding display version check to solve igt issue
>
> --v7
> -remove is_pipe_dsc check as its always true for D14 [Jani]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
>  drivers/gpu/drm/i915/display/intel_dp.c   |  3 -
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 72 ++++++++++++++++++++++-
>  3 files changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 003cac918228..f8c999fa3242 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>  	if (crtc_state->dsc.slice_count > 1)
>  		crtc_state->dsc.dsc_split = true;
>  
> -	vdsc_cfg->convert_rgb = true;
> -
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 73a7baccd7d0..250d9cdd14b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1470,9 +1470,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
>  		min(intel_dp_source_dsc_version_minor(intel_dp),
>  		    intel_dp_sink_dsc_version_minor(intel_dp));
>  
> -	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> -		DP_DSC_RGB;

Are the sink caps taken into account somewhere else?

> -
>  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
>  	if (!line_buf_depth) {
>  		drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ed16f63d6355..13ad853e24eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> -
> -	/* Gen 11 does not support YCbCr */
> +	/*
> +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
> +	 * else 1
> +	 */
> +	vdsc_cfg->convert_rgb = !(pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> +				  pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444);

Nitpick, IMO "format != x && format != y" reads better than "!(format ==
x || format == y)"

> +
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		vdsc_cfg->native_420 = true;
> +	/* We do not support YcBCr422 as of now */
> +	vdsc_cfg->native_422 = false;
> +	/* Gen 11 does not support YCbCr422 */
>  	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
>  
>  	/* Gen 11 only supports integral values of bpp */
>  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> +	/*
> +	 * According to DSC 1.2 specs if native_420 is set:
> +	 * -We need to double the current bpp.
> +	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
> +	 * height < 8.
> +	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
> +	 * preservation in second line.
> +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
> +	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
> +	 * fractional bits.
> +	 */
> +	if (vdsc_cfg->native_420) {
> +		vdsc_cfg->bits_per_pixel <<= 1;
> +		if (vdsc_cfg->slice_height >= 8)
> +			vdsc_cfg->second_line_bpg_offset = 12;
> +		else
> +			vdsc_cfg->second_line_bpg_offset =
> +				2 * (vdsc_cfg->slice_height - 1);
> +		vdsc_cfg->second_line_offset_adj = 512;
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
> +							vdsc_cfg->slice_height - 1);
> +	}
> +
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>  
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> @@ -594,8 +627,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  		DSC_VER_MIN_SHIFT |
>  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
>  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> -	if (vdsc_cfg->dsc_version_minor == 2)
> +	if (vdsc_cfg->dsc_version_minor == 2) {
>  		pps_val |= DSC_ALT_ICH_SEL;
> +		if (vdsc_cfg->native_420)
> +			pps_val |= DSC_NATIVE_420_ENABLE;
> +		if (vdsc_cfg->native_422)
> +			pps_val |= DSC_NATIVE_422_ENABLE;
> +	}
>  	if (vdsc_cfg->block_pred_enable)
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> @@ -906,6 +944,34 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  				       pps_val);
>  	}
>  
> +	if (DISPLAY_VER(dev_priv) >= 14) {
> +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
> +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> +				       pps_val);
> +
> +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> +			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
> +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> +		if (is_pipe_dsc(crtc, cpu_transcoder)) {

This is still always true for display ver >= 14.

> +			intel_de_write(dev_priv,
> +				       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> +				       pps_val);
> +			if (crtc_state->dsc.dsc_split)
> +				intel_de_write(dev_priv,
> +					       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> +					       pps_val);
> +		}
> +	}
>  	/* Populate the RC_BUF_THRESH registers */
>  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v9 5/7] drm/i915: Fill in native_420 field

[Kandpal, Suraj]

> On Tue, 07 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Now that we have laid the groundwork for YUV420 Enablement we fill up
> > native_420 field in vdsc_cfg and add appropriate checks wherever
> > required.
> >
> > ---v2
> > -adding native_422 field as 0 [Vandita] -filling in
> > second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> > vds_cfg when native_420 is true
> >
> > ---v3
> > -adding display version check to solve igt issue
> >
> > --v7
> > -remove is_pipe_dsc check as its always true for D14 [Jani]
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  3 -
> >  drivers/gpu/drm/i915/display/intel_vdsc.c | 72
> > ++++++++++++++++++++++-
> >  3 files changed, 69 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 003cac918228..f8c999fa3242 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
> >  	if (crtc_state->dsc.slice_count > 1)
> >  		crtc_state->dsc.dsc_split = true;
> >
> > -	vdsc_cfg->convert_rgb = true;
> > -
> >  	/* FIXME: initialize from VBT */
> >  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 73a7baccd7d0..250d9cdd14b8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1470,9 +1470,6 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
> >  		min(intel_dp_source_dsc_version_minor(intel_dp),
> >  		    intel_dp_sink_dsc_version_minor(intel_dp));
> >
> > -	vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> > -		DP_DSC_RGB;
> 
> Are the sink caps taken into account somewhere else?

Looking at it again I should move it after intel_dsc_compute_params and check sink capability 
If convert_rgb is set as true there

> 
> > -
> >  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp-
> >dsc_dpcd);
> >  	if (!line_buf_depth) {
> >  		drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ed16f63d6355..13ad853e24eb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
> >  	vdsc_cfg->pic_width = pipe_config-
> >hw.adjusted_mode.crtc_hdisplay;
> >  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> >  					     pipe_config->dsc.slice_count);
> > -
> > -	/* Gen 11 does not support YCbCr */
> > +	/*
> > +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb
> is 0
> > +	 * else 1
> > +	 */
> > +	vdsc_cfg->convert_rgb = !(pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > +				  pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR444);
> 
> Nitpick, IMO "format != x && format != y" reads better than "!(format == x ||
> format == y)"
> 

Sure will change this in the next revision

Regards,
Suraj Kandpal
> > +
> > +	if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> > +		vdsc_cfg->native_420 = true;
> > +	/* We do not support YcBCr422 as of now */
> > +	vdsc_cfg->native_422 = false;
> > +	/* Gen 11 does not support YCbCr422 */
> >  	vdsc_cfg->simple_422 = false;
> >  	/* Gen 11 does not support VBR */
> >  	vdsc_cfg->vbr_enable = false;
> >
> >  	/* Gen 11 only supports integral values of bpp */
> >  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> > +	/*
> > +	 * According to DSC 1.2 specs if native_420 is set:
> > +	 * -We need to double the current bpp.
> > +	 * -second_line_bpg_offset is 12 in general and equal to
> 2*(slice_height-1) if slice
> > +	 * height < 8.
> > +	 * -second_line_offset_adj is 512 as shown by emperical values to
> yeild best chroma
> > +	 * preservation in second line.
> > +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1
> then rounded
> > +	 * up to 16 fractional bits, we left shift second line offset by 11 to
> preserve 11
> > +	 * fractional bits.
> > +	 */
> > +	if (vdsc_cfg->native_420) {
> > +		vdsc_cfg->bits_per_pixel <<= 1;
> > +		if (vdsc_cfg->slice_height >= 8)
> > +			vdsc_cfg->second_line_bpg_offset = 12;
> > +		else
> > +			vdsc_cfg->second_line_bpg_offset =
> > +				2 * (vdsc_cfg->slice_height - 1);
> > +		vdsc_cfg->second_line_offset_adj = 512;
> > +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> >second_line_bpg_offset << 11,
> > +							vdsc_cfg-
> >slice_height - 1);
> > +	}
> > +
> >  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +627,13
> @@
> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> *crtc_state)
> >  		DSC_VER_MIN_SHIFT |
> >  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> >  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> > -	if (vdsc_cfg->dsc_version_minor == 2)
> > +	if (vdsc_cfg->dsc_version_minor == 2) {
> >  		pps_val |= DSC_ALT_ICH_SEL;
> > +		if (vdsc_cfg->native_420)
> > +			pps_val |= DSC_NATIVE_420_ENABLE;
> > +		if (vdsc_cfg->native_422)
> > +			pps_val |= DSC_NATIVE_422_ENABLE;
> > +	}
> >  	if (vdsc_cfg->block_pred_enable)
> >  		pps_val |= DSC_BLOCK_PREDICTION;
> >  	if (vdsc_cfg->convert_rgb)
> > @@ -906,6 +944,34 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
> >  				       pps_val);
> >  	}
> >
> > +	if (DISPLAY_VER(dev_priv) >= 14) {
> > +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> > +		pps_val = 0;
> > +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> > +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n",
> pps_val);
> > +		intel_de_write(dev_priv,
> > +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> > +			       pps_val);
> > +		if (crtc_state->dsc.dsc_split)
> > +			intel_de_write(dev_priv,
> > +
> MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> > +				       pps_val);
> > +
> > +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> > +		pps_val = 0;
> > +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg-
> >nsl_bpg_offset) |
> > +			   DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
> > +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n",
> pps_val);
> > +		if (is_pipe_dsc(crtc, cpu_transcoder)) {
> 
> This is still always true for display ver >= 14.
> 
> > +			intel_de_write(dev_priv,
> > +
> MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> > +				       pps_val);
> > +			if (crtc_state->dsc.dsc_split)
> > +				intel_de_write(dev_priv,
> > +
> MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> > +					       pps_val);
> > +		}
> > +	}
> >  	/* Populate the RC_BUF_THRESH registers */
> >  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

--v10
-keep sink capability check [Jani]
-move from !(x == y  || w == z) to x !=y && w != z [Jani]

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 05e749861658..7065203460d3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1a397ab710dd..baa5af7d3bdc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->dsc_version_minor =
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
+	if (vdsc_cfg->convert_rgb)
+		vdsc_cfg->convert_rgb =
+			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+			DP_DSC_RGB;
 
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..19f9fb53f139 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+				pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
+
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
+	/* Gen 11 does not support YCbCr422 */
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	/*
+	 * According to DSC 1.2 specs if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +627,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +944,32 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+	}
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
-- 
2.25.1

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Wednesday, February 15, 2023 8:47 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field

Append "display"

> 
> Now that we have laid the groundwork for YUV420 Enablement we fill up native_420
> field in vdsc_cfg and add appropriate checks wherever required.
> 
> ---v2
> -adding native_422 field as 0 [Vandita]
> -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> vds_cfg when native_420 is true
> 
> ---v3
> -adding display version check to solve igt issue
> 
> --v7
> -remove is_pipe_dsc check as its always true for D14 [Jani]
> 
> --v10
> -keep sink capability check [Jani]
> -move from !(x == y  || w == z) to x !=y && w != z [Jani]
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 05e749861658..7065203460d3 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
>  	if (crtc_state->dsc.slice_count > 1)
>  		crtc_state->dsc.dsc_split = true;
> 
> -	vdsc_cfg->convert_rgb = true;
> -
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1a397ab710dd..baa5af7d3bdc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	vdsc_cfg->dsc_version_minor =
>  		min(intel_dp_source_dsc_version_minor(intel_dp),
>  		    intel_dp_sink_dsc_version_minor(intel_dp));
> -
> -	vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> -		DP_DSC_RGB;
> +	if (vdsc_cfg->convert_rgb)
> +		vdsc_cfg->convert_rgb =
> +			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
> DP_DSC_SUPPORT] &
> +			DP_DSC_RGB;
> 
>  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
>  	if (!line_buf_depth) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ed16f63d6355..19f9fb53f139 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> -
> -	/* Gen 11 does not support YCbCr */
> +	/*
> +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
> +	 * else 1
> +	 */
> +	vdsc_cfg->convert_rgb = pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR420 &&
> +				pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		vdsc_cfg->native_420 = true;
> +	/* We do not support YcBCr422 as of now */
> +	vdsc_cfg->native_422 = false;
> +	/* Gen 11 does not support YCbCr422 */

This comment can be merged with the one above.

>  	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
> 
>  	/* Gen 11 only supports integral values of bpp */
>  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;

Leave a line gap here

> +	/*
> +	 * According to DSC 1.2 specs if native_420 is set:

It would be good to add the section name as well for ease of reference.

> +	 * -We need to double the current bpp.
> +	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if
> slice
> +	 * height < 8.
> +	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best
> chroma
> +	 * preservation in second line.
> +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then
> rounded
> +	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve
> 11
> +	 * fractional bits.
> +	 */
> +	if (vdsc_cfg->native_420) {
> +		vdsc_cfg->bits_per_pixel <<= 1;

Leave a line gap here

> +		if (vdsc_cfg->slice_height >= 8)
> +			vdsc_cfg->second_line_bpg_offset = 12;
> +		else
> +			vdsc_cfg->second_line_bpg_offset =
> +				2 * (vdsc_cfg->slice_height - 1);

Here as well

> +		vdsc_cfg->second_line_offset_adj = 512;
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> >second_line_bpg_offset << 11,
> +							vdsc_cfg->slice_height - 1);

The parameters we compute here are being programmed only for gen14. We should
limit the computation if they are going to be unused for prior platforms.

> +	}
> +
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> 
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +627,13 @@
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  		DSC_VER_MIN_SHIFT |
>  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
>  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> -	if (vdsc_cfg->dsc_version_minor == 2)
> +	if (vdsc_cfg->dsc_version_minor == 2) {
>  		pps_val |= DSC_ALT_ICH_SEL;
> +		if (vdsc_cfg->native_420)
> +			pps_val |= DSC_NATIVE_420_ENABLE;
> +		if (vdsc_cfg->native_422)
> +			pps_val |= DSC_NATIVE_422_ENABLE;
> +	}
>  	if (vdsc_cfg->block_pred_enable)
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> @@ -906,6 +944,32 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  				       pps_val);
>  	}
> 
> +	if (DISPLAY_VER(dev_priv) >= 14) {
> +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> +				       pps_val);
> +
> +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> +			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
> +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> +				       pps_val);
> +	}

Leave a line gap.

>  	/* Populate the RC_BUF_THRESH registers */
>  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> --
> 2.25.1

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field

[Kandpal, Suraj]

> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> > Suraj Kandpal
> > Sent: Wednesday, February 15, 2023 8:47 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420
> > field
> 
> Append "display"
> 

drm/i915/display ?

> >
> > Now that we have laid the groundwork for YUV420 Enablement we fill up
> > native_420 field in vdsc_cfg and add appropriate checks wherever
> required.
> >
> > ---v2
> > -adding native_422 field as 0 [Vandita] -filling in
> > second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> > vds_cfg when native_420 is true
> >
> > ---v3
> > -adding display version check to solve igt issue
> >
> > --v7
> > -remove is_pipe_dsc check as its always true for D14 [Jani]
> >
> > --v10
> > -keep sink capability check [Jani]
> > -move from !(x == y  || w == z) to x !=y && w != z [Jani]
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 05e749861658..7065203460d3 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct
> > intel_encoder *encoder,
> >  	if (crtc_state->dsc.slice_count > 1)
> >  		crtc_state->dsc.dsc_split = true;
> >
> > -	vdsc_cfg->convert_rgb = true;
> > -
> >  	/* FIXME: initialize from VBT */
> >  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 1a397ab710dd..baa5af7d3bdc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct
> > intel_encoder *encoder,
> >  	vdsc_cfg->dsc_version_minor =
> >  		min(intel_dp_source_dsc_version_minor(intel_dp),
> >  		    intel_dp_sink_dsc_version_minor(intel_dp));
> > -
> > -	vdsc_cfg->convert_rgb = intel_dp-
> > >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> > -		DP_DSC_RGB;
> > +	if (vdsc_cfg->convert_rgb)
> > +		vdsc_cfg->convert_rgb =
> > +			intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
> > DP_DSC_SUPPORT] &
> > +			DP_DSC_RGB;
> >
> >  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp-
> >dsc_dpcd);
> >  	if (!line_buf_depth) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ed16f63d6355..19f9fb53f139 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state
> > *pipe_config)
> >  	vdsc_cfg->pic_width = pipe_config-
> >hw.adjusted_mode.crtc_hdisplay;
> >  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> >  					     pipe_config->dsc.slice_count);
> > -
> > -	/* Gen 11 does not support YCbCr */
> > +	/*
> > +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb
> is 0
> > +	 * else 1
> > +	 */
> > +	vdsc_cfg->convert_rgb = pipe_config->output_format !=
> > INTEL_OUTPUT_FORMAT_YCBCR420 &&
> > +				pipe_config->output_format !=
> > INTEL_OUTPUT_FORMAT_YCBCR444;
> > +
> > +	if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> > +		vdsc_cfg->native_420 = true;
> > +	/* We do not support YcBCr422 as of now */
> > +	vdsc_cfg->native_422 = false;
> > +	/* Gen 11 does not support YCbCr422 */
> 
> This comment can be merged with the one above.
> 

Can I remove "/* Gen 11 does not support YCbCr422 */ "
And just keep "/* We do not support YcBCr422 as of now */" or
Make it something like " Gen 11+ does not support YCbCr422 "

> >  	vdsc_cfg->simple_422 = false;
> >  	/* Gen 11 does not support VBR */
> >  	vdsc_cfg->vbr_enable = false;
> >
> >  	/* Gen 11 only supports integral values of bpp */
> >  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> 
> Leave a line gap here
> 
> > +	/*
> > +	 * According to DSC 1.2 specs if native_420 is set:
> 
> It would be good to add the section name as well for ease of reference.
> 
> > +	 * -We need to double the current bpp.
> > +	 * -second_line_bpg_offset is 12 in general and equal to
> > +2*(slice_height-1) if
> > slice
> > +	 * height < 8.
> > +	 * -second_line_offset_adj is 512 as shown by emperical values to
> > +yeild best
> > chroma
> > +	 * preservation in second line.
> > +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height
> > +-1 then
> > rounded
> > +	 * up to 16 fractional bits, we left shift second line offset by 11
> > +to preserve
> > 11
> > +	 * fractional bits.
> > +	 */
> > +	if (vdsc_cfg->native_420) {
> > +		vdsc_cfg->bits_per_pixel <<= 1;
> 
> Leave a line gap here
> 
> > +		if (vdsc_cfg->slice_height >= 8)
> > +			vdsc_cfg->second_line_bpg_offset = 12;
> > +		else
> > +			vdsc_cfg->second_line_bpg_offset =
> > +				2 * (vdsc_cfg->slice_height - 1);
> 
> Here as well
> 
> > +		vdsc_cfg->second_line_offset_adj = 512;
> > +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> > >second_line_bpg_offset << 11,
> > +							vdsc_cfg-
> >slice_height - 1);
> 
> The parameters we compute here are being programmed only for gen14. We
> should limit the computation if they are going to be unused for prior
> platforms.

How about we make native_420 field of vdsc_cfg true only if DISPLAY_VER() >= 14
this should take care of not filling any extra fields or computations

Regards,
Suraj Kandpal
> 
> > +	}
> > +
> >  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +627,13
> @@
> > static void intel_dsc_pps_configure(const struct intel_crtc_state
> *crtc_state)
> >  		DSC_VER_MIN_SHIFT |
> >  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> >  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> > -	if (vdsc_cfg->dsc_version_minor == 2)
> > +	if (vdsc_cfg->dsc_version_minor == 2) {
> >  		pps_val |= DSC_ALT_ICH_SEL;
> > +		if (vdsc_cfg->native_420)
> > +			pps_val |= DSC_NATIVE_420_ENABLE;
> > +		if (vdsc_cfg->native_422)
> > +			pps_val |= DSC_NATIVE_422_ENABLE;
> > +	}
> >  	if (vdsc_cfg->block_pred_enable)
> >  		pps_val |= DSC_BLOCK_PREDICTION;
> >  	if (vdsc_cfg->convert_rgb)
> > @@ -906,6 +944,32 @@ static void intel_dsc_pps_configure(const struct
> > intel_crtc_state *crtc_state)
> >  				       pps_val);
> >  	}
> >
> > +	if (DISPLAY_VER(dev_priv) >= 14) {
> > +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> > +		pps_val = 0;
> > +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> > >second_line_bpg_offset);
> > +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n",
> pps_val);
> > +		intel_de_write(dev_priv,
> > +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> > +			       pps_val);
> > +		if (crtc_state->dsc.dsc_split)
> > +			intel_de_write(dev_priv,
> > +
> > MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> > +				       pps_val);
> > +
> > +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> > +		pps_val = 0;
> > +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg-
> >nsl_bpg_offset) |
> > +			   DSC_SL_OFFSET_ADJ(vdsc_cfg-
> >second_line_offset_adj);
> > +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n",
> pps_val);
> > +		intel_de_write(dev_priv,
> > +			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> > +			       pps_val);
> > +		if (crtc_state->dsc.dsc_split)
> > +			intel_de_write(dev_priv,
> > +
> > MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> > +				       pps_val);
> > +	}
> 
> Leave a line gap.
> 
> >  	/* Populate the RC_BUF_THRESH registers */
> >  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > --
> > 2.25.1

Re: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, February 21, 2023 10:11 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420 field
> 
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Suraj Kandpal
> > > Sent: Wednesday, February 15, 2023 8:47 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH v10 5/7] drm/i915: Fill in native_420
> > > field
> >
> > Append "display"
> >
> 
> drm/i915/display ?

Yes

> > >
> > > Now that we have laid the groundwork for YUV420 Enablement we fill
> > > up
> > > native_420 field in vdsc_cfg and add appropriate checks wherever
> > required.
> > >
> > > ---v2
> > > -adding native_422 field as 0 [Vandita] -filling in
> > > second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> > > vds_cfg when native_420 is true
> > >
> > > ---v3
> > > -adding display version check to solve igt issue
> > >
> > > --v7
> > > -remove is_pipe_dsc check as its always true for D14 [Jani]
> > >
> > > --v10
> > > -keep sink capability check [Jani]
> > > -move from !(x == y  || w == z) to x !=y && w != z [Jani]
> > >
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > index 05e749861658..7065203460d3 100644
> > > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > > @@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct
> > > intel_encoder *encoder,
> > >  	if (crtc_state->dsc.slice_count > 1)
> > >  		crtc_state->dsc.dsc_split = true;
> > >
> > > -	vdsc_cfg->convert_rgb = true;
> > > -
> > >  	/* FIXME: initialize from VBT */
> > >  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 1a397ab710dd..baa5af7d3bdc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct
> > > intel_encoder *encoder,
> > >  	vdsc_cfg->dsc_version_minor =
> > >  		min(intel_dp_source_dsc_version_minor(intel_dp),
> > >  		    intel_dp_sink_dsc_version_minor(intel_dp));
> > > -
> > > -	vdsc_cfg->convert_rgb = intel_dp-
> > > >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> > > -		DP_DSC_RGB;
> > > +	if (vdsc_cfg->convert_rgb)
> > > +		vdsc_cfg->convert_rgb =
> > > +			intel_dp-
> > >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -  DP_DSC_SUPPORT] &
> > > +			DP_DSC_RGB;
> > >
> > >  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp-
> > >dsc_dpcd);
> > >  	if (!line_buf_depth) {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > index ed16f63d6355..19f9fb53f139 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > > @@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct
> > >intel_crtc_state
> > > *pipe_config)
> > >  	vdsc_cfg->pic_width = pipe_config- hw.adjusted_mode.crtc_hdisplay;
> > >  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> > >  					     pipe_config->dsc.slice_count);
> > > -
> > > -	/* Gen 11 does not support YCbCr */
> > > +	/*
> > > +	 * According to DSC 1.2 specs if colorspace is YCbCr then
> > > +convert_rgb
> > is 0
> > > +	 * else 1
> > > +	 */
> > > +	vdsc_cfg->convert_rgb = pipe_config->output_format !=
> > > INTEL_OUTPUT_FORMAT_YCBCR420 &&
> > > +				pipe_config->output_format !=
> > > INTEL_OUTPUT_FORMAT_YCBCR444;
> > > +
> > > +	if (pipe_config->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR420)
> > > +		vdsc_cfg->native_420 = true;
> > > +	/* We do not support YcBCr422 as of now */
> > > +	vdsc_cfg->native_422 = false;
> > > +	/* Gen 11 does not support YCbCr422 */
> >
> > This comment can be merged with the one above.
> >
> 
> Can I remove "/* Gen 11 does not support YCbCr422 */ "
> And just keep "/* We do not support YcBCr422 as of now */" or Make it something
> like " Gen 11+ does not support YCbCr422 "

I think "/* We do not support YcBCr422 as of now */" looks better.

> > >  	vdsc_cfg->simple_422 = false;
> > >  	/* Gen 11 does not support VBR */
> > >  	vdsc_cfg->vbr_enable = false;
> > >
> > >  	/* Gen 11 only supports integral values of bpp */
> > >  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> >
> > Leave a line gap here
> >
> > > +	/*
> > > +	 * According to DSC 1.2 specs if native_420 is set:
> >
> > It would be good to add the section name as well for ease of reference.
> >
> > > +	 * -We need to double the current bpp.
> > > +	 * -second_line_bpg_offset is 12 in general and equal to
> > > +2*(slice_height-1) if
> > > slice
> > > +	 * height < 8.
> > > +	 * -second_line_offset_adj is 512 as shown by emperical values to
> > > +yeild best
> > > chroma
> > > +	 * preservation in second line.
> > > +	 * -nsl_bpg_offset is calculated as
> > > +second_line_offset/slice_height
> > > +-1 then
> > > rounded
> > > +	 * up to 16 fractional bits, we left shift second line offset by
> > > +11 to preserve
> > > 11
> > > +	 * fractional bits.
> > > +	 */
> > > +	if (vdsc_cfg->native_420) {
> > > +		vdsc_cfg->bits_per_pixel <<= 1;
> >
> > Leave a line gap here
> >
> > > +		if (vdsc_cfg->slice_height >= 8)
> > > +			vdsc_cfg->second_line_bpg_offset = 12;
> > > +		else
> > > +			vdsc_cfg->second_line_bpg_offset =
> > > +				2 * (vdsc_cfg->slice_height - 1);
> >
> > Here as well
> >
> > > +		vdsc_cfg->second_line_offset_adj = 512;
> > > +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> > > >second_line_bpg_offset << 11,
> > > +							vdsc_cfg-
> > >slice_height - 1);
> >
> > The parameters we compute here are being programmed only for gen14. We
> > should limit the computation if they are going to be unused for prior
> > platforms.
> 
> How about we make native_420 field of vdsc_cfg true only if DISPLAY_VER() >= 14
> this should take care of not filling any extra fields or computations

Yeah we can even do that

Regards
Uma Shankar
 
> Regards,
> Suraj Kandpal
> >
> > > +	}
> > > +
> > >  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> > >
> > >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +627,13
> > @@
> > > static void intel_dsc_pps_configure(const struct intel_crtc_state
> > *crtc_state)
> > >  		DSC_VER_MIN_SHIFT |
> > >  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
> > >  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> > > -	if (vdsc_cfg->dsc_version_minor == 2)
> > > +	if (vdsc_cfg->dsc_version_minor == 2) {
> > >  		pps_val |= DSC_ALT_ICH_SEL;
> > > +		if (vdsc_cfg->native_420)
> > > +			pps_val |= DSC_NATIVE_420_ENABLE;
> > > +		if (vdsc_cfg->native_422)
> > > +			pps_val |= DSC_NATIVE_422_ENABLE;
> > > +	}
> > >  	if (vdsc_cfg->block_pred_enable)
> > >  		pps_val |= DSC_BLOCK_PREDICTION;
> > >  	if (vdsc_cfg->convert_rgb)
> > > @@ -906,6 +944,32 @@ static void intel_dsc_pps_configure(const
> > > struct intel_crtc_state *crtc_state)
> > >  				       pps_val);
> > >  	}
> > >
> > > +	if (DISPLAY_VER(dev_priv) >= 14) {
> > > +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> > > +		pps_val = 0;
> > > +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> > > >second_line_bpg_offset);
> > > +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n",
> > pps_val);
> > > +		intel_de_write(dev_priv,
> > > +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> > > +			       pps_val);
> > > +		if (crtc_state->dsc.dsc_split)
> > > +			intel_de_write(dev_priv,
> > > +
> > > MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> > > +				       pps_val);
> > > +
> > > +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> > > +		pps_val = 0;
> > > +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg-
> > >nsl_bpg_offset) |
> > > +			   DSC_SL_OFFSET_ADJ(vdsc_cfg-
> > >second_line_offset_adj);
> > > +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n",
> > pps_val);
> > > +		intel_de_write(dev_priv,
> > > +			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> > > +			       pps_val);
> > > +		if (crtc_state->dsc.dsc_split)
> > > +			intel_de_write(dev_priv,
> > > +
> > > MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> > > +				       pps_val);
> > > +	}
> >
> > Leave a line gap.
> >
> > >  	/* Populate the RC_BUF_THRESH registers */
> > >  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
> > >  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > > --
> > > 2.25.1

[Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design requirement

[Suraj Kandpal]

Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement

--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]

--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 13ad853e24eb..6ebefc195e83 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
 	}
 }
 
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
+					    struct drm_dsc_config *vdsc_cfg)
+{
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+		if (vdsc_cfg->slice_height > 4095)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)
+			return -EINVAL;
+	} else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		if (vdsc_cfg->slice_width % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height > 4094)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
 	struct rc_parameters *rc = NULL;
+	int err;
 	u8 i = 0;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
+
+	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+	if (err) {
+		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+		return err;
+	}
+
 	/*
 	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
 	 * else 1
-- 
2.25.1

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design requirement

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Tuesday, February 7, 2023 1:14 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design requirement
> 
> Add function to check if slice design requirements are being met as defined in Bspec:
> 49259 in the section Slice Design Requirement
> 
> --v7
> -remove full bspec link [Jani]
> -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid
> [Jani]
> 
> --v8
> -fix condition to check if slice width and height are of two -fix minimum pixel in slice
> condition
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 13ad853e24eb..6ebefc195e83 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
>  	}
>  }
> 
> +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
> +					    struct drm_dsc_config *vdsc_cfg) {
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> +		if (vdsc_cfg->slice_height > 4095)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)

This should be greater than 15000 for valid case, please check

> +			return -EINVAL;
> +	} else if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420) {
> +		if (vdsc_cfg->slice_width % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height > 4094)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)

This should be greater than 30000 for valid case, please check

> +			return -EINVAL;
> +	}
> +
> +	return 0;

If code reaches here, format is 422 which should be EINVAL as of now.

> +}
> +
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)  {
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
>  	const struct rc_parameters *rc_params;
>  	struct rc_parameters *rc = NULL;
> +	int err;
>  	u8 i = 0;
> 
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> +
> +	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> +
> +	if (err) {
> +		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not
> met\n");
> +		return err;
> +	}
> +
>  	/*
>  	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
>  	 * else 1
> --
> 2.25.1

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design requirement

[Kandpal, Suraj]

> >
> > +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state
> *pipe_config,
> > +					    struct drm_dsc_config *vdsc_cfg) {
> > +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> > +	    pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR444) {
> > +		if (vdsc_cfg->slice_height > 4095)
> > +			return -EINVAL;
> > +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)
> 
> This should be greater than 15000 for valid case, please check
> 
> > +			return -EINVAL;
> > +	} else if (pipe_config->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR420) {
> > +		if (vdsc_cfg->slice_width % 2)
> > +			return -EINVAL;
> > +		if (vdsc_cfg->slice_height % 2)
> > +			return -EINVAL;
> > +		if (vdsc_cfg->slice_height > 4094)
> > +			return -EINVAL;
> > +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)
> 
> This should be greater than 30000 for valid case, please check
> 

I missed this will fix it the condition should have been < 30000/15000

> > +			return -EINVAL;
> > +	}
> > +
> > +	return 0;
> 
> If code reaches here, format is 422 which should be EINVAL as of now.
> 

Not necessarily code can also reach here if all the slice dimension requirements are
met for any format also AFAIK INTEL_OUTPUT_FORMAT_YCBCR422 has not been defined
yet hence can be found in crtc_state->output_format

Regards,
Suraj Kandpal

> > +}
> > +
> >  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)  {
> >  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state
> > *pipe_config)
> >  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> >  	const struct rc_parameters *rc_params;
> >  	struct rc_parameters *rc = NULL;
> > +	int err;
> >  	u8 i = 0;
> >
> >  	vdsc_cfg->pic_width = pipe_config-
> >hw.adjusted_mode.crtc_hdisplay;
> >  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> >  					     pipe_config->dsc.slice_count);
> > +
> > +	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> > +
> > +	if (err) {
> > +		drm_dbg_kms(&dev_priv->drm, "Slice dimension
> requirements not
> > met\n");
> > +		return err;
> > +	}
> > +
> >  	/*
> >  	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb
> is 0
> >  	 * else 1
> > --
> > 2.25.1

Re: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design requirement

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, February 21, 2023 9:51 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH v9 6/7] drm/i915/vdsc: Check slice design
> requirement
> 
> > >
> > > +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state
> > *pipe_config,
> > > +					    struct drm_dsc_config *vdsc_cfg) {
> > > +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> > > +	    pipe_config->output_format ==
> > INTEL_OUTPUT_FORMAT_YCBCR444) {
> > > +		if (vdsc_cfg->slice_height > 4095)
> > > +			return -EINVAL;
> > > +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)
> >
> > This should be greater than 15000 for valid case, please check
> >
> > > +			return -EINVAL;
> > > +	} else if (pipe_config->output_format ==
> > > INTEL_OUTPUT_FORMAT_YCBCR420) {
> > > +		if (vdsc_cfg->slice_width % 2)
> > > +			return -EINVAL;
> > > +		if (vdsc_cfg->slice_height % 2)
> > > +			return -EINVAL;
> > > +		if (vdsc_cfg->slice_height > 4094)
> > > +			return -EINVAL;
> > > +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)
> >
> > This should be greater than 30000 for valid case, please check
> >
> 
> I missed this will fix it the condition should have been < 30000/15000
> 
> > > +			return -EINVAL;
> > > +	}
> > > +
> > > +	return 0;
> >
> > If code reaches here, format is 422 which should be EINVAL as of now.
> >
> 
> Not necessarily code can also reach here if all the slice dimension requirements are
> met for any format also AFAIK INTEL_OUTPUT_FORMAT_YCBCR422 has not been
> defined yet hence can be found in crtc_state->output_format

Oh yeah, missed that. But it would be good to have a check for YCBCR422 just to
restrict it here.

Regards,
Uma Shankar

> Regards,
> Suraj Kandpal
> 
> > > +}
> > > +
> > >  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)  {
> > >  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > > @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct
> > > intel_crtc_state
> > > *pipe_config)
> > >  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> > >  	const struct rc_parameters *rc_params;
> > >  	struct rc_parameters *rc = NULL;
> > > +	int err;
> > >  	u8 i = 0;
> > >
> > >  	vdsc_cfg->pic_width = pipe_config- hw.adjusted_mode.crtc_hdisplay;
> > >  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> > >  					     pipe_config->dsc.slice_count);
> > > +
> > > +	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> > > +
> > > +	if (err) {
> > > +		drm_dbg_kms(&dev_priv->drm, "Slice dimension
> > requirements not
> > > met\n");
> > > +		return err;
> > > +	}
> > > +
> > >  	/*
> > >  	 * According to DSC 1.2 specs if colorspace is YCbCr then
> > > convert_rgb
> > is 0
> > >  	 * else 1
> > > --
> > > 2.25.1

[Intel-gfx] [PATCH v9 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Suraj Kandpal]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
Also, new debugfs entry is created to enforce output format. This is
required because of our driver policy. For ex. if a mode is supported
in both RGB and YCbCr420 output formats by the sink, our policy is to
try RGB first and fall back to YCbCr420, if mode cannot be shown
using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
we need a debugfs entry (force_dsc_output_format) to force this
output format.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
 .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 11 +++
 5 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..9913f22e0f79 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
 	WARN_ON_ONCE(output_types != 0);
 }
 
-static const char * const output_format_str[] = {
+const char * const output_format_str[] = {
 	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
 	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
 	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 };
 
-static const char *output_formats(enum intel_output_format format)
+const char *output_formats(enum intel_output_format format)
 {
 	if (format >= ARRAY_SIZE(output_format_str))
 		return "invalid";
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
index 9399c35b7e5e..daf0a7cc0702 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -8,9 +8,11 @@
 
 struct intel_crtc_state;
 struct intel_atomic_state;
+enum intel_output_format;
 
 void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
 			   struct intel_atomic_state *state,
 			   const char *context);
+const char *output_formats(enum intel_output_format format);
 
 #endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 9e2fb8626c96..27b7d8dafe66 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
 #include "i915_irq.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
@@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(crtc_state->dsc.compression_enable));
 		seq_printf(m, "DSC_Sink_Support: %s\n",
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_RGB)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr444)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_output_format_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "DSC_Output_Format: %s\n", output_formats(crtc_state->output_format));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_output_format_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int dsc_output_format = 0;
+	int ret;
+
+	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->force_dsc_output_format = dsc_output_format;
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_output_format_open(struct inode *inode,
+				       struct file *file)
+{
+	return single_open(file, i915_dsc_output_format_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_output_format_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_output_format_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_output_format_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_output_format", 0644, root,
+				    connector, &i915_dsc_output_format_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..9f7951b49c42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	int force_dsc_output_format;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 250d9cdd14b8..bd2d3d11e85b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,6 +76,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_crtc_state_dump.h"
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -2063,6 +2064,16 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
 	bool ycbcr_420_only;
 	int ret;
 
+	if (intel_dp->force_dsc_output_format) {
+		crtc_state->output_format = intel_dp->force_dsc_output_format;
+		drm_dbg_kms(&i915->drm, "DSC output format forced to %s",
+			    output_formats(crtc_state->output_format));
+
+		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
+						   respect_downstream_limits);
+		return ret;
+	}
+
 	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
 
 	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
-- 
2.25.1

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Jani Nikula]

On Tue, 07 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
>
> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
> to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
> Also, new debugfs entry is created to enforce output format. This is
> required because of our driver policy. For ex. if a mode is supported
> in both RGB and YCbCr420 output formats by the sink, our policy is to
> try RGB first and fall back to YCbCr420, if mode cannot be shown
> using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
> we need a debugfs entry (force_dsc_output_format) to force this
> output format.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
>  .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
>  .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 11 +++
>  5 files changed, 93 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 2422d6ef5777..9913f22e0f79 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
>  	WARN_ON_ONCE(output_types != 0);
>  }
>  
> -static const char * const output_format_str[] = {
> +const char * const output_format_str[] = {

Why?

>  	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>  	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>  	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>  };
>  
> -static const char *output_formats(enum intel_output_format format)
> +const char *output_formats(enum intel_output_format format)

output_formats is too generic a name to be non-static.

>  {
>  	if (format >= ARRAY_SIZE(output_format_str))
>  		return "invalid";
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> index 9399c35b7e5e..daf0a7cc0702 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> @@ -8,9 +8,11 @@
>  
>  struct intel_crtc_state;
>  struct intel_atomic_state;
> +enum intel_output_format;
>  
>  void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>  			   struct intel_atomic_state *state,
>  			   const char *context);
> +const char *output_formats(enum intel_output_format format);

And maybe the place for the function is not here at all if it's needed
in multiple places.

>  
>  #endif /* __INTEL_CRTC_STATE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 9e2fb8626c96..27b7d8dafe66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -12,6 +12,7 @@
>  #include "i915_irq.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_crtc_state_dump.h"
>  #include "intel_display_debugfs.h"
>  #include "intel_display_power.h"
>  #include "intel_display_power_well.h"
> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  			   str_yes_no(crtc_state->dsc.compression_enable));
>  		seq_printf(m, "DSC_Sink_Support: %s\n",
>  			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_RGB)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_YCbCr420_Native)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_YCbCr444)));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>  	.write = i915_dsc_bpc_write
>  };
>  
> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	crtc_state = to_intel_crtc_state(crtc->state);
> +	seq_printf(m, "DSC_Output_Format: %s\n", output_formats(crtc_state->output_format));
> +
> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_output_format_write(struct file *file,
> +					    const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	int dsc_output_format = 0;
> +	int ret;
> +
> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
> +	if (ret < 0)
> +		return ret;
> +
> +	intel_dp->force_dsc_output_format = dsc_output_format;
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_output_format_open(struct inode *inode,
> +				       struct file *file)
> +{
> +	return single_open(file, i915_dsc_output_format_show, inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_output_format_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_output_format_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_output_format_write
> +};
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  
>  		debugfs_create_file("i915_dsc_bpc", 0644, root,
>  				    connector, &i915_dsc_bpc_fops);
> +
> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
> +				    connector, &i915_dsc_output_format_fops);
>  	}
>  
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9ccae7a46020..9f7951b49c42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
>  
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
> +	int force_dsc_output_format;
>  	int force_dsc_bpc;
>  
>  	bool hobl_failed;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 250d9cdd14b8..bd2d3d11e85b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -76,6 +76,7 @@
>  #include "intel_tc.h"
>  #include "intel_vdsc.h"
>  #include "intel_vrr.h"
> +#include "intel_crtc_state_dump.h"
>  
>  /* DP DSC throughput values used for slice count calculations KPixels/s */
>  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> @@ -2063,6 +2064,16 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>  	bool ycbcr_420_only;
>  	int ret;
>  
> +	if (intel_dp->force_dsc_output_format) {
> +		crtc_state->output_format = intel_dp->force_dsc_output_format;
> +		drm_dbg_kms(&i915->drm, "DSC output format forced to %s",
> +			    output_formats(crtc_state->output_format));
> +
> +		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> +						   respect_downstream_limits);

Please don't duplicate the call to
intel_dp_compute_output_format(). Force the output format and try to use
the regular path otherwise. With the above approach, testing with the
forced output format uses a different path than is used otherwise.

BR,
Jani.

> +		return ret;
> +	}
> +
>  	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>  
>  	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Swati Sharma]

Hi Jani,

Thanks for the reviews. Please find my replies inline.

On 07-Feb-23 2:05 PM, Jani Nikula wrote:
> On Tue, 07 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
>> to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
>> Also, new debugfs entry is created to enforce output format. This is
>> required because of our driver policy. For ex. if a mode is supported
>> in both RGB and YCbCr420 output formats by the sink, our policy is to
>> try RGB first and fall back to YCbCr420, if mode cannot be shown
>> using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
>> we need a debugfs entry (force_dsc_output_format) to force this
>> output format.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>   .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
>>   .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
>>   .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       | 11 +++
>>   5 files changed, 93 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> index 2422d6ef5777..9913f22e0f79 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> @@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
>>   	WARN_ON_ONCE(output_types != 0);
>>   }
>>   
>> -static const char * const output_format_str[] = {
>> +const char * const output_format_str[] = {
> 
> Why?
> 
>>   	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>>   	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>>   	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>>   };
>>   
>> -static const char *output_formats(enum intel_output_format format)
>> +const char *output_formats(enum intel_output_format format)
> 
> output_formats is too generic a name to be non-static.

Is intel_output_formats name okay?

> 
>>   {
>>   	if (format >= ARRAY_SIZE(output_format_str))
>>   		return "invalid";
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> index 9399c35b7e5e..daf0a7cc0702 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> @@ -8,9 +8,11 @@
>>   
>>   struct intel_crtc_state;
>>   struct intel_atomic_state;
>> +enum intel_output_format;
>>   
>>   void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>>   			   struct intel_atomic_state *state,
>>   			   const char *context);
>> +const char *output_formats(enum intel_output_format format);
> 
> And maybe the place for the function is not here at all if it's needed
> in multiple places.

Can I create an inline static function in intel_display_types.h instead?
> 
>>   
>>   #endif /* __INTEL_CRTC_STATE_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 9e2fb8626c96..27b7d8dafe66 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -12,6 +12,7 @@
>>   #include "i915_irq.h"
>>   #include "i915_reg.h"
>>   #include "intel_de.h"
>> +#include "intel_crtc_state_dump.h"
>>   #include "intel_display_debugfs.h"
>>   #include "intel_display_power.h"
>>   #include "intel_display_power_well.h"
>> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>   			   str_yes_no(crtc_state->dsc.compression_enable));
>>   		seq_printf(m, "DSC_Sink_Support: %s\n",
>>   			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
>> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_RGB)),
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_YCbCr420_Native)),
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_YCbCr444)));
>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>   			   str_yes_no(intel_dp->force_dsc_en));
>>   		if (!intel_dp_is_edp(intel_dp))
>> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>>   	.write = i915_dsc_bpc_write
>>   };
>>   
>> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>> +{
>> +	struct drm_connector *connector = m->private;
>> +	struct drm_device *dev = connector->dev;
>> +	struct drm_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	int ret;
>> +
>> +	if (!encoder)
>> +		return -ENODEV;
>> +
>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>> +	if (ret)
>> +		return ret;
>> +
>> +	crtc = connector->state->crtc;
>> +	if (connector->status != connector_status_connected || !crtc) {
>> +		ret = -ENODEV;
>> +		goto out;
>> +	}
>> +
>> +	crtc_state = to_intel_crtc_state(crtc->state);
>> +	seq_printf(m, "DSC_Output_Format: %s\n", output_formats(crtc_state->output_format));
>> +
>> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>> +
>> +	return ret;
>> +}
>> +
>> +static ssize_t i915_dsc_output_format_write(struct file *file,
>> +					    const char __user *ubuf,
>> +					    size_t len, loff_t *offp)
>> +{
>> +	struct drm_connector *connector =
>> +		((struct seq_file *)file->private_data)->private;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +	int dsc_output_format = 0;
>> +	int ret;
>> +
>> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	intel_dp->force_dsc_output_format = dsc_output_format;
>> +	*offp += len;
>> +
>> +	return len;
>> +}
>> +
>> +static int i915_dsc_output_format_open(struct inode *inode,
>> +				       struct file *file)
>> +{
>> +	return single_open(file, i915_dsc_output_format_show, inode->i_private);
>> +}
>> +
>> +static const struct file_operations i915_dsc_output_format_fops = {
>> +	.owner = THIS_MODULE,
>> +	.open = i915_dsc_output_format_open,
>> +	.read = seq_read,
>> +	.llseek = seq_lseek,
>> +	.release = single_release,
>> +	.write = i915_dsc_output_format_write
>> +};
>> +
>>   /*
>>    * Returns the Current CRTC's bpc.
>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>   
>>   		debugfs_create_file("i915_dsc_bpc", 0644, root,
>>   				    connector, &i915_dsc_bpc_fops);
>> +
>> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
>> +				    connector, &i915_dsc_output_format_fops);
>>   	}
>>   
>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9ccae7a46020..9f7951b49c42 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1743,6 +1743,7 @@ struct intel_dp {
>>   
>>   	/* Display stream compression testing */
>>   	bool force_dsc_en;
>> +	int force_dsc_output_format;
>>   	int force_dsc_bpc;
>>   
>>   	bool hobl_failed;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 250d9cdd14b8..bd2d3d11e85b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -76,6 +76,7 @@
>>   #include "intel_tc.h"
>>   #include "intel_vdsc.h"
>>   #include "intel_vrr.h"
>> +#include "intel_crtc_state_dump.h"
>>   
>>   /* DP DSC throughput values used for slice count calculations KPixels/s */
>>   #define DP_DSC_PEAK_PIXEL_RATE			2720000
>> @@ -2063,6 +2064,16 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>   	bool ycbcr_420_only;
>>   	int ret;
>>   
>> +	if (intel_dp->force_dsc_output_format) {
>> +		crtc_state->output_format = intel_dp->force_dsc_output_format;
>> +		drm_dbg_kms(&i915->drm, "DSC output format forced to %s",
>> +			    output_formats(crtc_state->output_format));
>> +
>> +		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> +						   respect_downstream_limits);
> 
> Please don't duplicate the call to
> intel_dp_compute_output_format(). Force the output format and try to use
> the regular path otherwise. With the above approach, testing with the
> forced output format uses a different path than is used otherwise.

Jani, crtc_state->output_format will be set to force_dsc_output_format 
in case we are forcing o/p format and in normal case output format is 
computed from intel_dp_output_format(). That's it. We are not using 
different path. Please suggest if you see this otherwise.

> 
> BR,
> Jani.
> 
>> +		return ret;
>> +	}
>> +
>>   	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>>   
>>   	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
> 

-- 
~Swati Sharma

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Jani Nikula]

On Wed, 08 Feb 2023, Swati Sharma <swati2.sharma@intel.com> wrote:
> Hi Jani,
>
> Thanks for the reviews. Please find my replies inline.
>
> On 07-Feb-23 2:05 PM, Jani Nikula wrote:
>> On Tue, 07 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>> From: Swati Sharma <swati2.sharma@intel.com>
>>>
>>> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
>>> to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
>>> Also, new debugfs entry is created to enforce output format. This is
>>> required because of our driver policy. For ex. if a mode is supported
>>> in both RGB and YCbCr420 output formats by the sink, our policy is to
>>> try RGB first and fall back to YCbCr420, if mode cannot be shown
>>> using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
>>> we need a debugfs entry (force_dsc_output_format) to force this
>>> output format.
>>>
>>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>>> ---
>>>   .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
>>>   .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
>>>   .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>>   drivers/gpu/drm/i915/display/intel_dp.c       | 11 +++
>>>   5 files changed, 93 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>>> index 2422d6ef5777..9913f22e0f79 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>>> @@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
>>>   	WARN_ON_ONCE(output_types != 0);
>>>   }
>>>   
>>> -static const char * const output_format_str[] = {
>>> +const char * const output_format_str[] = {
>> 
>> Why?
>> 
>>>   	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>>>   	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>>>   	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>>>   };
>>>   
>>> -static const char *output_formats(enum intel_output_format format)
>>> +const char *output_formats(enum intel_output_format format)
>> 
>> output_formats is too generic a name to be non-static.
>
> Is intel_output_formats name okay?

intel_output_format_name() would be in line with all the similar
functions we have.

>
>> 
>>>   {
>>>   	if (format >= ARRAY_SIZE(output_format_str))
>>>   		return "invalid";
>>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>>> index 9399c35b7e5e..daf0a7cc0702 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>>> @@ -8,9 +8,11 @@
>>>   
>>>   struct intel_crtc_state;
>>>   struct intel_atomic_state;
>>> +enum intel_output_format;
>>>   
>>>   void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>>>   			   struct intel_atomic_state *state,
>>>   			   const char *context);
>>> +const char *output_formats(enum intel_output_format format);
>> 
>> And maybe the place for the function is not here at all if it's needed
>> in multiple places.
>
> Can I create an inline static function in intel_display_types.h instead?

I'd rather you left it here, no matter how out-of-place it feels,
instead of adding more static inlines anywhere.

>> 
>>>   
>>>   #endif /* __INTEL_CRTC_STATE_H__ */
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> index 9e2fb8626c96..27b7d8dafe66 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>>> @@ -12,6 +12,7 @@
>>>   #include "i915_irq.h"
>>>   #include "i915_reg.h"
>>>   #include "intel_de.h"
>>> +#include "intel_crtc_state_dump.h"
>>>   #include "intel_display_debugfs.h"
>>>   #include "intel_display_power.h"
>>>   #include "intel_display_power_well.h"
>>> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>>   			   str_yes_no(crtc_state->dsc.compression_enable));
>>>   		seq_printf(m, "DSC_Sink_Support: %s\n",
>>>   			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
>>> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
>>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>> +								      DP_DSC_RGB)),
>>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>> +								      DP_DSC_YCbCr420_Native)),
>>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>>> +								      DP_DSC_YCbCr444)));
>>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>>   			   str_yes_no(intel_dp->force_dsc_en));
>>>   		if (!intel_dp_is_edp(intel_dp))
>>> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>>>   	.write = i915_dsc_bpc_write
>>>   };
>>>   
>>> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>>> +{
>>> +	struct drm_connector *connector = m->private;
>>> +	struct drm_device *dev = connector->dev;
>>> +	struct drm_crtc *crtc;
>>> +	struct intel_crtc_state *crtc_state;
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	int ret;
>>> +
>>> +	if (!encoder)
>>> +		return -ENODEV;
>>> +
>>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	crtc = connector->state->crtc;
>>> +	if (connector->status != connector_status_connected || !crtc) {
>>> +		ret = -ENODEV;
>>> +		goto out;
>>> +	}
>>> +
>>> +	crtc_state = to_intel_crtc_state(crtc->state);
>>> +	seq_printf(m, "DSC_Output_Format: %s\n", output_formats(crtc_state->output_format));
>>> +
>>> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>>> +
>>> +	return ret;
>>> +}
>>> +
>>> +static ssize_t i915_dsc_output_format_write(struct file *file,
>>> +					    const char __user *ubuf,
>>> +					    size_t len, loff_t *offp)
>>> +{
>>> +	struct drm_connector *connector =
>>> +		((struct seq_file *)file->private_data)->private;
>>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>> +	int dsc_output_format = 0;
>>> +	int ret;
>>> +
>>> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
>>> +	if (ret < 0)
>>> +		return ret;
>>> +
>>> +	intel_dp->force_dsc_output_format = dsc_output_format;
>>> +	*offp += len;
>>> +
>>> +	return len;
>>> +}
>>> +
>>> +static int i915_dsc_output_format_open(struct inode *inode,
>>> +				       struct file *file)
>>> +{
>>> +	return single_open(file, i915_dsc_output_format_show, inode->i_private);
>>> +}
>>> +
>>> +static const struct file_operations i915_dsc_output_format_fops = {
>>> +	.owner = THIS_MODULE,
>>> +	.open = i915_dsc_output_format_open,
>>> +	.read = seq_read,
>>> +	.llseek = seq_lseek,
>>> +	.release = single_release,
>>> +	.write = i915_dsc_output_format_write
>>> +};
>>> +
>>>   /*
>>>    * Returns the Current CRTC's bpc.
>>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>>> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>>   
>>>   		debugfs_create_file("i915_dsc_bpc", 0644, root,
>>>   				    connector, &i915_dsc_bpc_fops);
>>> +
>>> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
>>> +				    connector, &i915_dsc_output_format_fops);
>>>   	}
>>>   
>>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 9ccae7a46020..9f7951b49c42 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1743,6 +1743,7 @@ struct intel_dp {
>>>   
>>>   	/* Display stream compression testing */
>>>   	bool force_dsc_en;
>>> +	int force_dsc_output_format;
>>>   	int force_dsc_bpc;
>>>   
>>>   	bool hobl_failed;
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index 250d9cdd14b8..bd2d3d11e85b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -76,6 +76,7 @@
>>>   #include "intel_tc.h"
>>>   #include "intel_vdsc.h"
>>>   #include "intel_vrr.h"
>>> +#include "intel_crtc_state_dump.h"
>>>   
>>>   /* DP DSC throughput values used for slice count calculations KPixels/s */
>>>   #define DP_DSC_PEAK_PIXEL_RATE			2720000
>>> @@ -2063,6 +2064,16 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>>   	bool ycbcr_420_only;
>>>   	int ret;
>>>   
>>> +	if (intel_dp->force_dsc_output_format) {
>>> +		crtc_state->output_format = intel_dp->force_dsc_output_format;
>>> +		drm_dbg_kms(&i915->drm, "DSC output format forced to %s",
>>> +			    output_formats(crtc_state->output_format));
>>> +
>>> +		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>>> +						   respect_downstream_limits);
>> 
>> Please don't duplicate the call to
>> intel_dp_compute_output_format(). Force the output format and try to use
>> the regular path otherwise. With the above approach, testing with the
>> forced output format uses a different path than is used otherwise.
>
> Jani, crtc_state->output_format will be set to force_dsc_output_format 
> in case we are forcing o/p format and in normal case output format is 
> computed from intel_dp_output_format(). That's it. We are not using 
> different path. Please suggest if you see this otherwise.

My point is, the whole intel_dp_compute_output_format() is completely
different, with different checks and different error handling, with
intel_dp->force_dsc_output_format set.

If you use this for testing, you're not testing any of the checks here.

And it's more lines of code to maintain and understand. The next person
to come along to add more stuff here will wonder whether their changes
should apply to the special path as well, or only the regular path.

Consider what it would all look like if you handled
intel_dp->force_dsc_output_format in intel_dp_output_format() instead:

static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
		       bool ycbcr_420_output)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);

	if (intel_dp->force_dsc_output_format)
		return intel_dp->force_dsc_output_format;

	if (intel_dp->dfp.rgb_to_ycbcr &&
	    intel_dp->dfp.ycbcr_444_to_420)
		return INTEL_OUTPUT_FORMAT_RGB;
...


BR,
Jani.

>
>> 
>> BR,
>> Jani.
>> 
>>> +		return ret;
>>> +	}
>>> +
>>>   	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
>>>   
>>>   	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [v10] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Swati Sharma]

DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
Also, new debugfs entry is created to enforce output format. This is
required because of our driver policy. For ex. if a mode is supported
in both RGB and YCbCr420 output formats by the sink, our policy is to
try RGB first and fall back to YCbCr420, if mode cannot be shown
using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
we need a debugfs entry (force_dsc_output_format) to force this
output format.

v2: -Func name changed to intel_output_format_name() (Jani N)
    -Return forced o/p format from intel_dp_output_format() (Jani N)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
 .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
 5 files changed, 87 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..2408ba88b0b6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
 	WARN_ON_ONCE(output_types != 0);
 }
 
-static const char * const output_format_str[] = {
+const char * const output_format_str[] = {
 	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
 	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
 	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 };
 
-static const char *output_formats(enum intel_output_format format)
+const char *intel_output_format_name(enum intel_output_format format)
 {
 	if (format >= ARRAY_SIZE(output_format_str))
 		return "invalid";
@@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		    "active: %s, output_types: %s (0x%x), output format: %s\n",
 		    str_yes_no(pipe_config->hw.active),
 		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
+		    intel_output_format_name(pipe_config->output_format));
 
 	drm_dbg_kms(&i915->drm,
 		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
index 9399c35b7e5e..780f3f1190d7 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -8,9 +8,11 @@
 
 struct intel_crtc_state;
 struct intel_atomic_state;
+enum intel_output_format;
 
 void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
 			   struct intel_atomic_state *state,
 			   const char *context);
+const char *intel_output_format_name(enum intel_output_format format);
 
 #endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 9e2fb8626c96..e4b04c690e4f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
 #include "i915_irq.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
@@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(crtc_state->dsc.compression_enable));
 		seq_printf(m, "DSC_Sink_Support: %s\n",
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_RGB)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr444)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_output_format_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_output_format_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int dsc_output_format = 0;
+	int ret;
+
+	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->force_dsc_output_format = dsc_output_format;
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_output_format_open(struct inode *inode,
+				       struct file *file)
+{
+	return single_open(file, i915_dsc_output_format_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_output_format_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_output_format_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_output_format_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_output_format", 0644, root,
+				    connector, &i915_dsc_output_format_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..9f7951b49c42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	int force_dsc_output_format;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4a5f7c476305..fccb69a58111 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,6 +76,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_crtc_state_dump.h"
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
+	if (intel_dp->force_dsc_output_format)
+		return intel_dp->force_dsc_output_format;
+
 	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 		return INTEL_OUTPUT_FORMAT_RGB;
 
-- 
2.25.1

Re: [Intel-gfx] [v10] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Jani Nikula]

On Tue, 14 Feb 2023, Swati Sharma <swati2.sharma@intel.com> wrote:
> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
> to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
> Also, new debugfs entry is created to enforce output format. This is
> required because of our driver policy. For ex. if a mode is supported
> in both RGB and YCbCr420 output formats by the sink, our policy is to
> try RGB first and fall back to YCbCr420, if mode cannot be shown
> using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
> we need a debugfs entry (force_dsc_output_format) to force this
> output format.
>
> v2: -Func name changed to intel_output_format_name() (Jani N)
>     -Return forced o/p format from intel_dp_output_format() (Jani N)
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
>  .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
>  .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
>  5 files changed, 87 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 2422d6ef5777..2408ba88b0b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
>  	WARN_ON_ONCE(output_types != 0);
>  }
>  
> -static const char * const output_format_str[] = {
> +const char * const output_format_str[] = {

This still must remain static.

>  	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>  	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>  	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>  };
>  
> -static const char *output_formats(enum intel_output_format format)
> +const char *intel_output_format_name(enum intel_output_format format)
>  {
>  	if (format >= ARRAY_SIZE(output_format_str))
>  		return "invalid";
> @@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  		    "active: %s, output_types: %s (0x%x), output format: %s\n",
>  		    str_yes_no(pipe_config->hw.active),
>  		    buf, pipe_config->output_types,
> -		    output_formats(pipe_config->output_format));
> +		    intel_output_format_name(pipe_config->output_format));
>  
>  	drm_dbg_kms(&i915->drm,
>  		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> index 9399c35b7e5e..780f3f1190d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> @@ -8,9 +8,11 @@
>  
>  struct intel_crtc_state;
>  struct intel_atomic_state;
> +enum intel_output_format;
>  
>  void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>  			   struct intel_atomic_state *state,
>  			   const char *context);
> +const char *intel_output_format_name(enum intel_output_format format);
>  
>  #endif /* __INTEL_CRTC_STATE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 9e2fb8626c96..e4b04c690e4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -12,6 +12,7 @@
>  #include "i915_irq.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_crtc_state_dump.h"
>  #include "intel_display_debugfs.h"
>  #include "intel_display_power.h"
>  #include "intel_display_power_well.h"
> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  			   str_yes_no(crtc_state->dsc.compression_enable));
>  		seq_printf(m, "DSC_Sink_Support: %s\n",
>  			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_RGB)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_YCbCr420_Native)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +								      DP_DSC_YCbCr444)));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>  	.write = i915_dsc_bpc_write
>  };
>  
> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	crtc_state = to_intel_crtc_state(crtc->state);
> +	seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format));
> +
> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_output_format_write(struct file *file,
> +					    const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;
> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	int dsc_output_format = 0;
> +	int ret;
> +
> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
> +	if (ret < 0)
> +		return ret;
> +
> +	intel_dp->force_dsc_output_format = dsc_output_format;
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_output_format_open(struct inode *inode,
> +				       struct file *file)
> +{
> +	return single_open(file, i915_dsc_output_format_show, inode->i_private);
> +}
> +
> +static const struct file_operations i915_dsc_output_format_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_output_format_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_output_format_write
> +};
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  
>  		debugfs_create_file("i915_dsc_bpc", 0644, root,
>  				    connector, &i915_dsc_bpc_fops);
> +
> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
> +				    connector, &i915_dsc_output_format_fops);
>  	}
>  
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9ccae7a46020..9f7951b49c42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
>  
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
> +	int force_dsc_output_format;
>  	int force_dsc_bpc;
>  
>  	bool hobl_failed;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4a5f7c476305..fccb69a58111 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -76,6 +76,7 @@
>  #include "intel_tc.h"
>  #include "intel_vdsc.h"
>  #include "intel_vrr.h"
> +#include "intel_crtc_state_dump.h"
>  
>  /* DP DSC throughput values used for slice count calculations KPixels/s */
>  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> @@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
>  {
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  
> +	if (intel_dp->force_dsc_output_format)
> +		return intel_dp->force_dsc_output_format;
> +
>  	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
>  		return INTEL_OUTPUT_FORMAT_RGB;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [v10] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Swati Sharma]

Done. Thanks for the feedback. Next rev floated
https://patchwork.freedesktop.org/patch/522697/?series=113729&rev=3

On 14-Feb-23 4:21 PM, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Swati Sharma <swati2.sharma@intel.com> wrote:
>> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
>> to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
>> Also, new debugfs entry is created to enforce output format. This is
>> required because of our driver policy. For ex. if a mode is supported
>> in both RGB and YCbCr420 output formats by the sink, our policy is to
>> try RGB first and fall back to YCbCr420, if mode cannot be shown
>> using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
>> we need a debugfs entry (force_dsc_output_format) to force this
>> output format.
>>
>> v2: -Func name changed to intel_output_format_name() (Jani N)
>>      -Return forced o/p format from intel_dp_output_format() (Jani N)
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>   .../drm/i915/display/intel_crtc_state_dump.c  |  6 +-
>>   .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
>>   .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
>>   5 files changed, 87 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> index 2422d6ef5777..2408ba88b0b6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
>> @@ -115,13 +115,13 @@ static void snprintf_output_types(char *buf, size_t len,
>>   	WARN_ON_ONCE(output_types != 0);
>>   }
>>   
>> -static const char * const output_format_str[] = {
>> +const char * const output_format_str[] = {
> 
> This still must remain static.
> 
>>   	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>>   	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>>   	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>>   };
>>   
>> -static const char *output_formats(enum intel_output_format format)
>> +const char *intel_output_format_name(enum intel_output_format format)
>>   {
>>   	if (format >= ARRAY_SIZE(output_format_str))
>>   		return "invalid";
>> @@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>>   		    "active: %s, output_types: %s (0x%x), output format: %s\n",
>>   		    str_yes_no(pipe_config->hw.active),
>>   		    buf, pipe_config->output_types,
>> -		    output_formats(pipe_config->output_format));
>> +		    intel_output_format_name(pipe_config->output_format));
>>   
>>   	drm_dbg_kms(&i915->drm,
>>   		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
>> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> index 9399c35b7e5e..780f3f1190d7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
>> @@ -8,9 +8,11 @@
>>   
>>   struct intel_crtc_state;
>>   struct intel_atomic_state;
>> +enum intel_output_format;
>>   
>>   void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>>   			   struct intel_atomic_state *state,
>>   			   const char *context);
>> +const char *intel_output_format_name(enum intel_output_format format);
>>   
>>   #endif /* __INTEL_CRTC_STATE_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 9e2fb8626c96..e4b04c690e4f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -12,6 +12,7 @@
>>   #include "i915_irq.h"
>>   #include "i915_reg.h"
>>   #include "intel_de.h"
>> +#include "intel_crtc_state_dump.h"
>>   #include "intel_display_debugfs.h"
>>   #include "intel_display_power.h"
>>   #include "intel_display_power_well.h"
>> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>>   			   str_yes_no(crtc_state->dsc.compression_enable));
>>   		seq_printf(m, "DSC_Sink_Support: %s\n",
>>   			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
>> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_RGB)),
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_YCbCr420_Native)),
>> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>> +								      DP_DSC_YCbCr444)));
>>   		seq_printf(m, "Force_DSC_Enable: %s\n",
>>   			   str_yes_no(intel_dp->force_dsc_en));
>>   		if (!intel_dp_is_edp(intel_dp))
>> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>>   	.write = i915_dsc_bpc_write
>>   };
>>   
>> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>> +{
>> +	struct drm_connector *connector = m->private;
>> +	struct drm_device *dev = connector->dev;
>> +	struct drm_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	int ret;
>> +
>> +	if (!encoder)
>> +		return -ENODEV;
>> +
>> +	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
>> +	if (ret)
>> +		return ret;
>> +
>> +	crtc = connector->state->crtc;
>> +	if (connector->status != connector_status_connected || !crtc) {
>> +		ret = -ENODEV;
>> +		goto out;
>> +	}
>> +
>> +	crtc_state = to_intel_crtc_state(crtc->state);
>> +	seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format));
>> +
>> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>> +
>> +	return ret;
>> +}
>> +
>> +static ssize_t i915_dsc_output_format_write(struct file *file,
>> +					    const char __user *ubuf,
>> +					    size_t len, loff_t *offp)
>> +{
>> +	struct drm_connector *connector =
>> +		((struct seq_file *)file->private_data)->private;
>> +	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
>> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +	int dsc_output_format = 0;
>> +	int ret;
>> +
>> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	intel_dp->force_dsc_output_format = dsc_output_format;
>> +	*offp += len;
>> +
>> +	return len;
>> +}
>> +
>> +static int i915_dsc_output_format_open(struct inode *inode,
>> +				       struct file *file)
>> +{
>> +	return single_open(file, i915_dsc_output_format_show, inode->i_private);
>> +}
>> +
>> +static const struct file_operations i915_dsc_output_format_fops = {
>> +	.owner = THIS_MODULE,
>> +	.open = i915_dsc_output_format_open,
>> +	.read = seq_read,
>> +	.llseek = seq_lseek,
>> +	.release = single_release,
>> +	.write = i915_dsc_output_format_write
>> +};
>> +
>>   /*
>>    * Returns the Current CRTC's bpc.
>>    * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
>> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>   
>>   		debugfs_create_file("i915_dsc_bpc", 0644, root,
>>   				    connector, &i915_dsc_bpc_fops);
>> +
>> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
>> +				    connector, &i915_dsc_output_format_fops);
>>   	}
>>   
>>   	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9ccae7a46020..9f7951b49c42 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1743,6 +1743,7 @@ struct intel_dp {
>>   
>>   	/* Display stream compression testing */
>>   	bool force_dsc_en;
>> +	int force_dsc_output_format;
>>   	int force_dsc_bpc;
>>   
>>   	bool hobl_failed;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 4a5f7c476305..fccb69a58111 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -76,6 +76,7 @@
>>   #include "intel_tc.h"
>>   #include "intel_vdsc.h"
>>   #include "intel_vrr.h"
>> +#include "intel_crtc_state_dump.h"
>>   
>>   /* DP DSC throughput values used for slice count calculations KPixels/s */
>>   #define DP_DSC_PEAK_PIXEL_RATE			2720000
>> @@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
>>   {
>>   	struct intel_dp *intel_dp = intel_attached_dp(connector);
>>   
>> +	if (intel_dp->force_dsc_output_format)
>> +		return intel_dp->force_dsc_output_format;
>> +
>>   	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
>>   		return INTEL_OUTPUT_FORMAT_RGB;
> 

-- 
~Swati Sharma

[Intel-gfx] [v11] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Swati Sharma]

DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
Also, new debugfs entry is created to enforce output format. This is
required because of our driver policy. For ex. if a mode is supported
in both RGB and YCbCr420 output formats by the sink, our policy is to
try RGB first and fall back to YCbCr420, if mode cannot be shown
using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
we need a debugfs entry (force_dsc_output_format) to force this
output format.

v2: -Func name changed to intel_output_format_name() (Jani N)
    -Return forced o/p format from intel_dp_output_format() (Jani N)
v3: -output_format_str[] to remain static (Jani N)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
 .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
 5 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..45655efc9468 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -121,7 +121,7 @@ static const char * const output_format_str[] = {
 	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 };
 
-static const char *output_formats(enum intel_output_format format)
+const char *intel_output_format_name(enum intel_output_format format)
 {
 	if (format >= ARRAY_SIZE(output_format_str))
 		return "invalid";
@@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		    "active: %s, output_types: %s (0x%x), output format: %s\n",
 		    str_yes_no(pipe_config->hw.active),
 		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
+		    intel_output_format_name(pipe_config->output_format));
 
 	drm_dbg_kms(&i915->drm,
 		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
index 9399c35b7e5e..780f3f1190d7 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -8,9 +8,11 @@
 
 struct intel_crtc_state;
 struct intel_atomic_state;
+enum intel_output_format;
 
 void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
 			   struct intel_atomic_state *state,
 			   const char *context);
+const char *intel_output_format_name(enum intel_output_format format);
 
 #endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 9e2fb8626c96..e4b04c690e4f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
 #include "i915_irq.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
@@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(crtc_state->dsc.compression_enable));
 		seq_printf(m, "DSC_Sink_Support: %s\n",
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_RGB)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr444)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_output_format_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_output_format_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int dsc_output_format = 0;
+	int ret;
+
+	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->force_dsc_output_format = dsc_output_format;
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_output_format_open(struct inode *inode,
+				       struct file *file)
+{
+	return single_open(file, i915_dsc_output_format_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_output_format_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_output_format_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_output_format_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_output_format", 0644, root,
+				    connector, &i915_dsc_output_format_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..9f7951b49c42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	int force_dsc_output_format;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4a5f7c476305..fccb69a58111 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,6 +76,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_crtc_state_dump.h"
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
+	if (intel_dp->force_dsc_output_format)
+		return intel_dp->force_dsc_output_format;
+
 	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 		return INTEL_OUTPUT_FORMAT_RGB;
 
-- 
2.25.1

Re: [Intel-gfx] [v11] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Swati
> Sharma
> Sent: Tuesday, February 14, 2023 4:33 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [v11] drm/i915/dsc: Add debugfs entry to validate DSC output
> formats
> 
> DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show to
> depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
> Also, new debugfs entry is created to enforce output format. This is required
> because of our driver policy. For ex. if a mode is supported in both RGB and
> YCbCr420 output formats by the sink, our policy is to try RGB first and fall back to
> YCbCr420, if mode cannot be shown using RGB. So, to test other output formats like
> YCbCr420 or YCbCr444, we need a debugfs entry (force_dsc_output_format) to
> force this output format.
> 
> v2: -Func name changed to intel_output_format_name() (Jani N)
>     -Return forced o/p format from intel_dp_output_format() (Jani N)
> v3: -output_format_str[] to remain static (Jani N)

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>  .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
> .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
> .../drm/i915/display/intel_display_debugfs.c  | 77 +++++++++++++++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
>  5 files changed, 86 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 2422d6ef5777..45655efc9468 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -121,7 +121,7 @@ static const char * const output_format_str[] = {
>  	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",  };
> 
> -static const char *output_formats(enum intel_output_format format)
> +const char *intel_output_format_name(enum intel_output_format format)
>  {
>  	if (format >= ARRAY_SIZE(output_format_str))
>  		return "invalid";
> @@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state
> *pipe_config,
>  		    "active: %s, output_types: %s (0x%x), output format: %s\n",
>  		    str_yes_no(pipe_config->hw.active),
>  		    buf, pipe_config->output_types,
> -		    output_formats(pipe_config->output_format));
> +		    intel_output_format_name(pipe_config->output_format));
> 
>  	drm_dbg_kms(&i915->drm,
>  		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", diff --git
> a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> index 9399c35b7e5e..780f3f1190d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
> @@ -8,9 +8,11 @@
> 
>  struct intel_crtc_state;
>  struct intel_atomic_state;
> +enum intel_output_format;
> 
>  void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
>  			   struct intel_atomic_state *state,
>  			   const char *context);
> +const char *intel_output_format_name(enum intel_output_format format);
> 
>  #endif /* __INTEL_CRTC_STATE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 9e2fb8626c96..e4b04c690e4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -12,6 +12,7 @@
>  #include "i915_irq.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_crtc_state_dump.h"
>  #include "intel_display_debugfs.h"
>  #include "intel_display_power.h"
>  #include "intel_display_power_well.h"
> @@ -1770,6 +1771,13 @@ static int i915_dsc_fec_support_show(struct seq_file
> *m, void *data)
>  			   str_yes_no(crtc_state->dsc.compression_enable));
>  		seq_printf(m, "DSC_Sink_Support: %s\n",
>  			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp-
> >dsc_dpcd)));
> +		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s
> YCBCR420: %s YCBCR444: %s\n",
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp-
> >dsc_dpcd,
> +								      DP_DSC_RGB)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp-
> >dsc_dpcd,
> +
> DP_DSC_YCbCr420_Native)),
> +			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp-
> >dsc_dpcd,
> +
> DP_DSC_YCbCr444)));
>  		seq_printf(m, "Force_DSC_Enable: %s\n",
>  			   str_yes_no(intel_dp->force_dsc_en));
>  		if (!intel_dp_is_edp(intel_dp))
> @@ -1895,6 +1903,72 @@ static const struct file_operations i915_dsc_bpc_fops = {
>  	.write = i915_dsc_bpc_write
>  };
> 
> +static int i915_dsc_output_format_show(struct seq_file *m, void *data)
> +{
> +	struct drm_connector *connector = m->private;
> +	struct drm_device *dev = connector->dev;
> +	struct drm_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> +	int ret;
> +
> +	if (!encoder)
> +		return -ENODEV;
> +
> +	ret = drm_modeset_lock_single_interruptible(&dev-
> >mode_config.connection_mutex);
> +	if (ret)
> +		return ret;
> +
> +	crtc = connector->state->crtc;
> +	if (connector->status != connector_status_connected || !crtc) {
> +		ret = -ENODEV;
> +		goto out;
> +	}
> +
> +	crtc_state = to_intel_crtc_state(crtc->state);
> +	seq_printf(m, "DSC_Output_Format: %s\n",
> +intel_output_format_name(crtc_state->output_format));
> +
> +out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> +	return ret;
> +}
> +
> +static ssize_t i915_dsc_output_format_write(struct file *file,
> +					    const char __user *ubuf,
> +					    size_t len, loff_t *offp)
> +{
> +	struct drm_connector *connector =
> +		((struct seq_file *)file->private_data)->private;
> +	struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	int dsc_output_format = 0;
> +	int ret;
> +
> +	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
> +	if (ret < 0)
> +		return ret;
> +
> +	intel_dp->force_dsc_output_format = dsc_output_format;
> +	*offp += len;
> +
> +	return len;
> +}
> +
> +static int i915_dsc_output_format_open(struct inode *inode,
> +				       struct file *file)
> +{
> +	return single_open(file, i915_dsc_output_format_show,
> +inode->i_private); }
> +
> +static const struct file_operations i915_dsc_output_format_fops = {
> +	.owner = THIS_MODULE,
> +	.open = i915_dsc_output_format_open,
> +	.read = seq_read,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_dsc_output_format_write
> +};
> +
>  /*
>   * Returns the Current CRTC's bpc.
>   * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1966,6 +2040,9 @@ void intel_connector_debugfs_add(struct intel_connector
> *intel_connector)
> 
>  		debugfs_create_file("i915_dsc_bpc", 0644, root,
>  				    connector, &i915_dsc_bpc_fops);
> +
> +		debugfs_create_file("i915_dsc_output_format", 0644, root,
> +				    connector, &i915_dsc_output_format_fops);
>  	}
> 
>  	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || diff --
> git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9ccae7a46020..9f7951b49c42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
> 
>  	/* Display stream compression testing */
>  	bool force_dsc_en;
> +	int force_dsc_output_format;
>  	int force_dsc_bpc;
> 
>  	bool hobl_failed;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4a5f7c476305..fccb69a58111 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -76,6 +76,7 @@
>  #include "intel_tc.h"
>  #include "intel_vdsc.h"
>  #include "intel_vrr.h"
> +#include "intel_crtc_state_dump.h"
> 
>  /* DP DSC throughput values used for slice count calculations KPixels/s */
>  #define DP_DSC_PEAK_PIXEL_RATE			2720000
> @@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
> {
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
> 
> +	if (intel_dp->force_dsc_output_format)
> +		return intel_dp->force_dsc_output_format;
> +
>  	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
>  		return INTEL_OUTPUT_FORMAT_RGB;
> 
> --
> 2.25.1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/113729/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3690 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12707 -> Patchwork_113729v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/index.html

Participating hosts (37 -> 35)
------------------------------

  Missing    (2): fi-kbl-soraka fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_113729v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_tiled_blits@basic:
    - fi-pnv-d510:        [PASS][1] -> [SKIP][2] ([fdo#109271])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/fi-pnv-d510/igt@gem_tiled_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/fi-pnv-d510/igt@gem_tiled_blits@basic.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg1-5:          [PASS][3] -> [ABORT][4] ([i915#4983])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/bat-dg1-5/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/bat-dg1-5/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][5] ([i915#7229]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live@gt_lrc:
    - {bat-dg2-11}:       [INCOMPLETE][7] ([i915#7609] / [i915#7913]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913


Build changes
-------------

  * Linux: CI_DRM_12707 -> Patchwork_113729v1

  CI-20190529: 20190529
  CI_DRM_12707: 4553eb97820406ff3cbc51a3348ffabfe3b3110e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7152: 790b81207a0a6705213ec5ea645bc5e223b2ce1d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v1: 4553eb97820406ff3cbc51a3348ffabfe3b3110e @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3430efbafaba drm/i915/dsc: Add debugfs entry to validate DSC output formats
f467d8e93b5f drm/i915/vdsc: Check slice design requirement
963dc1002ca0 drm/i915: Fill in native_420 field
fb083ecc1dcd drm/i915: Enable YCbCr420 for VDSC
c5efe64a4570 drm/i915: Adding the new registers for DSC
f11a601a6476 drm/i915/dp: Check if DSC supports the given output_format
15a0b532b825 drm/dp_helper: Add helper to check if the sink supports given format with DSC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/index.html

[-- Attachment #2: Type: text/html, Size: 4225 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable YCbCr420 for VDSC

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 23956 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12707_full -> Patchwork_113729v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/index.html

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113729v1_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - {shard-rkl}:        [SKIP][1] ([i915#7828]) -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_cursor_crc@cursor-random-256x85:
    - {shard-rkl}:        [SKIP][3] ([i915#4098]) -> [SKIP][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@kms_cursor_crc@cursor-random-256x85.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85.html

  
Known issues
------------

  Here are the changes found in Patchwork_113729v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][5] -> [FAIL][6] ([i915#2842]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-glk:          NOTRUN -> [SKIP][7] ([fdo#109271]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-glk4/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#79])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - {shard-rkl}:        [FAIL][10] ([i915#7742]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@fbdev@info:
    - {shard-tglu}:       [SKIP][12] ([i915#2582]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@fbdev@info.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@fbdev@info.html

  * igt@fbdev@nullptr:
    - {shard-rkl}:        [SKIP][14] ([i915#2582]) -> [PASS][15] +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@fbdev@nullptr.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@fbdev@nullptr.html

  * igt@gem_ctx_persistence@hang:
    - {shard-rkl}:        [SKIP][16] ([i915#6252]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-5/igt@gem_ctx_persistence@hang.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-1/igt@gem_ctx_persistence@hang.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - {shard-rkl}:        [FAIL][18] ([i915#2842]) -> [PASS][19] +3 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-1/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - {shard-rkl}:        [SKIP][20] ([i915#3281]) -> [PASS][21] +11 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-cpu.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_readwrite@beyond-eob:
    - {shard-rkl}:        [SKIP][22] ([i915#3282]) -> [PASS][23] +2 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-6/igt@gem_readwrite@beyond-eob.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@gem_readwrite@beyond-eob.html

  * igt@gen9_exec_parse@bb-start-out:
    - {shard-rkl}:        [SKIP][24] ([i915#2527]) -> [PASS][25] +3 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@gen9_exec_parse@bb-start-out.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_pm_dc@dc9-dpms:
    - {shard-rkl}:        [SKIP][26] ([i915#3361]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - {shard-tglu}:       [SKIP][28] ([i915#3547]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@i915_pm_rpm@drm-resources-equal.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@i915_pm_rpm@fences:
    - {shard-rkl}:        [SKIP][30] ([i915#1849]) -> [PASS][31] +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-4/igt@i915_pm_rpm@fences.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@i915_pm_rpm@fences.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - {shard-tglu}:       [SKIP][32] ([i915#1397]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@i915_pm_rpm@modeset-lpsp.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - {shard-tglu}:       [SKIP][34] ([i915#1845] / [i915#7651]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][36] ([i915#1845] / [i915#4098]) -> [PASS][37] +30 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
    - {shard-tglu}:       [SKIP][38] ([i915#1849]) -> [PASS][39] +3 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
    - {shard-rkl}:        [SKIP][40] ([i915#1849] / [i915#4098]) -> [PASS][41] +18 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html

  * igt@kms_psr@primary_render:
    - {shard-rkl}:        [SKIP][42] ([i915#1072]) -> [PASS][43] +3 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-4/igt@kms_psr@primary_render.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@kms_psr@primary_render.html

  * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a:
    - {shard-tglu}:       [SKIP][44] ([fdo#109274]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-a.html

  * igt@kms_universal_plane@universal-plane-pipe-a-sanity:
    - {shard-rkl}:        [SKIP][46] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html

  * igt@kms_vblank@pipe-d-wait-busy:
    - {shard-tglu}:       [SKIP][48] ([i915#7651]) -> [PASS][49] +9 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-tglu-6/igt@kms_vblank@pipe-d-wait-busy.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-tglu-1/igt@kms_vblank@pipe-d-wait-busy.html

  * igt@perf@gen12-oa-tlb-invalidate:
    - {shard-rkl}:        [SKIP][50] ([fdo#109289]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-1/igt@perf@gen12-oa-tlb-invalidate.html

  * igt@perf@stress-open-close:
    - shard-glk:          [ABORT][52] ([i915#5213]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-glk8/igt@perf@stress-open-close.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-glk4/igt@perf@stress-open-close.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-rkl}:        [FAIL][54] ([i915#4349]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-1/igt@perf_pmu@idle@rcs0.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-3/igt@perf_pmu@idle@rcs0.html

  * igt@prime_vgem@basic-write:
    - {shard-rkl}:        [SKIP][56] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-rkl-6/igt@prime_vgem@basic-write.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-rkl-5/igt@prime_vgem@basic-write.html

  * igt@sysfs_heartbeat_interval@nopreempt@bcs0:
    - shard-glk:          [FAIL][58] -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12707/shard-glk8/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/shard-glk4/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
  [i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981


Build changes
-------------

  * Linux: CI_DRM_12707 -> Patchwork_113729v1

  CI-20190529: 20190529
  CI_DRM_12707: 4553eb97820406ff3cbc51a3348ffabfe3b3110e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7152: 790b81207a0a6705213ec5ea645bc5e223b2ce1d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v1: 4553eb97820406ff3cbc51a3348ffabfe3b3110e @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v1/index.html

[-- Attachment #2: Type: text/html, Size: 16199 bytes --]

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev3)

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev3)
URL   : https://patchwork.freedesktop.org/series/113729/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9010 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev3)
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12738 -> Patchwork_113729v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/index.html

Participating hosts (38 -> 39)
------------------------------

  Additional (3): fi-kbl-soraka fi-rkl-11600 fi-elk-e7500 
  Missing    (2): bat-atsm-1 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_113729v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - fi-rkl-11600:       NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@debugfs_test@basic-hwmon.html

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][2] -> [FAIL][3] ([i915#7229])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-rkl-11600:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][8] ([i915#3282])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][9] ([i915#7561])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-elk-e7500:       NOTRUN -> [SKIP][10] ([fdo#109271]) +30 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-elk-e7500/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@execlists:
    - fi-kbl-soraka:      NOTRUN -> [INCOMPLETE][11] ([i915#7156] / [i915#7913])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-kbl-soraka/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][12] ([i915#1886])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][13] ([fdo#109271]) +15 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - fi-rkl-11600:       NOTRUN -> [SKIP][14] ([i915#7828]) +8 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
    - fi-rkl-11600:       NOTRUN -> [SKIP][15] ([i915#4103])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
    - fi-blb-e6850:       NOTRUN -> [SKIP][16] ([fdo#109271]) +9 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-blb-e6850/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][17] ([fdo#109285] / [i915#4098])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-rkl-11600:       NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][19] ([i915#3555] / [i915#4098])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-read:
    - fi-rkl-11600:       NOTRUN -> [SKIP][20] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][21] ([fdo#109295] / [i915#3301] / [i915#3708])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-rkl-11600/igt@prime_vgem@basic-userptr.html

  
#### Possible fixes ####

  * igt@fbdev@write:
    - fi-blb-e6850:       [SKIP][22] ([fdo#109271]) -> [PASS][23] +5 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/fi-blb-e6850/igt@fbdev@write.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/fi-blb-e6850/igt@fbdev@write.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
    - {bat-dg1-7}:        [FAIL][24] ([fdo#103375]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/bat-dg1-7/igt@gem_exec_suspend@basic-s3@lmem0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/bat-dg1-7/igt@gem_exec_suspend@basic-s3@lmem0.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913


Build changes
-------------

  * Linux: CI_DRM_12738 -> Patchwork_113729v3

  CI-20190529: 20190529
  CI_DRM_12738: aad037693df25f8c83ba6cef9facc8e47c7937c3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v3: aad037693df25f8c83ba6cef9facc8e47c7937c3 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

da291c6daf93 drm/i915/dsc: Add debugfs entry to validate DSC output formats
39c45b9638f0 drm/i915/vdsc: Check slice design requirement
720119ff9db7 drm/i915: Fill in native_420 field
3aaf8c4dc0a5 drm/i915: Enable YCbCr420 for VDSC
9419d31c8564 drm/i915: Adding the new registers for DSC
5a2aa9d66da1 drm/i915/dp: Check if DSC supports the given output_format
0507e368b509 drm/dp_helper: Add helper to check if the sink supports given format with DSC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/index.html

[-- Attachment #2: Type: text/html, Size: 10731 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable YCbCr420 for VDSC (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 18950 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev3)
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12738_full -> Patchwork_113729v3_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/index.html

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_113729v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [PASS][1] -> [ABORT][2] ([i915#5566])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-glk1/igt@gen9_exec_parse@allowed-single.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-glk5/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][3] ([fdo#109271]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#79])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-glk:          NOTRUN -> [SKIP][6] ([fdo#109271]) +4 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-glk9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271]) +16 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-snb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - {shard-rkl}:        [FAIL][8] ([i915#7742]) -> [PASS][9] +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-2/igt@drm_fdinfo@virtual-idle.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html

  * igt@gem_ctx_persistence@engines-hang@bcs0:
    - {shard-rkl}:        [SKIP][10] ([i915#6252]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-3/igt@gem_ctx_persistence@engines-hang@bcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][12] ([i915#2842]) -> [PASS][13] +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [FAIL][14] ([i915#2842]) -> [PASS][15] +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - {shard-rkl}:        [SKIP][16] ([i915#3281]) -> [PASS][17] +8 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - {shard-rkl}:        [SKIP][18] ([i915#3282]) -> [PASS][19] +4 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-apl:          [ABORT][20] ([i915#5566]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-apl3/igt@gen9_exec_parse@allowed-single.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-apl7/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - {shard-rkl}:        [SKIP][22] ([i915#2527]) -> [PASS][23] +3 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_hangman@gt-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][24] ([i915#6258]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-2/igt@i915_hangman@gt-engine-error@bcs0.html

  * igt@i915_pm_rps@engine-order:
    - shard-apl:          [FAIL][26] ([i915#6537]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-apl6/igt@i915_pm_rps@engine-order.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-apl1/igt@i915_pm_rps@engine-order.html

  * igt@i915_pm_sseu@full-enable:
    - {shard-rkl}:        [SKIP][28] ([i915#4387]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-4/igt@i915_pm_sseu@full-enable.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@i915_pm_sseu@full-enable.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - {shard-tglu}:       [SKIP][30] ([i915#1845] / [i915#7651]) -> [PASS][31] +11 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-tglu-6/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-tglu-2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
    - shard-glk:          [FAIL][32] ([i915#79]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
    - {shard-tglu}:       [SKIP][34] ([i915#1849]) -> [PASS][35] +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
    - {shard-tglu}:       [SKIP][36] ([i915#1849] / [i915#3558]) -> [PASS][37] +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-tglu-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-tglu-2/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html

  * igt@perf@gen12-oa-tlb-invalidate:
    - {shard-rkl}:        [SKIP][38] ([fdo#109289]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-3/igt@perf@gen12-oa-tlb-invalidate.html

  * igt@perf@mi-rpc:
    - {shard-rkl}:        [SKIP][40] ([i915#2434]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-4/igt@perf@mi-rpc.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@perf@mi-rpc.html

  * igt@perf@polling-small-buf:
    - {shard-tglu}:       [FAIL][42] ([i915#1722]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-tglu-6/igt@perf@polling-small-buf.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-tglu-2/igt@perf@polling-small-buf.html

  * igt@prime_vgem@basic-read:
    - {shard-rkl}:        [SKIP][44] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12738/shard-rkl-2/igt@prime_vgem@basic-read.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/shard-rkl-5/igt@prime_vgem@basic-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150


Build changes
-------------

  * Linux: CI_DRM_12738 -> Patchwork_113729v3

  CI-20190529: 20190529
  CI_DRM_12738: aad037693df25f8c83ba6cef9facc8e47c7937c3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v3: aad037693df25f8c83ba6cef9facc8e47c7937c3 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v3/index.html

[-- Attachment #2: Type: text/html, Size: 13073 bytes --]

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev4)

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev4)
URL   : https://patchwork.freedesktop.org/series/113729/
State : warning

== Summary ==

Error: dim checkpatch failed
6cdd40baf8cf drm/dp_helper: Add helper to check if the sink supports given format with DSC
04c83ea19cea drm/i915/dp: Check if DSC supports the given output_format
80ca3b9cb354 drm/i915: Adding the new registers for DSC
bc52e4f42491 drm/i915: Enable YCbCr420 for VDSC
-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_row' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)

-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_col' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)

total: 0 errors, 0 warnings, 2 checks, 228 lines checked
6b12844735fd drm/i915: Fill in native_420 field
e3abb5a999a6 drm/i915/vdsc: Check slice design requirement
ce3c95890351 drm/i915/dsc: Add debugfs entry to validate DSC output formats
-:114: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:1909:
+	seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format));

total: 0 errors, 1 warnings, 0 checks, 151 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4832 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev4)
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12739 -> Patchwork_113729v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/index.html

Participating hosts (39 -> 37)
------------------------------

  Additional (1): bat-rpls-2 
  Missing    (3): fi-kbl-soraka fi-blb-e6850 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113729v4:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@basic-s2idle-without-i915:
    - {bat-rpls-1}:       NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html

  
Known issues
------------

  Here are the changes found in Patchwork_113729v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][2] -> [ABORT][3] ([i915#7911])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][4] ([i915#5334]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-1}:       [ABORT][6] ([i915#4983]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/bat-rpls-1/igt@i915_selftest@live@reset.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/bat-rpls-1/igt@i915_selftest@live@reset.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996


Build changes
-------------

  * Linux: CI_DRM_12739 -> Patchwork_113729v4

  CI-20190529: 20190529
  CI_DRM_12739: 5fc904286af94038fbf2c7cda50ed871b70cf4e8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v4: 5fc904286af94038fbf2c7cda50ed871b70cf4e8 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

4cf9e7dff922 drm/i915/dsc: Add debugfs entry to validate DSC output formats
05c6ec9e5ff4 drm/i915/vdsc: Check slice design requirement
5eaadf0006f8 drm/i915: Fill in native_420 field
16c71a0f64d5 drm/i915: Enable YCbCr420 for VDSC
a5bccef5d67d drm/i915: Adding the new registers for DSC
0b9daac93e28 drm/i915/dp: Check if DSC supports the given output_format
6aa69e525d67 drm/dp_helper: Add helper to check if the sink supports given format with DSC

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/index.html

[-- Attachment #2: Type: text/html, Size: 4349 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Enable YCbCr420 for VDSC (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 40634 bytes --]

== Series Details ==

Series: Enable YCbCr420 for VDSC (rev4)
URL   : https://patchwork.freedesktop.org/series/113729/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12739_full -> Patchwork_113729v4_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/index.html

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-rkl0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113729v4_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@basic-s3-without-i915:
    - {shard-tglu}:       NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-tglu-2/igt@i915_suspend@basic-s3-without-i915.html

  
New tests
---------

  New tests have been introduced between CI_DRM_12739_full and Patchwork_113729v4_full:

### New IGT tests (177) ###

  * igt@drm_fdinfo@busy-check-all@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-check-all@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-check-all@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-check-all@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-check-all@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-hang@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-hang@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-hang@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-hang@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-hang@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle-check-all@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle-check-all@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle-check-all@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle-check-all@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle-check-all@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy-idle@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@busy@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@idle@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@idle@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@idle@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@idle@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@idle@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@isolation@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@isolation@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@isolation@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@isolation@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@isolation@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - Statuses : 1 fail(s) 2 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-check-all@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-check-all@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-idle-check-all@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-idle-check-all@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-idle-check-all@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@drm_fdinfo@most-busy-idle-check-all@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@clean@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@clean@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@clean@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@clean@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@clean@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-create@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-create@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-create@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-create@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-create@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-switch@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-switch@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-switch@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-switch@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@dirty-switch@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv-switch@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv-switch@rcs0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv-switch@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv-switch@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv-switch@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@nonpriv@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-reset@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-reset@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-reset@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-reset@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-reset@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_isolation@preservation@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-shared-gtt@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-shared-gtt@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-shared-gtt@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-shared-gtt@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-shared-gtt@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-single-timeline@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-single-timeline@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-single-timeline@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-single-timeline@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@exec-single-timeline@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-in-order@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-in-order@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-in-order@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-in-order@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-in-order@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-independent@bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-independent@rcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-independent@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-independent@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-out-order@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-out-order@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-out-order@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-out-order@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-out-order@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-promotion@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-promotion@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-promotion@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-promotion@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-promotion@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-smoketest@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-smoketest@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-smoketest@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-smoketest@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@gem_ctx_shared@q-smoketest@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_lmem_swapping@verify-ccs@lmem0:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_lmem_swapping@verify-random-ccs@lmem0:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@kms_cursor_edge_walk@64x64-top-bottom@pipe-b-edp-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@idempotent@bcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@idempotent@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@idempotent@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@idempotent@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@invalid@bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@invalid@rcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@invalid@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@invalid@vecs0:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@mixed@vcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@mixed@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@nopreempt@bcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@nopreempt@rcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@nopreempt@vcs0:
    - Statuses : 3 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@nopreempt@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@precise@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@precise@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@precise@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@precise@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@idempotent@bcs0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@idempotent@rcs0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@idempotent@vcs0:
    - Statuses : 5 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@idempotent@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@idempotent@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@invalid@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@invalid@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@invalid@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@invalid@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@invalid@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@timeout@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@timeout@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@timeout@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@timeout@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_preempt_timeout@timeout@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@duration@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@duration@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@duration@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@duration@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@duration@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@idempotent@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@idempotent@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@idempotent@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@idempotent@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@invalid@bcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@invalid@rcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@invalid@vcs0:
    - Statuses : 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@invalid@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@invalid@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@timeout@bcs0:
    - Statuses : 1 fail(s) 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@timeout@rcs0:
    - Statuses : 1 fail(s) 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@timeout@vcs0:
    - Statuses : 1 fail(s) 4 pass(s) 1 skip(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@timeout@vcs1:
    - Statuses : 1 fail(s) 1 pass(s)
    - Exec time: [0.0] s

  * igt@sysfs_timeslice_duration@timeout@vecs0:
    - Statuses : 1 fail(s) 4 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_113729v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0 (NEW):
    - {shard-rkl}:        NOTRUN -> [FAIL][2] ([i915#7742])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [PASS][5] -> [FAIL][6] ([i915#2842])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@i915_pm_rps@engine-order:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#6537])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-apl2/igt@i915_pm_rps@engine-order.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-apl4/igt@i915_pm_rps@engine-order.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2521])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk8/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2346])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#79])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [SKIP][15] ([fdo#109271]) +16 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-snb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [FAIL][16] ([i915#5465]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@sysfs_timeslice_duration@timeout@rcs0 (NEW):
    - {shard-dg1}:        NOTRUN -> [FAIL][17] ([i915#1755]) +4 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-dg1-18/igt@sysfs_timeslice_duration@timeout@rcs0.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - {shard-rkl}:        [FAIL][18] ([i915#7742]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-3/igt@drm_fdinfo@virtual-idle.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html

  * igt@gem_ctx_persistence@hang:
    - {shard-rkl}:        [SKIP][20] ([i915#6252]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-5/igt@gem_ctx_persistence@hang.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@gem_ctx_persistence@hang.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - {shard-rkl}:        [FAIL][22] ([i915#2842]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][24] ([i915#2842]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - {shard-rkl}:        [SKIP][26] ([fdo#109313]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-2/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - {shard-rkl}:        [SKIP][28] ([i915#3281]) -> [PASS][29] +7 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - {shard-rkl}:        [SKIP][30] ([i915#3282]) -> [PASS][31] +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gen9_exec_parse@shadow-peek:
    - {shard-rkl}:        [SKIP][32] ([i915#2527]) -> [PASS][33] +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][34] ([i915#1845] / [i915#4098]) -> [PASS][35] +22 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-apl:          [FAIL][36] ([i915#2346]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][38] ([i915#79]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
    - {shard-rkl}:        [SKIP][40] ([i915#1849] / [i915#4098]) -> [PASS][41] +17 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right@pipe-a-planes:
    - {shard-rkl}:        [SKIP][42] ([i915#1849]) -> [PASS][43] +3 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-5/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html

  * igt@kms_psr@cursor_blt:
    - {shard-rkl}:        [SKIP][44] ([i915#1072]) -> [PASS][45] +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-3/igt@kms_psr@cursor_blt.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@kms_psr@cursor_blt.html

  * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b:
    - {shard-rkl}:        [SKIP][46] ([i915#4098]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-5/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html

  * igt@perf@mi-rpc:
    - {shard-rkl}:        [SKIP][48] ([i915#2434]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-6/igt@perf@mi-rpc.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-5/igt@perf@mi-rpc.html

  * igt@prime_vgem@basic-fence-flip:
    - {shard-rkl}:        [SKIP][50] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12739/shard-rkl-2/igt@prime_vgem@basic-fence-flip.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8018]: https://gitlab.freedesktop.org/drm/intel/issues/8018
  [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
  [i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155


Build changes
-------------

  * Linux: CI_DRM_12739 -> Patchwork_113729v4

  CI-20190529: 20190529
  CI_DRM_12739: 5fc904286af94038fbf2c7cda50ed871b70cf4e8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113729v4: 5fc904286af94038fbf2c7cda50ed871b70cf4e8 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113729v4/index.html

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