[PATCH v2 0/8] Add _PICK_EVEN_2RANGES

[PATCH v2 0/8] Add _PICK_EVEN_2RANGES

[Lucas De Marchi]

Add a new macro, _PICK_EVEN_2RANGES, that supports using 2 address
ranges. This can be considered a v2 of
https://patchwork.freedesktop.org/series/109606/

I think I converted all the _PICK() uses that could be easily done
without making it much harder to read. We do have some cases of 3
ranges: I left those alone.

As commented in the original series and like Jani I think we may need
something else to cover all the use cases in future. Right now I don't
think we have a good alternative though. This new macro both improves
the current code and can be used for cases the ranges change in new
platforms, so I think it's good enough.  In future I think just saving
the reg during initialization and using different functions if the
bitfields change may be an alternative.

This was lightly tested on ADL-S and DG2.

Lucas De Marchi (8):
  drm/i915: Add _PICK_EVEN_2RANGES()
  drm/i915: Fix coding style on DPLL*_ENABLE defines
  drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
  drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
  drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
  drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
  drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
  drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

 .../drm/i915/display/intel_display_reg_defs.h |  10 +-
 .../gpu/drm/i915/display/intel_mg_phy_regs.h  |   4 +-
 drivers/gpu/drm/i915/i915_reg.h               | 106 +++++++++---------
 drivers/gpu/drm/i915/i915_reg_defs.h          |  28 +++++
 4 files changed, 89 insertions(+), 59 deletions(-)

-- 
2.39.0

[Intel-gfx] [PATCH v2 0/8] Add _PICK_EVEN_2RANGES

[Lucas De Marchi]

Add a new macro, _PICK_EVEN_2RANGES, that supports using 2 address
ranges. This can be considered a v2 of
https://patchwork.freedesktop.org/series/109606/

I think I converted all the _PICK() uses that could be easily done
without making it much harder to read. We do have some cases of 3
ranges: I left those alone.

As commented in the original series and like Jani I think we may need
something else to cover all the use cases in future. Right now I don't
think we have a good alternative though. This new macro both improves
the current code and can be used for cases the ranges change in new
platforms, so I think it's good enough.  In future I think just saving
the reg during initialization and using different functions if the
bitfields change may be an alternative.

This was lightly tested on ADL-S and DG2.

Lucas De Marchi (8):
  drm/i915: Add _PICK_EVEN_2RANGES()
  drm/i915: Fix coding style on DPLL*_ENABLE defines
  drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
  drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
  drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
  drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
  drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
  drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

 .../drm/i915/display/intel_display_reg_defs.h |  10 +-
 .../gpu/drm/i915/display/intel_mg_phy_regs.h  |   4 +-
 drivers/gpu/drm/i915/i915_reg.h               | 106 +++++++++---------
 drivers/gpu/drm/i915/i915_reg_defs.h          |  28 +++++
 4 files changed, 89 insertions(+), 59 deletions(-)

-- 
2.39.0

[PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..b7ec87464d69 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,34 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * The first range is used for indexes below @__c_index, and the second
+ * range is used for anything above it. Example::
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa100,
+ *	4: 0xa200,
+ *	5: 0xa300,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

[Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..b7ec87464d69 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,34 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * The first range is used for indexes below @__c_index, and the second
+ * range is used for anything above it. Example::
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa100,
+ *	4: 0xa200,
+ *	5: 0xa300,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

[PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE defines

[Lucas De Marchi]

Abide by the rules in the top of the header: 2 spaces for bitfield,
prefix offsets with underscore and prefer the use of REG_BIT().

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b2642397b82..8da3546d82fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7224,20 +7224,20 @@ enum skl_power_gate {
 							ADLS_DPCLKA_DDIK_SEL_MASK)
 
 /* ICL PLL */
-#define DPLL0_ENABLE		0x46010
-#define DPLL1_ENABLE		0x46014
+#define _DPLL0_ENABLE		0x46010
+#define _DPLL1_ENABLE		0x46014
 #define _ADLS_DPLL2_ENABLE	0x46018
 #define _ADLS_DPLL3_ENABLE	0x46030
-#define  PLL_ENABLE		(1 << 31)
-#define  PLL_LOCK		(1 << 30)
-#define  PLL_POWER_ENABLE	(1 << 27)
-#define  PLL_POWER_STATE	(1 << 26)
-#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define   PLL_ENABLE		REG_BIT(31)
+#define   PLL_LOCK		REG_BIT(30)
+#define   PLL_POWER_ENABLE	REG_BIT(27)
+#define   PLL_POWER_STATE	REG_BIT(26)
+#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define _DG2_PLL3_ENABLE	0x4601C
 
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 				       _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
@@ -7246,12 +7246,12 @@ enum skl_power_gate {
 #define _MG_PLL2_ENABLE		0x46034
 #define _MG_PLL3_ENABLE		0x46038
 #define _MG_PLL4_ENABLE		0x4603C
-/* Bits are the same as DPLL0_ENABLE */
+/* Bits are the same as _DPLL0_ENABLE */
 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
 					   _MG_PLL2_ENABLE)
 
 /* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
 
 /* ADL-P Type C PLL */
-- 
2.39.0

[Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE defines

[Lucas De Marchi]

Abide by the rules in the top of the header: 2 spaces for bitfield,
prefix offsets with underscore and prefer the use of REG_BIT().

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b2642397b82..8da3546d82fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7224,20 +7224,20 @@ enum skl_power_gate {
 							ADLS_DPCLKA_DDIK_SEL_MASK)
 
 /* ICL PLL */
-#define DPLL0_ENABLE		0x46010
-#define DPLL1_ENABLE		0x46014
+#define _DPLL0_ENABLE		0x46010
+#define _DPLL1_ENABLE		0x46014
 #define _ADLS_DPLL2_ENABLE	0x46018
 #define _ADLS_DPLL3_ENABLE	0x46030
-#define  PLL_ENABLE		(1 << 31)
-#define  PLL_LOCK		(1 << 30)
-#define  PLL_POWER_ENABLE	(1 << 27)
-#define  PLL_POWER_STATE	(1 << 26)
-#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define   PLL_ENABLE		REG_BIT(31)
+#define   PLL_LOCK		REG_BIT(30)
+#define   PLL_POWER_ENABLE	REG_BIT(27)
+#define   PLL_POWER_STATE	REG_BIT(26)
+#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define _DG2_PLL3_ENABLE	0x4601C
 
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 				       _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
@@ -7246,12 +7246,12 @@ enum skl_power_gate {
 #define _MG_PLL2_ENABLE		0x46034
 #define _MG_PLL3_ENABLE		0x46038
 #define _MG_PLL4_ENABLE		0x4603C
-/* Bits are the same as DPLL0_ENABLE */
+/* Bits are the same as _DPLL0_ENABLE */
 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
 					   _MG_PLL2_ENABLE)
 
 /* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
 					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
 
 /* ADL-P Type C PLL */
-- 
2.39.0

[PATCH v2 3/8] drm/i915: Convert pll macros to _PICK_EVEN_2RANGES

[Lucas De Marchi]

Avoid the array lookup, converting the PLL macros after ICL to
_PICK_EVEN_RANGES. This provides the following reduction in code size:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4027456  185703    6984 4220143  4064ef build64/drivers/gpu/drm/i915/i915.o.old
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.new

At the same time it's safer, avoiding out-of-bounds array access.  This
allows to remove _MMIO_PLL3() that is now unused.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_reg_defs.h |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 59 +++++++++----------
 2 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 02605418ff08..a4ed1c530799 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -34,7 +34,6 @@
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8da3546d82fb..dd1eb8b10e0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7232,13 +7232,15 @@ enum skl_power_gate {
 #define   PLL_LOCK		REG_BIT(30)
 #define   PLL_POWER_ENABLE	REG_BIT(27)
 #define   PLL_POWER_STATE	REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
+#define ICL_DPLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
 
 #define _DG2_PLL3_ENABLE	0x4601C
 
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-				       _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
+#define DG2_PLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
 
@@ -7251,8 +7253,9 @@ enum skl_power_gate {
 					   _MG_PLL2_ENABLE)
 
 /* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+#define DG1_DPLL_ENABLE(pll)    _MMIO(_PICK_EVEN_2RANGES(pll, 2,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
 
 /* ADL-P Type C PLL */
 #define PORTTC1_PLL_ENABLE	0x46038
@@ -7312,9 +7315,9 @@ enum skl_power_gate {
 #define _TGL_DPLL0_CFGCR0		0x164284
 #define _TGL_DPLL1_CFGCR0		0x16428C
 #define _TGL_TBTPLL_CFGCR0		0x16429C
-#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						  _TGL_DPLL1_CFGCR0, \
-						  _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
 #define RKL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
 						  _TGL_DPLL1_CFGCR0)
 
@@ -7327,40 +7330,36 @@ enum skl_power_gate {
 #define _TGL_DPLL0_CFGCR1		0x164288
 #define _TGL_DPLL1_CFGCR1		0x164290
 #define _TGL_TBTPLL_CFGCR1		0x1642A0
-#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
 #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
 						  _TGL_DPLL1_CFGCR1)
 
 #define _DG1_DPLL2_CFGCR0		0x16C284
 #define _DG1_DPLL3_CFGCR0		0x16C28C
-#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						   _TGL_DPLL1_CFGCR0, \
-						   _DG1_DPLL2_CFGCR0, \
-						   _DG1_DPLL3_CFGCR0)
+#define DG1_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
 
 #define _DG1_DPLL2_CFGCR1               0x16C288
 #define _DG1_DPLL3_CFGCR1               0x16C290
-#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _DG1_DPLL2_CFGCR1, \
-						   _DG1_DPLL3_CFGCR1)
+#define DG1_DPLL_CFGCR1(pll)            _MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
 
 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL3_CFGCR0		0x1642C0
 #define _ADLS_DPLL4_CFGCR0		0x164294
-#define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						   _TGL_DPLL1_CFGCR0, \
-						   _ADLS_DPLL4_CFGCR0, \
-						   _ADLS_DPLL3_CFGCR0)
+#define _ADLS_DPLL3_CFGCR0		0x1642C0
+#define ADLS_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
 
-#define _ADLS_DPLL3_CFGCR1		0x1642C4
 #define _ADLS_DPLL4_CFGCR1		0x164298
-#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _ADLS_DPLL4_CFGCR1, \
-						   _ADLS_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR1		0x1642C4
+#define ADLS_DPLL_CFGCR1(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
-- 
2.39.0

[Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to _PICK_EVEN_2RANGES

[Lucas De Marchi]

Avoid the array lookup, converting the PLL macros after ICL to
_PICK_EVEN_RANGES. This provides the following reduction in code size:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4027456  185703    6984 4220143  4064ef build64/drivers/gpu/drm/i915/i915.o.old
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.new

At the same time it's safer, avoiding out-of-bounds array access.  This
allows to remove _MMIO_PLL3() that is now unused.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_reg_defs.h |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 59 +++++++++----------
 2 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index 02605418ff08..a4ed1c530799 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -34,7 +34,6 @@
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8da3546d82fb..dd1eb8b10e0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7232,13 +7232,15 @@ enum skl_power_gate {
 #define   PLL_LOCK		REG_BIT(30)
 #define   PLL_POWER_ENABLE	REG_BIT(27)
 #define   PLL_POWER_STATE	REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
+#define ICL_DPLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
 
 #define _DG2_PLL3_ENABLE	0x4601C
 
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-				       _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
+#define DG2_PLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
 
@@ -7251,8 +7253,9 @@ enum skl_power_gate {
 					   _MG_PLL2_ENABLE)
 
 /* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
-					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+#define DG1_DPLL_ENABLE(pll)    _MMIO(_PICK_EVEN_2RANGES(pll, 2,			\
+							_DPLL0_ENABLE, _DPLL1_ENABLE,	\
+							_MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
 
 /* ADL-P Type C PLL */
 #define PORTTC1_PLL_ENABLE	0x46038
@@ -7312,9 +7315,9 @@ enum skl_power_gate {
 #define _TGL_DPLL0_CFGCR0		0x164284
 #define _TGL_DPLL1_CFGCR0		0x16428C
 #define _TGL_TBTPLL_CFGCR0		0x16429C
-#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						  _TGL_DPLL1_CFGCR0, \
-						  _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
 #define RKL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
 						  _TGL_DPLL1_CFGCR0)
 
@@ -7327,40 +7330,36 @@ enum skl_power_gate {
 #define _TGL_DPLL0_CFGCR1		0x164288
 #define _TGL_DPLL1_CFGCR1		0x164290
 #define _TGL_TBTPLL_CFGCR1		0x1642A0
-#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
 #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
 						  _TGL_DPLL1_CFGCR1)
 
 #define _DG1_DPLL2_CFGCR0		0x16C284
 #define _DG1_DPLL3_CFGCR0		0x16C28C
-#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						   _TGL_DPLL1_CFGCR0, \
-						   _DG1_DPLL2_CFGCR0, \
-						   _DG1_DPLL3_CFGCR0)
+#define DG1_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
 
 #define _DG1_DPLL2_CFGCR1               0x16C288
 #define _DG1_DPLL3_CFGCR1               0x16C290
-#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _DG1_DPLL2_CFGCR1, \
-						   _DG1_DPLL3_CFGCR1)
+#define DG1_DPLL_CFGCR1(pll)            _MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
 
 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL3_CFGCR0		0x1642C0
 #define _ADLS_DPLL4_CFGCR0		0x164294
-#define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
-						   _TGL_DPLL1_CFGCR0, \
-						   _ADLS_DPLL4_CFGCR0, \
-						   _ADLS_DPLL3_CFGCR0)
+#define _ADLS_DPLL3_CFGCR0		0x1642C0
+#define ADLS_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,	\
+					      _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
 
-#define _ADLS_DPLL3_CFGCR1		0x1642C4
 #define _ADLS_DPLL4_CFGCR1		0x164298
-#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
-						   _TGL_DPLL1_CFGCR1, \
-						   _ADLS_DPLL4_CFGCR1, \
-						   _ADLS_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR1		0x1642C4
+#define ADLS_DPLL_CFGCR1(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
+					      _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,	\
+					      _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
 
 /* BXT display engine PLL */
 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
-- 
2.39.0

[PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()

[Lucas De Marchi]

As done previously for pll, also convert users of _PHY3() to
_PICK_EVEN_2RANGES(). Size comparison of i915.o:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.old
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.new

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_reg_defs.h    |  3 ---
 drivers/gpu/drm/i915/i915_reg.h                  | 16 +++++++++-------
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index a4ed1c530799..f1681e1396b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -29,11 +29,8 @@
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
 #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
 
-#define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
-
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd1eb8b10e0e..fe6385443c4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -541,9 +541,10 @@
 #define _BXT_PHY0_BASE			0x6C000
 #define _BXT_PHY1_BASE			0x162000
 #define _BXT_PHY2_BASE			0x163000
-#define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
-						     _BXT_PHY1_BASE, \
-						     _BXT_PHY2_BASE)
+#define BXT_PHY_BASE(phy)							\
+	 _PICK_EVEN_2RANGES(phy, 1,						\
+			    _BXT_PHY0_BASE, _BXT_PHY0_BASE,			\
+			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)
 
 #define _BXT_PHY(phy, reg)						\
 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
@@ -566,13 +567,14 @@
 #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
 							 _BXT_PHY_CTL_DDI_B)
 
-#define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI		0x64C90
+#define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
 #define   COMMON_RESET_DIS		(1 << 31)
-#define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
-							  _PHY_CTL_FAMILY_EDP, \
-							  _PHY_CTL_FAMILY_DDI_C)
+#define BXT_PHY_CTL_FAMILY(phy)							\
+	 _MMIO(_PICK_EVEN_2RANGES(phy, 1,					\
+				  _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI,	\
+				  _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
 
 /* BXT PHY PLL registers */
 #define _PORT_PLL_A			0x46074
-- 
2.39.0

[Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()

[Lucas De Marchi]

As done previously for pll, also convert users of _PHY3() to
_PICK_EVEN_2RANGES(). Size comparison of i915.o:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.old
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.new

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_reg_defs.h    |  3 ---
 drivers/gpu/drm/i915/i915_reg.h                  | 16 +++++++++-------
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index a4ed1c530799..f1681e1396b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -29,11 +29,8 @@
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
 #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
 
-#define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
-
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd1eb8b10e0e..fe6385443c4a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -541,9 +541,10 @@
 #define _BXT_PHY0_BASE			0x6C000
 #define _BXT_PHY1_BASE			0x162000
 #define _BXT_PHY2_BASE			0x163000
-#define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
-						     _BXT_PHY1_BASE, \
-						     _BXT_PHY2_BASE)
+#define BXT_PHY_BASE(phy)							\
+	 _PICK_EVEN_2RANGES(phy, 1,						\
+			    _BXT_PHY0_BASE, _BXT_PHY0_BASE,			\
+			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)
 
 #define _BXT_PHY(phy, reg)						\
 	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
@@ -566,13 +567,14 @@
 #define BXT_PHY_CTL(port)		_MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
 							 _BXT_PHY_CTL_DDI_B)
 
-#define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI		0x64C90
+#define _PHY_CTL_FAMILY_EDP		0x64C80
 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
 #define   COMMON_RESET_DIS		(1 << 31)
-#define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
-							  _PHY_CTL_FAMILY_EDP, \
-							  _PHY_CTL_FAMILY_DDI_C)
+#define BXT_PHY_CTL_FAMILY(phy)							\
+	 _MMIO(_PICK_EVEN_2RANGES(phy, 1,					\
+				  _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI,	\
+				  _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
 
 /* BXT PHY PLL registers */
 #define _PORT_PLL_A			0x46074
-- 
2.39.0

[PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

Like done for when __var_args__ were used, but size-wise it's also
benefitial to avoid _PICK() used for 3 ports/pipes:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.old
	4025496  185703    6984 4218183  405d47 build64/drivers/gpu/drm/i915/i915.o.new

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index f1681e1396b5..755c1ea8225c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -13,7 +13,7 @@
 #define VLV_DISPLAY_BASE		0x180000
 
 /*
- * Named helper wrappers around _PICK_EVEN() and _PICK().
+ * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES().
  */
 #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
 #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
@@ -29,8 +29,8 @@
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
 #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
 
-#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
+#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
-- 
2.39.0

[Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

Like done for when __var_args__ were used, but size-wise it's also
benefitial to avoid _PICK() used for 3 ports/pipes:

	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
	   text    data     bss     dec     hex filename
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.old
	4025496  185703    6984 4218183  405d47 build64/drivers/gpu/drm/i915/i915.o.new

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
index f1681e1396b5..755c1ea8225c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -13,7 +13,7 @@
 #define VLV_DISPLAY_BASE		0x180000
 
 /*
- * Named helper wrappers around _PICK_EVEN() and _PICK().
+ * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES().
  */
 #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
 #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
@@ -29,8 +29,8 @@
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
 #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
 
-#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
+#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
-- 
2.39.0

[PATCH v2 6/8] drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

_FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the
size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
index 0e8248bce52d..0306ade2bc30 100644
--- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
@@ -142,7 +142,9 @@
 #define FIA1_BASE			0x163000
 #define FIA2_BASE			0x16E000
 #define FIA3_BASE			0x16F000
-#define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _FIA(fia)			_PICK_EVEN_2RANGES((fia), 1,		\
+							   FIA1_BASE, FIA1_BASE,\
+							   FIA2_BASE, FIA3_BASE)
 #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
 
 /* ICL PHY DFLEX registers */
-- 
2.39.0

[Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

_FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the
size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
index 0e8248bce52d..0306ade2bc30 100644
--- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
@@ -142,7 +142,9 @@
 #define FIA1_BASE			0x163000
 #define FIA2_BASE			0x16E000
 #define FIA3_BASE			0x16F000
-#define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
+#define _FIA(fia)			_PICK_EVEN_2RANGES((fia), 1,		\
+							   FIA1_BASE, FIA1_BASE,\
+							   FIA2_BASE, FIA3_BASE)
 #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
 
 /* ICL PHY DFLEX registers */
-- 
2.39.0

[Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which
reduces the size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe6385443c4a..3d6ad4424265 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1040,9 +1040,11 @@
 #define _MBUS_ABOX0_CTL			0x45038
 #define _MBUS_ABOX1_CTL			0x45048
 #define _MBUS_ABOX2_CTL			0x4504C
-#define MBUS_ABOX_CTL(x)		_MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
-						    _MBUS_ABOX1_CTL, \
-						    _MBUS_ABOX2_CTL))
+#define MBUS_ABOX_CTL(x)							\
+	_MMIO(_PICK_EVEN_2RANGES(x, 2,						\
+				 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,		\
+				 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
+
 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
-- 
2.39.0

[PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which
reduces the size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe6385443c4a..3d6ad4424265 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1040,9 +1040,11 @@
 #define _MBUS_ABOX0_CTL			0x45038
 #define _MBUS_ABOX1_CTL			0x45048
 #define _MBUS_ABOX2_CTL			0x4504C
-#define MBUS_ABOX_CTL(x)		_MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
-						    _MBUS_ABOX1_CTL, \
-						    _MBUS_ABOX2_CTL))
+#define MBUS_ABOX_CTL(x)							\
+	_MMIO(_PICK_EVEN_2RANGES(x, 2,						\
+				 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,		\
+				 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
+
 #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
 #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
-- 
2.39.0

[PATCH v2 8/8] drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which
reduces the size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d6ad4424265..b134a1f357c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1734,10 +1734,11 @@
 #define   PALETTE_10BIT_BLUE_EXP_MASK	REG_GENMASK(7, 6)
 #define   PALETTE_10BIT_BLUE_MANT_MASK	REG_GENMASK(5, 2)
 #define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)
-#define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
-				      _PICK((pipe), _PALETTE_A,		\
-					    _PALETTE_B, _CHV_PALETTE_C) + \
-				      (i) * 4)
+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +			\
+			       _PICK_EVEN_2RANGES(pipe, 2,			\
+						  _PALETTE_A, _PALETTE_B,	\
+						  _CHV_PALETTE_C, _CHV_PALETTE_C) + \
+						  (i) * 4)
 
 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
 
-- 
2.39.0

[Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Lucas De Marchi]

PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which
reduces the size and is safer.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d6ad4424265..b134a1f357c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1734,10 +1734,11 @@
 #define   PALETTE_10BIT_BLUE_EXP_MASK	REG_GENMASK(7, 6)
 #define   PALETTE_10BIT_BLUE_MANT_MASK	REG_GENMASK(5, 2)
 #define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)
-#define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
-				      _PICK((pipe), _PALETTE_A,		\
-					    _PALETTE_B, _CHV_PALETTE_C) + \
-				      (i) * 4)
+#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +			\
+			       _PICK_EVEN_2RANGES(pipe, 2,			\
+						  _PALETTE_A, _PALETTE_B,	\
+						  _CHV_PALETTE_C, _CHV_PALETTE_C) + \
+						  (i) * 4)
 
 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
 
-- 
2.39.0

RE: [Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE defines

[Srivatsa, Anusha]

Changes look good.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE
> defines
>
> Abide by the rules in the top of the header: 2 spaces for bitfield, prefix offsets
> with underscore and prefer the use of REG_BIT().
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b2642397b82..8da3546d82fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7224,20 +7224,20 @@ enum skl_power_gate {
>
>       ADLS_DPCLKA_DDIK_SEL_MASK)
>
>  /* ICL PLL */
> -#define DPLL0_ENABLE         0x46010
> -#define DPLL1_ENABLE         0x46014
> +#define _DPLL0_ENABLE                0x46010
> +#define _DPLL1_ENABLE                0x46014
>  #define _ADLS_DPLL2_ENABLE   0x46018
>  #define _ADLS_DPLL3_ENABLE   0x46030
> -#define  PLL_ENABLE          (1 << 31)
> -#define  PLL_LOCK            (1 << 30)
> -#define  PLL_POWER_ENABLE    (1 << 27)
> -#define  PLL_POWER_STATE     (1 << 26)
> -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define   PLL_ENABLE         REG_BIT(31)
> +#define   PLL_LOCK           REG_BIT(30)
> +#define   PLL_POWER_ENABLE   REG_BIT(27)
> +#define   PLL_POWER_STATE    REG_BIT(26)
> +#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
>                                          _ADLS_DPLL2_ENABLE,
> _ADLS_DPLL3_ENABLE)
>
>  #define _DG2_PLL3_ENABLE     0x4601C
>
> -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> +_DPLL1_ENABLE, \
>                                      _ADLS_DPLL2_ENABLE,
> _DG2_PLL3_ENABLE)
>
>  #define TBT_PLL_ENABLE               _MMIO(0x46020)
> @@ -7246,12 +7246,12 @@ enum skl_power_gate {
>  #define _MG_PLL2_ENABLE              0x46034
>  #define _MG_PLL3_ENABLE              0x46038
>  #define _MG_PLL4_ENABLE              0x4603C
> -/* Bits are the same as DPLL0_ENABLE */
> +/* Bits are the same as _DPLL0_ENABLE */
>  #define MG_PLL_ENABLE(tc_port)       _MMIO_PORT((tc_port),
> _MG_PLL1_ENABLE, \
>                                          _MG_PLL2_ENABLE)
>
>  /* DG1 PLL */
> -#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
>                                          _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE)
>
>  /* ADL-P Type C PLL */
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE defines

[Srivatsa, Anusha]

Changes look good.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE
> defines
> 
> Abide by the rules in the top of the header: 2 spaces for bitfield, prefix offsets
> with underscore and prefer the use of REG_BIT().
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b2642397b82..8da3546d82fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7224,20 +7224,20 @@ enum skl_power_gate {
> 
> 	ADLS_DPCLKA_DDIK_SEL_MASK)
> 
>  /* ICL PLL */
> -#define DPLL0_ENABLE		0x46010
> -#define DPLL1_ENABLE		0x46014
> +#define _DPLL0_ENABLE		0x46010
> +#define _DPLL1_ENABLE		0x46014
>  #define _ADLS_DPLL2_ENABLE	0x46018
>  #define _ADLS_DPLL3_ENABLE	0x46030
> -#define  PLL_ENABLE		(1 << 31)
> -#define  PLL_LOCK		(1 << 30)
> -#define  PLL_POWER_ENABLE	(1 << 27)
> -#define  PLL_POWER_STATE	(1 << 26)
> -#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define   PLL_ENABLE		REG_BIT(31)
> +#define   PLL_LOCK		REG_BIT(30)
> +#define   PLL_POWER_ENABLE	REG_BIT(27)
> +#define   PLL_POWER_STATE	REG_BIT(26)
> +#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
>  					   _ADLS_DPLL2_ENABLE,
> _ADLS_DPLL3_ENABLE)
> 
>  #define _DG2_PLL3_ENABLE	0x4601C
> 
> -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> +_DPLL1_ENABLE, \
>  				       _ADLS_DPLL2_ENABLE,
> _DG2_PLL3_ENABLE)
> 
>  #define TBT_PLL_ENABLE		_MMIO(0x46020)
> @@ -7246,12 +7246,12 @@ enum skl_power_gate {
>  #define _MG_PLL2_ENABLE		0x46034
>  #define _MG_PLL3_ENABLE		0x46038
>  #define _MG_PLL4_ENABLE		0x4603C
> -/* Bits are the same as DPLL0_ENABLE */
> +/* Bits are the same as _DPLL0_ENABLE */
>  #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port),
> _MG_PLL1_ENABLE, \
>  					   _MG_PLL2_ENABLE)
> 
>  /* DG1 PLL */
> -#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE,
> DPLL1_ENABLE, \
> +#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
>  					   _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE)
> 
>  /* ADL-P Type C PLL */
> --
> 2.39.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add _PICK_EVEN_2RANGES

[Patchwork]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES
URL   : https://patchwork.freedesktop.org/series/113177/
State : warning

== Summary ==

Error: dim checkpatch failed
1158a61386b5 drm/i915: Add _PICK_EVEN_2RANGES()
-:55: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__index' - possible side-effects?
#55: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:145:
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))

-:55: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__c_index' - possible side-effects?
#55: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:145:
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))

total: 0 errors, 0 warnings, 2 checks, 34 lines checked
a0415313f5fb drm/i915: Fix coding style on DPLL*_ENABLE defines
96b62304aa0f drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4027456  185703    6984 4220143  4064ef build64/drivers/gpu/drm/i915/i915.o.old

total: 0 errors, 1 warnings, 0 checks, 106 lines checked
cabcdfc08547 drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.old

total: 0 errors, 1 warnings, 0 checks, 42 lines checked
78f1ef0205b6 drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.old

-:35: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects?
#35: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:32:
+#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:33:
+#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

total: 0 errors, 1 warnings, 2 checks, 18 lines checked
0fce45deb660 drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
14144930cc2a drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
43ff8ea467c8 drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Intel-gfx] ✓ Fi.CI.BAT: success for Add _PICK_EVEN_2RANGES

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6557 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES
URL   : https://patchwork.freedesktop.org/series/113177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12618 -> Patchwork_113177v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/index.html

Participating hosts (36 -> 35)
------------------------------

  Additional (1): fi-bsw-kefka 
  Missing    (2): fi-rkl-11600 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_113177v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][1] -> [FAIL][2] ([i915#7229])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_module_load@load:
    - fi-ctg-p8600:       [PASS][3] -> [DMESG-WARN][4] ([i915#6020])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/fi-ctg-p8600/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-ctg-p8600/igt@i915_module_load@load.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg1-5:          [PASS][5] -> [INCOMPLETE][6] ([i915#4983])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/bat-dg1-5/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/bat-dg1-5/igt@i915_selftest@live@workarounds.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
    - fi-bsw-n3050:       [PASS][7] -> [FAIL][8] ([i915#6298])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1:
    - fi-ctg-p8600:       [PASS][9] -> [FAIL][10] ([fdo#103375])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/fi-ctg-p8600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-ctg-p8600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-bsw-kefka:       NOTRUN -> [SKIP][11] ([fdo#109271]) +26 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-bsw-kefka/igt@prime_vgem@basic-fence-flip.html

  * igt@runner@aborted:
    - bat-dg1-5:          NOTRUN -> [FAIL][12] ([i915#4312])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/bat-dg1-5/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - {bat-jsl-1}:        [DMESG-FAIL][13] ([i915#5334]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
    - {bat-rpls-2}:       [DMESG-FAIL][15] ([i915#4258]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@slpc:
    - {bat-rpls-1}:       [DMESG-FAIL][17] ([i915#6367]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-n3050:       [FAIL][19] ([i915#6298]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#6020]: https://gitlab.freedesktop.org/drm/intel/issues/6020
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443


Build changes
-------------

  * Linux: CI_DRM_12618 -> Patchwork_113177v1

  CI-20190529: 20190529
  CI_DRM_12618: 7ba8ff20ba23bc940e928ffe3a9054225fff418e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7129: 7816773163a1b0d248dd9dd34d14e632ad8903be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v1: 7ba8ff20ba23bc940e928ffe3a9054225fff418e @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

34ad2dbae567 drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()
23e47c47f6d1 drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
684e8f62f7a4 drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
0f06420e937c drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
c5283d408429 drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
4a14e42776a1 drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
526e9e6a8927 drm/i915: Fix coding style on DPLL*_ENABLE defines
f4d3551678c3 drm/i915: Add _PICK_EVEN_2RANGES()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/index.html

[-- Attachment #2: Type: text/html, Size: 7353 bytes --]

RE: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

Verified that the new macro evaluates to the right register offsets.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with
> _PICK_EVEN_2RANGES()
>
> As done previously for pll, also convert users of _PHY3() to
> _PICK_EVEN_2RANGES(). Size comparison of i915.o:
>
>       $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
>          text    data     bss     dec     hex filename
>       4026997  185703    6984 4219684  406324
> build64/drivers/gpu/drm/i915/i915.o.old
>       4026288  185703    6984 4218975  40605f
> build64/drivers/gpu/drm/i915/i915.o.new
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_reg_defs.h    |  3 ---
>  drivers/gpu/drm/i915/i915_reg.h                  | 16 +++++++++-------
>  2 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index a4ed1c530799..f1681e1396b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -29,11 +29,8 @@
>  #define _MMIO_PLL(pll, a, b)         _MMIO(_PLL(pll, a, b))
>  #define _MMIO_PHY(phy, a, b)         _MMIO(_PHY(phy, a, b))
>
> -#define _PHY3(phy, ...)                      _PICK(phy, __VA_ARGS__)
> -
>  #define _MMIO_PIPE3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PHY3(phy, a, b, c)     _MMIO(_PHY3(phy, a, b, c))
>
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dd1eb8b10e0e..fe6385443c4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -541,9 +541,10 @@
>  #define _BXT_PHY0_BASE                       0x6C000
>  #define _BXT_PHY1_BASE                       0x162000
>  #define _BXT_PHY2_BASE                       0x163000
> -#define BXT_PHY_BASE(phy)            _PHY3((phy), _BXT_PHY0_BASE, \
> -                                                  _BXT_PHY1_BASE, \
> -                                                  _BXT_PHY2_BASE)
> +#define BXT_PHY_BASE(phy)
>       \
> +      _PICK_EVEN_2RANGES(phy, 1,
>       \
> +                         _BXT_PHY0_BASE, _BXT_PHY0_BASE,
>       \
> +                         _BXT_PHY1_BASE, _BXT_PHY2_BASE)
>
>  #define _BXT_PHY(phy, reg)                                           \
>       _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13
> +567,14 @@
>  #define BXT_PHY_CTL(port)            _MMIO_PORT(port,
> _BXT_PHY_CTL_DDI_A, \
>
> _BXT_PHY_CTL_DDI_B)
>
> -#define _PHY_CTL_FAMILY_EDP          0x64C80
>  #define _PHY_CTL_FAMILY_DDI          0x64C90
> +#define _PHY_CTL_FAMILY_EDP          0x64C80
>  #define _PHY_CTL_FAMILY_DDI_C                0x64CA0
>  #define   COMMON_RESET_DIS           (1 << 31)
> -#define BXT_PHY_CTL_FAMILY(phy)              _MMIO_PHY3((phy),
> _PHY_CTL_FAMILY_DDI, \
> -
> _PHY_CTL_FAMILY_EDP, \
> -
> _PHY_CTL_FAMILY_DDI_C)
> +#define BXT_PHY_CTL_FAMILY(phy)
>               \
> +      _MMIO(_PICK_EVEN_2RANGES(phy, 1,
>       \
> +                               _PHY_CTL_FAMILY_DDI,
> _PHY_CTL_FAMILY_DDI,  \
> +                               _PHY_CTL_FAMILY_EDP,
> _PHY_CTL_FAMILY_DDI_C))
>
>  /* BXT PHY PLL registers */
>  #define _PORT_PLL_A                  0x46074
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

Verified that the new macro evaluates to the right register offsets.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with
> _PICK_EVEN_2RANGES()
> 
> As done previously for pll, also convert users of _PHY3() to
> _PICK_EVEN_2RANGES(). Size comparison of i915.o:
> 
> 	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
> 	   text    data     bss     dec     hex filename
> 	4026997  185703    6984 4219684  406324
> build64/drivers/gpu/drm/i915/i915.o.old
> 	4026288  185703    6984 4218975  40605f
> build64/drivers/gpu/drm/i915/i915.o.new
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_reg_defs.h    |  3 ---
>  drivers/gpu/drm/i915/i915_reg.h                  | 16 +++++++++-------
>  2 files changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index a4ed1c530799..f1681e1396b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -29,11 +29,8 @@
>  #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
>  #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
> 
> -#define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
> -
>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> 
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dd1eb8b10e0e..fe6385443c4a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -541,9 +541,10 @@
>  #define _BXT_PHY0_BASE			0x6C000
>  #define _BXT_PHY1_BASE			0x162000
>  #define _BXT_PHY2_BASE			0x163000
> -#define BXT_PHY_BASE(phy)		_PHY3((phy), _BXT_PHY0_BASE, \
> -						     _BXT_PHY1_BASE, \
> -						     _BXT_PHY2_BASE)
> +#define BXT_PHY_BASE(phy)
> 	\
> +	 _PICK_EVEN_2RANGES(phy, 1,
> 	\
> +			    _BXT_PHY0_BASE, _BXT_PHY0_BASE,
> 	\
> +			    _BXT_PHY1_BASE, _BXT_PHY2_BASE)
> 
>  #define _BXT_PHY(phy, reg)						\
>  	_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13
> +567,14 @@
>  #define BXT_PHY_CTL(port)		_MMIO_PORT(port,
> _BXT_PHY_CTL_DDI_A, \
> 
> _BXT_PHY_CTL_DDI_B)
> 
> -#define _PHY_CTL_FAMILY_EDP		0x64C80
>  #define _PHY_CTL_FAMILY_DDI		0x64C90
> +#define _PHY_CTL_FAMILY_EDP		0x64C80
>  #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
>  #define   COMMON_RESET_DIS		(1 << 31)
> -#define BXT_PHY_CTL_FAMILY(phy)		_MMIO_PHY3((phy),
> _PHY_CTL_FAMILY_DDI, \
> -
> _PHY_CTL_FAMILY_EDP, \
> -
> _PHY_CTL_FAMILY_DDI_C)
> +#define BXT_PHY_CTL_FAMILY(phy)
> 		\
> +	 _MMIO(_PICK_EVEN_2RANGES(phy, 1,
> 	\
> +				  _PHY_CTL_FAMILY_DDI,
> _PHY_CTL_FAMILY_DDI,	\
> +				  _PHY_CTL_FAMILY_EDP,
> _PHY_CTL_FAMILY_DDI_C))
> 
>  /* BXT PHY PLL registers */
>  #define _PORT_PLL_A			0x46074
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to
> _PICK_EVEN_2RANGES()
>
> Like done for when __var_args__ were used, but size-wise it's also benefitial to
> avoid _PICK() used for 3 ports/pipes:
>
>       $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
>          text    data     bss     dec     hex filename
>       4026288  185703    6984 4218975  40605f
> build64/drivers/gpu/drm/i915/i915.o.old
>       4025496  185703    6984 4218183  405d47
> build64/drivers/gpu/drm/i915/i915.o.new
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index f1681e1396b5..755c1ea8225c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -13,7 +13,7 @@
>  #define VLV_DISPLAY_BASE             0x180000
>
>  /*
> - * Named helper wrappers around _PICK_EVEN() and _PICK().
> + * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES().
>   */
>  #define _PIPE(pipe, a, b)            _PICK_EVEN(pipe, a, b)
>  #define _PLANE(plane, a, b)          _PICK_EVEN(plane, a, b)
> @@ -29,8 +29,8 @@
>  #define _MMIO_PLL(pll, a, b)         _MMIO(_PLL(pll, a, b))
>  #define _MMIO_PHY(phy, a, b)         _MMIO(_PHY(phy, a, b))
>
> -#define _MMIO_PIPE3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PORT3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PIPE3(pipe, a, b, c)   _MMIO(_PICK_EVEN_2RANGES(pipe,
> 1, a, a, b, c))
> +#define _MMIO_PORT3(pipe, a, b, c)   _MMIO(_PICK_EVEN_2RANGES(pipe,
> 1, a, a, b, c))
>
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to
> _PICK_EVEN_2RANGES()
> 
> Like done for when __var_args__ were used, but size-wise it's also benefitial to
> avoid _PICK() used for 3 ports/pipes:
> 
> 	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
> 	   text    data     bss     dec     hex filename
> 	4026288  185703    6984 4218975  40605f
> build64/drivers/gpu/drm/i915/i915.o.old
> 	4025496  185703    6984 4218183  405d47
> build64/drivers/gpu/drm/i915/i915.o.new
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index f1681e1396b5..755c1ea8225c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -13,7 +13,7 @@
>  #define VLV_DISPLAY_BASE		0x180000
> 
>  /*
> - * Named helper wrappers around _PICK_EVEN() and _PICK().
> + * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES().
>   */
>  #define _PIPE(pipe, a, b)		_PICK_EVEN(pipe, a, b)
>  #define _PLANE(plane, a, b)		_PICK_EVEN(plane, a, b)
> @@ -29,8 +29,8 @@
>  #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
>  #define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
> 
> -#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe,
> 1, a, a, b, c))
> +#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe,
> 1, a, a, b, c))
> 
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to
> _PICK_EVEN_2RANGES()
>
> _FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size
> and is safer.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> index 0e8248bce52d..0306ade2bc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> @@ -142,7 +142,9 @@
>  #define FIA1_BASE                    0x163000
>  #define FIA2_BASE                    0x16E000
>  #define FIA3_BASE                    0x16F000
> -#define _FIA(fia)                    _PICK((fia), FIA1_BASE, FIA2_BASE,
> FIA3_BASE)
> +#define _FIA(fia)                    _PICK_EVEN_2RANGES((fia), 1,
>       \
> +                                                        FIA1_BASE,
> FIA1_BASE,\
> +                                                        FIA2_BASE,
> FIA3_BASE)
>  #define _MMIO_FIA(fia, off)          _MMIO(_FIA(fia) + (off))
>
>  /* ICL PHY DFLEX registers */
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to
> _PICK_EVEN_2RANGES()
> 
> _FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size
> and is safer.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> index 0e8248bce52d..0306ade2bc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
> @@ -142,7 +142,9 @@
>  #define FIA1_BASE			0x163000
>  #define FIA2_BASE			0x16E000
>  #define FIA3_BASE			0x16F000
> -#define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE,
> FIA3_BASE)
> +#define _FIA(fia)			_PICK_EVEN_2RANGES((fia), 1,
> 	\
> +							   FIA1_BASE,
> FIA1_BASE,\
> +							   FIA2_BASE,
> FIA3_BASE)
>  #define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
> 
>  /* ICL PHY DFLEX registers */
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to
> _PICK_EVEN_2RANGES()
>
> MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which
> reduces the size and is safer.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good!

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fe6385443c4a..3d6ad4424265 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1040,9 +1040,11 @@
>  #define _MBUS_ABOX0_CTL                      0x45038
>  #define _MBUS_ABOX1_CTL                      0x45048
>  #define _MBUS_ABOX2_CTL                      0x4504C
> -#define MBUS_ABOX_CTL(x)             _MMIO(_PICK(x, _MBUS_ABOX0_CTL,
> \
> -                                                 _MBUS_ABOX1_CTL, \
> -                                                 _MBUS_ABOX2_CTL))
> +#define MBUS_ABOX_CTL(x)
>       \
> +     _MMIO(_PICK_EVEN_2RANGES(x, 2,
>               \
> +                              _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,
>               \
> +                              _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
> +
>  #define MBUS_ABOX_BW_CREDIT_MASK     (3 << 20)
>  #define MBUS_ABOX_BW_CREDIT(x)               ((x) << 20)
>  #define MBUS_ABOX_B_CREDIT_MASK              (0xF << 16)
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to
> _PICK_EVEN_2RANGES()
> 
> MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which
> reduces the size and is safer.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Looks good!

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fe6385443c4a..3d6ad4424265 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1040,9 +1040,11 @@
>  #define _MBUS_ABOX0_CTL			0x45038
>  #define _MBUS_ABOX1_CTL			0x45048
>  #define _MBUS_ABOX2_CTL			0x4504C
> -#define MBUS_ABOX_CTL(x)		_MMIO(_PICK(x, _MBUS_ABOX0_CTL,
> \
> -						    _MBUS_ABOX1_CTL, \
> -						    _MBUS_ABOX2_CTL))
> +#define MBUS_ABOX_CTL(x)
> 	\
> +	_MMIO(_PICK_EVEN_2RANGES(x, 2,
> 		\
> +				 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,
> 		\
> +				 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
> +
>  #define MBUS_ABOX_BW_CREDIT_MASK	(3 << 20)
>  #define MBUS_ABOX_BW_CREDIT(x)		((x) << 20)
>  #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to
> _PICK_EVEN_2RANGES()
>
> PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the
> size and is safer.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d6ad4424265..b134a1f357c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1734,10 +1734,11 @@
>  #define   PALETTE_10BIT_BLUE_EXP_MASK        REG_GENMASK(7, 6)
>  #define   PALETTE_10BIT_BLUE_MANT_MASK       REG_GENMASK(5, 2)
>  #define   PALETTE_10BIT_BLUE_UDW_MASK        REG_GENMASK(1, 0)
> -#define PALETTE(pipe, i)     _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> -                                   _PICK((pipe), _PALETTE_A,         \
> -                                         _PALETTE_B, _CHV_PALETTE_C) + \
> -                                   (i) * 4)
> +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
>               \
> +                            _PICK_EVEN_2RANGES(pipe, 2,
>       \
> +                                               _PALETTE_A, _PALETTE_B,
>       \
> +                                               _CHV_PALETTE_C,
> _CHV_PALETTE_C) + \
> +                                               (i) * 4)
>
>  #define PEG_BAND_GAP_DATA    _MMIO(0x14d68)
>
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to
> _PICK_EVEN_2RANGES()
> 
> PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the
> size and is safer.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa<anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d6ad4424265..b134a1f357c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1734,10 +1734,11 @@
>  #define   PALETTE_10BIT_BLUE_EXP_MASK	REG_GENMASK(7, 6)
>  #define   PALETTE_10BIT_BLUE_MANT_MASK	REG_GENMASK(5, 2)
>  #define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)
> -#define PALETTE(pipe, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> -				      _PICK((pipe), _PALETTE_A,		\
> -					    _PALETTE_B, _CHV_PALETTE_C) + \
> -				      (i) * 4)
> +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 		\
> +			       _PICK_EVEN_2RANGES(pipe, 2,
> 	\
> +						  _PALETTE_A, _PALETTE_B,
> 	\
> +						  _CHV_PALETTE_C,
> _CHV_PALETTE_C) + \
> +						  (i) * 4)
> 
>  #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
> 
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
> 
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
> needs to be used.  Using _PICK() is discouraged due to some reasons like:
> 
> 1) It increases the code size since the array is declared
>    in each call site
> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
> 
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
> to use depending on the index value.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..b7ec87464d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
> 
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::
> + *
> + * #define _FOO_A			0xf000
> + * #define _FOO_B			0xf004
> + * #define _FOO_C			0xf008
> + * #define _SUPER_FOO_A			0xa000
> + * #define _SUPER_FOO_B			0xa100
> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
> 		\
> + *					      _FOO_A, _FOO_B,
> 	\
> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *	0: 0xf000,
> + *	1: 0xf004,
> + *	2: 0xf008,
> + *	3: 0xa100,
You mean 3:0xa000

> + *	4: 0xa200,
4:0xa100

> + *	5: 0xa300,
5:0xa200

Anusha 
> + *	...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
> 	\
> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> 	\
> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
> 	\
> +				   _PICK_EVEN((__index) - (__c_index), __c,
> __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
>
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
> needs to be used.  Using _PICK() is discouraged due to some reasons like:
>
> 1) It increases the code size since the array is declared
>    in each call site
> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
>
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
> to use depending on the index value.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..b7ec87464d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::
> + *
> + * #define _FOO_A                    0xf000
> + * #define _FOO_B                    0xf004
> + * #define _FOO_C                    0xf008
> + * #define _SUPER_FOO_A                      0xa000
> + * #define _SUPER_FOO_B                      0xa100
> + * #define FOO(x)                    _MMIO(_PICK_EVEN_RANGES(x, 3,
>               \
> + *                                         _FOO_A, _FOO_B,
>       \
> + *                                         _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *   0: 0xf000,
> + *   1: 0xf004,
> + *   2: 0xf008,
> + *   3: 0xa100,
You mean 3:0xa000

> + *   4: 0xa200,
4:0xa100

> + *   5: 0xa300,
5:0xa200

Anusha
> + *   ...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
>       \
> +     (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
>       \
> +      ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
>       \
> +                                _PICK_EVEN((__index) - (__c_index), __c,
> __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *
> --
> 2.39.0

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add _PICK_EVEN_2RANGES

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 23989 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES
URL   : https://patchwork.freedesktop.org/series/113177/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12618_full -> Patchwork_113177v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_113177v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_113177v1_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/index.html

Participating hosts (12 -> 9)
------------------------------

  Missing    (3): shard-rkl0 pig-kbl-iris pig-skl-6260u 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113177v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_schedule@wide@rcs0:
    - shard-glk:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk9/igt@gem_exec_schedule@wide@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk9/igt@gem_exec_schedule@wide@rcs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_113177v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk2/igt@gem_exec_fair@basic-none@vcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk4/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-glk:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-glk:          NOTRUN -> [FAIL][6] ([i915#3318])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@gem_userptr_blits@vma-merge.html

  * igt@i915_pm_rc6_residency@rc6-idle@vecs0:
    - shard-glk:          NOTRUN -> [FAIL][7] ([i915#3591])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2521])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk2/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cdclk@mode-transition:
    - shard-glk:          NOTRUN -> [SKIP][11] ([fdo#109271]) +46 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@kms_cdclk@mode-transition.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [PASS][12] -> [FAIL][13] ([i915#2346])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-glk:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#7205])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
    - shard-glk:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#658])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@perf@stress-open-close:
    - shard-glk:          [PASS][16] -> [INCOMPLETE][17] ([i915#5213])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk1/igt@perf@stress-open-close.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk4/igt@perf@stress-open-close.html

  * igt@runner@aborted:
    - shard-glk:          NOTRUN -> [FAIL][18] ([i915#4312])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk4/igt@runner@aborted.html

  * igt@sysfs_clients@sema-50:
    - shard-glk:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2994])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk1/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - {shard-rkl}:        [FAIL][20] ([i915#7742]) -> [PASS][21] +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-5/igt@drm_fdinfo@virtual-idle.html

  * igt@fbdev@read:
    - {shard-rkl}:        [SKIP][22] ([i915#2582]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@fbdev@read.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@fbdev@read.html

  * igt@gem_bad_reloc@negative-reloc:
    - {shard-rkl}:        [SKIP][24] ([i915#3281]) -> [PASS][25] +4 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-6/igt@gem_bad_reloc@negative-reloc.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-5/igt@gem_bad_reloc@negative-reloc.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][26] ([i915#6268]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_eio@suspend:
    - {shard-rkl}:        [FAIL][28] ([i915#7052]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@gem_eio@suspend.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-2/igt@gem_eio@suspend.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][30] ([i915#2842]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_mmap_wc@set-cache-level:
    - {shard-tglu}:       [SKIP][32] ([i915#1850]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-tglu-6/igt@gem_mmap_wc@set-cache-level.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-tglu-4/igt@gem_mmap_wc@set-cache-level.html

  * igt@gem_pread@snoop:
    - {shard-rkl}:        [SKIP][34] ([i915#3282]) -> [PASS][35] +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-2/igt@gem_pread@snoop.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-5/igt@gem_pread@snoop.html

  * igt@gen9_exec_parse@bb-start-out:
    - {shard-rkl}:        [SKIP][36] ([i915#2527]) -> [PASS][37] +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-6/igt@gen9_exec_parse@bb-start-out.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html

  * igt@i915_pm_rpm@i2c:
    - {shard-rkl}:        [SKIP][38] ([fdo#109308]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@i915_pm_rpm@i2c.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - {shard-dg1}:        [SKIP][40] ([i915#1397]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-dg1-17/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - {shard-rkl}:        [SKIP][42] ([i915#1845] / [i915#4098]) -> [PASS][43] +20 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
    - {shard-tglu}:       [SKIP][44] ([i915#7651]) -> [PASS][45] +8 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-tglu-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - {shard-rkl}:        [FAIL][46] ([i915#3743]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [FAIL][48] ([i915#2346]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - {shard-tglu}:       [SKIP][50] ([i915#1849]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - {shard-rkl}:        [SKIP][52] ([i915#1849] / [i915#4098]) -> [PASS][53] +14 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-badstride.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-badstride.html

  * igt@kms_plane@plane-panning-top-left@pipe-a-planes:
    - {shard-rkl}:        [SKIP][54] ([i915#1849]) -> [PASS][55] +2 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@kms_plane@plane-panning-top-left@pipe-a-planes.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@kms_plane@plane-panning-top-left@pipe-a-planes.html

  * igt@kms_psr@cursor_plane_onoff:
    - {shard-rkl}:        [SKIP][56] ([i915#1072]) -> [PASS][57] +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@kms_psr@cursor_plane_onoff.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@kms_psr@cursor_plane_onoff.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-a:
    - {shard-tglu}:       [SKIP][58] ([fdo#109274]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-tglu-4/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html

  * igt@kms_vblank@pipe-c-wait-forked:
    - {shard-tglu}:       [SKIP][60] ([i915#1845] / [i915#7651]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-tglu-6/igt@kms_vblank@pipe-c-wait-forked.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-tglu-4/igt@kms_vblank@pipe-c-wait-forked.html

  * igt@testdisplay:
    - {shard-rkl}:        [SKIP][62] ([i915#4098]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12618/shard-rkl-4/igt@testdisplay.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/shard-rkl-6/igt@testdisplay.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
  [i915#7205]: https://gitlab.freedesktop.org/drm/intel/issues/7205
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828


Build changes
-------------

  * Linux: CI_DRM_12618 -> Patchwork_113177v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12618: 7ba8ff20ba23bc940e928ffe3a9054225fff418e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7129: 7816773163a1b0d248dd9dd34d14e632ad8903be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v1: 7ba8ff20ba23bc940e928ffe3a9054225fff418e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v1/index.html

[-- Attachment #2: Type: text/html, Size: 18298 bytes --]

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

On Fri, Jan 20, 2023 at 10:14:19PM -0800, Anusha Srivatsa wrote:
>
>
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
>> De Marchi
>> Sent: Friday, January 20, 2023 11:35 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
>> devel@lists.freedesktop.org
>> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
>>
>> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
>> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
>> needs to be used.  Using _PICK() is discouraged due to some reasons like:
>>
>> 1) It increases the code size since the array is declared
>>    in each call site
>> 2) Developers need to be careful not to incur an
>>    out-of-bounds array access
>> 3) Developers need to be careful that the indexes match the
>>    table. For that it may be that the table needs to contain
>>    holes, making (1) even worse.
>>
>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
>> to use depending on the index value.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
>> b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index be43580a6979..b7ec87464d69 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> @@ -119,6 +119,34 @@
>>   */
>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>>
>> +/*
>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
>> + * The first range is used for indexes below @__c_index, and the second
>> + * range is used for anything above it. Example::
>> + *
>> + * #define _FOO_A			0xf000
>> + * #define _FOO_B			0xf004
>> + * #define _FOO_C			0xf008
>> + * #define _SUPER_FOO_A			0xa000
>> + * #define _SUPER_FOO_B			0xa100
>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
>> 		\
>> + *					      _FOO_A, _FOO_B,
>> 	\
>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
>> + *
>> + * This expands to:
>> + *	0: 0xf000,
>> + *	1: 0xf004,
>> + *	2: 0xf008,
>> + *	3: 0xa100,
>You mean 3:0xa000

doesn't really matter. This is an example of register addresses. They
don't need to start from 0, it's whatever the hw gives us.

Lucas De Marchi

>
>> + *	4: 0xa200,
>4:0xa100
>
>> + *	5: 0xa300,
>5:0xa200
>
>Anusha
>> + *	...
>> + */
>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
>> 	\
>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
>> 	\
>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
>> 	\
>> +				   _PICK_EVEN((__index) - (__c_index), __c,
>> __d)))
>> +
>>  /*
>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>>   *
>> --
>> 2.39.0
>

Re: [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Jani Nikula]

On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs
> based on port, phy, pll, etc. When that happens, instead of using
> _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
> due to some reasons like:
>
> 1) It increases the code size since the array is declared
>    in each call site

Would be interesting to see what this does, and whether the compiler has
the smarts to combine these within each file:

-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+#define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])

> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
>
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
> one to use depending on the index value.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..b7ec87464d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>  
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::

I'd like this to be clear about which range is used for index ==
__c_index, instead of saying "below" and "above".

No need for the double colon :: because this isn't a kernel-doc comment.

> + *
> + * #define _FOO_A			0xf000
> + * #define _FOO_B			0xf004
> + * #define _FOO_C			0xf008
> + * #define _SUPER_FOO_A			0xa000
> + * #define _SUPER_FOO_B			0xa100
> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\

The example uses a different name for the macro.

> + *					      _FOO_A, _FOO_B,			\
> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *	0: 0xf000,
> + *	1: 0xf004,
> + *	2: 0xf008,
> + *	3: 0xa100,

With the above definitions, this would be 3: 0xa000.

> + *	4: 0xa200,
> + *	5: 0xa300,
> + *	...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
> +				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Jani Nikula]

On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs
> based on port, phy, pll, etc. When that happens, instead of using
> _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
> due to some reasons like:
>
> 1) It increases the code size since the array is declared
>    in each call site

Would be interesting to see what this does, and whether the compiler has
the smarts to combine these within each file:

-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+#define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])

> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
>
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
> one to use depending on the index value.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..b7ec87464d69 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>  
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::

I'd like this to be clear about which range is used for index ==
__c_index, instead of saying "below" and "above".

No need for the double colon :: because this isn't a kernel-doc comment.

> + *
> + * #define _FOO_A			0xf000
> + * #define _FOO_B			0xf004
> + * #define _FOO_C			0xf008
> + * #define _SUPER_FOO_A			0xa000
> + * #define _SUPER_FOO_B			0xa100
> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\

The example uses a different name for the macro.

> + *					      _FOO_A, _FOO_B,			\
> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *	0: 0xf000,
> + *	1: 0xf004,
> + *	2: 0xf008,
> + *	3: 0xa100,

With the above definitions, this would be 3: 0xa000.

> + *	4: 0xa200,
> + *	5: 0xa300,
> + *	...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
> +				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH v2 0/8] Add _PICK_EVEN_2RANGES

[Jani Nikula]

On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Add a new macro, _PICK_EVEN_2RANGES, that supports using 2 address
> ranges. This can be considered a v2 of
> https://patchwork.freedesktop.org/series/109606/
>
> I think I converted all the _PICK() uses that could be easily done
> without making it much harder to read. We do have some cases of 3
> ranges: I left those alone.
>
> As commented in the original series and like Jani I think we may need
> something else to cover all the use cases in future. Right now I don't
> think we have a good alternative though. This new macro both improves
> the current code and can be used for cases the ranges change in new
> platforms, so I think it's good enough.  In future I think just saving
> the reg during initialization and using different functions if the
> bitfields change may be an alternative.

Did not review, but on the approach,

Acked-by: Jani Nikula <jani.nikula@intel.com>

>
> This was lightly tested on ADL-S and DG2.
>
> Lucas De Marchi (8):
>   drm/i915: Add _PICK_EVEN_2RANGES()
>   drm/i915: Fix coding style on DPLL*_ENABLE defines
>   drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
>   drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
>   drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
>   drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
>   drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
>   drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()
>
>  .../drm/i915/display/intel_display_reg_defs.h |  10 +-
>  .../gpu/drm/i915/display/intel_mg_phy_regs.h  |   4 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 106 +++++++++---------
>  drivers/gpu/drm/i915/i915_reg_defs.h          |  28 +++++
>  4 files changed, 89 insertions(+), 59 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 0/8] Add _PICK_EVEN_2RANGES

[Jani Nikula]

On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Add a new macro, _PICK_EVEN_2RANGES, that supports using 2 address
> ranges. This can be considered a v2 of
> https://patchwork.freedesktop.org/series/109606/
>
> I think I converted all the _PICK() uses that could be easily done
> without making it much harder to read. We do have some cases of 3
> ranges: I left those alone.
>
> As commented in the original series and like Jani I think we may need
> something else to cover all the use cases in future. Right now I don't
> think we have a good alternative though. This new macro both improves
> the current code and can be used for cases the ranges change in new
> platforms, so I think it's good enough.  In future I think just saving
> the reg during initialization and using different functions if the
> bitfields change may be an alternative.

Did not review, but on the approach,

Acked-by: Jani Nikula <jani.nikula@intel.com>

>
> This was lightly tested on ADL-S and DG2.
>
> Lucas De Marchi (8):
>   drm/i915: Add _PICK_EVEN_2RANGES()
>   drm/i915: Fix coding style on DPLL*_ENABLE defines
>   drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
>   drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
>   drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
>   drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
>   drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
>   drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()
>
>  .../drm/i915/display/intel_display_reg_defs.h |  10 +-
>  .../gpu/drm/i915/display/intel_mg_phy_regs.h  |   4 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 106 +++++++++---------
>  drivers/gpu/drm/i915/i915_reg_defs.h          |  28 +++++
>  4 files changed, 89 insertions(+), 59 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Jani Nikula]

On Sat, 21 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Fri, Jan 20, 2023 at 10:14:19PM -0800, Anusha Srivatsa wrote:
>>
>>
>>> -----Original Message-----
>>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
>>> De Marchi
>>> Sent: Friday, January 20, 2023 11:35 AM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
>>> devel@lists.freedesktop.org
>>> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
>>>
>>> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
>>> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
>>> needs to be used.  Using _PICK() is discouraged due to some reasons like:
>>>
>>> 1) It increases the code size since the array is declared
>>>    in each call site
>>> 2) Developers need to be careful not to incur an
>>>    out-of-bounds array access
>>> 3) Developers need to be careful that the indexes match the
>>>    table. For that it may be that the table needs to contain
>>>    holes, making (1) even worse.
>>>
>>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
>>> to use depending on the index value.
>>>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>>>  1 file changed, 28 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
>>> b/drivers/gpu/drm/i915/i915_reg_defs.h
>>> index be43580a6979..b7ec87464d69 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>>> @@ -119,6 +119,34 @@
>>>   */
>>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>>>
>>> +/*
>>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
>>> + * The first range is used for indexes below @__c_index, and the second
>>> + * range is used for anything above it. Example::
>>> + *
>>> + * #define _FOO_A			0xf000
>>> + * #define _FOO_B			0xf004
>>> + * #define _FOO_C			0xf008
>>> + * #define _SUPER_FOO_A			0xa000
>>> + * #define _SUPER_FOO_B			0xa100
>>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
>>> 		\
>>> + *					      _FOO_A, _FOO_B,
>>> 	\
>>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
>>> + *
>>> + * This expands to:
>>> + *	0: 0xf000,
>>> + *	1: 0xf004,
>>> + *	2: 0xf008,
>>> + *	3: 0xa100,
>>You mean 3:0xa000
>
> doesn't really matter. This is an example of register addresses. They
> don't need to start from 0, it's whatever the hw gives us.

I think the point is that the example is inconsistent between
_SUPER_FOO_A and "3: 0xa100".

BR,
Jani.

>
> Lucas De Marchi
>
>>
>>> + *	4: 0xa200,
>>4:0xa100
>>
>>> + *	5: 0xa300,
>>5:0xa200
>>
>>Anusha
>>> + *	...
>>> + */
>>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
>>> 	\
>>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
>>> 	\
>>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
>>> 	\
>>> +				   _PICK_EVEN((__index) - (__c_index), __c,
>>> __d)))
>>> +
>>>  /*
>>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>>>   *
>>> --
>>> 2.39.0
>>

-- 
Jani Nikula, Intel Open Source Graphics Center

RE: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, January 23, 2023 3:01 AM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
> 
> On Sat, 21 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > On Fri, Jan 20, 2023 at 10:14:19PM -0800, Anusha Srivatsa wrote:
> >>
> >>
> >>> -----Original Message-----
> >>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >>> Of Lucas De Marchi
> >>> Sent: Friday, January 20, 2023 11:35 AM
> >>> To: intel-gfx@lists.freedesktop.org
> >>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> >>> devel@lists.freedesktop.org
> >>> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add
> >>> _PICK_EVEN_2RANGES()
> >>>
> >>> It's a constant pattern in the driver to need to use 2 ranges of
> >>> MMIOs based on port, phy, pll, etc. When that happens, instead of
> >>> using _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
> due to some reasons like:
> >>>
> >>> 1) It increases the code size since the array is declared
> >>>    in each call site
> >>> 2) Developers need to be careful not to incur an
> >>>    out-of-bounds array access
> >>> 3) Developers need to be careful that the indexes match the
> >>>    table. For that it may be that the table needs to contain
> >>>    holes, making (1) even worse.
> >>>
> >>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects
> >>> which one to use depending on the index value.
> >>>
> >>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28
> >>> ++++++++++++++++++++++++++++
> >>>  1 file changed, 28 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> b/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> index be43580a6979..b7ec87464d69 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> @@ -119,6 +119,34 @@
> >>>   */
> >>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) -
> >>> (__a)))
> >>>
> >>> +/*
> >>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address
> offsets.
> >>> + * The first range is used for indexes below @__c_index, and the
> >>> +second
> >>> + * range is used for anything above it. Example::
> >>> + *
> >>> + * #define _FOO_A			0xf000
> >>> + * #define _FOO_B			0xf004
> >>> + * #define _FOO_C			0xf008
> >>> + * #define _SUPER_FOO_A			0xa000
> >>> + * #define _SUPER_FOO_B			0xa100
> >>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
> >>> 		\
> >>> + *					      _FOO_A, _FOO_B,
> >>> 	\
> >>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> >>> + *
> >>> + * This expands to:
> >>> + *	0: 0xf000,
> >>> + *	1: 0xf004,
> >>> + *	2: 0xf008,
> >>> + *	3: 0xa100,
> >>You mean 3:0xa000
> >
> > doesn't really matter. This is an example of register addresses. They
> > don't need to start from 0, it's whatever the hw gives us.
> 
> I think the point is that the example is inconsistent between _SUPER_FOO_A and
> "3: 0xa100".

Yes. It's the inconsistency with _SUPER_FOO_A that I was pointing out.

Anusha
> BR,
> Jani.
> 
> >
> > Lucas De Marchi
> >
> >>
> >>> + *	4: 0xa200,
> >>4:0xa100
> >>
> >>> + *	5: 0xa300,
> >>5:0xa200
> >>
> >>Anusha
> >>> + *	...
> >>> + */
> >>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
> >>> 	\
> >>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> >>> 	\
> >>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
> >>> 	\
> >>> +				   _PICK_EVEN((__index) - (__c_index), __c,
> >>> __d)))
> >>> +
> >>>  /*
> >>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th
> number.
> >>>   *
> >>> --
> >>> 2.39.0
> >>
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, January 23, 2023 3:01 AM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
> 
> On Sat, 21 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> > On Fri, Jan 20, 2023 at 10:14:19PM -0800, Anusha Srivatsa wrote:
> >>
> >>
> >>> -----Original Message-----
> >>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >>> Of Lucas De Marchi
> >>> Sent: Friday, January 20, 2023 11:35 AM
> >>> To: intel-gfx@lists.freedesktop.org
> >>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> >>> devel@lists.freedesktop.org
> >>> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add
> >>> _PICK_EVEN_2RANGES()
> >>>
> >>> It's a constant pattern in the driver to need to use 2 ranges of
> >>> MMIOs based on port, phy, pll, etc. When that happens, instead of
> >>> using _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
> due to some reasons like:
> >>>
> >>> 1) It increases the code size since the array is declared
> >>>    in each call site
> >>> 2) Developers need to be careful not to incur an
> >>>    out-of-bounds array access
> >>> 3) Developers need to be careful that the indexes match the
> >>>    table. For that it may be that the table needs to contain
> >>>    holes, making (1) even worse.
> >>>
> >>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects
> >>> which one to use depending on the index value.
> >>>
> >>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28
> >>> ++++++++++++++++++++++++++++
> >>>  1 file changed, 28 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> b/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> index be43580a6979..b7ec87464d69 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> >>> @@ -119,6 +119,34 @@
> >>>   */
> >>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) -
> >>> (__a)))
> >>>
> >>> +/*
> >>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address
> offsets.
> >>> + * The first range is used for indexes below @__c_index, and the
> >>> +second
> >>> + * range is used for anything above it. Example::
> >>> + *
> >>> + * #define _FOO_A			0xf000
> >>> + * #define _FOO_B			0xf004
> >>> + * #define _FOO_C			0xf008
> >>> + * #define _SUPER_FOO_A			0xa000
> >>> + * #define _SUPER_FOO_B			0xa100
> >>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
> >>> 		\
> >>> + *					      _FOO_A, _FOO_B,
> >>> 	\
> >>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> >>> + *
> >>> + * This expands to:
> >>> + *	0: 0xf000,
> >>> + *	1: 0xf004,
> >>> + *	2: 0xf008,
> >>> + *	3: 0xa100,
> >>You mean 3:0xa000
> >
> > doesn't really matter. This is an example of register addresses. They
> > don't need to start from 0, it's whatever the hw gives us.
> 
> I think the point is that the example is inconsistent between _SUPER_FOO_A and
> "3: 0xa100".

Yes. It's the inconsistency with _SUPER_FOO_A that I was pointing out.

Anusha
> BR,
> Jani.
> 
> >
> > Lucas De Marchi
> >
> >>
> >>> + *	4: 0xa200,
> >>4:0xa100
> >>
> >>> + *	5: 0xa300,
> >>5:0xa200
> >>
> >>Anusha
> >>> + *	...
> >>> + */
> >>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
> >>> 	\
> >>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> >>> 	\
> >>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
> >>> 	\
> >>> +				   _PICK_EVEN((__index) - (__c_index), __c,
> >>> __d)))
> >>> +
> >>>  /*
> >>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th
> number.
> >>>   *
> >>> --
> >>> 2.39.0
> >>
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

On Mon, Jan 23, 2023 at 08:15:16AM -0800, Anusha Srivatsa wrote:
>
>
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Monday, January 23, 2023 3:01 AM
>> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Srivatsa, Anusha
>> <anusha.srivatsa@intel.com>
>> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()
>>
>> On Sat, 21 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> > On Fri, Jan 20, 2023 at 10:14:19PM -0800, Anusha Srivatsa wrote:
>> >>
>> >>
>> >>> -----Original Message-----
>> >>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
>> >>> Of Lucas De Marchi
>> >>> Sent: Friday, January 20, 2023 11:35 AM
>> >>> To: intel-gfx@lists.freedesktop.org
>> >>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
>> >>> devel@lists.freedesktop.org
>> >>> Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add
>> >>> _PICK_EVEN_2RANGES()
>> >>>
>> >>> It's a constant pattern in the driver to need to use 2 ranges of
>> >>> MMIOs based on port, phy, pll, etc. When that happens, instead of
>> >>> using _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
>> due to some reasons like:
>> >>>
>> >>> 1) It increases the code size since the array is declared
>> >>>    in each call site
>> >>> 2) Developers need to be careful not to incur an
>> >>>    out-of-bounds array access
>> >>> 3) Developers need to be careful that the indexes match the
>> >>>    table. For that it may be that the table needs to contain
>> >>>    holes, making (1) even worse.
>> >>>
>> >>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects
>> >>> which one to use depending on the index value.
>> >>>
>> >>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >>> ---
>> >>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28
>> >>> ++++++++++++++++++++++++++++
>> >>>  1 file changed, 28 insertions(+)
>> >>>
>> >>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
>> >>> b/drivers/gpu/drm/i915/i915_reg_defs.h
>> >>> index be43580a6979..b7ec87464d69 100644
>> >>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> >>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> >>> @@ -119,6 +119,34 @@
>> >>>   */
>> >>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) -
>> >>> (__a)))
>> >>>
>> >>> +/*
>> >>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address
>> offsets.
>> >>> + * The first range is used for indexes below @__c_index, and the
>> >>> +second
>> >>> + * range is used for anything above it. Example::
>> >>> + *
>> >>> + * #define _FOO_A			0xf000
>> >>> + * #define _FOO_B			0xf004
>> >>> + * #define _FOO_C			0xf008
>> >>> + * #define _SUPER_FOO_A			0xa000
>> >>> + * #define _SUPER_FOO_B			0xa100
>> >>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
>> >>> 		\
>> >>> + *					      _FOO_A, _FOO_B,
>> >>> 	\
>> >>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
>> >>> + *
>> >>> + * This expands to:
>> >>> + *	0: 0xf000,
>> >>> + *	1: 0xf004,
>> >>> + *	2: 0xf008,
>> >>> + *	3: 0xa100,
>> >>You mean 3:0xa000
>> >
>> > doesn't really matter. This is an example of register addresses. They
>> > don't need to start from 0, it's whatever the hw gives us.
>>
>> I think the point is that the example is inconsistent between _SUPER_FOO_A and
>> "3: 0xa100".
>
>Yes. It's the inconsistency with _SUPER_FOO_A that I was pointing out.

ah, ok. I will send a fixup to this patch.

thanks
Lucas De Marchi

[PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

v2: Fix the address expansion in the  example (Anusha)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..bab6a9ec2ddd 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,34 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * The first range is used for indexes below @__c_index, and the second
+ * range is used for anything above it. Example::
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa000,
+ *	4: 0xa100,
+ *	5: 0xa200,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

[Intel-gfx] [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

v2: Fix the address expansion in the  example (Anusha)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..bab6a9ec2ddd 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,34 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * The first range is used for indexes below @__c_index, and the second
+ * range is used for anything above it. Example::
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa000,
+ *	4: 0xa100,
+ *	5: 0xa200,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

RE: [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Monday, January 23, 2023 9:16 AM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()
> 
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
> needs to be used.  Using _PICK() is discouraged due to some reasons like:
> 
> 1) It increases the code size since the array is declared
>    in each call site
> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
> 
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
> to use depending on the index value.
> 
> v2: Fix the address expansion in the  example (Anusha)
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..bab6a9ec2ddd 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
> 
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::
> + *
> + * #define _FOO_A			0xf000
> + * #define _FOO_B			0xf004
> + * #define _FOO_C			0xf008
> + * #define _SUPER_FOO_A			0xa000
> + * #define _SUPER_FOO_B			0xa100
> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
> 		\
> + *					      _FOO_A, _FOO_B,
> 	\
> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *	0: 0xf000,
> + *	1: 0xf004,
> + *	2: 0xf008,
> + *	3: 0xa000,
> + *	4: 0xa100,
> + *	5: 0xa200,
> + *	...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
> 	\
> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> 	\
> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
> 	\
> +				   _PICK_EVEN((__index) - (__c_index), __c,
> __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()

[Srivatsa, Anusha]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Monday, January 23, 2023 9:16 AM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Srivatsa, Anusha <anusha.srivatsa@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: [PATCH v2.1] drm/i915: Add _PICK_EVEN_2RANGES()
> 
> It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on
> port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK()
> needs to be used.  Using _PICK() is discouraged due to some reasons like:
> 
> 1) It increases the code size since the array is declared
>    in each call site
> 2) Developers need to be careful not to incur an
>    out-of-bounds array access
> 3) Developers need to be careful that the indexes match the
>    table. For that it may be that the table needs to contain
>    holes, making (1) even worse.
> 
> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one
> to use depending on the index value.
> 
> v2: Fix the address expansion in the  example (Anusha)
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> index be43580a6979..bab6a9ec2ddd 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -119,6 +119,34 @@
>   */
>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
> 
> +/*
> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
> + * The first range is used for indexes below @__c_index, and the second
> + * range is used for anything above it. Example::
> + *
> + * #define _FOO_A			0xf000
> + * #define _FOO_B			0xf004
> + * #define _FOO_C			0xf008
> + * #define _SUPER_FOO_A			0xa000
> + * #define _SUPER_FOO_B			0xa100
> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,
> 		\
> + *					      _FOO_A, _FOO_B,
> 	\
> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
> + *
> + * This expands to:
> + *	0: 0xf000,
> + *	1: 0xf004,
> + *	2: 0xf008,
> + *	3: 0xa000,
> + *	4: 0xa100,
> + *	5: 0xa200,
> + *	...
> + */
> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)
> 	\
> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> 	\
> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :
> 	\
> +				   _PICK_EVEN((__index) - (__c_index), __c,
> __d)))
> +
>  /*
>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>   *
> --
> 2.39.0

RE: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to _PICK_EVEN_2RANGES

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to
> _PICK_EVEN_2RANGES
>
> Avoid the array lookup, converting the PLL macros after ICL to
> _PICK_EVEN_RANGES. This provides the following reduction in code size:
>
>       $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
>          text    data     bss     dec     hex filename
>       4027456  185703    6984 4220143  4064ef
> build64/drivers/gpu/drm/i915/i915.o.old
>       4026997  185703    6984 4219684  406324
> build64/drivers/gpu/drm/i915/i915.o.new
>
> At the same time it's safer, avoiding out-of-bounds array access.  This allows to
> remove _MMIO_PLL3() that is now unused.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../drm/i915/display/intel_display_reg_defs.h |  1 -
>  drivers/gpu/drm/i915/i915_reg.h               | 59 +++++++++----------
>  2 files changed, 29 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index 02605418ff08..a4ed1c530799 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -34,7 +34,6 @@
>  #define _MMIO_PIPE3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)   _MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PHY3(phy, a, b, c)     _MMIO(_PHY3(phy, a, b, c))
> -#define _MMIO_PLL3(pll, ...)         _MMIO(_PICK(pll, __VA_ARGS__))
>
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8da3546d82fb..dd1eb8b10e0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7232,13 +7232,15 @@ enum skl_power_gate {
>  #define   PLL_LOCK           REG_BIT(30)
>  #define   PLL_POWER_ENABLE   REG_BIT(27)
>  #define   PLL_POWER_STATE    REG_BIT(26)
> -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -                                        _ADLS_DPLL2_ENABLE,
> _ADLS_DPLL3_ENABLE)
> +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3,
>               \
> +                                                     _DPLL0_ENABLE,
> _DPLL1_ENABLE,        \
> +
>       _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
>
>  #define _DG2_PLL3_ENABLE     0x4601C
>
> -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -                                    _ADLS_DPLL2_ENABLE,
> _DG2_PLL3_ENABLE)
> +#define DG2_PLL_ENABLE(pll)  _MMIO(_PICK_EVEN_2RANGES(pll, 3,
>               \
> +                                                     _DPLL0_ENABLE,
> _DPLL1_ENABLE,        \
> +                                                     _DG2_PLL3_ENABLE,
> _DG2_PLL3_ENABLE))
>
>  #define TBT_PLL_ENABLE               _MMIO(0x46020)
>
> @@ -7251,8 +7253,9 @@ enum skl_power_gate {
>                                          _MG_PLL2_ENABLE)
>
>  /* DG1 PLL */
> -#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -                                        _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE)
> +#define DG1_DPLL_ENABLE(pll)    _MMIO(_PICK_EVEN_2RANGES(pll, 2,
>               \
> +                                                     _DPLL0_ENABLE,
> _DPLL1_ENABLE,        \
> +                                                     _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE))
>
>  /* ADL-P Type C PLL */
>  #define PORTTC1_PLL_ENABLE   0x46038
> @@ -7312,9 +7315,9 @@ enum skl_power_gate {
>  #define _TGL_DPLL0_CFGCR0            0x164284
>  #define _TGL_DPLL1_CFGCR0            0x16428C
>  #define _TGL_TBTPLL_CFGCR0           0x16429C
> -#define TGL_DPLL_CFGCR0(pll)         _MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -                                               _TGL_DPLL1_CFGCR0, \
> -                                               _TGL_TBTPLL_CFGCR0)
> +#define TGL_DPLL_CFGCR0(pll)         _MMIO(_PICK_EVEN_2RANGES(pll, 2,
>               \
> +                                           _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,    \
> +                                           _TGL_TBTPLL_CFGCR0,
> _TGL_TBTPLL_CFGCR0))
>  #define RKL_DPLL_CFGCR0(pll)         _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0,
> \
>                                                 _TGL_DPLL1_CFGCR0)
>
> @@ -7327,40 +7330,36 @@ enum skl_power_gate {
>  #define _TGL_DPLL0_CFGCR1            0x164288
>  #define _TGL_DPLL1_CFGCR1            0x164290
>  #define _TGL_TBTPLL_CFGCR1           0x1642A0
> -#define TGL_DPLL_CFGCR1(pll)         _MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR1, \
> -                                                _TGL_DPLL1_CFGCR1, \
> -                                                _TGL_TBTPLL_CFGCR1)
> +#define TGL_DPLL_CFGCR1(pll)         _MMIO(_PICK_EVEN_2RANGES(pll, 2,
>               \
> +                                           _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,    \
> +                                           _TGL_TBTPLL_CFGCR1,
> _TGL_TBTPLL_CFGCR1))
>  #define RKL_DPLL_CFGCR1(pll)         _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1,
> \
>                                                 _TGL_DPLL1_CFGCR1)
>
>  #define _DG1_DPLL2_CFGCR0            0x16C284
>  #define _DG1_DPLL3_CFGCR0            0x16C28C
> -#define DG1_DPLL_CFGCR0(pll)         _MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -                                                _TGL_DPLL1_CFGCR0, \
> -                                                _DG1_DPLL2_CFGCR0, \
> -                                                _DG1_DPLL3_CFGCR0)
> +#define DG1_DPLL_CFGCR0(pll)         _MMIO(_PICK_EVEN_2RANGES(pll, 2,
>               \
> +                                           _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,    \
> +                                           _DG1_DPLL2_CFGCR0,
> _DG1_DPLL3_CFGCR0))
>
>  #define _DG1_DPLL2_CFGCR1               0x16C288
>  #define _DG1_DPLL3_CFGCR1               0x16C290
> -#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> -                                                _TGL_DPLL1_CFGCR1, \
> -                                                _DG1_DPLL2_CFGCR1, \
> -                                                _DG1_DPLL3_CFGCR1)
> +#define DG1_DPLL_CFGCR1(pll)            _MMIO(_PICK_EVEN_2RANGES(pll, 2,
>               \
> +                                           _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,    \
> +                                           _DG1_DPLL2_CFGCR1,
> _DG1_DPLL3_CFGCR1))
>
>  /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
> -#define _ADLS_DPLL3_CFGCR0           0x1642C0
>  #define _ADLS_DPLL4_CFGCR0           0x164294
> -#define ADLS_DPLL_CFGCR0(pll)                _MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -                                                _TGL_DPLL1_CFGCR0, \
> -                                                _ADLS_DPLL4_CFGCR0, \
> -                                                _ADLS_DPLL3_CFGCR0)
> +#define _ADLS_DPLL3_CFGCR0           0x1642C0
> +#define ADLS_DPLL_CFGCR0(pll)
>       _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
> +                                           _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,    \
> +                                           _ADLS_DPLL4_CFGCR0,
> _ADLS_DPLL3_CFGCR0))
>
> -#define _ADLS_DPLL3_CFGCR1           0x1642C4
>  #define _ADLS_DPLL4_CFGCR1           0x164298
> -#define ADLS_DPLL_CFGCR1(pll)                _MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR1, \
> -                                                _TGL_DPLL1_CFGCR1, \
> -                                                _ADLS_DPLL4_CFGCR1, \
> -                                                _ADLS_DPLL3_CFGCR1)
> +#define _ADLS_DPLL3_CFGCR1           0x1642C4
> +#define ADLS_DPLL_CFGCR1(pll)
>       _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
> +                                           _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,    \
> +                                           _ADLS_DPLL4_CFGCR1,
> _ADLS_DPLL3_CFGCR1))
>
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL                       _MMIO(0x6d000)
> --
> 2.39.0

Re: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to _PICK_EVEN_2RANGES

[Srivatsa, Anusha]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Friday, January 20, 2023 11:35 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; dri-
> devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to
> _PICK_EVEN_2RANGES
> 
> Avoid the array lookup, converting the PLL macros after ICL to
> _PICK_EVEN_RANGES. This provides the following reduction in code size:
> 
> 	$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
> 	   text    data     bss     dec     hex filename
> 	4027456  185703    6984 4220143  4064ef
> build64/drivers/gpu/drm/i915/i915.o.old
> 	4026997  185703    6984 4219684  406324
> build64/drivers/gpu/drm/i915/i915.o.new
> 
> At the same time it's safer, avoiding out-of-bounds array access.  This allows to
> remove _MMIO_PLL3() that is now unused.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> ---
>  .../drm/i915/display/intel_display_reg_defs.h |  1 -
>  drivers/gpu/drm/i915/i915_reg.h               | 59 +++++++++----------
>  2 files changed, 29 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> index 02605418ff08..a4ed1c530799 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
> @@ -34,7 +34,6 @@
>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> -#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
> 
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8da3546d82fb..dd1eb8b10e0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7232,13 +7232,15 @@ enum skl_power_gate {
>  #define   PLL_LOCK		REG_BIT(30)
>  #define   PLL_POWER_ENABLE	REG_BIT(27)
>  #define   PLL_POWER_STATE	REG_BIT(26)
> -#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -					   _ADLS_DPLL2_ENABLE,
> _ADLS_DPLL3_ENABLE)
> +#define ICL_DPLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,
> 		\
> +							_DPLL0_ENABLE,
> _DPLL1_ENABLE,	\
> +
> 	_ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
> 
>  #define _DG2_PLL3_ENABLE	0x4601C
> 
> -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -				       _ADLS_DPLL2_ENABLE,
> _DG2_PLL3_ENABLE)
> +#define DG2_PLL_ENABLE(pll)	_MMIO(_PICK_EVEN_2RANGES(pll, 3,
> 		\
> +							_DPLL0_ENABLE,
> _DPLL1_ENABLE,	\
> +							_DG2_PLL3_ENABLE,
> _DG2_PLL3_ENABLE))
> 
>  #define TBT_PLL_ENABLE		_MMIO(0x46020)
> 
> @@ -7251,8 +7253,9 @@ enum skl_power_gate {
>  					   _MG_PLL2_ENABLE)
> 
>  /* DG1 PLL */
> -#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, _DPLL0_ENABLE,
> _DPLL1_ENABLE, \
> -					   _MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE)
> +#define DG1_DPLL_ENABLE(pll)    _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> 		\
> +							_DPLL0_ENABLE,
> _DPLL1_ENABLE,	\
> +							_MG_PLL1_ENABLE,
> _MG_PLL2_ENABLE))
> 
>  /* ADL-P Type C PLL */
>  #define PORTTC1_PLL_ENABLE	0x46038
> @@ -7312,9 +7315,9 @@ enum skl_power_gate {
>  #define _TGL_DPLL0_CFGCR0		0x164284
>  #define _TGL_DPLL1_CFGCR0		0x16428C
>  #define _TGL_TBTPLL_CFGCR0		0x16429C
> -#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -						  _TGL_DPLL1_CFGCR0, \
> -						  _TGL_TBTPLL_CFGCR0)
> +#define TGL_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,
> 		\
> +					      _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,	\
> +					      _TGL_TBTPLL_CFGCR0,
> _TGL_TBTPLL_CFGCR0))
>  #define RKL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR0,
> \
>  						  _TGL_DPLL1_CFGCR0)
> 
> @@ -7327,40 +7330,36 @@ enum skl_power_gate {
>  #define _TGL_DPLL0_CFGCR1		0x164288
>  #define _TGL_DPLL1_CFGCR1		0x164290
>  #define _TGL_TBTPLL_CFGCR1		0x1642A0
> -#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR1, \
> -						   _TGL_DPLL1_CFGCR1, \
> -						   _TGL_TBTPLL_CFGCR1)
> +#define TGL_DPLL_CFGCR1(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,
> 		\
> +					      _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,	\
> +					      _TGL_TBTPLL_CFGCR1,
> _TGL_TBTPLL_CFGCR1))
>  #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1,
> \
>  						  _TGL_DPLL1_CFGCR1)
> 
>  #define _DG1_DPLL2_CFGCR0		0x16C284
>  #define _DG1_DPLL3_CFGCR0		0x16C28C
> -#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -						   _TGL_DPLL1_CFGCR0, \
> -						   _DG1_DPLL2_CFGCR0, \
> -						   _DG1_DPLL3_CFGCR0)
> +#define DG1_DPLL_CFGCR0(pll)		_MMIO(_PICK_EVEN_2RANGES(pll, 2,
> 		\
> +					      _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,	\
> +					      _DG1_DPLL2_CFGCR0,
> _DG1_DPLL3_CFGCR0))
> 
>  #define _DG1_DPLL2_CFGCR1               0x16C288
>  #define _DG1_DPLL3_CFGCR1               0x16C290
> -#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> -						   _TGL_DPLL1_CFGCR1, \
> -						   _DG1_DPLL2_CFGCR1, \
> -						   _DG1_DPLL3_CFGCR1)
> +#define DG1_DPLL_CFGCR1(pll)            _MMIO(_PICK_EVEN_2RANGES(pll, 2,
> 		\
> +					      _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,	\
> +					      _DG1_DPLL2_CFGCR1,
> _DG1_DPLL3_CFGCR1))
> 
>  /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
> -#define _ADLS_DPLL3_CFGCR0		0x1642C0
>  #define _ADLS_DPLL4_CFGCR0		0x164294
> -#define ADLS_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR0, \
> -						   _TGL_DPLL1_CFGCR0, \
> -						   _ADLS_DPLL4_CFGCR0, \
> -						   _ADLS_DPLL3_CFGCR0)
> +#define _ADLS_DPLL3_CFGCR0		0x1642C0
> +#define ADLS_DPLL_CFGCR0(pll)
> 	_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
> +					      _TGL_DPLL0_CFGCR0,
> _TGL_DPLL1_CFGCR0,	\
> +					      _ADLS_DPLL4_CFGCR0,
> _ADLS_DPLL3_CFGCR0))
> 
> -#define _ADLS_DPLL3_CFGCR1		0x1642C4
>  #define _ADLS_DPLL4_CFGCR1		0x164298
> -#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll,
> _TGL_DPLL0_CFGCR1, \
> -						   _TGL_DPLL1_CFGCR1, \
> -						   _ADLS_DPLL4_CFGCR1, \
> -						   _ADLS_DPLL3_CFGCR1)
> +#define _ADLS_DPLL3_CFGCR1		0x1642C4
> +#define ADLS_DPLL_CFGCR1(pll)
> 	_MMIO(_PICK_EVEN_2RANGES(pll, 2,		\
> +					      _TGL_DPLL0_CFGCR1,
> _TGL_DPLL1_CFGCR1,	\
> +					      _ADLS_DPLL4_CFGCR1,
> _ADLS_DPLL3_CFGCR1))
> 
>  /* BXT display engine PLL */
>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> --
> 2.39.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add _PICK_EVEN_2RANGES (rev2)

[Patchwork]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev2)
URL   : https://patchwork.freedesktop.org/series/113177/
State : warning

== Summary ==

Error: dim checkpatch failed
7b9046444db2 drm/i915: Add _PICK_EVEN_2RANGES()
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__index' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:145:
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))

-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__c_index' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:145:
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))

total: 0 errors, 0 warnings, 2 checks, 34 lines checked
ceebaa623fa3 drm/i915: Fix coding style on DPLL*_ENABLE defines
3cd72fb54cf9 drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4027456  185703    6984 4220143  4064ef build64/drivers/gpu/drm/i915/i915.o.old

total: 0 errors, 1 warnings, 0 checks, 106 lines checked
ee6f334b5960 drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4026997  185703    6984 4219684  406324 build64/drivers/gpu/drm/i915/i915.o.old

total: 0 errors, 1 warnings, 0 checks, 42 lines checked
032484a878c9 drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
	4026288  185703    6984 4218975  40605f build64/drivers/gpu/drm/i915/i915.o.old

-:36: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects?
#36: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:32:
+#define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/display/intel_display_reg_defs.h:33:
+#define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c))

total: 0 errors, 1 warnings, 2 checks, 18 lines checked
63cd3e50d93a drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
377d7638eb55 drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
9a055281abe7 drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()

[Intel-gfx] ✓ Fi.CI.BAT: success for Add _PICK_EVEN_2RANGES (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6406 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev2)
URL   : https://patchwork.freedesktop.org/series/113177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12624 -> Patchwork_113177v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/index.html

Participating hosts (38 -> 37)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (2): fi-rkl-11600 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_113177v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-n3050:       [PASS][1] -> [INCOMPLETE][2] ([i915#6972] / [i915#7911])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-bsw-n3050/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@mman:
    - fi-rkl-guc:         [PASS][3] -> [TIMEOUT][4] ([i915#6794])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/fi-rkl-guc/igt@i915_selftest@live@mman.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-rkl-guc/igt@i915_selftest@live@mman.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-n3050:       [PASS][5] -> [FAIL][6] ([i915#6298])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1:
    - fi-ctg-p8600:       [PASS][7] -> [FAIL][8] ([fdo#103375])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/fi-ctg-p8600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-ctg-p8600/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-lvds-1.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][9] ([fdo#109271]) +44 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@runner@aborted:
    - fi-bsw-n3050:       NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#4312])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-bsw-n3050/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_mocs:
    - {bat-rpls-1}:       [DMESG-FAIL][11] ([i915#7059]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/bat-rpls-1/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@requests:
    - {bat-rpls-2}:       [INCOMPLETE][13] ([i915#6257]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/bat-rpls-2/igt@i915_selftest@live@requests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/bat-rpls-2/igt@i915_selftest@live@requests.html
    - {bat-rpls-1}:       [INCOMPLETE][15] ([i915#4983]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/bat-rpls-1/igt@i915_selftest@live@requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-kefka:       [FAIL][17] ([i915#6298]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
  [i915#6972]: https://gitlab.freedesktop.org/drm/intel/issues/6972
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
  [i915#7625]: https://gitlab.freedesktop.org/drm/intel/issues/7625
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911


Build changes
-------------

  * Linux: CI_DRM_12624 -> Patchwork_113177v2

  CI-20190529: 20190529
  CI_DRM_12624: 18fa3d2237f6df82980349f6bef5281096dfc91d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7134: 61b8c0a0c8a9611c47749c0b1a262843892cccd7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v2: 18fa3d2237f6df82980349f6bef5281096dfc91d @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

44eeb7383959 drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()
fd92e1c2ce24 drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
3b7561562f35 drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
aa8c06afe4cf drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
7c23d67d1a60 drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
d3a097fa91eb drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
3d4ff90ce638 drm/i915: Fix coding style on DPLL*_ENABLE defines
1051f1191d0e drm/i915: Add _PICK_EVEN_2RANGES()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/index.html

[-- Attachment #2: Type: text/html, Size: 7028 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Add _PICK_EVEN_2RANGES (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 18477 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev2)
URL   : https://patchwork.freedesktop.org/series/113177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12624_full -> Patchwork_113177v2_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/index.html

Participating hosts (12 -> 10)
------------------------------

  Missing    (2): pig-skl-6260u pig-kbl-iris 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113177v2_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ccs@ctrl-surf-copy:
    - {shard-rkl}:        [SKIP][1] ([i915#3555] / [i915#5325]) -> [SKIP][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - {shard-rkl}:        [SKIP][3] ([i915#5325]) -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-4/igt@gem_ccs@suspend-resume.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_eio@suspend:
    - {shard-rkl}:        [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-6/igt@gem_eio@suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_eio@suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_113177v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-glk9/igt@gem_exec_fair@basic-deadline.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-glk3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-glk:          [PASS][11] -> [DMESG-FAIL][12] ([i915#5334])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-glk4/igt@i915_selftest@live@gt_heartbeat.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-glk1/igt@i915_selftest@live@gt_heartbeat.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - {shard-rkl}:        [FAIL][13] ([i915#7742]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-3/igt@drm_fdinfo@virtual-idle.html

  * igt@fbdev@info:
    - {shard-rkl}:        [SKIP][15] ([i915#2582]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@fbdev@info.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@fbdev@info.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - {shard-rkl}:        [SKIP][17] ([i915#6252]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-2/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - {shard-rkl}:        [FAIL][19] ([i915#2842]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_reloc@basic-wc-read-noreloc:
    - {shard-rkl}:        [SKIP][21] ([i915#3281]) -> [PASS][22] +9 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-4/igt@gem_exec_reloc@basic-wc-read-noreloc.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_exec_reloc@basic-wc-read-noreloc.html

  * igt@gem_set_tiling_vs_pwrite:
    - {shard-rkl}:        [SKIP][23] ([i915#3282]) -> [PASS][24] +5 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html

  * igt@gen9_exec_parse@bb-start-param:
    - {shard-rkl}:        [SKIP][25] ([i915#2527]) -> [PASS][26] +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-4/igt@gen9_exec_parse@bb-start-param.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_hangman@gt-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][27] ([i915#6258]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@i915_hangman@gt-engine-error@bcs0.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - {shard-rkl}:        [SKIP][29] ([fdo#109308]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@i915_pm_rpm@drm-resources-equal.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@i915_pm_sseu@full-enable:
    - {shard-rkl}:        [SKIP][31] ([i915#4387]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-4/igt@i915_pm_sseu@full-enable.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-5/igt@i915_pm_sseu@full-enable.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - {shard-rkl}:        [SKIP][33] ([i915#1845] / [i915#4098]) -> [PASS][34] +17 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [FAIL][35] ([i915#2346]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
    - {shard-rkl}:        [SKIP][37] ([i915#1849] / [i915#4098]) -> [PASS][38] +13 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_plane@pixel-format@pipe-b-planes:
    - {shard-rkl}:        [SKIP][39] ([i915#1849]) -> [PASS][40] +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@kms_plane@pixel-format@pipe-b-planes.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@kms_plane@pixel-format@pipe-b-planes.html

  * igt@kms_psr@primary_mmap_cpu:
    - {shard-rkl}:        [SKIP][41] ([i915#1072]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-5/igt@kms_psr@primary_mmap_cpu.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@kms_psr@primary_mmap_cpu.html

  * igt@kms_universal_plane@universal-plane-pipe-a-functional:
    - {shard-rkl}:        [SKIP][43] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-functional.html

  * igt@perf@gen12-mi-rpc:
    - {shard-rkl}:        [SKIP][45] ([fdo#109289]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12624/shard-rkl-5/igt@perf@gen12-mi-rpc.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/shard-rkl-2/igt@perf@gen12-mi-rpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828


Build changes
-------------

  * Linux: CI_DRM_12624 -> Patchwork_113177v2
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12624: 18fa3d2237f6df82980349f6bef5281096dfc91d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7134: 61b8c0a0c8a9611c47749c0b1a262843892cccd7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v2: 18fa3d2237f6df82980349f6bef5281096dfc91d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v2/index.html

[-- Attachment #2: Type: text/html, Size: 13076 bytes --]

Re: [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

(I missed this review you did before I had sent a v2.1, I will incorporate
what is missing in the next version)

On Mon, Jan 23, 2023 at 12:38:28PM +0200, Jani Nikula wrote:
>On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> It's a constant pattern in the driver to need to use 2 ranges of MMIOs
>> based on port, phy, pll, etc. When that happens, instead of using
>> _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
>> due to some reasons like:
>>
>> 1) It increases the code size since the array is declared
>>    in each call site
>
>Would be interesting to see what this does, and whether the compiler has
>the smarts to combine these within each file:
>
>-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>+#define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])

if the compiler is smart, it would be at least 1 per compilation unit.
gcc doesn't seem smart enough to even compile it though:

../drivers/gpu/drm/i915/i915_reg_defs.h:155:52: error: expected ‘)’ before ‘{’ token                                                                                                                               
   155 | #define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])                                                                                                                              
       |                              ~                     ^    

What I'm thinking for the remaining uses of _PICK() is to be explicit
and statically define them in a good .c depending on the use.
Then use that in the macro.

>
>> 2) Developers need to be careful not to incur an
>>    out-of-bounds array access
>> 3) Developers need to be careful that the indexes match the
>>    table. For that it may be that the table needs to contain
>>    holes, making (1) even worse.
>>
>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
>> one to use depending on the index value.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index be43580a6979..b7ec87464d69 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> @@ -119,6 +119,34 @@
>>   */
>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>>
>> +/*
>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
>> + * The first range is used for indexes below @__c_index, and the second
>> + * range is used for anything above it. Example::
>
>I'd like this to be clear about which range is used for index ==
>__c_index, instead of saying "below" and "above".
>
>No need for the double colon :: because this isn't a kernel-doc comment.

ok, what about this?

  * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
  * @__c_index corresponds to the index in which the second range starts
  * to be used. Using math interval notation, the first range is used
  * for indexes [ 0, @__c_index), while the second range is used for
  * [ @__c_index, ... ). Example:


>
>> + *
>> + * #define _FOO_A			0xf000
>> + * #define _FOO_B			0xf004
>> + * #define _FOO_C			0xf008
>> + * #define _SUPER_FOO_A			0xa000
>> + * #define _SUPER_FOO_B			0xa100
>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
>
>The example uses a different name for the macro.

yeah, that was the previous name I was using... good catch, will fix.

>
>> + *					      _FOO_A, _FOO_B,			\
>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
>> + *
>> + * This expands to:
>> + *	0: 0xf000,
>> + *	1: 0xf004,
>> + *	2: 0xf008,
>> + *	3: 0xa100,
>
>With the above definitions, this would be 3: 0xa000.

fixed


thanks
Lucas De Marchi

>
>> + *	4: 0xa200,
>> + *	5: 0xa300,
>> + *	...
>> + */
>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
>> +				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
>> +
>>  /*
>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>>   *
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

(I missed this review you did before I had sent a v2.1, I will incorporate
what is missing in the next version)

On Mon, Jan 23, 2023 at 12:38:28PM +0200, Jani Nikula wrote:
>On Fri, 20 Jan 2023, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> It's a constant pattern in the driver to need to use 2 ranges of MMIOs
>> based on port, phy, pll, etc. When that happens, instead of using
>> _PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
>> due to some reasons like:
>>
>> 1) It increases the code size since the array is declared
>>    in each call site
>
>Would be interesting to see what this does, and whether the compiler has
>the smarts to combine these within each file:
>
>-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>+#define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])

if the compiler is smart, it would be at least 1 per compilation unit.
gcc doesn't seem smart enough to even compile it though:

../drivers/gpu/drm/i915/i915_reg_defs.h:155:52: error: expected ‘)’ before ‘{’ token                                                                                                                               
   155 | #define _PICK(__index, ...) (((static const u32 []){ __VA_ARGS__ })[__index])                                                                                                                              
       |                              ~                     ^    

What I'm thinking for the remaining uses of _PICK() is to be explicit
and statically define them in a good .c depending on the use.
Then use that in the macro.

>
>> 2) Developers need to be careful not to incur an
>>    out-of-bounds array access
>> 3) Developers need to be careful that the indexes match the
>>    table. For that it may be that the table needs to contain
>>    holes, making (1) even worse.
>>
>> Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
>> one to use depending on the index value.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
>> index be43580a6979..b7ec87464d69 100644
>> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
>> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
>> @@ -119,6 +119,34 @@
>>   */
>>  #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>>
>> +/*
>> + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
>> + * The first range is used for indexes below @__c_index, and the second
>> + * range is used for anything above it. Example::
>
>I'd like this to be clear about which range is used for index ==
>__c_index, instead of saying "below" and "above".
>
>No need for the double colon :: because this isn't a kernel-doc comment.

ok, what about this?

  * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
  * @__c_index corresponds to the index in which the second range starts
  * to be used. Using math interval notation, the first range is used
  * for indexes [ 0, @__c_index), while the second range is used for
  * [ @__c_index, ... ). Example:


>
>> + *
>> + * #define _FOO_A			0xf000
>> + * #define _FOO_B			0xf004
>> + * #define _FOO_C			0xf008
>> + * #define _SUPER_FOO_A			0xa000
>> + * #define _SUPER_FOO_B			0xa100
>> + * #define FOO(x)			_MMIO(_PICK_EVEN_RANGES(x, 3,		\
>
>The example uses a different name for the macro.

yeah, that was the previous name I was using... good catch, will fix.

>
>> + *					      _FOO_A, _FOO_B,			\
>> + *					      _SUPER_FOO_A, _SUPER_FOO_B))
>> + *
>> + * This expands to:
>> + *	0: 0xf000,
>> + *	1: 0xf004,
>> + *	2: 0xf008,
>> + *	3: 0xa100,
>
>With the above definitions, this would be 3: 0xa000.

fixed


thanks
Lucas De Marchi

>
>> + *	4: 0xa200,
>> + *	5: 0xa300,
>> + *	...
>> + */
>> +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
>> +	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
>> +	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
>> +				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
>> +
>>  /*
>>   * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>>   *
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

[PATCH v2.2] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

v2: Fix the address expansion in the example (Anusha)
v3: Also rename macro to _PICK_EVEN_2RANGES() in the documentation
    and reword it to clarify what ranges are chosen based on the index
    (Jani)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 29 ++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..983c5aa3045b 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,35 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * @__c_index corresponds to the index in which the second range starts to be
+ * used. Using math interval notation, the first range is used for indexes [ 0,
+ * @__c_index), while the second range is used for [ @__c_index, ... ). Example:
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_2RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa000,
+ *	4: 0xa100,
+ *	5: 0xa200,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

[Intel-gfx] [PATCH v2.2] drm/i915: Add _PICK_EVEN_2RANGES()

[Lucas De Marchi]

It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used.  Using _PICK() is discouraged
due to some reasons like:

1) It increases the code size since the array is declared
   in each call site
2) Developers need to be careful not to incur an
   out-of-bounds array access
3) Developers need to be careful that the indexes match the
   table. For that it may be that the table needs to contain
   holes, making (1) even worse.

Add a variant of _PICK_EVEN() that works with 2 ranges and selects which
one to use depending on the index value.

v2: Fix the address expansion in the example (Anusha)
v3: Also rename macro to _PICK_EVEN_2RANGES() in the documentation
    and reword it to clarify what ranges are chosen based on the index
    (Jani)

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg_defs.h | 29 ++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index be43580a6979..983c5aa3045b 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -119,6 +119,35 @@
  */
 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
 
+/*
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
+ * @__c_index corresponds to the index in which the second range starts to be
+ * used. Using math interval notation, the first range is used for indexes [ 0,
+ * @__c_index), while the second range is used for [ @__c_index, ... ). Example:
+ *
+ * #define _FOO_A			0xf000
+ * #define _FOO_B			0xf004
+ * #define _FOO_C			0xf008
+ * #define _SUPER_FOO_A			0xa000
+ * #define _SUPER_FOO_B			0xa100
+ * #define FOO(x)			_MMIO(_PICK_EVEN_2RANGES(x, 3,		\
+ *					      _FOO_A, _FOO_B,			\
+ *					      _SUPER_FOO_A, _SUPER_FOO_B))
+ *
+ * This expands to:
+ *	0: 0xf000,
+ *	1: 0xf004,
+ *	2: 0xf008,
+ *	3: 0xa000,
+ *	4: 0xa100,
+ *	5: 0xa200,
+ *	...
+ */
+#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
+	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
+	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
+				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
+
 /*
  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
  *
-- 
2.39.0

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add _PICK_EVEN_2RANGES (rev3)

[Patchwork]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev3)
URL   : https://patchwork.freedesktop.org/series/113177/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Add _PICK_EVEN_2RANGES (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5559 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev3)
URL   : https://patchwork.freedesktop.org/series/113177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12640 -> Patchwork_113177v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/index.html

Participating hosts (37 -> 37)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_113177v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - fi-ctg-p8600:       [PASS][1] -> [DMESG-WARN][2] ([i915#6020])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-ctg-p8600/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-ctg-p8600/igt@i915_module_load@load.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-kbl-8809g:       [PASS][3] -> [INCOMPLETE][4] ([i915#4817])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-kbl-8809g/igt@i915_suspend@basic-s3-without-i915.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-kbl-8809g/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-bsw-nick:        NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - fi-ivb-3770:        NOTRUN -> [SKIP][6] ([fdo#109271])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-ivb-3770/igt@kms_pipe_crc_basic@suspend-read-crc.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-adlp-9}:       [DMESG-WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/bat-adlp-9/igt@gem_exec_suspend@basic-s0@smem.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/bat-adlp-9/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][9] ([i915#7911]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@migrate:
    - {bat-dg2-11}:       [DMESG-WARN][11] ([i915#7699]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/bat-dg2-11/igt@i915_selftest@live@migrate.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size:
    - fi-bsw-n3050:       [FAIL][13] ([i915#2346]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-bsw-n3050/igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-bsw-n3050/igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size.html

  
#### Warnings ####

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       [FAIL][15] ([fdo#103375]) -> [INCOMPLETE][16] ([i915#4817])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
  [i915#6020]: https://gitlab.freedesktop.org/drm/intel/issues/6020
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911


Build changes
-------------

  * Linux: CI_DRM_12640 -> Patchwork_113177v3

  CI-20190529: 20190529
  CI_DRM_12640: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7136: 31b6af91747ad8c705399c9006cdb81cb1864146 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v3: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

22dae415f850 drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES()
54a0b0f92453 drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES()
9199d583cce1 drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES()
3688ddf11a6c drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES()
fb0b6ba401a5 drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES()
53c4943f0a5a drm/i915: Convert pll macros to _PICK_EVEN_2RANGES
578fc8810577 drm/i915: Fix coding style on DPLL*_ENABLE defines
ad8617cbcb74 drm/i915: Add _PICK_EVEN_2RANGES()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/index.html

[-- Attachment #2: Type: text/html, Size: 6431 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Add _PICK_EVEN_2RANGES (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 20467 bytes --]

== Series Details ==

Series: Add _PICK_EVEN_2RANGES (rev3)
URL   : https://patchwork.freedesktop.org/series/113177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12640_full -> Patchwork_113177v3_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/index.html

Participating hosts (12 -> 10)
------------------------------

  Missing    (2): pig-skl-6260u pig-kbl-iris 

Known issues
------------

  Here are the changes found in Patchwork_113177v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([i915#2842])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk4/igt@gem_exec_fair@basic-pace@vecs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-glk5/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2346])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@perf@stress-open-close:
    - shard-glk:          [PASS][5] -> [INCOMPLETE][6] ([i915#5213])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk6/igt@perf@stress-open-close.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-glk4/igt@perf@stress-open-close.html

  * igt@runner@aborted:
    - shard-glk:          NOTRUN -> [FAIL][7] ([i915#4312])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-glk4/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@fbdev@unaligned-read:
    - {shard-rkl}:        [SKIP][8] ([i915#2582]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@fbdev@unaligned-read.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@feature_discovery@psr1:
    - {shard-rkl}:        [SKIP][10] ([i915#658]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@feature_discovery@psr1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@feature_discovery@psr1.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - {shard-rkl}:        [SKIP][12] ([i915#6252]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-1/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - {shard-rkl}:        [FAIL][14] ([i915#2842]) -> [PASS][15] +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - {shard-rkl}:        [SKIP][16] ([i915#3281]) -> [PASS][17] +4 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-active.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@semaphore-power:
    - {shard-rkl}:        [SKIP][18] ([i915#7276]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@gem_exec_schedule@semaphore-power.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_pread@self:
    - {shard-rkl}:        [SKIP][20] ([i915#3282]) -> [PASS][21] +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gem_pread@self.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@gem_pread@self.html

  * igt@gen9_exec_parse@shadow-peek:
    - {shard-rkl}:        [SKIP][22] ([i915#2527]) -> [PASS][23] +2 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gen9_exec_parse@shadow-peek.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_hangman@gt-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][24] ([i915#6258]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-1/igt@i915_hangman@gt-engine-error@bcs0.html

  * igt@i915_pipe_stress@stress-xrgb8888-untiled:
    - {shard-rkl}:        [SKIP][26] ([i915#4098]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@i915_pipe_stress@stress-xrgb8888-untiled.html

  * igt@i915_pm_rpm@fences:
    - {shard-rkl}:        [SKIP][28] ([i915#1849]) -> [PASS][29] +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@i915_pm_rpm@fences.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@i915_pm_rpm@fences.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - {shard-rkl}:        [SKIP][30] ([i915#1397]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_pm_sseu@full-enable:
    - {shard-rkl}:        [SKIP][32] ([i915#4387]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@i915_pm_sseu@full-enable.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@i915_pm_sseu@full-enable.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - {shard-rkl}:        [SKIP][34] ([i915#1845] / [i915#4098]) -> [PASS][35] +23 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
    - {shard-rkl}:        [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +13 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_psr@cursor_mmap_gtt:
    - {shard-rkl}:        [SKIP][38] ([i915#1072]) -> [PASS][39] +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@kms_psr@cursor_mmap_gtt.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html

  * igt@kms_universal_plane@cursor-fb-leak-pipe-b:
    - {shard-rkl}:        [SKIP][40] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html

  * igt@perf@polling-small-buf:
    - {shard-rkl}:        [FAIL][42] ([i915#1722]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@perf@polling-small-buf.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@perf@polling-small-buf.html

  * igt@perf_pmu@idle@rcs0:
    - {shard-rkl}:        [FAIL][44] ([i915#4349]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-6/igt@perf_pmu@idle@rcs0.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@perf_pmu@idle@rcs0.html

  * igt@prime_vgem@basic-fence-flip:
    - {shard-rkl}:        [SKIP][46] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@prime_vgem@basic-fence-flip.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - {shard-rkl}:        [SKIP][48] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@prime_vgem@basic-fence-read.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/shard-rkl-5/igt@prime_vgem@basic-fence-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957


Build changes
-------------

  * Linux: CI_DRM_12640 -> Patchwork_113177v3
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12640: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7136: 31b6af91747ad8c705399c9006cdb81cb1864146 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113177v3: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113177v3/index.html

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