* [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 @ 2020-10-14 14:59 ` Tejas Upadhyay 0 siblings, 0 replies; 11+ messages in thread From: Tejas Upadhyay @ 2020-10-14 14:59 UTC (permalink / raw) To: intel-gfx, dri-devel JSL has update in vswing table for eDP. BSpec: 21257 Cc: Souza Jose <jose.souza@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bb0b9930958f..7ab694c6d8df 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { + /* NT mV Trans mV db */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ +}; + +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ +}; + struct icl_mg_phy_ddi_buf_trans { u32 cri_txdeemph_override_11_6; u32 cri_txdeemph_override_5_0; @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); + return icl_combo_phy_ddi_translations_hdmi; +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); + return icl_combo_phy_ddi_translations_dp_hbr2; +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + if (dev_priv->vbt.edp.low_vswing) { + if (crtc_state->port_clock > 270000) { + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); + return jsl_combo_phy_ddi_translations_edp_hbr2; + } else { + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); + return jsl_combo_phy_ddi_translations_edp_hbr; + } + } + + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct cnl_ddi_buf_trans * tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, else tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); } else if (INTEL_GEN(dev_priv) == 11) { - if (IS_JSL_EHL(dev_priv)) + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, if (INTEL_GEN(dev_priv) >= 12) ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (IS_JSL_EHL(dev_priv)) + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); -- 2.28.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 @ 2020-10-14 14:59 ` Tejas Upadhyay 0 siblings, 0 replies; 11+ messages in thread From: Tejas Upadhyay @ 2020-10-14 14:59 UTC (permalink / raw) To: intel-gfx, dri-devel JSL has update in vswing table for eDP. BSpec: 21257 Cc: Souza Jose <jose.souza@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bb0b9930958f..7ab694c6d8df 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { + /* NT mV Trans mV db */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ +}; + +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { + /* NT mV Trans mV db */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ +}; + struct icl_mg_phy_ddi_buf_trans { u32 cri_txdeemph_override_11_6; u32 cri_txdeemph_override_5_0; @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); + return icl_combo_phy_ddi_translations_hdmi; +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); + return icl_combo_phy_ddi_translations_dp_hbr2; +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + if (dev_priv->vbt.edp.low_vswing) { + if (crtc_state->port_clock > 270000) { + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); + return jsl_combo_phy_ddi_translations_edp_hbr2; + } else { + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); + return jsl_combo_phy_ddi_translations_edp_hbr; + } + } + + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + +static const struct cnl_ddi_buf_trans * +jsl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + int *n_entries) +{ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); + else + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); +} + static const struct cnl_ddi_buf_trans * tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, else tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); } else if (INTEL_GEN(dev_priv) == 11) { - if (IS_JSL_EHL(dev_priv)) + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, if (INTEL_GEN(dev_priv) >= 12) ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); - else if (IS_JSL_EHL(dev_priv)) + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) 2020-10-14 14:59 ` [Intel-gfx] " Tejas Upadhyay (?) @ 2020-10-14 15:41 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-10-14 15:41 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx == Series Details == Series: drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) URL : https://patchwork.freedesktop.org/series/82206/ State : warning == Summary == $ dim checkpatch origin/drm-tip ecc43963cb27 drm/i915/edp/jsl: Update vswing table for HBR and HBR2 -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #58: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1195: +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1204: +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #76: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213: +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:85: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #85: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: + return jsl_combo_phy_ddi_translations_edp_hbr2; + } else { -:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #96: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1233: +jsl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, total: 0 errors, 1 warnings, 4 checks, 111 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) 2020-10-14 14:59 ` [Intel-gfx] " Tejas Upadhyay (?) (?) @ 2020-10-14 16:07 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-10-14 16:07 UTC (permalink / raw) To: Tejas Upadhyay; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6608 bytes --] == Series Details == Series: drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) URL : https://patchwork.freedesktop.org/series/82206/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9138 -> Patchwork_18699 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18699 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18699, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18699: ### IGT changes ### #### Possible regressions #### * igt@i915_pm_rpm@module-reload: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html Known issues ------------ Here are the changes found in Patchwork_18699 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@execlists: - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] ([i915#2276]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-icl-y/igt@i915_selftest@live@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-icl-y/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-tgl-u2: [PASS][5] -> [INCOMPLETE][6] ([i915#2557]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-u2/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_busy@basic@flip: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-y/igt@kms_busy@basic@flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-y/igt@kms_busy@basic@flip.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@vgem_basic@sysfs: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-y/igt@vgem_basic@sysfs.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-y/igt@vgem_basic@sysfs.html #### Possible fixes #### * igt@debugfs_test@read_all_entries: - {fi-kbl-7560u}: [INCOMPLETE][13] ([i915#2417]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html * igt@i915_module_load@reload: - fi-tgl-y: [DMESG-WARN][15] ([i915#1982] / [k.org#205379]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-y/igt@i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-y/igt@i915_module_load@reload.html - fi-icl-y: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-icl-y/igt@i915_module_load@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-icl-y/igt@i915_module_load@reload.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html #### Warnings #### * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-tgl-y: [DMESG-WARN][23] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][24] ([i915#2411]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9138/fi-tgl-y/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/fi-tgl-y/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417 [i915#2557]: https://gitlab.freedesktop.org/drm/intel/issues/2557 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379 Participating hosts (46 -> 40) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_9138 -> Patchwork_18699 CI-20190529: 20190529 CI_DRM_9138: 5e4234f97efbaa30f0beb243dcf98fe0a0bb0945 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5814: 7671d004f4b86d45ae54ee6443b14a18552548bd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18699: ecc43963cb276ac5b595974b376eee62ba7a99e4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ecc43963cb27 drm/i915/edp/jsl: Update vswing table for HBR and HBR2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18699/index.html [-- Attachment #1.2: Type: text/html, Size: 7981 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-14 14:59 ` [Intel-gfx] " Tejas Upadhyay @ 2020-10-16 20:41 ` Souza, Jose -1 siblings, 0 replies; 11+ messages in thread From: Souza, Jose @ 2020-10-16 20:41 UTC (permalink / raw) To: Surendrakumar Upadhyay, TejaskumarX, dri-devel, intel-gfx Please fix the checkpatch errors, you can run it locally by running "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch and setup dim. Also no need to CC drm-devel for patches that only touches i915, drm-devel is for drivers that don't have it's own list and for changes in drm subsystem that affects all other drm based drivers. On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > JSL has update in vswing table for eDP. > > BSpec: 21257 > > Cc: Souza Jose <jose.souza@intel.com> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++- > 1 file changed, 85 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index bb0b9930958f..7ab694c6d8df 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { > + /* NT mV Trans mV db */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > +}; > + > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { > + /* NT mV Trans mV db */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > +}; > + > struct icl_mg_phy_ddi_buf_trans { > u32 cri_txdeemph_override_11_6; > u32 cri_txdeemph_override_5_0; > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, > return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > + return icl_combo_phy_ddi_translations_hdmi; > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > + return icl_combo_phy_ddi_translations_dp_hbr2; > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > + if (dev_priv->vbt.edp.low_vswing) { > + if (crtc_state->port_clock > 270000) { > + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > + return jsl_combo_phy_ddi_translations_edp_hbr2; > + } else { > + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > + return jsl_combo_phy_ddi_translations_edp_hbr; > + } > + } > + > + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct cnl_ddi_buf_trans * > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, > else > tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); > } else if (INTEL_GEN(dev_priv) == 11) { > - if (IS_JSL_EHL(dev_priv)) > + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > else if (intel_phy_is_combo(dev_priv, phy)) > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > > > if (INTEL_GEN(dev_priv) >= 12) > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (IS_JSL_EHL(dev_priv)) > + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > else > ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 @ 2020-10-16 20:41 ` Souza, Jose 0 siblings, 0 replies; 11+ messages in thread From: Souza, Jose @ 2020-10-16 20:41 UTC (permalink / raw) To: Surendrakumar Upadhyay, TejaskumarX, dri-devel, intel-gfx Please fix the checkpatch errors, you can run it locally by running "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch and setup dim. Also no need to CC drm-devel for patches that only touches i915, drm-devel is for drivers that don't have it's own list and for changes in drm subsystem that affects all other drm based drivers. On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > JSL has update in vswing table for eDP. > > BSpec: 21257 > > Cc: Souza Jose <jose.souza@intel.com> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 87 +++++++++++++++++++++++- > 1 file changed, 85 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index bb0b9930958f..7ab694c6d8df 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { > + /* NT mV Trans mV db */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > + { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > + { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > +}; > + > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { > + /* NT mV Trans mV db */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > + { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > + { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > + { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > +}; > + > struct icl_mg_phy_ddi_buf_trans { > u32 cri_txdeemph_override_11_6; > u32 cri_txdeemph_override_5_0; > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, > return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > } > > > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > + return icl_combo_phy_ddi_translations_hdmi; > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > + return icl_combo_phy_ddi_translations_dp_hbr2; > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > + if (dev_priv->vbt.edp.low_vswing) { > + if (crtc_state->port_clock > 270000) { > + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > + return jsl_combo_phy_ddi_translations_edp_hbr2; > + } else { > + *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > + return jsl_combo_phy_ddi_translations_edp_hbr; > + } > + } > + > + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > +static const struct cnl_ddi_buf_trans * > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > + int *n_entries) > +{ > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > + return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > + return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > + else > + return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); > +} > + > static const struct cnl_ddi_buf_trans * > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > @@ -2363,7 +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, > else > tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); > } else if (INTEL_GEN(dev_priv) == 11) { > - if (IS_JSL_EHL(dev_priv)) > + if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > + jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > else if (intel_phy_is_combo(dev_priv, phy)) > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > @@ -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > > > if (INTEL_GEN(dev_priv) >= 12) > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > - else if (IS_JSL_EHL(dev_priv)) > + else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > + ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > + else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > else > ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-16 20:41 ` [Intel-gfx] " Souza, Jose (?) @ 2020-10-19 11:08 ` Surendrakumar Upadhyay, TejaskumarX 2020-10-19 17:09 ` Souza, Jose -1 siblings, 1 reply; 11+ messages in thread From: Surendrakumar Upadhyay, TejaskumarX @ 2020-10-19 11:08 UTC (permalink / raw) To: Souza, Jose, intel-gfx Hi Jose, I use scripts/checkpatch.pl. And it has reported me following : drm-tip# ./scripts/checkpatch.pl 0001-drm-i915-edp-jsl-Update-vswing-table-for-HBR-and-HBR.patch WARNING: else is not generally useful after a break or return #88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: + return jsl_combo_phy_ddi_translations_edp_hbr2; + } else { total: 0 errors, 1 warnings, 111 lines checked I have got 1 warning, which is because I have tried to maintain same format which is there in other similar functions in intel_ddi.c. If I will change to resolve this warning, everything else also needs similar change as applicable. Please let me know how you want me to proceed. Thanks, Tejas > -----Original Message----- > From: Souza, Jose <jose.souza@intel.com> > Sent: 17 October 2020 02:11 > To: Surendrakumar Upadhyay, TejaskumarX > <tejaskumarx.surendrakumar.upadhyay@intel.com>; dri- > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and > HBR2 > > Please fix the checkpatch errors, you can run it locally by running "dim > checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch > and setup dim. > > Also no need to CC drm-devel for patches that only touches i915, drm-devel > is for drivers that don't have it's own list and for changes in drm subsystem > that affects all other drm based drivers. > > On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > > JSL has update in vswing table for eDP. > > > > BSpec: 21257 > > > > Cc: Souza Jose <jose.souza@intel.com> > > Signed-off-by: Tejas Upadhyay > > <tejaskumarx.surendrakumar.upadhyay@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 > > +++++++++++++++++++++++- > > 1 file changed, 85 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index bb0b9930958f..7ab694c6d8df 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans > ehl_combo_phy_ddi_translations_dp[] = { > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */ > > }; > > > > > > +static const struct cnl_ddi_buf_trans > jsl_combo_phy_ddi_translations_edp_hbr[] = { > > +/* NT mV Trans mV db */ > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > +{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > > +{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > > +{ 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > +{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > > +{ 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > +}; > > + > > +static const struct cnl_ddi_buf_trans > jsl_combo_phy_ddi_translations_edp_hbr2[] = { > > +/* NT mV Trans mV db */ > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > > +{ 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > > +{ 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > +}; > > + > > struct icl_mg_phy_ddi_buf_trans { > > u32 cri_txdeemph_override_11_6; > > u32 cri_txdeemph_override_5_0; > > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder > > *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, > > n_entries); } > > > > > > +static const struct cnl_ddi_buf_trans * > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > + int *n_entries) > > +{ > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > > +return icl_combo_phy_ddi_translations_hdmi; > > +} > > + > > +static const struct cnl_ddi_buf_trans * > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > + int *n_entries) > > +{ > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > > +return icl_combo_phy_ddi_translations_dp_hbr2; > > +} > > + > > +static const struct cnl_ddi_buf_trans * > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > + int *n_entries) > > +{ > > +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + > > +if (dev_priv->vbt.edp.low_vswing) { > > +if (crtc_state->port_clock > 270000) { *n_entries = > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > > +return jsl_combo_phy_ddi_translations_edp_hbr2; > > +} else { > > +*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > > +return jsl_combo_phy_ddi_translations_edp_hbr; > > +} > > +} > > + > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > + > > +static const struct cnl_ddi_buf_trans * > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > + int *n_entries) > > +{ > > +if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return > > +jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); else if > > +(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return > > +jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > + > > static const struct cnl_ddi_buf_trans * > > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > const struct intel_crtc_state *crtc_state, @@ -2363,7 +2442,9 @@ > > static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, else > > tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); } else if > > (INTEL_GEN(dev_priv) == 11) { -if (IS_JSL_EHL(dev_priv)) > > +if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(encoder, > > crtc_state, &n_entries); @@ -2544,7 +2625,9 @@ static void > > icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > > > > > > if (INTEL_GEN(dev_priv) >= 12) > > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, > > &n_entries); -else if (IS_JSL_EHL(dev_priv)) > > +else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) ddi_translations = > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, > > &n_entries); else ddi_translations = > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-19 11:08 ` Surendrakumar Upadhyay, TejaskumarX @ 2020-10-19 17:09 ` Souza, Jose 2020-10-19 18:13 ` Surendrakumar Upadhyay, TejaskumarX 0 siblings, 1 reply; 11+ messages in thread From: Souza, Jose @ 2020-10-19 17:09 UTC (permalink / raw) To: Surendrakumar Upadhyay, TejaskumarX, intel-gfx I don't think that checkpatch.pl has all the style rules that we follow in drm. Check the output of "✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2)" there more style errors than that. On Mon, 2020-10-19 at 11:08 +0000, Surendrakumar Upadhyay, TejaskumarX wrote: > Hi Jose, > > I use scripts/checkpatch.pl. And it has reported me following : > > drm-tip# ./scripts/checkpatch.pl 0001-drm-i915-edp-jsl-Update-vswing-table-for-HBR-and-HBR.patch > WARNING: else is not generally useful after a break or return > #88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > + return jsl_combo_phy_ddi_translations_edp_hbr2; > + } else { > > total: 0 errors, 1 warnings, 111 lines checked > > I have got 1 warning, which is because I have tried to maintain same format which is there in other similar functions in intel_ddi.c. If I will change to resolve this warning, everything else also needs similar change as applicable. > > Please let me know how you want me to proceed. > > Thanks, > Tejas > > > -----Original Message----- > > From: Souza, Jose <jose.souza@intel.com> > > Sent: 17 October 2020 02:11 > > To: Surendrakumar Upadhyay, TejaskumarX > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; dri- > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and > > HBR2 > > > > Please fix the checkpatch errors, you can run it locally by running "dim > > checkpatch drm-tip/drm-tip..HEAD", search for instructions of how to fetch > > and setup dim. > > > > Also no need to CC drm-devel for patches that only touches i915, drm-devel > > is for drivers that don't have it's own list and for changes in drm subsystem > > that affects all other drm based drivers. > > > > On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > > > JSL has update in vswing table for eDP. > > > > > > BSpec: 21257 > > > > > > Cc: Souza Jose <jose.souza@intel.com> > > > Signed-off-by: Tejas Upadhyay > > > <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 > > > +++++++++++++++++++++++- > > > 1 file changed, 85 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index bb0b9930958f..7ab694c6d8df 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans > > ehl_combo_phy_ddi_translations_dp[] = { > > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */ > > > }; > > > > > > > > > +static const struct cnl_ddi_buf_trans > > jsl_combo_phy_ddi_translations_edp_hbr[] = { > > > +/* NT mV Trans mV db */ > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > +{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > > > +{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > > > +{ 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > +{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > > > +{ 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > +}; > > > + > > > +static const struct cnl_ddi_buf_trans > > jsl_combo_phy_ddi_translations_edp_hbr2[] = { > > > +/* NT mV Trans mV db */ > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > > > +{ 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > > > +{ 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > +}; > > > + > > > struct icl_mg_phy_ddi_buf_trans { > > > u32 cri_txdeemph_override_11_6; > > > u32 cri_txdeemph_override_5_0; > > > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct intel_encoder > > > *encoder, return ehl_get_combo_buf_trans_dp(encoder, crtc_state, > > > n_entries); } > > > > > > > > > +static const struct cnl_ddi_buf_trans * > > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state, > > > + int *n_entries) > > > +{ > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > > > +return icl_combo_phy_ddi_translations_hdmi; > > > +} > > > + > > > +static const struct cnl_ddi_buf_trans * > > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state, > > > + int *n_entries) > > > +{ > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > > > +return icl_combo_phy_ddi_translations_dp_hbr2; > > > +} > > > + > > > +static const struct cnl_ddi_buf_trans * > > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state, > > > + int *n_entries) > > > +{ > > > +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > + > > > +if (dev_priv->vbt.edp.low_vswing) { > > > +if (crtc_state->port_clock > 270000) { *n_entries = > > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > > > +return jsl_combo_phy_ddi_translations_edp_hbr2; > > > +} else { > > > +*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > > > +return jsl_combo_phy_ddi_translations_edp_hbr; > > > +} > > > +} > > > + > > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > > + > > > +static const struct cnl_ddi_buf_trans * > > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > > + const struct intel_crtc_state *crtc_state, > > > + int *n_entries) > > > +{ > > > +if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return > > > +jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); else if > > > +(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return > > > +jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); else > > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > > + > > > static const struct cnl_ddi_buf_trans * > > > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > const struct intel_crtc_state *crtc_state, @@ -2363,7 +2442,9 @@ > > > static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, else > > > tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries); } else if > > > (INTEL_GEN(dev_priv) == 11) { -if (IS_JSL_EHL(dev_priv)) > > > +if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > > (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(encoder, > > > crtc_state, &n_entries); @@ -2544,7 +2625,9 @@ static void > > > icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > > > > > > > > > if (INTEL_GEN(dev_priv) >= 12) > > > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, > > > &n_entries); -else if (IS_JSL_EHL(dev_priv)) > > > +else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) ddi_translations = > > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, > > > &n_entries); else ddi_translations = > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-19 17:09 ` Souza, Jose @ 2020-10-19 18:13 ` Surendrakumar Upadhyay, TejaskumarX 2020-10-19 18:15 ` Souza, Jose 0 siblings, 1 reply; 11+ messages in thread From: Surendrakumar Upadhyay, TejaskumarX @ 2020-10-19 18:13 UTC (permalink / raw) To: Souza, Jose, intel-gfx Hi Jose, root@tejas-System-Product-Name:/home/tejas/all-external/drm-tip# ./dim checkpatch a11736f058e7 (HEAD -> latest) drm/i915/edp/jsl: Update vswing table for HBR and HBR2 -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #58: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1195: +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1204: +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #76: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213: +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, -:85: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #85: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: + return jsl_combo_phy_ddi_translations_edp_hbr2; + } else { -:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #96: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1233: +jsl_get_combo_buf_trans(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, total: 0 errors, 1 warnings, 4 checks, 111 lines checked I see 1 warnings and 4 checks. Do you want me to solve those 4 checks? And this 1 warning is same that I was getting using ./scripts/checkpatch.pl and that is present in previous code as well thus fixing that will break uniformity. Please advise. Thanks, Tejas > -----Original Message----- > From: Souza, Jose <jose.souza@intel.com> > Sent: 19 October 2020 22:40 > To: Surendrakumar Upadhyay, TejaskumarX > <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and > HBR2 > > I don't think that checkpatch.pl has all the style rules that we follow in drm. > Check the output of "✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: > Update vswing table for HBR and HBR2 (rev2)" there more style errors than > that. > > On Mon, 2020-10-19 at 11:08 +0000, Surendrakumar Upadhyay, TejaskumarX > wrote: > > Hi Jose, > > > > I use scripts/checkpatch.pl. And it has reported me following : > > > > drm-tip# ./scripts/checkpatch.pl > > 0001-drm-i915-edp-jsl-Update-vswing-table-for-HBR-and-HBR.patch > > WARNING: else is not generally useful after a break or return > > #88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > > + return jsl_combo_phy_ddi_translations_edp_hbr2; > > + } else { > > > > total: 0 errors, 1 warnings, 111 lines checked > > > > I have got 1 warning, which is because I have tried to maintain same format > which is there in other similar functions in intel_ddi.c. If I will change to > resolve this warning, everything else also needs similar change as applicable. > > > > Please let me know how you want me to proceed. > > > > Thanks, > > Tejas > > > > > -----Original Message----- > > > From: Souza, Jose <jose.souza@intel.com> > > > Sent: 17 October 2020 02:11 > > > To: Surendrakumar Upadhyay, TejaskumarX > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; dri- > > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR > > > and > > > HBR2 > > > > > > Please fix the checkpatch errors, you can run it locally by running > > > "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of > > > how to fetch and setup dim. > > > > > > Also no need to CC drm-devel for patches that only touches i915, > > > drm-devel is for drivers that don't have it's own list and for > > > changes in drm subsystem that affects all other drm based drivers. > > > > > > On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > > > > JSL has update in vswing table for eDP. > > > > > > > > BSpec: 21257 > > > > > > > > Cc: Souza Jose <jose.souza@intel.com> > > > > Signed-off-by: Tejas Upadhyay > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 > > > > +++++++++++++++++++++++- > > > > 1 file changed, 85 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index bb0b9930958f..7ab694c6d8df 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans > > > ehl_combo_phy_ddi_translations_dp[] = { > > > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */ > > > > }; > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans > > > jsl_combo_phy_ddi_translations_edp_hbr[] = { > > > > +/* NT mV Trans mV db */ > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > +{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > > > > +{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > > > > +{ 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > +{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > > > > +{ 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > +}; > > > > + > > > > +static const struct cnl_ddi_buf_trans > > > jsl_combo_phy_ddi_translations_edp_hbr2[] = { > > > > +/* NT mV Trans mV db */ > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > > > > +{ 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > > > > +{ 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > +}; > > > > + > > > > struct icl_mg_phy_ddi_buf_trans { > > > > u32 cri_txdeemph_override_11_6; > > > > u32 cri_txdeemph_override_5_0; > > > > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct > > > > intel_encoder *encoder, return > > > > ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans * > > > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > + const struct intel_crtc_state *crtc_state, > > > > + int *n_entries) > > > > +{ > > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > > > > +return icl_combo_phy_ddi_translations_hdmi; > > > > +} > > > > + > > > > +static const struct cnl_ddi_buf_trans * > > > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > > > + const struct intel_crtc_state *crtc_state, > > > > + int *n_entries) > > > > +{ > > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > > > > +return icl_combo_phy_ddi_translations_dp_hbr2; > > > > +} > > > > + > > > > +static const struct cnl_ddi_buf_trans * > > > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > > > + const struct intel_crtc_state *crtc_state, > > > > + int *n_entries) > > > > +{ > > > > +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > + > > > > +if (dev_priv->vbt.edp.low_vswing) { if (crtc_state->port_clock > > > > > +270000) { *n_entries = > > > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > > > > +return jsl_combo_phy_ddi_translations_edp_hbr2; > > > > +} else { > > > > +*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > > > > +return jsl_combo_phy_ddi_translations_edp_hbr; > > > > +} > > > > +} > > > > + > > > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, > > > > +n_entries); } > > > > + > > > > +static const struct cnl_ddi_buf_trans * > > > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > > > + const struct intel_crtc_state *crtc_state, > > > > + int *n_entries) > > > > +{ > > > > +if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return > > > > +jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > > > > +else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > > > > +return jsl_get_combo_buf_trans_edp(encoder, crtc_state, > > > > +n_entries); else return jsl_get_combo_buf_trans_dp(encoder, > > > > +crtc_state, n_entries); } > > > > + > > > > static const struct cnl_ddi_buf_trans * > > > > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > const struct intel_crtc_state *crtc_state, @@ -2363,7 > > > > +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp > > > > *intel_dp, else tgl_get_dkl_buf_trans(encoder, crtc_state, > > > > &n_entries); } else if > > > > (INTEL_GEN(dev_priv) == 11) { -if (IS_JSL_EHL(dev_priv)) > > > > +if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else > > > > if (intel_phy_is_combo(dev_priv, phy)) > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); @@ > > > > -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct > > > > intel_encoder *encoder, > > > > > > > > > > > > if (INTEL_GEN(dev_priv) >= 12) > > > > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, > > > > &n_entries); -else if (IS_JSL_EHL(dev_priv)) > > > > +else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > +ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, > > > > +&n_entries); else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, > > > > &n_entries); else ddi_translations = > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-19 18:13 ` Surendrakumar Upadhyay, TejaskumarX @ 2020-10-19 18:15 ` Souza, Jose 2020-10-20 5:47 ` Surendrakumar Upadhyay, TejaskumarX 0 siblings, 1 reply; 11+ messages in thread From: Souza, Jose @ 2020-10-19 18:15 UTC (permalink / raw) To: Surendrakumar Upadhyay, TejaskumarX, intel-gfx Yes On Mon, 2020-10-19 at 18:13 +0000, Surendrakumar Upadhyay, TejaskumarX wrote: > Hi Jose, > > root@tejas-System-Product-Name:/home/tejas/all-external/drm-tip# ./dim checkpatch > a11736f058e7 (HEAD -> latest) drm/i915/edp/jsl: Update vswing table for HBR and HBR2 > -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #58: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1195: > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > > -:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1204: > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > > -:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #76: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213: > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > > -:85: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return > #85: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > + return jsl_combo_phy_ddi_translations_edp_hbr2; > + } else { > > -:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #96: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1233: > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state, > > total: 0 errors, 1 warnings, 4 checks, 111 lines checked > > I see 1 warnings and 4 checks. Do you want me to solve those 4 checks? And this 1 warning is same that I was getting using ./scripts/checkpatch.pl and that is present in previous code as well thus fixing that will break uniformity. > > Please advise. > > Thanks, > Tejas > > > -----Original Message----- > > From: Souza, Jose <jose.souza@intel.com> > > Sent: 19 October 2020 22:40 > > To: Surendrakumar Upadhyay, TejaskumarX > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel- > > gfx@lists.freedesktop.org > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and > > HBR2 > > > > I don't think that checkpatch.pl has all the style rules that we follow in drm. > > Check the output of "✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: > > Update vswing table for HBR and HBR2 (rev2)" there more style errors than > > that. > > > > On Mon, 2020-10-19 at 11:08 +0000, Surendrakumar Upadhyay, TejaskumarX > > wrote: > > > Hi Jose, > > > > > > I use scripts/checkpatch.pl. And it has reported me following : > > > > > > drm-tip# ./scripts/checkpatch.pl > > > 0001-drm-i915-edp-jsl-Update-vswing-table-for-HBR-and-HBR.patch > > > WARNING: else is not generally useful after a break or return > > > #88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > > > + return jsl_combo_phy_ddi_translations_edp_hbr2; > > > + } else { > > > > > > total: 0 errors, 1 warnings, 111 lines checked > > > > > > I have got 1 warning, which is because I have tried to maintain same format > > which is there in other similar functions in intel_ddi.c. If I will change to > > resolve this warning, everything else also needs similar change as applicable. > > > > > > Please let me know how you want me to proceed. > > > > > > Thanks, > > > Tejas > > > > > > > -----Original Message----- > > > > From: Souza, Jose <jose.souza@intel.com> > > > > Sent: 17 October 2020 02:11 > > > > To: Surendrakumar Upadhyay, TejaskumarX > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; dri- > > > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > > > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR > > > > and > > > > HBR2 > > > > > > > > Please fix the checkpatch errors, you can run it locally by running > > > > "dim checkpatch drm-tip/drm-tip..HEAD", search for instructions of > > > > how to fetch and setup dim. > > > > > > > > Also no need to CC drm-devel for patches that only touches i915, > > > > drm-devel is for drivers that don't have it's own list and for > > > > changes in drm subsystem that affects all other drm based drivers. > > > > > > > > On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > > > > > JSL has update in vswing table for eDP. > > > > > > > > > > BSpec: 21257 > > > > > > > > > > Cc: Souza Jose <jose.souza@intel.com> > > > > > Signed-off-by: Tejas Upadhyay > > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 > > > > > +++++++++++++++++++++++- > > > > > 1 file changed, 85 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > index bb0b9930958f..7ab694c6d8df 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans > > > > ehl_combo_phy_ddi_translations_dp[] = { > > > > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */ > > > > > }; > > > > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans > > > > jsl_combo_phy_ddi_translations_edp_hbr[] = { > > > > > +/* NT mV Trans mV db */ > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > > +{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > > > > > +{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > > > > > +{ 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > > +{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > > > > > +{ 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > > +}; > > > > > + > > > > > +static const struct cnl_ddi_buf_trans > > > > jsl_combo_phy_ddi_translations_edp_hbr2[] = { > > > > > +/* NT mV Trans mV db */ > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > > > > > +{ 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > > > > > +{ 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > > +}; > > > > > + > > > > > struct icl_mg_phy_ddi_buf_trans { > > > > > u32 cri_txdeemph_override_11_6; > > > > > u32 cri_txdeemph_override_5_0; > > > > > @@ -1162,6 +1190,57 @@ ehl_get_combo_buf_trans(struct > > > > > intel_encoder *encoder, return > > > > > ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > > > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans * > > > > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > > + const struct intel_crtc_state *crtc_state, > > > > > + int *n_entries) > > > > > +{ > > > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > > > > > +return icl_combo_phy_ddi_translations_hdmi; > > > > > +} > > > > > + > > > > > +static const struct cnl_ddi_buf_trans * > > > > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > > > > + const struct intel_crtc_state *crtc_state, > > > > > + int *n_entries) > > > > > +{ > > > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > > > > > +return icl_combo_phy_ddi_translations_dp_hbr2; > > > > > +} > > > > > + > > > > > +static const struct cnl_ddi_buf_trans * > > > > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > > > > + const struct intel_crtc_state *crtc_state, > > > > > + int *n_entries) > > > > > +{ > > > > > +struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > + > > > > > +if (dev_priv->vbt.edp.low_vswing) { if (crtc_state->port_clock > > > > > > +270000) { *n_entries = > > > > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > > > > > +return jsl_combo_phy_ddi_translations_edp_hbr2; > > > > > +} else { > > > > > +*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > > > > > +return jsl_combo_phy_ddi_translations_edp_hbr; > > > > > +} > > > > > +} > > > > > + > > > > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, > > > > > +n_entries); } > > > > > + > > > > > +static const struct cnl_ddi_buf_trans * > > > > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > > > > + const struct intel_crtc_state *crtc_state, > > > > > + int *n_entries) > > > > > +{ > > > > > +if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return > > > > > +jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); > > > > > +else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > > > > > +return jsl_get_combo_buf_trans_edp(encoder, crtc_state, > > > > > +n_entries); else return jsl_get_combo_buf_trans_dp(encoder, > > > > > +crtc_state, n_entries); } > > > > > + > > > > > static const struct cnl_ddi_buf_trans * > > > > > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > > const struct intel_crtc_state *crtc_state, @@ -2363,7 > > > > > +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp > > > > > *intel_dp, else tgl_get_dkl_buf_trans(encoder, crtc_state, > > > > > &n_entries); } else if > > > > > (INTEL_GEN(dev_priv) == 11) { -if (IS_JSL_EHL(dev_priv)) > > > > > +if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else if > > > > > +(IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > > > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); else > > > > > if (intel_phy_is_combo(dev_priv, phy)) > > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); @@ > > > > > -2544,7 +2625,9 @@ static void icl_ddi_combo_vswing_program(struct > > > > > intel_encoder *encoder, > > > > > > > > > > > > > > > if (INTEL_GEN(dev_priv) >= 12) > > > > > ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, > > > > > &n_entries); -else if (IS_JSL_EHL(dev_priv)) > > > > > +else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > > +ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, > > > > > +&n_entries); else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > > > ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, > > > > > &n_entries); else ddi_translations = > > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 2020-10-19 18:15 ` Souza, Jose @ 2020-10-20 5:47 ` Surendrakumar Upadhyay, TejaskumarX 0 siblings, 0 replies; 11+ messages in thread From: Surendrakumar Upadhyay, TejaskumarX @ 2020-10-20 5:47 UTC (permalink / raw) To: Souza, Jose, intel-gfx Sent new version https://patchwork.freedesktop.org/patch/395898/ . Thanks, Tejas > -----Original Message----- > From: Souza, Jose <jose.souza@intel.com> > Sent: 19 October 2020 23:45 > To: Surendrakumar Upadhyay, TejaskumarX > <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and > HBR2 > > Yes > > On Mon, 2020-10-19 at 18:13 +0000, Surendrakumar Upadhyay, TejaskumarX > wrote: > > Hi Jose, > > > > root@tejas-System-Product-Name:/home/tejas/all-external/drm-tip# ./dim > > checkpatch > > a11736f058e7 (HEAD -> latest) drm/i915/edp/jsl: Update vswing table > > for HBR and HBR2 > > -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open > > parenthesis > > #58: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1195: > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > > > -:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open > > parenthesis > > #67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1204: > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > > > -:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open > > parenthesis > > #76: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213: > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > > > -:85: WARNING:UNNECESSARY_ELSE: else is not generally useful after a > > break or return > > #85: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > > + return jsl_combo_phy_ddi_translations_edp_hbr2; > > + } else { > > > > -:96: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open > > parenthesis > > #96: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1233: > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state, > > > > total: 0 errors, 1 warnings, 4 checks, 111 lines checked > > > > I see 1 warnings and 4 checks. Do you want me to solve those 4 checks? > And this 1 warning is same that I was getting using ./scripts/checkpatch.pl > and that is present in previous code as well thus fixing that will break > uniformity. > > > > Please advise. > > > > Thanks, > > Tejas > > > > > -----Original Message----- > > > From: Souza, Jose <jose.souza@intel.com> > > > Sent: 19 October 2020 22:40 > > > To: Surendrakumar Upadhyay, TejaskumarX > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; intel- > > > gfx@lists.freedesktop.org > > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for HBR > > > and > > > HBR2 > > > > > > I don't think that checkpatch.pl has all the style rules that we follow in > drm. > > > Check the output of "✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: > > > Update vswing table for HBR and HBR2 (rev2)" there more style errors > > > than that. > > > > > > On Mon, 2020-10-19 at 11:08 +0000, Surendrakumar Upadhyay, > > > TejaskumarX > > > wrote: > > > > Hi Jose, > > > > > > > > I use scripts/checkpatch.pl. And it has reported me following : > > > > > > > > drm-tip# ./scripts/checkpatch.pl > > > > 0001-drm-i915-edp-jsl-Update-vswing-table-for-HBR-and-HBR.patch > > > > WARNING: else is not generally useful after a break or return > > > > #88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1222: > > > > + return jsl_combo_phy_ddi_translations_edp_hbr2; > > > > + } else { > > > > > > > > total: 0 errors, 1 warnings, 111 lines checked > > > > > > > > I have got 1 warning, which is because I have tried to maintain > > > > same format > > > which is there in other similar functions in intel_ddi.c. If I will > > > change to resolve this warning, everything else also needs similar change > as applicable. > > > > > > > > Please let me know how you want me to proceed. > > > > > > > > Thanks, > > > > Tejas > > > > > > > > > -----Original Message----- > > > > > From: Souza, Jose <jose.souza@intel.com> > > > > > Sent: 17 October 2020 02:11 > > > > > To: Surendrakumar Upadhyay, TejaskumarX > > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com>; dri- > > > > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > > > > > Subject: Re: [PATCH] drm/i915/edp/jsl: Update vswing table for > > > > > HBR and > > > > > HBR2 > > > > > > > > > > Please fix the checkpatch errors, you can run it locally by > > > > > running "dim checkpatch drm-tip/drm-tip..HEAD", search for > > > > > instructions of how to fetch and setup dim. > > > > > > > > > > Also no need to CC drm-devel for patches that only touches i915, > > > > > drm-devel is for drivers that don't have it's own list and for > > > > > changes in drm subsystem that affects all other drm based drivers. > > > > > > > > > > On Wed, 2020-10-14 at 20:29 +0530, Tejas Upadhyay wrote: > > > > > > JSL has update in vswing table for eDP. > > > > > > > > > > > > BSpec: 21257 > > > > > > > > > > > > Cc: Souza Jose <jose.souza@intel.com> > > > > > > Signed-off-by: Tejas Upadhyay > > > > > > <tejaskumarx.surendrakumar.upadhyay@intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 > > > > > > +++++++++++++++++++++++- > > > > > > 1 file changed, 85 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > > index bb0b9930958f..7ab694c6d8df 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > > > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans > > > > > ehl_combo_phy_ddi_translations_dp[] = { > > > > > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */ > > > > > > }; > > > > > > > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans > > > > > jsl_combo_phy_ddi_translations_edp_hbr[] = { > > > > > > +/* NT mV Trans mV db */ > > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > > > +{ 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ > > > > > > +{ 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ > > > > > > +{ 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ > > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > > > +{ 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ > > > > > > +{ 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ > > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > > > +}; > > > > > > + > > > > > > +static const struct cnl_ddi_buf_trans > > > > > jsl_combo_phy_ddi_translations_edp_hbr2[] = { > > > > > > +/* NT mV Trans mV db */ > > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ > > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ > > > > > > +{ 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ > > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ > > > > > > +{ 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ > > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ > > > > > > +{ 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ > > > > > > +{ 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ > > > > > > +{ 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ > > > > > > +{ 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > > > > > > +}; > > > > > > + > > > > > > struct icl_mg_phy_ddi_buf_trans { > > > > > > u32 cri_txdeemph_override_11_6; > > > > > > u32 cri_txdeemph_override_5_0; @@ -1162,6 +1190,57 @@ > > > > > > ehl_get_combo_buf_trans(struct intel_encoder *encoder, return > > > > > > ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); } > > > > > > > > > > > > > > > > > > +static const struct cnl_ddi_buf_trans * > > > > > > +jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > > > + const struct intel_crtc_state *crtc_state, > > > > > > + int *n_entries) > > > > > > +{ > > > > > > +*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > > > > > > +return icl_combo_phy_ddi_translations_hdmi; > > > > > > +} > > > > > > + > > > > > > +static const struct cnl_ddi_buf_trans * > > > > > > +jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, > > > > > > + const struct intel_crtc_state *crtc_state, > > > > > > + int *n_entries) > > > > > > +{ > > > > > > +*n_entries = > > > > > > +ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); > > > > > > +return icl_combo_phy_ddi_translations_dp_hbr2; > > > > > > +} > > > > > > + > > > > > > +static const struct cnl_ddi_buf_trans * > > > > > > +jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, > > > > > > + const struct intel_crtc_state *crtc_state, > > > > > > + int *n_entries) > > > > > > +{ > > > > > > +struct drm_i915_private *dev_priv = > > > > > > +to_i915(encoder->base.dev); > > > > > > + > > > > > > +if (dev_priv->vbt.edp.low_vswing) { if > > > > > > +(crtc_state->port_clock > > > > > > > +270000) { *n_entries = > > > > > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); > > > > > > +return jsl_combo_phy_ddi_translations_edp_hbr2; > > > > > > +} else { > > > > > > +*n_entries = > > > > > > +ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); > > > > > > +return jsl_combo_phy_ddi_translations_edp_hbr; > > > > > > +} > > > > > > +} > > > > > > + > > > > > > +return jsl_get_combo_buf_trans_dp(encoder, crtc_state, > > > > > > +n_entries); } > > > > > > + > > > > > > +static const struct cnl_ddi_buf_trans * > > > > > > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, > > > > > > + const struct intel_crtc_state *crtc_state, > > > > > > + int *n_entries) > > > > > > +{ > > > > > > +if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > > > > > > +return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, > > > > > > +n_entries); else if (intel_crtc_has_type(crtc_state, > > > > > > +INTEL_OUTPUT_EDP)) return > > > > > > +jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); > > > > > > +else return jsl_get_combo_buf_trans_dp(encoder, > > > > > > +crtc_state, n_entries); } > > > > > > + > > > > > > static const struct cnl_ddi_buf_trans * > > > > > > tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, > > > > > > const struct intel_crtc_state *crtc_state, @@ -2363,7 > > > > > > +2442,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp > > > > > > *intel_dp, else tgl_get_dkl_buf_trans(encoder, crtc_state, > > > > > > &n_entries); } else if > > > > > > (INTEL_GEN(dev_priv) == 11) { -if (IS_JSL_EHL(dev_priv)) > > > > > > +if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > > > +jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > +else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > > > > > > ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > else if (intel_phy_is_combo(dev_priv, phy)) > > > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); @@ > > > > > > -2544,7 +2625,9 @@ static void > > > > > > icl_ddi_combo_vswing_program(struct > > > > > > intel_encoder *encoder, > > > > > > > > > > > > > > > > > > if (INTEL_GEN(dev_priv) >= 12) ddi_translations = > > > > > > tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > -else if (IS_JSL_EHL(dev_priv)) > > > > > > +else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)) > > > > > > +ddi_translations = jsl_get_combo_buf_trans(encoder, > > > > > > +crtc_state, &n_entries); else if (IS_PLATFORM(dev_priv, > > > > > > +INTEL_ELKHARTLAKE)) > > > > > > ddi_translations = ehl_get_combo_buf_trans(encoder, > > > > > > crtc_state, &n_entries); else ddi_translations = > > > > > > icl_get_combo_buf_trans(encoder, crtc_state, &n_entries); > > > > > > > > > > > > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-10-20 5:48 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-14 14:59 [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 Tejas Upadhyay 2020-10-14 14:59 ` [Intel-gfx] " Tejas Upadhyay 2020-10-14 15:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/edp/jsl: Update vswing table for HBR and HBR2 (rev2) Patchwork 2020-10-14 16:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2020-10-16 20:41 ` [PATCH] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 Souza, Jose 2020-10-16 20:41 ` [Intel-gfx] " Souza, Jose 2020-10-19 11:08 ` Surendrakumar Upadhyay, TejaskumarX 2020-10-19 17:09 ` Souza, Jose 2020-10-19 18:13 ` Surendrakumar Upadhyay, TejaskumarX 2020-10-19 18:15 ` Souza, Jose 2020-10-20 5:47 ` Surendrakumar Upadhyay, TejaskumarX
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