From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> To: Biju Das <biju.das@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: Simon Horman <horms@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>, "linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Chris Paterson <Chris.Paterson2@renesas.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, John Stultz <john.stultz@linaro.org> Subject: RE: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes Date: Fri, 26 Oct 2018 09:48:05 +0000 [thread overview] Message-ID: <TYXPR01MB1775D59976A9B263E1B610F8C0F00@TYXPR01MB1775.jpnprd01.prod.outlook.com> (raw) In-Reply-To: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> > Subject: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes > > This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > This patch is tested against renesas-dev > > I have executed on inconsistency-check, nanosleep and clocksource_switch > selftests on this arm64 SoC. The inconsistency-check and nanosleep tests > are working fine.The clocksource_switch asynchronous test is failing due > to inconsistency-check failure on "arch_sys_counter". > > But if i skip the clocksource_switching of "arch_sys_counter", the > asynchronous test is passing for CMT0/1/2/3 timer. > > Has any one noticed this issue? > --- > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > index 1ec6aaa..d62febd0 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -401,6 +401,76 @@ > reg = <0 0xe6060000 0 0x50c>; > }; > > +cmt0: timer@e60f0000 { > +compatible = "renesas,r8a7796-cmt0", > + "renesas,rcar-gen3-cmt0"; > +reg = <0 0xe60f0000 0 0x1004>; > +interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 303>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 303>; > +status = "disabled"; > +}; > + > +cmt1: timer@e6130000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6130000 0 0x1004>; > +interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 302>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 302>; > +status = "disabled"; > +}; > + > +cmt2: timer@e6140000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6140000 0 0x1004>; > +interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 301>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 301>; > +status = "disabled"; > +}; > + > +cmt3: timer@e6148000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6148000 0 0x1004>; > +interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 300>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 300>; > +status = "disabled"; > +}; > + > cpg: clock-controller@e6150000 { > compatible = "renesas,r8a7796-cpg-mssr"; > reg = <0 0xe6150000 0 0x1000>; > -- > 2.7.4 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
WARNING: multiple messages have this Message-ID (diff)
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> To: Biju Das <biju.das@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com> Cc: Biju Das <biju.das@bp.renesas.com>, Simon Horman <horms@verge.net.au>, Magnus Damm <magnus.damm@gmail.com>, "linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Chris Paterson <Chris.Paterson2@renesas.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, John Stultz <john.stultz@linaro.org> Subject: RE: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes Date: Fri, 26 Oct 2018 09:48:05 +0000 [thread overview] Message-ID: <TYXPR01MB1775D59976A9B263E1B610F8C0F00@TYXPR01MB1775.jpnprd01.prod.outlook.com> (raw) In-Reply-To: <1540542307-63158-1-git-send-email-biju.das@bp.renesas.com> > Subject: [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes > > This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > This patch is tested against renesas-dev > > I have executed on inconsistency-check, nanosleep and clocksource_switch > selftests on this arm64 SoC. The inconsistency-check and nanosleep tests > are working fine.The clocksource_switch asynchronous test is failing due > to inconsistency-check failure on "arch_sys_counter". > > But if i skip the clocksource_switching of "arch_sys_counter", the > asynchronous test is passing for CMT0/1/2/3 timer. > > Has any one noticed this issue? > --- > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > index 1ec6aaa..d62febd0 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi > @@ -401,6 +401,76 @@ > reg = <0 0xe6060000 0 0x50c>; > }; > > +cmt0: timer@e60f0000 { > +compatible = "renesas,r8a7796-cmt0", > + "renesas,rcar-gen3-cmt0"; > +reg = <0 0xe60f0000 0 0x1004>; > +interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 303>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 303>; > +status = "disabled"; > +}; > + > +cmt1: timer@e6130000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6130000 0 0x1004>; > +interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 302>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 302>; > +status = "disabled"; > +}; > + > +cmt2: timer@e6140000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6140000 0 0x1004>; > +interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 301>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 301>; > +status = "disabled"; > +}; > + > +cmt3: timer@e6148000 { > +compatible = "renesas,r8a7796-cmt1", > + "renesas,rcar-gen3-cmt1"; > +reg = <0 0xe6148000 0 0x1004>; > +interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; > +clocks = <&cpg CPG_MOD 300>; > +clock-names = "fck"; > +power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; > +resets = <&cpg 300>; > +status = "disabled"; > +}; > + > cpg: clock-controller@e6150000 { > compatible = "renesas,r8a7796-cpg-mssr"; > reg = <0 0xe6150000 0 0x1000>; > -- > 2.7.4 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
next prev parent reply other threads:[~2018-10-26 9:48 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-26 8:25 [PATCH] arm64: dts: renesas: r8a7796: Add CMT device nodes Biju Das 2018-10-26 9:48 ` Fabrizio Castro [this message] 2018-10-26 9:48 ` Fabrizio Castro 2018-11-19 8:27 ` Biju Das 2018-11-19 9:36 ` Daniel Lezcano 2018-11-19 10:26 ` Daniel Lezcano 2018-11-19 10:32 ` Geert Uytterhoeven 2018-11-19 10:35 ` Biju Das 2018-11-19 11:01 ` Daniel Lezcano 2018-11-19 15:50 ` Biju Das 2018-11-19 17:14 ` Daniel Lezcano 2018-11-22 9:46 ` Biju Das 2018-11-22 13:47 ` Daniel Lezcano 2018-11-22 15:16 ` Biju Das 2018-11-22 15:16 ` Biju Das 2018-11-22 15:30 ` Daniel Lezcano 2018-11-22 15:30 ` Daniel Lezcano 2018-11-22 15:55 ` Marc Zyngier 2018-11-22 15:55 ` Marc Zyngier 2018-11-21 10:24 ` Simon Horman 2018-11-21 10:27 ` Biju Das 2018-11-23 12:37 ` Simon Horman 2019-01-24 10:15 ` Geert Uytterhoeven 2019-01-24 10:15 ` Geert Uytterhoeven 2019-01-25 11:30 ` Biju Das 2019-01-25 11:30 ` Biju Das 2019-01-25 12:26 ` Biju Das 2019-01-25 12:26 ` Biju Das 2019-01-25 14:06 ` Vincent Guittot 2019-01-25 14:06 ` Vincent Guittot 2019-01-25 14:29 ` Biju Das 2019-01-25 14:29 ` Biju Das 2019-01-25 14:44 ` Biju Das 2019-01-25 14:44 ` Biju Das 2019-01-25 14:48 ` Vincent Guittot 2019-01-25 14:48 ` Vincent Guittot 2019-01-25 14:53 ` Vincent Guittot 2019-01-25 14:53 ` Vincent Guittot 2019-01-25 15:12 ` Biju Das 2019-01-25 15:20 ` Vincent Guittot 2019-01-25 15:20 ` Vincent Guittot
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