* [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
@ 2019-08-19 8:27 Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC Yangbo Lu
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Yangbo Lu @ 2019-08-19 8:27 UTC (permalink / raw)
To: u-boot
This patch-set is to clean up fsl_esdhc code.
Yangbo Lu (3):
mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
mmc: fsl_esdhc: clean up code
mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
drivers/mmc/fsl_esdhc.c | 371 +++++++++++++++++++-----------------------------
include/fsl_esdhc.h | 203 ++++++++++++--------------
2 files changed, 240 insertions(+), 334 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
2019-08-19 8:27 [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Yangbo Lu
@ 2019-08-19 8:27 ` Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code Yangbo Lu
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Yangbo Lu @ 2019-08-19 8:27 UTC (permalink / raw)
To: u-boot
Current fsl_esdhc driver had support DM_MMC with BLK enabled.
Since BLK will be hard requirement of DM_MMC, let's do this
now in fsl_esdhc driver. Don't keep BLK conditioanl compiling.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/mmc/fsl_esdhc.c | 35 +----------------------------------
1 file changed, 1 insertion(+), 34 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0731847..ff5565c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -23,10 +23,6 @@
#include <asm/io.h>
#include <dm.h>
-#if !CONFIG_IS_ENABLED(BLK)
-#include "mmc_private.h"
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -35,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
IRQSTATEN_DINT)
-#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
@@ -98,7 +93,7 @@ struct fsl_esdhc_priv {
struct clk per_clk;
unsigned int clock;
unsigned int bus_width;
-#if !CONFIG_IS_ENABLED(BLK)
+#if !CONFIG_IS_ENABLED(DM_MMC)
struct mmc *mmc;
#endif
struct udevice *dev;
@@ -961,9 +956,6 @@ static int fsl_esdhc_probe(struct udevice *dev)
fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
-#if !CONFIG_IS_ENABLED(BLK)
- struct blk_desc *bdesc;
-#endif
int ret;
addr = dev_read_addr(dev);
@@ -1027,32 +1019,12 @@ static int fsl_esdhc_probe(struct udevice *dev)
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
mmc->dev = dev;
-#if !CONFIG_IS_ENABLED(BLK)
- mmc->priv = priv;
-
- /* Setup dsr related values */
- mmc->dsr_imp = 0;
- mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
- /* Setup the universal parts of the block interface just once */
- bdesc = mmc_get_blk_desc(mmc);
- bdesc->if_type = IF_TYPE_MMC;
- bdesc->removable = 1;
- bdesc->devnum = mmc_get_next_devnum();
- bdesc->block_read = mmc_bread;
- bdesc->block_write = mmc_bwrite;
- bdesc->block_erase = mmc_berase;
-
- /* setup initial part type */
- bdesc->part_type = mmc->cfg->part_type;
- mmc_list_add(mmc);
-#endif
upriv->mmc = mmc;
return esdhc_init_common(priv, mmc);
}
-#if CONFIG_IS_ENABLED(DM_MMC)
static int fsl_esdhc_get_cd(struct udevice *dev)
{
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
@@ -1082,30 +1054,25 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
.send_cmd = fsl_esdhc_send_cmd,
.set_ios = fsl_esdhc_set_ios,
};
-#endif
static const struct udevice_id fsl_esdhc_ids[] = {
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
-#if CONFIG_IS_ENABLED(BLK)
static int fsl_esdhc_bind(struct udevice *dev)
{
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}
-#endif
U_BOOT_DRIVER(fsl_esdhc) = {
.name = "fsl-esdhc-mmc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
.ops = &fsl_esdhc_ops,
-#if CONFIG_IS_ENABLED(BLK)
.bind = fsl_esdhc_bind,
-#endif
.probe = fsl_esdhc_probe,
.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
2019-08-19 8:27 [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC Yangbo Lu
@ 2019-08-19 8:27 ` Yangbo Lu
2019-08-23 8:44 ` Lukasz Majewski
2019-08-19 8:27 ` [U-Boot] [PATCH 3/3] mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg Yangbo Lu
2019-09-04 4:22 ` [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Y.b. Lu
3 siblings, 1 reply; 10+ messages in thread
From: Yangbo Lu @ 2019-08-19 8:27 UTC (permalink / raw)
To: u-boot
This patch is just to clean up code. There were not changes on function.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/mmc/fsl_esdhc.c | 288 ++++++++++++++++++++++++------------------------
include/fsl_esdhc.h | 203 ++++++++++++++++------------------
2 files changed, 238 insertions(+), 253 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ff5565c..d176bb3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -25,12 +25,13 @@
DECLARE_GLOBAL_DATA_PTR;
-#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
- IRQSTATEN_CINT | \
- IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
- IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
- IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
- IRQSTATEN_DINT)
+#define ESDHC_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
+ IRQSTATEN_DINT | IRQSTATEN_BWR | \
+ IRQSTATEN_BRR | IRQSTATEN_CINT | \
+ IRQSTATEN_CTOE | IRQSTATEN_CCE | \
+ IRQSTATEN_CEBE | IRQSTATEN_CIE | \
+ IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+ IRQSTATEN_DEBE)
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
@@ -76,16 +77,15 @@ struct fsl_esdhc_plat {
* struct fsl_esdhc_priv
*
* @esdhc_regs: registers of the sdhc controller
- * @sdhc_clk: Current clk of the sdhc controller
+ * @sdhc_clk: reference clk of the sdhc controller
+ * @per_clk: peripheral clock
+ * @clock: target clock
* @bus_width: bus width, 1bit, 4bit or 8bit
- * @cfg: mmc config
* @mmc: mmc
* Following is used when Driver Model is enabled for MMC
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
* @wp_enable: 1: enable checking wp; 0: no check
- * @cd_gpio: gpio for card detection
- * @wp_gpio: gpio for write protection
*/
struct fsl_esdhc_priv {
struct fsl_esdhc *esdhc_regs;
@@ -102,7 +102,7 @@ struct fsl_esdhc_priv {
};
/* Return the XFERTYP flags for a given command and data packet */
-static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+static uint esdhc_setup_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
uint xfertyp = 0;
@@ -310,9 +310,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
return 0;
}
-static void check_and_invalidate_dcache_range
- (struct mmc_cmd *cmd,
- struct mmc_data *data) {
+static void esdhc_invalidate_dcache_range(struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
unsigned start = 0;
unsigned end = 0;
unsigned size = roundup(ARCH_DMA_MINALIGN,
@@ -377,11 +377,11 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
return err;
if (data->flags & MMC_DATA_READ)
- check_and_invalidate_dcache_range(cmd, data);
+ esdhc_invalidate_dcache_range(cmd, data);
}
/* Figure out the transfer arguments */
- xfertyp = esdhc_xfertyp(cmd, data);
+ xfertyp = esdhc_setup_xfertyp(cmd, data);
/* Mask all irqs */
esdhc_write32(®s->irqsigen, 0);
@@ -479,7 +479,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
* speculative pre-fetching etc.
*/
if (data->flags & MMC_DATA_READ) {
- check_and_invalidate_dcache_range(cmd, data);
+ esdhc_invalidate_dcache_range(cmd, data);
}
#endif
}
@@ -506,7 +506,8 @@ out:
return err;
}
-static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
+static void esdhc_set_clock(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+ uint clock)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
@@ -581,7 +582,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#endif
/* Set the clock speed */
if (priv->clock != mmc->clock)
- set_sysctl(priv, mmc, mmc->clock);
+ esdhc_set_clock(priv, mmc, mmc->clock);
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
@@ -669,43 +670,7 @@ static int esdhc_reset(struct fsl_esdhc *regs)
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int esdhc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_getcd_common(priv);
-}
-
-static int esdhc_init(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_init_common(priv, mmc);
-}
-
-static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_send_cmd_common(priv, mmc, cmd, data);
-}
-
-static int esdhc_set_ios(struct mmc *mmc)
-{
- struct fsl_esdhc_priv *priv = mmc->priv;
-
- return esdhc_set_ios_common(priv, mmc);
-}
-
-static const struct mmc_ops esdhc_ops = {
- .getcd = esdhc_getcd,
- .init = esdhc_init,
- .send_cmd = esdhc_send_cmd,
- .set_ios = esdhc_set_ios,
-};
-#endif
+static const struct mmc_ops esdhc_ops;
static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
struct fsl_esdhc_plat *plat)
@@ -728,7 +693,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
SYSCTL_IPGEN | SYSCTL_CKEN);
- writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
+ writel(ESDHC_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
#ifndef CONFIG_DM_MMC
memset(cfg, '\0', sizeof(*cfg));
@@ -738,20 +703,19 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
caps = esdhc_read32(®s->hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
- caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
- ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+ caps = caps & ~(HOSTCAPBLT2_SRS | HOSTCAPBLT2_VS18 | HOSTCAPBLT2_VS30);
#endif
/* T4240 host controller capabilities register should have VS33 bit */
#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- caps = caps | ESDHC_HOSTCAPBLT_VS33;
+ caps = caps | HOSTCAPBLT2_VS33;
#endif
- if (caps & ESDHC_HOSTCAPBLT_VS18)
+ if (caps & HOSTCAPBLT2_VS18)
voltage_caps |= MMC_VDD_165_195;
- if (caps & ESDHC_HOSTCAPBLT_VS30)
+ if (caps & HOSTCAPBLT2_VS30)
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
- if (caps & ESDHC_HOSTCAPBLT_VS33)
+ if (caps & HOSTCAPBLT2_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->name = "FSL_SDHC";
@@ -785,7 +749,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
cfg->host_caps &= ~MMC_MODE_4BIT;
}
- if (caps & ESDHC_HOSTCAPBLT_HSS)
+ if (caps & HOSTCAPBLT2_HSS)
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
@@ -801,76 +765,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
return 0;
}
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
- struct fsl_esdhc_priv *priv)
-{
- if (!cfg || !priv)
- return -EINVAL;
-
- priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
- priv->bus_width = cfg->max_bus_width;
- priv->sdhc_clk = cfg->sdhc_clk;
- priv->wp_enable = cfg->wp_enable;
-
- return 0;
-};
-
-int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
-{
- struct fsl_esdhc_plat *plat;
- struct fsl_esdhc_priv *priv;
- struct mmc *mmc;
- int ret;
-
- if (!cfg)
- return -EINVAL;
-
- priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
- if (!priv)
- return -ENOMEM;
- plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
- if (!plat) {
- free(priv);
- return -ENOMEM;
- }
-
- ret = fsl_esdhc_cfg_to_priv(cfg, priv);
- if (ret) {
- debug("%s xlate failure\n", __func__);
- free(plat);
- free(priv);
- return ret;
- }
-
- ret = fsl_esdhc_init(priv, plat);
- if (ret) {
- debug("%s init failure\n", __func__);
- free(plat);
- free(priv);
- return ret;
- }
-
- mmc = mmc_create(&plat->cfg, priv);
- if (!mmc)
- return -EIO;
-
- priv->mmc = mmc;
-
- return 0;
-}
-
-int fsl_esdhc_mmc_init(bd_t *bis)
-{
- struct fsl_esdhc_cfg *cfg;
-
- cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->arch.sdhc_clk;
- return fsl_esdhc_initialize(bis, cfg);
-}
-#endif
-
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
void mmc_adapter_card_type_ident(void)
{
@@ -944,7 +838,115 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
-#if CONFIG_IS_ENABLED(DM_MMC)
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_init_common(priv, mmc);
+}
+
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+ struct fsl_esdhc_priv *priv = mmc->priv;
+
+ return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+ .getcd = esdhc_getcd,
+ .init = esdhc_init,
+ .send_cmd = esdhc_send_cmd,
+ .set_ios = esdhc_set_ios,
+};
+
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+
+ return 0;
+};
+
+/* eSDHC initialization requiring cfg */
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+ struct fsl_esdhc_plat *plat;
+ struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
+ int ret;
+
+ if (!cfg)
+ return -EINVAL;
+
+ priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+ if (!priv)
+ return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+ if (ret) {
+ debug("%s xlate failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ ret = fsl_esdhc_init(priv, plat);
+ if (ret) {
+ debug("%s init failure\n", __func__);
+ free(plat);
+ free(priv);
+ return ret;
+ }
+
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
+ return 0;
+}
+
+/* eSDHC complete initialization */
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+ struct fsl_esdhc_cfg *cfg;
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
+ return fsl_esdhc_initialize(bis, cfg);
+}
+
+#else /* DM_MMC */
+
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
@@ -1068,13 +1070,13 @@ static int fsl_esdhc_bind(struct udevice *dev)
}
U_BOOT_DRIVER(fsl_esdhc) = {
- .name = "fsl-esdhc-mmc",
- .id = UCLASS_MMC,
- .of_match = fsl_esdhc_ids,
- .ops = &fsl_esdhc_ops,
- .bind = fsl_esdhc_bind,
- .probe = fsl_esdhc_probe,
- .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
- .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+ .name = "fsl-esdhc-mmc",
+ .id = UCLASS_MMC,
+ .of_match = fsl_esdhc_ids,
+ .ops = &fsl_esdhc_ops,
+ .bind = fsl_esdhc_bind,
+ .probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+ .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
#endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 7d7e946..e18044b 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -19,101 +19,19 @@
#include "../board/freescale/common/qixis.h"
#endif
-/* FSL eSDHC-specific constants */
-#define SYSCTL 0x0002e02c
-#define SYSCTL_INITA 0x08000000
-#define SYSCTL_TIMEOUT_MASK 0x000f0000
-#define SYSCTL_CLOCK_MASK 0x0000fff0
-#define SYSCTL_CKEN 0x00000008
-#define SYSCTL_PEREN 0x00000004
-#define SYSCTL_HCKEN 0x00000002
-#define SYSCTL_IPGEN 0x00000001
-#define SYSCTL_RSTA 0x01000000
-#define SYSCTL_RSTC 0x02000000
-#define SYSCTL_RSTD 0x04000000
-
-#define IRQSTAT 0x0002e030
-#define IRQSTAT_DMAE (0x10000000)
-#define IRQSTAT_AC12E (0x01000000)
-#define IRQSTAT_DEBE (0x00400000)
-#define IRQSTAT_DCE (0x00200000)
-#define IRQSTAT_DTOE (0x00100000)
-#define IRQSTAT_CIE (0x00080000)
-#define IRQSTAT_CEBE (0x00040000)
-#define IRQSTAT_CCE (0x00020000)
-#define IRQSTAT_CTOE (0x00010000)
-#define IRQSTAT_CINT (0x00000100)
-#define IRQSTAT_CRM (0x00000080)
-#define IRQSTAT_CINS (0x00000040)
-#define IRQSTAT_BRR (0x00000020)
-#define IRQSTAT_BWR (0x00000010)
-#define IRQSTAT_DINT (0x00000008)
-#define IRQSTAT_BGE (0x00000004)
-#define IRQSTAT_TC (0x00000002)
-#define IRQSTAT_CC (0x00000001)
-
-#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
-#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
- IRQSTAT_DMAE)
-#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
-
-#define IRQSTATEN 0x0002e034
-#define IRQSTATEN_DMAE (0x10000000)
-#define IRQSTATEN_AC12E (0x01000000)
-#define IRQSTATEN_DEBE (0x00400000)
-#define IRQSTATEN_DCE (0x00200000)
-#define IRQSTATEN_DTOE (0x00100000)
-#define IRQSTATEN_CIE (0x00080000)
-#define IRQSTATEN_CEBE (0x00040000)
-#define IRQSTATEN_CCE (0x00020000)
-#define IRQSTATEN_CTOE (0x00010000)
-#define IRQSTATEN_CINT (0x00000100)
-#define IRQSTATEN_CRM (0x00000080)
-#define IRQSTATEN_CINS (0x00000040)
-#define IRQSTATEN_BRR (0x00000020)
-#define IRQSTATEN_BWR (0x00000010)
-#define IRQSTATEN_DINT (0x00000008)
-#define IRQSTATEN_BGE (0x00000004)
-#define IRQSTATEN_TC (0x00000002)
-#define IRQSTATEN_CC (0x00000001)
-
-#define ESDHCCTL 0x0002e40c
-#define ESDHCCTL_PCS (0x00080000)
-
-#define PRSSTAT 0x0002e024
-#define PRSSTAT_DAT0 (0x01000000)
-#define PRSSTAT_CLSL (0x00800000)
-#define PRSSTAT_WPSPL (0x00080000)
-#define PRSSTAT_CDPL (0x00040000)
-#define PRSSTAT_CINS (0x00010000)
-#define PRSSTAT_BREN (0x00000800)
-#define PRSSTAT_BWEN (0x00000400)
-#define PRSSTAT_SDSTB (0X00000008)
-#define PRSSTAT_DLA (0x00000004)
-#define PRSSTAT_CICHB (0x00000002)
-#define PRSSTAT_CIDHB (0x00000001)
-
-#define PROCTL 0x0002e028
-#define PROCTL_INIT 0x00000020
-#define PROCTL_DTW_4 0x00000002
-#define PROCTL_DTW_8 0x00000004
-#define PROCTL_D3CD 0x00000008
-
-#define CMDARG 0x0002e008
-
-#define XFERTYP 0x0002e00c
+/* eSDHC_XFERTYP register: 0x0000000c */
#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
-#define XFERTYP_CMDTYP_NORMAL 0x0
-#define XFERTYP_CMDTYP_SUSPEND 0x00400000
-#define XFERTYP_CMDTYP_RESUME 0x00800000
#define XFERTYP_CMDTYP_ABORT 0x00c00000
+#define XFERTYP_CMDTYP_RESUME 0x00800000
+#define XFERTYP_CMDTYP_SUSPEND 0x00400000
+#define XFERTYP_CMDTYP_NORMAL 0x00000000
#define XFERTYP_DPSEL 0x00200000
#define XFERTYP_CICEN 0x00100000
#define XFERTYP_CCCEN 0x00080000
-#define XFERTYP_RSPTYP_NONE 0
-#define XFERTYP_RSPTYP_136 0x00010000
-#define XFERTYP_RSPTYP_48 0x00020000
#define XFERTYP_RSPTYP_48_BUSY 0x00030000
+#define XFERTYP_RSPTYP_48 0x00020000
+#define XFERTYP_RSPTYP_136 0x00010000
+#define XFERTYP_RSPTYP_NONE 0x00000000
#define XFERTYP_MSBSEL 0x00000020
#define XFERTYP_DTDSEL 0x00000010
#define XFERTYP_DDREN 0x00000008
@@ -121,20 +39,84 @@
#define XFERTYP_BCEN 0x00000002
#define XFERTYP_DMAEN 0x00000001
-#define CINS_TIMEOUT 1000
-#define PIO_TIMEOUT 500
+/* eSDHC_PRSSTAT register: 0x00000024 */
+#define PRSSTAT_DAT0 0x01000000
+#define PRSSTAT_CLSL 0x00800000
+#define PRSSTAT_WPSPL 0x00080000
+#define PRSSTAT_CDPL 0x00040000
+#define PRSSTAT_CINS 0x00010000
+#define PRSSTAT_BREN 0x00000800
+#define PRSSTAT_BWEN 0x00000400
+#define PRSSTAT_SDSTB 0X00000008
+#define PRSSTAT_DLA 0x00000004
+#define PRSSTAT_CICHB 0x00000002
+#define PRSSTAT_CIDHB 0x00000001
+
+/* eSDHC_PROCTL register: 0x00000028 */
+#define PROCTL_INIT 0x00000020
+#define PROCTL_D3CD 0x00000008
+#define PROCTL_DTW_8 0x00000004
+#define PROCTL_DTW_4 0x00000002
-#define DSADDR 0x2e004
+/* eSDHC_SYSCTL register: 0x0000002c */
+#define SYSCTL_INITA 0x08000000
+#define SYSCTL_RSTD 0x04000000
+#define SYSCTL_RSTC 0x02000000
+#define SYSCTL_RSTA 0x01000000
+#define SYSCTL_CKEN 0x00000008
+#define SYSCTL_PEREN 0x00000004
+#define SYSCTL_HCKEN 0x00000002
+#define SYSCTL_IPGEN 0x00000001
+#define SYSCTL_TIMEOUT_MASK 0x000f0000
+#define SYSCTL_CLOCK_MASK 0x0000fff0
-#define CMDRSP0 0x2e010
-#define CMDRSP1 0x2e014
-#define CMDRSP2 0x2e018
-#define CMDRSP3 0x2e01c
+/* eSDHC_IRQSTAT register: 0x00000030 */
+#define IRQSTAT_DMAE 0x10000000
+#define IRQSTAT_AC12E 0x01000000
+#define IRQSTAT_DEBE 0x00400000
+#define IRQSTAT_DCE 0x00200000
+#define IRQSTAT_DTOE 0x00100000
+#define IRQSTAT_CIE 0x00080000
+#define IRQSTAT_CEBE 0x00040000
+#define IRQSTAT_CCE 0x00020000
+#define IRQSTAT_CTOE 0x00010000
+#define IRQSTAT_CINT 0x00000100
+#define IRQSTAT_CRM 0x00000080
+#define IRQSTAT_CINS 0x00000040
+#define IRQSTAT_BRR 0x00000020
+#define IRQSTAT_BWR 0x00000010
+#define IRQSTAT_DINT 0x00000008
+#define IRQSTAT_BGE 0x00000004
+#define IRQSTAT_TC 0x00000002
+#define IRQSTAT_CC 0x00000001
-#define DATPORT 0x2e020
+#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+ IRQSTAT_DMAE)
+#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
-#define WML 0x2e044
-#define WML_WRITE 0x00010000
+/* eSDHC_IRQSTATEN register: 0x00000034 */
+#define IRQSTATEN_DMAE 0x10000000
+#define IRQSTATEN_AC12E 0x01000000
+#define IRQSTATEN_DEBE 0x00400000
+#define IRQSTATEN_DCE 0x00200000
+#define IRQSTATEN_DTOE 0x00100000
+#define IRQSTATEN_CIE 0x00080000
+#define IRQSTATEN_CEBE 0x00040000
+#define IRQSTATEN_CCE 0x00020000
+#define IRQSTATEN_CTOE 0x00010000
+#define IRQSTATEN_CINT 0x00000100
+#define IRQSTATEN_CRM 0x00000080
+#define IRQSTATEN_CINS 0x00000040
+#define IRQSTATEN_BRR 0x00000020
+#define IRQSTATEN_BWR 0x00000010
+#define IRQSTATEN_DINT 0x00000008
+#define IRQSTATEN_BGE 0x00000004
+#define IRQSTATEN_TC 0x00000002
+#define IRQSTATEN_CC 0x00000001
+
+/* eSDHC_WML register: 0x00000044 */
+#define WML_WRITE 0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
#define WML_RD_WML_MAX 0x80
#define WML_WR_WML_MAX 0x80
@@ -151,17 +133,18 @@
#define WML_WR_WML_MASK 0xff0000
#endif
-#define BLKATTR 0x2e004
-#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
-#define BLKATTR_SIZE(x) (x & 0x1fff)
-#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
+/* eSDHC_HOSTCAPBLT2 register: 0x00000114 */
+#define HOSTCAPBLT2_VS18 0x04000000
+#define HOSTCAPBLT2_VS30 0x02000000
+#define HOSTCAPBLT2_VS33 0x01000000
+#define HOSTCAPBLT2_SRS 0x00800000
+#define HOSTCAPBLT2_DMAS 0x00400000
+#define HOSTCAPBLT2_HSS 0x00200000
+
+/* eSDHC_ESDHCCTL register: 0x0000040c */
+#define ESDHCCTL_PCS 0x00080000
-#define ESDHC_HOSTCAPBLT_VS18 0x04000000
-#define ESDHC_HOSTCAPBLT_VS30 0x02000000
-#define ESDHC_HOSTCAPBLT_VS33 0x01000000
-#define ESDHC_HOSTCAPBLT_SRS 0x00800000
-#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
-#define ESDHC_HOSTCAPBLT_HSS 0x00200000
+#define PIO_TIMEOUT 500
struct fsl_esdhc_cfg {
phys_addr_t esdhc_base;
@@ -173,7 +156,7 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if defined CONFIG_SYS_FSL_ESDHC_LE
+#if defined(CONFIG_SYS_FSL_ESDHC_LE)
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/3] mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
2019-08-19 8:27 [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code Yangbo Lu
@ 2019-08-19 8:27 ` Yangbo Lu
2019-09-04 4:22 ` [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Y.b. Lu
3 siblings, 0 replies; 10+ messages in thread
From: Yangbo Lu @ 2019-08-19 8:27 UTC (permalink / raw)
To: u-boot
For non-DM code, below functions had similar names.
- fsl_esdhc_initialize
- fsl_esdhc_mmc_init
- fsl_esdhc_init
However fsl_esdhc_init was mainly used to get cfg. So rename it
to fsl_esdhc_get_cfg. Fix up bus-width capability handling, and
drop controller initialization because it will be re-initialized
in later esdhc_init_common for DM or esdhc_init for non-DM when use
it.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/mmc/fsl_esdhc.c | 68 ++++++++-----------------------------------------
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d176bb3..bdf5b14 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -25,14 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ESDHC_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
- IRQSTATEN_DINT | IRQSTATEN_BWR | \
- IRQSTATEN_BRR | IRQSTATEN_CINT | \
- IRQSTATEN_CTOE | IRQSTATEN_CCE | \
- IRQSTATEN_CEBE | IRQSTATEN_CIE | \
- IRQSTATEN_DTOE | IRQSTATEN_DCE | \
- IRQSTATEN_DEBE)
-
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
uint blkattr; /* Block attributes register */
@@ -651,55 +643,23 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
return timeout > 0;
}
-static int esdhc_reset(struct fsl_esdhc *regs)
-{
- ulong start;
-
- /* reset the controller */
- esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
-
- /* hardware clears the bit when it is done */
- start = get_timer(0);
- while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
- if (get_timer(start) > 100) {
- printf("MMC/SD: Reset never completed.\n");
- return -ETIMEDOUT;
- }
- }
-
- return 0;
-}
-
static const struct mmc_ops esdhc_ops;
-static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
- struct fsl_esdhc_plat *plat)
+static int fsl_esdhc_get_cfg(struct fsl_esdhc_priv *priv,
+ struct fsl_esdhc_plat *plat)
{
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ u32 caps, voltage_caps = 0;
struct mmc_config *cfg;
- struct fsl_esdhc *regs;
- u32 caps, voltage_caps;
- int ret;
if (!priv)
return -EINVAL;
- regs = priv->esdhc_regs;
-
- /* First reset the eSDHC controller */
- ret = esdhc_reset(regs);
- if (ret)
- return ret;
-
- esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
- SYSCTL_IPGEN | SYSCTL_CKEN);
-
- writel(ESDHC_IRQ_EN_BITS, ®s->irqstaten);
cfg = &plat->cfg;
#ifndef CONFIG_DM_MMC
memset(cfg, '\0', sizeof(*cfg));
#endif
- voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
@@ -737,18 +697,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
else if (priv->bus_width == 4)
cfg->host_caps = MMC_MODE_4BIT;
- cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
cfg->host_caps |= MMC_MODE_DDR_52MHz;
#endif
- if (priv->bus_width > 0) {
- if (priv->bus_width < 8)
- cfg->host_caps &= ~MMC_MODE_8BIT;
- if (priv->bus_width < 4)
- cfg->host_caps &= ~MMC_MODE_4BIT;
- }
-
if (caps & HOSTCAPBLT2_HSS)
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
@@ -759,7 +711,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
cfg->f_min = 400000;
cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
-
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
return 0;
@@ -882,7 +833,10 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
return -EINVAL;
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
- priv->bus_width = cfg->max_bus_width;
+ if (cfg->max_bus_width)
+ priv->bus_width = cfg->max_bus_width;
+ else
+ priv->bus_width = 4;
priv->sdhc_clk = cfg->sdhc_clk;
priv->wp_enable = cfg->wp_enable;
@@ -917,7 +871,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
return ret;
}
- ret = fsl_esdhc_init(priv, plat);
+ ret = fsl_esdhc_get_cfg(priv, plat);
if (ret) {
debug("%s init failure\n", __func__);
free(plat);
@@ -1012,9 +966,9 @@ static int fsl_esdhc_probe(struct udevice *dev)
}
}
- ret = fsl_esdhc_init(priv, plat);
+ ret = fsl_esdhc_get_cfg(priv, plat);
if (ret) {
- dev_err(dev, "fsl_esdhc_init failure\n");
+ dev_err(dev, "fsl_esdhc_get_cfg failure\n");
return ret;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
2019-08-19 8:27 ` [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code Yangbo Lu
@ 2019-08-23 8:44 ` Lukasz Majewski
2019-09-03 3:31 ` Y.b. Lu
0 siblings, 1 reply; 10+ messages in thread
From: Lukasz Majewski @ 2019-08-23 8:44 UTC (permalink / raw)
To: u-boot
On Mon, 19 Aug 2019 16:27:49 +0800
Yangbo Lu <yangbo.lu@nxp.com> wrote:
> /* Return the XFERTYP flags for a given command and data packet */
> -static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
> +static uint esdhc_setup_xfertyp(struct mmc_cmd *cmd, struct mmc_data
> *data) {
> uint xfertyp = 0;
>
> @@ -310,9 +310,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> *priv, struct mmc *mmc, return 0;
> }
>
> -static void check_and_invalidate_dcache_range
> - (struct mmc_cmd *cmd,
> - struct mmc_data *data) {
> +static void esdhc_invalidate_dcache_range(struct mmc_cmd *cmd,
> + struct mmc_data *data)
^^^^ - it shall be aligned
with the (
Could you double check this patch set with ./tools/checkpatch.py if it
is clean?
(You can also test tools/patman - which does automatic checkpatch check)
> +{
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 488 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20190823/5ec66c0b/attachment.sig>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
2019-08-23 8:44 ` Lukasz Majewski
@ 2019-09-03 3:31 ` Y.b. Lu
0 siblings, 0 replies; 10+ messages in thread
From: Y.b. Lu @ 2019-09-03 3:31 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
Sorry for my late response. Please see my comments inline.
> -----Original Message-----
> From: Lukasz Majewski <lukma@denx.de>
> Sent: Friday, August 23, 2019 4:45 PM
> To: Y.b. Lu <yangbo.lu@nxp.com>
> Cc: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com>
> Subject: Re: [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code
>
> On Mon, 19 Aug 2019 16:27:49 +0800
> Yangbo Lu <yangbo.lu@nxp.com> wrote:
>
> > /* Return the XFERTYP flags for a given command and data packet */
> > -static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
> > +static uint esdhc_setup_xfertyp(struct mmc_cmd *cmd, struct mmc_data
> > *data) {
> > uint xfertyp = 0;
> >
> > @@ -310,9 +310,9 @@ static int esdhc_setup_data(struct fsl_esdhc_priv
> > *priv, struct mmc *mmc, return 0;
> > }
> >
> > -static void check_and_invalidate_dcache_range
> > - (struct mmc_cmd *cmd,
> > - struct mmc_data *data) {
> > +static void esdhc_invalidate_dcache_range(struct mmc_cmd *cmd,
> > + struct mmc_data *data)
> ^^^^ - it shall be aligned
> with the (
[Y.b. Lu] Although it's not aligned with the ( in email, it's aligned after applying the patch.
I believe there is no issue, and the checkpatch passed before I sent out the patches.
Thanks.
>
> Could you double check this patch set with ./tools/checkpatch.py if it
> is clean?
>
> (You can also test tools/patman - which does automatic checkpatch check)
>
> > +{
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
2019-08-19 8:27 [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Yangbo Lu
` (2 preceding siblings ...)
2019-08-19 8:27 ` [U-Boot] [PATCH 3/3] mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg Yangbo Lu
@ 2019-09-04 4:22 ` Y.b. Lu
2019-09-04 7:52 ` Peng Fan
2019-09-06 2:12 ` Peng Fan
3 siblings, 2 replies; 10+ messages in thread
From: Y.b. Lu @ 2019-09-04 4:22 UTC (permalink / raw)
To: u-boot
Any comments?
Thanks:)
> -----Original Message-----
> From: Yangbo Lu <yangbo.lu@nxp.com>
> Sent: Monday, August 19, 2019 4:28 PM
> To: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com>
> Cc: Y.b. Lu <yangbo.lu@nxp.com>
> Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code
>
> This patch-set is to clean up fsl_esdhc code.
>
> Yangbo Lu (3):
> mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
> mmc: fsl_esdhc: clean up code
> mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
>
> drivers/mmc/fsl_esdhc.c | 371 +++++++++++++++++++-----------------------------
> include/fsl_esdhc.h | 203 ++++++++++++--------------
> 2 files changed, 240 insertions(+), 334 deletions(-)
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
2019-09-04 4:22 ` [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Y.b. Lu
@ 2019-09-04 7:52 ` Peng Fan
2019-09-06 2:12 ` Peng Fan
1 sibling, 0 replies; 10+ messages in thread
From: Peng Fan @ 2019-09-04 7:52 UTC (permalink / raw)
To: u-boot
> Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code
>
> Any comments?
I'll pick up.
Regards,
Peng.
> Thanks:)
>
> > -----Original Message-----
> > From: Yangbo Lu <yangbo.lu@nxp.com>
> > Sent: Monday, August 19, 2019 4:28 PM
> > To: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com>
> > Cc: Y.b. Lu <yangbo.lu@nxp.com>
> > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code
> >
> > This patch-set is to clean up fsl_esdhc code.
> >
> > Yangbo Lu (3):
> > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
> > mmc: fsl_esdhc: clean up code
> > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
> >
> > drivers/mmc/fsl_esdhc.c | 371
> +++++++++++++++++++-----------------------------
> > include/fsl_esdhc.h | 203 ++++++++++++--------------
> > 2 files changed, 240 insertions(+), 334 deletions(-)
> >
> > --
> > 2.7.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
2019-09-04 4:22 ` [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Y.b. Lu
2019-09-04 7:52 ` Peng Fan
@ 2019-09-06 2:12 ` Peng Fan
2019-09-06 6:02 ` Y.b. Lu
1 sibling, 1 reply; 10+ messages in thread
From: Peng Fan @ 2019-09-06 2:12 UTC (permalink / raw)
To: u-boot
> Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code
>
> Any comments?
Patchset break build https://travis-ci.org/MrVan/u-boot/jobs/581073165
Please take a look.
Regards,
Peng.
> Thanks:)
>
> > -----Original Message-----
> > From: Yangbo Lu <yangbo.lu@nxp.com>
> > Sent: Monday, August 19, 2019 4:28 PM
> > To: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com>
> > Cc: Y.b. Lu <yangbo.lu@nxp.com>
> > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code
> >
> > This patch-set is to clean up fsl_esdhc code.
> >
> > Yangbo Lu (3):
> > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
> > mmc: fsl_esdhc: clean up code
> > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
> >
> > drivers/mmc/fsl_esdhc.c | 371
> +++++++++++++++++++-----------------------------
> > include/fsl_esdhc.h | 203 ++++++++++++--------------
> > 2 files changed, 240 insertions(+), 334 deletions(-)
> >
> > --
> > 2.7.4
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code
2019-09-06 2:12 ` Peng Fan
@ 2019-09-06 6:02 ` Y.b. Lu
0 siblings, 0 replies; 10+ messages in thread
From: Y.b. Lu @ 2019-09-06 6:02 UTC (permalink / raw)
To: u-boot
Hi Peng,
> -----Original Message-----
> From: Peng Fan
> Sent: Friday, September 6, 2019 10:12 AM
> To: Y.b. Lu <yangbo.lu@nxp.com>; u-boot at lists.denx.de
> Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code
>
> > Subject: RE: [PATCH 0/3] mmc: fsl_esdhc: clean up code
> >
> > Any comments?
>
> Patchset break build https://travis-ci.org/MrVan/u-boot/jobs/581073165
>
> Please take a look.
[Y.b. Lu] Sorry. I hadn't seen this issue with my toolchain. I have reproduced with buildman.
Let me send out v2 patch-set. The esdhc_ops declaration should be involved in non-DM conditional build.
Thanks.
>
> Regards,
> Peng.
>
> > Thanks:)
> >
> > > -----Original Message-----
> > > From: Yangbo Lu <yangbo.lu@nxp.com>
> > > Sent: Monday, August 19, 2019 4:28 PM
> > > To: u-boot at lists.denx.de; Peng Fan <peng.fan@nxp.com>
> > > Cc: Y.b. Lu <yangbo.lu@nxp.com>
> > > Subject: [PATCH 0/3] mmc: fsl_esdhc: clean up code
> > >
> > > This patch-set is to clean up fsl_esdhc code.
> > >
> > > Yangbo Lu (3):
> > > mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
> > > mmc: fsl_esdhc: clean up code
> > > mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg
> > >
> > > drivers/mmc/fsl_esdhc.c | 371
> > +++++++++++++++++++-----------------------------
> > > include/fsl_esdhc.h | 203 ++++++++++++--------------
> > > 2 files changed, 240 insertions(+), 334 deletions(-)
> > >
> > > --
> > > 2.7.4
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-09-06 6:02 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-19 8:27 [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 1/3] mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC Yangbo Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 2/3] mmc: fsl_esdhc: clean up code Yangbo Lu
2019-08-23 8:44 ` Lukasz Majewski
2019-09-03 3:31 ` Y.b. Lu
2019-08-19 8:27 ` [U-Boot] [PATCH 3/3] mmc: fsl_esdhc: rename fsl_esdhc_init to fsl_esdhc_get_cfg Yangbo Lu
2019-09-04 4:22 ` [U-Boot] [PATCH 0/3] mmc: fsl_esdhc: clean up code Y.b. Lu
2019-09-04 7:52 ` Peng Fan
2019-09-06 2:12 ` Peng Fan
2019-09-06 6:02 ` Y.b. Lu
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.