* [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines
@ 2019-10-17 9:21 Laurentiu Tudor
2019-10-17 9:21 ` [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Laurentiu Tudor @ 2019-10-17 9:21 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index d9d125e8ba..9462298fbf 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
index 49e27553b1..23743ae10c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
@@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor @ 2019-10-17 9:21 ` Laurentiu Tudor 2019-10-18 6:32 ` Horia Geanta 2019-10-17 9:21 ` [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor ` (4 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-17 9:21 UTC (permalink / raw) To: u-boot From: Laurentiu Tudor <laurentiu.tudor@nxp.com> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this compilation error happens: arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by adding an intermediate macro to handle the problem. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 37e2fe4e66..398bb4eb86 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -164,9 +164,15 @@ extern int fman_icid_tbl_sz; QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR, QDMA_IS_LE) +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define SEC_FW_SUPPORT CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#else +#define SEC_FW_SUPPORT 0 +#endif + #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ + (SEC_FW_SUPPORT && \ (FSL_SEC_JR##jr_num##_OFFSET == \ SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ ? NULL \ -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled 2019-10-17 9:21 ` [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor @ 2019-10-18 6:32 ` Horia Geanta 2019-10-18 7:25 ` Laurentiu Tudor 0 siblings, 1 reply; 15+ messages in thread From: Horia Geanta @ 2019-10-18 6:32 UTC (permalink / raw) To: u-boot On 10/17/2019 12:21 PM, Laurentiu Tudor wrote: > From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > > If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this > compilation error happens: > arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: > 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) > > Fix it by adding an intermediate macro to handle the problem. > > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> > --- > arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h > index 37e2fe4e66..398bb4eb86 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h > @@ -164,9 +164,15 @@ extern int fman_icid_tbl_sz; > QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ > QDMA_BASE_ADDR, QDMA_IS_LE) > > +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT > +#define SEC_FW_SUPPORT CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT > +#else > +#define SEC_FW_SUPPORT 0 > +#endif > + > #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ > SET_ICID_ENTRY( \ > - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ > + (SEC_FW_SUPPORT && \ > (FSL_SEC_JR##jr_num##_OFFSET == \ > SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ > ? NULL \ > How about using CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) instead of CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT? This would also account for CONFIG_SPL_ARMV8_SEC_FIRMWARE_SUPPORT. Horia ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled 2019-10-18 6:32 ` Horia Geanta @ 2019-10-18 7:25 ` Laurentiu Tudor 0 siblings, 0 replies; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-18 7:25 UTC (permalink / raw) To: u-boot On 18.10.2019 09:32, Horia Geanta wrote: > On 10/17/2019 12:21 PM, Laurentiu Tudor wrote: >> From: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> >> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this >> compilation error happens: >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: >> 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) >> >> Fix it by adding an intermediate macro to handle the problem. >> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> --- >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> index 37e2fe4e66..398bb4eb86 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h >> @@ -164,9 +164,15 @@ extern int fman_icid_tbl_sz; >> QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ >> QDMA_BASE_ADDR, QDMA_IS_LE) >> >> +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT >> +#define SEC_FW_SUPPORT CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT >> +#else >> +#define SEC_FW_SUPPORT 0 >> +#endif >> + >> #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ >> SET_ICID_ENTRY( \ >> - (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ >> + (SEC_FW_SUPPORT && \ >> (FSL_SEC_JR##jr_num##_OFFSET == \ >> SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ >> ? NULL \ >> > How about using CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) instead of > CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT? > That's pretty cool, didn't new about it. Sure I'll use it. --- Thanks & Best Regards, Laurentiu ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor 2019-10-17 9:21 ` [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor @ 2019-10-17 9:21 ` Laurentiu Tudor 2019-10-18 6:41 ` Horia Geanta 2019-10-17 9:22 ` [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor ` (3 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-17 9:21 UTC (permalink / raw) To: u-boot From: Laurentiu Tudor <laurentiu.tudor@nxp.com> Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 33 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +- board/freescale/ls2080aqds/ls2080aqds.c | 3 ++ board/freescale/ls2080ardb/ls2080ardb.c | 3 ++ 5 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index efecbc07e7..f00ef817b1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -28,6 +28,7 @@ endif ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o +obj-y += icid.o ls2088_ids.o endif ifneq ($(CONFIG_ARCH_LS1043A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c new file mode 100644 index 0000000000..9556e93de9 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3fd34e3a43..924f5f3fe8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif -#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ + defined(CONFIG_ARCH_LS2080A) set_icids(); #endif } diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 91c80353ed..25e80c8ac6 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -20,6 +20,7 @@ #include <hwconfig.h> #include <fsl_sec.h> #include <asm/arch/ppa.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #include "../common/qixis.h" @@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + return 0; } #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index e20267f27c..6a1b8e3f53 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -22,6 +22,7 @@ #include <asm/arch/soc.h> #include <asm/arch/ppa.h> #include <fsl_sec.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" @@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); + return 0; } #endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices 2019-10-17 9:21 ` [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor @ 2019-10-18 6:41 ` Horia Geanta 0 siblings, 0 replies; 15+ messages in thread From: Horia Geanta @ 2019-10-18 6:41 UTC (permalink / raw) To: u-boot On 10/17/2019 12:22 PM, Laurentiu Tudor wrote: > +struct icid_id_table icid_tbl[] = { > + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), > + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), > + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), > + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID), > + SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID), > +#ifdef CONFIG_FSL_CAAM > + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), > + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), > + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), > + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), > + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), > + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), > + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), > + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), > + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), > + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), > + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), > + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), > +#endif The crypto engine on ls2088a has 6 DECOs. Horia ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor 2019-10-17 9:21 ` [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor 2019-10-17 9:21 ` [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor @ 2019-10-17 9:22 ` Laurentiu Tudor 2019-10-18 6:22 ` [U-Boot] [u-boot] " Priyanka Jain 2019-10-17 9:22 ` [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-17 9:22 UTC (permalink / raw) To: u-boot From: Laurentiu Tudor <laurentiu.tudor@nxp.com> There are chips that have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..0e4bf331fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [u-boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses 2019-10-17 9:22 ` [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor @ 2019-10-18 6:22 ` Priyanka Jain 0 siblings, 0 replies; 15+ messages in thread From: Priyanka Jain @ 2019-10-18 6:22 UTC (permalink / raw) To: u-boot >-----Original Message----- From: u-boot-bounces@linux.nxdi.nxp.com <u-boot- >bounces at linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >Sent: Thursday, October 17, 2019 2:52 PM >To: u-boot at lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >Subject: [u-boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and >SATA4 base addresses Is "missing" string required in subject? > >From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > >There are chips that have 4 sata controllers. Add missing base addresses for >SATA3 and SATA4. > Which chips? Please mention >Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >--- <snip> --priyankajain ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor ` (2 preceding siblings ...) 2019-10-17 9:22 ` [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor @ 2019-10-17 9:22 ` Laurentiu Tudor 2019-10-18 6:20 ` [U-Boot] [u-boot] " Priyanka Jain 2019-10-18 8:10 ` [U-Boot] " Horia Geanta 2019-10-17 9:22 ` [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround Laurentiu Tudor 2019-10-18 6:07 ` [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Horia Geanta 5 siblings, 2 replies; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-17 9:22 UTC (permalink / raw) To: u-boot From: Laurentiu Tudor <laurentiu.tudor@nxp.com> Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + board/freescale/lx2160a/lx2160a.c | 2 + include/fsl_sec.h | 3 +- 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index f00ef817b1..e398aecd12 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -24,6 +24,7 @@ endif ifneq ($(CONFIG_ARCH_LX2160A),) obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +obj-y += icid.o lx2160_ids.o endif ifneq ($(CONFIG_ARCH_LS2080A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c new file mode 100644 index 0000000000..3a0ed1fa55 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> + +struct icid_id_table icid_tbl[] = { + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 924f5f3fe8..4dea8361fc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ - defined(CONFIG_ARCH_LS2080A) + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0e4bf331fd..f86835a33d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -447,7 +447,9 @@ struct ccsr_gur { u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; - u8 res_558[0x570-0x558]; /* add more registers when needed */ + u32 sata3_amqr; + u32 sata4_amqr; + u8 res_558[0x570 - 0x560]; /* add more registers when needed */ u32 misc1_amqr; u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 93bdcc4caa..0b36416ad3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -108,5 +108,7 @@ #define FSL_EDMA_STREAM_ID 70 #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 +#define FSL_SATA3_STREAM_ID 73 +#define FSL_SATA4_STREAM_ID 74 #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index b509c0312e..eff12747b4 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -27,6 +27,7 @@ #include "../common/qixis.h" #include "../common/vid.h" #include <fsl_immap.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" @@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fsl_mc_fixup_iommu_map_entry(blob); fdt_fixup_board_enet(blob); #endif + fdt_fixup_icid(blob); return 0; } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index be08a2b88b..c0d2c7e866 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -93,8 +93,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* DECO LIODN Register, MS */ u32 ls; /* DECO LIODN Register, LS */ - } decoliodnr[8]; - u8 res4[0x40]; + } decoliodnr[16]; u32 dar; /* DECO Avail Register */ u32 drr; /* DECO Reset Register */ u8 res5[0x4d8]; -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices 2019-10-17 9:22 ` [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor @ 2019-10-18 6:20 ` Priyanka Jain 2019-10-18 7:29 ` Laurentiu Tudor 2019-10-18 8:10 ` [U-Boot] " Horia Geanta 1 sibling, 1 reply; 15+ messages in thread From: Priyanka Jain @ 2019-10-18 6:20 UTC (permalink / raw) To: u-boot >-----Original Message----- From: u-boot-bounces@linux.nxdi.nxp.com <u-boot- >bounces at linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >Sent: Thursday, October 17, 2019 2:52 PM >To: u-boot at lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform >devices > >From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > >Add ICID setup for the platform devices contained on this chip: usb, sata, >sdhc, sec. > >Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >--- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + > .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- > .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + > board/freescale/lx2160a/lx2160a.c | 2 + > include/fsl_sec.h | 3 +- > 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 >arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c > >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >index f00ef817b1..e398aecd12 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >@@ -24,6 +24,7 @@ endif > > ifneq ($(CONFIG_ARCH_LX2160A),) > obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o >+obj-y += icid.o lx2160_ids.o > endif > > ifneq ($(CONFIG_ARCH_LS2080A),) >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >new file mode 100644 >index 0000000000..3a0ed1fa55 >--- /dev/null >+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >@@ -0,0 +1,48 @@ >+// SPDX-License-Identifier: GPL-2.0+ >+/* >+ * Copyright 2019 NXP >+ */ >+ >+#include <common.h> >+#include <asm/arch-fsl-layerscape/immap_lsch3.h> >+#include <asm/arch-fsl-layerscape/fsl_icid.h> >+#include <asm/arch-fsl-layerscape/fsl_portals.h> >+ >+struct icid_id_table icid_tbl[] = { >+ SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), >+ SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), >+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), >+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), >+ SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), >+ SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), >+ SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), >+ SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef >+CONFIG_FSL_CAAM >+ SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), >+ SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), >+ SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif }; >+ >+int icid_tbl_sz = ARRAY_SIZE(icid_tbl); >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >index 924f5f3fe8..4dea8361fc 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >@@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif > > #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ >- defined(CONFIG_ARCH_LS2080A) >+ defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) > set_icids(); > #endif > } >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >index 0e4bf331fd..f86835a33d 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >@@ -447,7 +447,9 @@ struct ccsr_gur { > u8 res_538[0x550 - 0x538]; /* add more registers when needed */ > u32 sata1_amqr; > u32 sata2_amqr; >- u8 res_558[0x570-0x558]; /* add more registers when needed */ >+ u32 sata3_amqr; >+ u32 sata4_amqr; >+ u8 res_558[0x570 - 0x560]; /* add more registers when needed */ This will change the byte position for below variables. Please confirm that you have cross-checked and tested this update for all lsch3 SoC > u32 misc1_amqr; > u8 res_574[0x590-0x574]; /* add more registers when needed */ > u32 spare1_amqr; >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >index 93bdcc4caa..0b36416ad3 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >@@ -108,5 +108,7 @@ > #define FSL_EDMA_STREAM_ID 70 > #define FSL_GPU_STREAM_ID 71 > #define FSL_DISPLAY_STREAM_ID 72 >+#define FSL_SATA3_STREAM_ID 73 >+#define FSL_SATA4_STREAM_ID 74 > > #endif >diff --git a/board/freescale/lx2160a/lx2160a.c >b/board/freescale/lx2160a/lx2160a.c >index b509c0312e..eff12747b4 100644 >--- a/board/freescale/lx2160a/lx2160a.c >+++ b/board/freescale/lx2160a/lx2160a.c >@@ -27,6 +27,7 @@ > #include "../common/qixis.h" > #include "../common/vid.h" > #include <fsl_immap.h> >+#include <asm/arch-fsl-layerscape/fsl_icid.h> > > #ifdef CONFIG_EMC2305 > #include "../common/emc2305.h" >@@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd) > fdt_fsl_mc_fixup_iommu_map_entry(blob); > fdt_fixup_board_enet(blob); > #endif >+ fdt_fixup_icid(blob); > > return 0; > } >diff --git a/include/fsl_sec.h b/include/fsl_sec.h index >be08a2b88b..c0d2c7e866 100644 >--- a/include/fsl_sec.h >+++ b/include/fsl_sec.h >@@ -93,8 +93,7 @@ typedef struct ccsr_sec { > struct { > u32 ms; /* DECO LIODN Register, MS */ > u32 ls; /* DECO LIODN Register, LS */ >- } decoliodnr[8]; >- u8 res4[0x40]; >+ } decoliodnr[16]; > u32 dar; /* DECO Avail Register */ > u32 drr; /* DECO Reset Register */ > u8 res5[0x4d8]; >-- >2.17.1 > >_______________________________________________ >u-boot mailing list >u-boot at linux.nxdi.nxp.com >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flinux.nx >di.nxp.com%2Fmailman%2Flistinfo%2Fu- >boot&data=02%7C01%7Cpriyanka.jain%40nxp.com%7C156db694a8db47 >894e7708d752e37b7e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C >637069009296949567&sdata=7qWllov0N5cxFDtlJfjLQJu35aM2jYZfKN0nf2 >hYkdQ%3D&reserved=0 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices 2019-10-18 6:20 ` [U-Boot] [u-boot] " Priyanka Jain @ 2019-10-18 7:29 ` Laurentiu Tudor 0 siblings, 0 replies; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-18 7:29 UTC (permalink / raw) To: u-boot On 18.10.2019 09:20, Priyanka Jain wrote: > > >> -----Original Message----- >> From: u-boot-bounces at linux.nxdi.nxp.com <u-boot- >> bounces at linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >> Sent: Thursday, October 17, 2019 2:52 PM >> To: u-boot at lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >> Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform >> devices >> >> From: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> >> Add ICID setup for the platform devices contained on this chip: usb, sata, >> sdhc, sec. >> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >> --- >> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + >> .../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++++++++++++++++++ >> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- >> .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- >> .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 2 + >> board/freescale/lx2160a/lx2160a.c | 2 + >> include/fsl_sec.h | 3 +- >> 7 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 >> arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> index f00ef817b1..e398aecd12 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile >> @@ -24,6 +24,7 @@ endif >> >> ifneq ($(CONFIG_ARCH_LX2160A),) >> obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o >> +obj-y += icid.o lx2160_ids.o >> endif >> >> ifneq ($(CONFIG_ARCH_LS2080A),) >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> new file mode 100644 >> index 0000000000..3a0ed1fa55 >> --- /dev/null >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c >> @@ -0,0 +1,48 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Copyright 2019 NXP >> + */ >> + >> +#include <common.h> >> +#include <asm/arch-fsl-layerscape/immap_lsch3.h> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h> >> +#include <asm/arch-fsl-layerscape/fsl_portals.h> >> + >> +struct icid_id_table icid_tbl[] = { >> + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), >> + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), >> + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), >> + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), >> + SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID), >> + SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID), >> + SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID), >> + SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID), #ifdef >> +CONFIG_FSL_CAAM >> + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), >> + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >> + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID), >> + SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID), #endif }; >> + >> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> index 924f5f3fe8..4dea8361fc 100644 >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c >> @@ -342,7 +342,7 @@ void fsl_lsch3_early_init_f(void) #endif >> >> #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ >> - defined(CONFIG_ARCH_LS2080A) >> + defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) >> set_icids(); >> #endif >> } >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> index 0e4bf331fd..f86835a33d 100644 >> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h >> @@ -447,7 +447,9 @@ struct ccsr_gur { >> u8 res_538[0x550 - 0x538]; /* add more registers when needed */ >> u32 sata1_amqr; >> u32 sata2_amqr; >> - u8 res_558[0x570-0x558]; /* add more registers when needed */ >> + u32 sata3_amqr; >> + u32 sata4_amqr; >> + u8 res_558[0x570 - 0x560]; /* add more registers when needed */ > This will change the byte position for below variables. > Please confirm that you have cross-checked and tested this update for all lsch3 SoC I'm adding 8 bytes but adjusting the res_558 (which btw, I should rename it to res_560) by subtracting the previously added 8 bytes, so things should align properly as before. --- Best Regards, Laurentiu ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices 2019-10-17 9:22 ` [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor 2019-10-18 6:20 ` [U-Boot] [u-boot] " Priyanka Jain @ 2019-10-18 8:10 ` Horia Geanta 1 sibling, 0 replies; 15+ messages in thread From: Horia Geanta @ 2019-10-18 8:10 UTC (permalink / raw) To: u-boot On 10/17/2019 12:22 PM, Laurentiu Tudor wrote: > From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > > Add ICID setup for the platform devices contained on this chip: usb, > sata, sdhc, sec. > > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Thanks, Horia ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor ` (3 preceding siblings ...) 2019-10-17 9:22 ` [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor @ 2019-10-17 9:22 ` Laurentiu Tudor 2019-10-18 6:27 ` Priyanka Jain 2019-10-18 6:07 ` [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Horia Geanta 5 siblings, 1 reply; 15+ messages in thread From: Laurentiu Tudor @ 2019-10-17 9:22 UTC (permalink / raw) To: u-boot From: Laurentiu Tudor <laurentiu.tudor@nxp.com> Description: The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not correctly forwarded to the SMMU. Workaround: Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 24c606a232..046dcf539e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT + select SYS_FSL_ERRATUM_A050382 imply PANIC_HANG config ARCH_LS1043A @@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A050382 + bool config SYS_FSL_HAS_RGMII bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 0b36416ad3..4c9e1e72f0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -105,7 +105,22 @@ #define FSL_SEC_JR4_STREAM_ID 68 #define FSL_SDMMC2_STREAM_ID 69 + +/* + * Erratum A050382 workaround + * + * Description: + * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not + * correctly forwarded to the SMMU. + * Workaround: + * Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 +#define FSL_EDMA_STREAM_ID 40 +#else #define FSL_EDMA_STREAM_ID 70 +#endif + #define FSL_GPU_STREAM_ID 71 #define FSL_DISPLAY_STREAM_ID 72 #define FSL_SATA3_STREAM_ID 73 -- 2.17.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround 2019-10-17 9:22 ` [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround Laurentiu Tudor @ 2019-10-18 6:27 ` Priyanka Jain 0 siblings, 0 replies; 15+ messages in thread From: Priyanka Jain @ 2019-10-18 6:27 UTC (permalink / raw) To: u-boot >-----Original Message----- From: u-boot-bounces@linux.nxdi.nxp.com <u-boot- >bounces at linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor >Sent: Thursday, October 17, 2019 2:52 PM >To: u-boot at lists.denx.de; Prabhakar X <prabhakar.kushwaha@nxp.com> >Subject: [u-boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround "Add erratum" > >From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > >Description: Whose description? Please reword to something like "erratum A050382 states that " > The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not > correctly forwarded to the SMMU. >Workaround: > Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. > >Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> >--- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 15 +++++++++++++++ > 2 files changed, 18 insertions(+) > >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >index 24c606a232..046dcf539e 100644 >--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig >@@ -45,6 +45,7 @@ config ARCH_LS1028A > select SYS_FSL_ERRATUM_A008514 if !TFABOOT > select SYS_FSL_ERRATUM_A009663 if !TFABOOT > select SYS_FSL_ERRATUM_A009942 if !TFABOOT >+ select SYS_FSL_ERRATUM_A050382 > imply PANIC_HANG > > config ARCH_LS1043A >@@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660 config >SYS_FSL_ERRATUM_A009929 > bool > >+config SYS_FSL_ERRATUM_A050382 >+ bool > > config SYS_FSL_HAS_RGMII > bool >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >index 0b36416ad3..4c9e1e72f0 100644 >--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h >@@ -105,7 +105,22 @@ > #define FSL_SEC_JR4_STREAM_ID 68 > > #define FSL_SDMMC2_STREAM_ID 69 >+ >+/* >+ * Erratum A050382 workaround >+ * >+ * Description: >+ * The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not >+ * correctly forwarded to the SMMU. >+ * Workaround: >+ * Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28. Mention (decimal value:40) for better code readability >+ */ >+#ifdef CONFIG_SYS_FSL_ERRATUM_A050382 >+#define FSL_EDMA_STREAM_ID 40 >+#else > #define FSL_EDMA_STREAM_ID 70 >+#endif >+ > #define FSL_GPU_STREAM_ID 71 > #define FSL_DISPLAY_STREAM_ID 72 > #define FSL_SATA3_STREAM_ID 73 >-- >2.17.1 > --priyankajain ^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor ` (4 preceding siblings ...) 2019-10-17 9:22 ` [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround Laurentiu Tudor @ 2019-10-18 6:07 ` Horia Geanta 5 siblings, 0 replies; 15+ messages in thread From: Horia Geanta @ 2019-10-18 6:07 UTC (permalink / raw) To: u-boot On 10/17/2019 12:21 PM, Laurentiu Tudor wrote: > From: Laurentiu Tudor <laurentiu.tudor@nxp.com> > > These macros should only be used when CONFIG_FSL_CAAM is present. > > Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Thanks, Horia ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-10-18 8:10 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-17 9:21 [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Laurentiu Tudor 2019-10-17 9:21 ` [U-Boot] [PATCH 2/6] armv8: fsl-layerscape: fix compile error with sec fw disabled Laurentiu Tudor 2019-10-18 6:32 ` Horia Geanta 2019-10-18 7:25 ` Laurentiu Tudor 2019-10-17 9:21 ` [U-Boot] [PATCH 3/6] armv8: ls2088a: add icid setup for platform devices Laurentiu Tudor 2019-10-18 6:41 ` Horia Geanta 2019-10-17 9:22 ` [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses Laurentiu Tudor 2019-10-18 6:22 ` [U-Boot] [u-boot] " Priyanka Jain 2019-10-17 9:22 ` [U-Boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform devices Laurentiu Tudor 2019-10-18 6:20 ` [U-Boot] [u-boot] " Priyanka Jain 2019-10-18 7:29 ` Laurentiu Tudor 2019-10-18 8:10 ` [U-Boot] " Horia Geanta 2019-10-17 9:22 ` [U-Boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround Laurentiu Tudor 2019-10-18 6:27 ` Priyanka Jain 2019-10-18 6:07 ` [U-Boot] [PATCH 1/6] armv8: fsl-layerscape: guard caam specific defines Horia Geanta
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