[Intel-gfx] [PATCH 00/10] drm/i915/dvo: Further DVO fixes/cleanups

[Intel-gfx] [PATCH 00/10] drm/i915/dvo: Further DVO fixes/cleanups

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Decided to do a bit more work on the DVO code. Started
with just some register definition cleanups/modernization
but ended up actually fixing suspend/resume for a two
of my ADD cards.

Ville Syrjälä (10):
  drm/i915/dvo/ch7xxx: Fix suspend/resume
  drm/i915/dvo/sil164: Nuke pointless return statements
  drm/i915/dvo/sil164: Fix suspend/resume
  drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers
  drm/i915/dvo: Define a few more DVO register bits
  drm/i915/dvo: Rename the "active data order" bits
  drm/i915/dvo: Use REG_BIT() & co. for DVO registers
  drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable
  drm/i915/dvo: Extract intel_dvo_regs.h
  drm/i915/dvo: Log about what was detected on which DVO port

 drivers/gpu/drm/i915/display/dvo_ch7xxx.c     | 22 ++++-
 drivers/gpu/drm/i915/display/dvo_sil164.c     | 12 ++-
 drivers/gpu/drm/i915/display/intel_dvo.c      | 87 ++++++++-----------
 drivers/gpu/drm/i915/display/intel_dvo_dev.h  |  7 +-
 drivers/gpu/drm/i915/display/intel_dvo_regs.h | 54 ++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 40 ---------
 6 files changed, 126 insertions(+), 96 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dvo_regs.h

-- 
2.37.4

[Intel-gfx] [PATCH 01/10] drm/i915/dvo/ch7xxx: Fix suspend/resume

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Poke a few more bits into the ch7xxx to make
it output a picture after being reset during S3.

In particular we need to set the input buffer select (IBS),
and enable VGA vsync output on the BCO pin. Selecting
VGA hsync on the c/h sync pin doesn't actually seem necessary
on my ADD card at least, but the BIOS selects it so why not.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/dvo_ch7xxx.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
index 54f58ba44b9f..6d948520e9a6 100644
--- a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
+++ b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
@@ -50,15 +50,26 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CH7xxx_INPUT_CLOCK	0x1d
 #define CH7xxx_GPIO		0x1e
 #define CH7xxx_GPIO_HPIR	(1<<3)
+
 #define CH7xxx_IDF		0x1f
-
+#define CH7xxx_IDF_IBS		(1<<7)
+#define CH7xxx_IDF_DES		(1<<6)
 #define CH7xxx_IDF_HSP		(1<<3)
 #define CH7xxx_IDF_VSP		(1<<4)
 
 #define CH7xxx_CONNECTION_DETECT 0x20
 #define CH7xxx_CDET_DVI		(1<<5)
 
-#define CH7301_DAC_CNTL		0x21
+#define CH7xxx_DAC_CNTL		0x21
+#define CH7xxx_SYNCO_MASK	(3 << 3)
+#define CH7xxx_SYNCO_VGA_HSYNC	(1 << 3)
+
+#define CH7xxx_CLOCK_OUTPUT	0x22
+#define CH7xxx_BCOEN		(1 << 4)
+#define CH7xxx_BCOP		(1 << 3)
+#define CH7xxx_BCO_MASK		(7 << 0)
+#define CH7xxx_BCO_VGA_VSYNC	(6 << 0)
+
 #define CH7301_HOTPLUG		0x23
 #define CH7xxx_TCTL		0x31
 #define CH7xxx_TVCO		0x32
@@ -301,6 +312,8 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
 
 	ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
 
+	idf |= CH7xxx_IDF_IBS;
+
 	idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 		idf |= CH7xxx_IDF_HSP;
@@ -309,6 +322,11 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
 		idf |= CH7xxx_IDF_VSP;
 
 	ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
+
+	ch7xxx_writeb(dvo, CH7xxx_DAC_CNTL,
+		      CH7xxx_SYNCO_VGA_HSYNC);
+	ch7xxx_writeb(dvo, CH7xxx_CLOCK_OUTPUT,
+		      CH7xxx_BCOEN | CH7xxx_BCO_VGA_VSYNC);
 }
 
 /* set the CH7xxx power state */
-- 
2.37.4

[Intel-gfx] [PATCH 02/10] drm/i915/dvo/sil164: Nuke pointless return statements

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop the pointless return statements at the end of void
functions.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/dvo_sil164.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c
index 0dfa0a0209ff..32dd3b969946 100644
--- a/drivers/gpu/drm/i915/display/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/display/dvo_sil164.c
@@ -205,7 +205,6 @@ static void sil164_mode_set(struct intel_dvo_device *dvo,
 	  sil164_writeb(sil, 0x0c, 0x89);
 	  sil164_writeb(sil, 0x08, 0x31);*/
 	/* don't do much */
-	return;
 }
 
 /* set the SIL164 power state */
@@ -224,7 +223,6 @@ static void sil164_dpms(struct intel_dvo_device *dvo, bool enable)
 		ch &= ~SIL164_8_PD;
 
 	sil164_writeb(dvo, SIL164_REG8, ch);
-	return;
 }
 
 static bool sil164_get_hw_state(struct intel_dvo_device *dvo)
-- 
2.37.4

[Intel-gfx] [PATCH 03/10] drm/i915/dvo/sil164: Fix suspend/resume

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Poke a few more bits into the SiI164 to make it
recover after S3. HEN/VEN are the important bits,
the rest PLL filter/HPD detection I just did
for good measure to match the BIOS programming.

Note that the spec recommended SCNT bit in REGC
isn't set by the BIOS at least for me, so I left
it out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/dvo_sil164.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c
index 32dd3b969946..4acc8ce29c0b 100644
--- a/drivers/gpu/drm/i915/display/dvo_sil164.c
+++ b/drivers/gpu/drm/i915/display/dvo_sil164.c
@@ -58,6 +58,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define SIL164_9_MDI (1<<0)
 
 #define SIL164_REGC 0x0c
+#define SIL164_C_SCNT (1<<7)
+#define SIL164_C_PLLF_MASK (0xf<<1)
+#define SIL164_C_PLLF_REC (4<<1)
+#define SIL164_C_PFEN (1<<0)
 
 struct sil164_priv {
 	//I2CDevRec d;
@@ -205,6 +209,13 @@ static void sil164_mode_set(struct intel_dvo_device *dvo,
 	  sil164_writeb(sil, 0x0c, 0x89);
 	  sil164_writeb(sil, 0x08, 0x31);*/
 	/* don't do much */
+
+	sil164_writeb(dvo, SIL164_REG8,
+		      SIL164_8_VEN | SIL164_8_HEN);
+	sil164_writeb(dvo, SIL164_REG9,
+		      SIL164_9_TSEL);
+	sil164_writeb(dvo, SIL164_REGC,
+		      SIL164_C_PLLF_REC | SIL164_C_PFEN);
 }
 
 /* set the SIL164 power state */
-- 
2.37.4

[Intel-gfx] [PATCH 04/10] drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Get rid of the dvo_reg/dvo_srcdim_reg stuff by parametrizing
the DVO port registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c     | 73 ++++++++------------
 drivers/gpu/drm/i915/display/intel_dvo_dev.h |  7 +-
 drivers/gpu/drm/i915/i915_reg.h              | 11 ++-
 3 files changed, 37 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 575cb920bd43..d20334d3394c 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -56,48 +56,42 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
 	{
 		.type = INTEL_DVO_CHIP_TMDS,
 		.name = "sil164",
-		.dvo_reg = DVOC,
-		.dvo_srcdim_reg = DVOC_SRCDIM,
+		.port = PORT_C,
 		.slave_addr = SIL164_ADDR,
 		.dev_ops = &sil164_ops,
 	},
 	{
 		.type = INTEL_DVO_CHIP_TMDS,
 		.name = "ch7xxx",
-		.dvo_reg = DVOC,
-		.dvo_srcdim_reg = DVOC_SRCDIM,
+		.port = PORT_C,
 		.slave_addr = CH7xxx_ADDR,
 		.dev_ops = &ch7xxx_ops,
 	},
 	{
 		.type = INTEL_DVO_CHIP_TMDS,
 		.name = "ch7xxx",
-		.dvo_reg = DVOC,
-		.dvo_srcdim_reg = DVOC_SRCDIM,
+		.port = PORT_C,
 		.slave_addr = 0x75, /* For some ch7010 */
 		.dev_ops = &ch7xxx_ops,
 	},
 	{
 		.type = INTEL_DVO_CHIP_LVDS,
 		.name = "ivch",
-		.dvo_reg = DVOA,
-		.dvo_srcdim_reg = DVOA_SRCDIM,
+		.port = PORT_A,
 		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
 		.dev_ops = &ivch_ops,
 	},
 	{
 		.type = INTEL_DVO_CHIP_TMDS,
 		.name = "tfp410",
-		.dvo_reg = DVOC,
-		.dvo_srcdim_reg = DVOC_SRCDIM,
+		.port = PORT_C,
 		.slave_addr = TFP410_ADDR,
 		.dev_ops = &tfp410_ops,
 	},
 	{
 		.type = INTEL_DVO_CHIP_LVDS,
 		.name = "ch7017",
-		.dvo_reg = DVOC,
-		.dvo_srcdim_reg = DVOC_SRCDIM,
+		.port = PORT_C,
 		.slave_addr = 0x75,
 		.gpio = GMBUS_PIN_DPB,
 		.dev_ops = &ch7017_ops,
@@ -105,8 +99,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
 	{
 		.type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
 		.name = "ns2501",
-		.dvo_reg = DVOB,
-		.dvo_srcdim_reg = DVOB_SRCDIM,
+		.port = PORT_B,
 		.slave_addr = NS2501_ADDR,
 		.dev_ops = &ns2501_ops,
 	},
@@ -133,10 +126,12 @@ static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector)
 static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
-	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
+	struct intel_encoder *encoder = intel_attached_encoder(connector);
+	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
+	enum port port = encoder->port;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
+	tmp = intel_de_read(i915, DVO(port));
 
 	if (!(tmp & DVO_ENABLE))
 		return false;
@@ -148,10 +143,10 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
+	enum port port = encoder->port;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
+	tmp = intel_de_read(i915, DVO(port));
 
 	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
 
@@ -162,12 +157,12 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
+	enum port port = encoder->port;
 	u32 tmp, flags = 0;
 
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
 
-	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
+	tmp = intel_de_read(i915, DVO(port));
 	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
 		flags |= DRM_MODE_FLAG_PHSYNC;
 	else
@@ -189,12 +184,12 @@ static void intel_disable_dvo(struct intel_atomic_state *state,
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
-	u32 temp = intel_de_read(i915, dvo_reg);
+	enum port port = encoder->port;
+	u32 temp = intel_de_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
-	intel_de_write(i915, dvo_reg, temp & ~DVO_ENABLE);
-	intel_de_read(i915, dvo_reg);
+	intel_de_write(i915, DVO(port), temp & ~DVO_ENABLE);
+	intel_de_read(i915, DVO(port));
 }
 
 static void intel_enable_dvo(struct intel_atomic_state *state,
@@ -204,15 +199,15 @@ static void intel_enable_dvo(struct intel_atomic_state *state,
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
-	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
-	u32 temp = intel_de_read(i915, dvo_reg);
+	enum port port = encoder->port;
+	u32 temp = intel_de_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
 					 &pipe_config->hw.mode,
 					 &pipe_config->hw.adjusted_mode);
 
-	intel_de_write(i915, dvo_reg, temp | DVO_ENABLE);
-	intel_de_read(i915, dvo_reg);
+	intel_de_write(i915, DVO(port), temp | DVO_ENABLE);
+	intel_de_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
 }
@@ -289,14 +284,12 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
+	enum port port = encoder->port;
 	enum pipe pipe = crtc->pipe;
 	u32 dvo_val;
-	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
-	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
 
 	/* Save the data order, since I don't know what it should be set to. */
-	dvo_val = intel_de_read(i915, dvo_reg) &
+	dvo_val = intel_de_read(i915, DVO(port)) &
 		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
 		   DVO_BLANK_ACTIVE_HIGH;
@@ -308,9 +301,9 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
 
-	intel_de_write(i915, dvo_srcdim_reg,
+	intel_de_write(i915, DVO_SRCDIM(port),
 		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
-	intel_de_write(i915, dvo_reg, dvo_val);
+	intel_de_write(i915, DVO(port), dvo_val);
 }
 
 static enum drm_connector_status
@@ -378,16 +371,6 @@ static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
 	.destroy = intel_dvo_enc_destroy,
 };
 
-static enum port intel_dvo_port(i915_reg_t dvo_reg)
-{
-	if (i915_mmio_reg_equal(dvo_reg, DVOA))
-		return PORT_A;
-	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
-		return PORT_B;
-	else
-		return PORT_C;
-}
-
 static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo)
 {
 	switch (dvo->type) {
@@ -528,7 +511,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
 
 	encoder->type = INTEL_OUTPUT_DVO;
 	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
-	encoder->port = intel_dvo_port(intel_dvo->dev.dvo_reg);
+	encoder->port = intel_dvo->dev.port;
 	encoder->pipe_mask = ~0;
 
 	if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS)
diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
index ecff7b190856..ea8eb7dcee38 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
+++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
@@ -25,6 +25,8 @@
 
 #include "i915_reg_defs.h"
 
+#include "intel_display.h"
+
 enum drm_connector_status;
 struct drm_display_mode;
 struct i2c_adapter;
@@ -32,9 +34,8 @@ struct i2c_adapter;
 struct intel_dvo_device {
 	const char *name;
 	int type;
-	/* DVOA/B/C output register */
-	i915_reg_t dvo_reg;
-	i915_reg_t dvo_srcdim_reg;
+	/* DVOA/B/C */
+	enum port port;
 	/* GPIO register used for i2c bus to control this device */
 	u32 gpio;
 	int slave_addr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e1892d14774..f5ae171eaee0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2578,11 +2578,9 @@
 
 /* DVO port control */
 #define _DVOA			0x61120
-#define DVOA			_MMIO(_DVOA)
 #define _DVOB			0x61140
-#define DVOB			_MMIO(_DVOB)
 #define _DVOC			0x61160
-#define DVOC			_MMIO(_DVOC)
+#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
 #define   DVO_ENABLE			(1 << 31)
 #define   DVO_PIPE_SEL_SHIFT		30
 #define   DVO_PIPE_SEL_MASK		(1 << 30)
@@ -2609,9 +2607,10 @@
 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
 #define   DVO_PRESERVE_MASK		(0x7 << 24)
-#define DVOA_SRCDIM		_MMIO(0x61124)
-#define DVOB_SRCDIM		_MMIO(0x61144)
-#define DVOC_SRCDIM		_MMIO(0x61164)
+#define _DVOA_SRCDIM		0x61124
+#define _DVOB_SRCDIM		0x61144
+#define _DVOC_SRCDIM		0x61164
+#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
 #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
 
-- 
2.37.4

[Intel-gfx] [PATCH 05/10] drm/i915/dvo: Define a few more DVO register bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Define a few extra interrupt related bits on the DVO register.
One of these we included in the DVO_PRESERVE_MASK already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index d20334d3394c..255deb55b932 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -290,7 +290,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 
 	/* Save the data order, since I don't know what it should be set to. */
 	dvo_val = intel_de_read(i915, DVO(port)) &
-		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
+		  (DVO_DEDICATED_INT_ENABLE |
+		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
 		   DVO_BLANK_ACTIVE_HIGH;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5ae171eaee0..89c834d8fff8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2589,6 +2589,9 @@
 #define   DVO_PIPE_STALL		(1 << 28)
 #define   DVO_PIPE_STALL_TV		(2 << 28)
 #define   DVO_PIPE_STALL_MASK		(3 << 28)
+#define   DVO_INTERRUPT_SELECT		(1 << 27)
+#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
+#define   DVO_PRESERVE_MASK		(0x3 << 24)
 #define   DVO_USE_VGA_SYNC		(1 << 15)
 #define   DVO_DATA_ORDER_I740		(0 << 14)
 #define   DVO_DATA_ORDER_FP		(1 << 14)
@@ -2606,7 +2609,6 @@
 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
-#define   DVO_PRESERVE_MASK		(0x7 << 24)
 #define _DVOA_SRCDIM		0x61124
 #define _DVOB_SRCDIM		0x61144
 #define _DVOC_SRCDIM		0x61164
-- 
2.37.4

[Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have two sets of bits for DVO "data order" stuff. Rename
one set to ACT_DATA_ORDER to make it clear they are separate
bitfields.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h          | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 255deb55b932..b36c3a620250 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 	enum pipe pipe = crtc->pipe;
 	u32 dvo_val;
 
-	/* Save the data order, since I don't know what it should be set to. */
+	/* Save the active data order, since I don't know what it should be set to. */
 	dvo_val = intel_de_read(i915, DVO(port)) &
 		  (DVO_DEDICATED_INT_ENABLE |
-		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
+		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
 		   DVO_BLANK_ACTIVE_HIGH;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 89c834d8fff8..464be86d6125 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2600,10 +2600,10 @@
 #define   DVO_VSYNC_TRISTATE		(1 << 9)
 #define   DVO_HSYNC_TRISTATE		(1 << 8)
 #define   DVO_BORDER_ENABLE		(1 << 7)
-#define   DVO_DATA_ORDER_GBRG		(1 << 6)
-#define   DVO_DATA_ORDER_RGGB		(0 << 6)
-#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
-#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
+#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)
+#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)
+#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)
+#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)
 #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
 #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
-- 
2.37.4

[Intel-gfx] [PATCH 07/10] drm/i915/dvo: Use REG_BIT() & co. for DVO registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Polish the DVO port regisesters with REG_BIT()/etc.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c |  7 +--
 drivers/gpu/drm/i915/i915_reg.h          | 63 +++++++++++++-----------
 2 files changed, 37 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index b36c3a620250..a5c464c82e5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -148,7 +148,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
 
 	tmp = intel_de_read(i915, DVO(port));
 
-	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
+	*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);
 
 	return tmp & DVO_ENABLE;
 }
@@ -291,7 +291,7 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 	/* Save the active data order, since I don't know what it should be set to. */
 	dvo_val = intel_de_read(i915, DVO(port)) &
 		  (DVO_DEDICATED_INT_ENABLE |
-		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
+		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK);
 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
 		   DVO_BLANK_ACTIVE_HIGH;
 
@@ -303,7 +303,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
 
 	intel_de_write(i915, DVO_SRCDIM(port),
-		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
+		       DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) |
+		       DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay));
 	intel_de_write(i915, DVO(port), dvo_val);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 464be86d6125..08fdc0107212 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2581,40 +2581,43 @@
 #define _DVOB			0x61140
 #define _DVOC			0x61160
 #define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
-#define   DVO_ENABLE			(1 << 31)
-#define   DVO_PIPE_SEL_SHIFT		30
-#define   DVO_PIPE_SEL_MASK		(1 << 30)
-#define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
-#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
-#define   DVO_PIPE_STALL		(1 << 28)
-#define   DVO_PIPE_STALL_TV		(2 << 28)
-#define   DVO_PIPE_STALL_MASK		(3 << 28)
-#define   DVO_INTERRUPT_SELECT		(1 << 27)
-#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
-#define   DVO_PRESERVE_MASK		(0x3 << 24)
-#define   DVO_USE_VGA_SYNC		(1 << 15)
-#define   DVO_DATA_ORDER_I740		(0 << 14)
-#define   DVO_DATA_ORDER_FP		(1 << 14)
-#define   DVO_VSYNC_DISABLE		(1 << 11)
-#define   DVO_HSYNC_DISABLE		(1 << 10)
-#define   DVO_VSYNC_TRISTATE		(1 << 9)
-#define   DVO_HSYNC_TRISTATE		(1 << 8)
-#define   DVO_BORDER_ENABLE		(1 << 7)
-#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)
-#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)
-#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)
-#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)
-#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
-#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
-#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
-#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
-#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
+#define   DVO_ENABLE				REG_BIT(31)
+#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
+#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
+#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
+#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
+#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
+#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
+#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
+#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
+#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
+#define   DVO_USE_VGA_SYNC			REG_BIT(15)
+#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
+#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
+#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
+#define   DVO_VSYNC_DISABLE			REG_BIT(11)
+#define   DVO_HSYNC_DISABLE			REG_BIT(10)
+#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
+#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
+#define   DVO_BORDER_ENABLE			REG_BIT(7)
+#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
+#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
+#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
+#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
+#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
+#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
+#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
+#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
+#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
+#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
 #define _DVOA_SRCDIM		0x61124
 #define _DVOB_SRCDIM		0x61144
 #define _DVOC_SRCDIM		0x61164
 #define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
-#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
-#define   DVO_SRCDIM_VERTICAL_SHIFT	0
+#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
+#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
+#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
+#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
 
 /* LVDS port control */
 #define LVDS			_MMIO(0x61180)
-- 
2.37.4

[Intel-gfx] [PATCH 08/10] drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the hand rolled RMW with intel_de_rmw() in the DVO
port enable/disable functions. Also switch to intel_de_posting_read()
for the posting read (though maybe it should be just be nuked...).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index a5c464c82e5c..c590a92205f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -185,11 +185,11 @@ static void intel_disable_dvo(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	enum port port = encoder->port;
-	u32 temp = intel_de_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
-	intel_de_write(i915, DVO(port), temp & ~DVO_ENABLE);
-	intel_de_read(i915, DVO(port));
+
+	intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0);
+	intel_de_posting_read(i915, DVO(port));
 }
 
 static void intel_enable_dvo(struct intel_atomic_state *state,
@@ -200,14 +200,13 @@ static void intel_enable_dvo(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
 	enum port port = encoder->port;
-	u32 temp = intel_de_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
 					 &pipe_config->hw.mode,
 					 &pipe_config->hw.adjusted_mode);
 
-	intel_de_write(i915, DVO(port), temp | DVO_ENABLE);
-	intel_de_read(i915, DVO(port));
+	intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE);
+	intel_de_posting_read(i915, DVO(port));
 
 	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
 }
-- 
2.37.4

[Intel-gfx] [PATCH 09/10] drm/i915/dvo: Extract intel_dvo_regs.h

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the DVO port register definitons into their own header
to declutter i915_reg.h a bit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c      |  1 +
 drivers/gpu/drm/i915/display/intel_dvo_regs.h | 54 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 44 ---------------
 3 files changed, 55 insertions(+), 44 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dvo_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index c590a92205f0..4a4b98bfce29 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -38,6 +38,7 @@
 #include "intel_display_types.h"
 #include "intel_dvo.h"
 #include "intel_dvo_dev.h"
+#include "intel_dvo_regs.h"
 #include "intel_gmbus.h"
 #include "intel_panel.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_dvo_regs.h b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
new file mode 100644
index 000000000000..6f9058462850
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DVO_REGS_H__
+#define __INTEL_DVO_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _DVOA			0x61120
+#define _DVOB			0x61140
+#define _DVOC			0x61160
+#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
+#define   DVO_ENABLE				REG_BIT(31)
+#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
+#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
+#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
+#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
+#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
+#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
+#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
+#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
+#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
+#define   DVO_USE_VGA_SYNC			REG_BIT(15)
+#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
+#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
+#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
+#define   DVO_VSYNC_DISABLE			REG_BIT(11)
+#define   DVO_HSYNC_DISABLE			REG_BIT(10)
+#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
+#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
+#define   DVO_BORDER_ENABLE			REG_BIT(7)
+#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
+#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
+#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
+#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
+#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
+#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
+#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
+#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
+#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
+#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
+
+#define _DVOA_SRCDIM		0x61124
+#define _DVOB_SRCDIM		0x61144
+#define _DVOC_SRCDIM		0x61164
+#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
+#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
+#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
+#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
+#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
+
+#endif /* __INTEL_DVO_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 08fdc0107212..991e2a908314 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2575,50 +2575,6 @@
 #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
 #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
 
-
-/* DVO port control */
-#define _DVOA			0x61120
-#define _DVOB			0x61140
-#define _DVOC			0x61160
-#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
-#define   DVO_ENABLE				REG_BIT(31)
-#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
-#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
-#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
-#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
-#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
-#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
-#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
-#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
-#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
-#define   DVO_USE_VGA_SYNC			REG_BIT(15)
-#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
-#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
-#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
-#define   DVO_VSYNC_DISABLE			REG_BIT(11)
-#define   DVO_HSYNC_DISABLE			REG_BIT(10)
-#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
-#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
-#define   DVO_BORDER_ENABLE			REG_BIT(7)
-#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
-#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
-#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
-#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
-#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
-#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
-#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
-#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
-#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
-#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
-#define _DVOA_SRCDIM		0x61124
-#define _DVOB_SRCDIM		0x61144
-#define _DVOC_SRCDIM		0x61164
-#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
-#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
-#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
-#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
-#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
-
 /* LVDS port control */
 #define LVDS			_MMIO(0x61180)
 /*
-- 
2.37.4

[Intel-gfx] [PATCH 10/10] drm/i915/dvo: Log about what was detected on which DVO port

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently it's not 100% obvious which DVO encoder chip was
found on which port. Leave a slightly better trace in log.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 4a4b98bfce29..4aeae0f3ac91 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -525,6 +525,10 @@ void intel_dvo_init(struct drm_i915_private *i915)
 			 intel_dvo_encoder_type(&intel_dvo->dev),
 			 "DVO %c", port_name(encoder->port));
 
+	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] detected %s\n",
+		    encoder->base.base.id, encoder->base.name,
+		    intel_dvo->dev.name);
+
 	if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS)
 		connector->polled = DRM_CONNECTOR_POLL_CONNECT |
 			DRM_CONNECTOR_POLL_DISCONNECT;
-- 
2.37.4

Re: [Intel-gfx] [PATCH 01/10] drm/i915/dvo/ch7xxx: Fix suspend/resume

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Poke a few more bits into the ch7xxx to make
> it output a picture after being reset during S3.
>
> In particular we need to set the input buffer select (IBS),
> and enable VGA vsync output on the BCO pin. Selecting
> VGA hsync on the c/h sync pin doesn't actually seem necessary
> on my ADD card at least, but the BIOS selects it so why not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

First things first.

I'll r-b anything that I've actually reviewed in the series, although
the subject matter being what it is, I may not have reviewed it as
thoroughly as I would other code that I review.

If r-b would require me to look stuff up in the specs, I really couldn't
be bothered, so I'll just a-b that stuff if it looks reasonable. I don't
think anyone else is going to show up for review either, and if you end
up breaking something, I think you're the only one to show up to fix it
anyway.

Fair enough?

With that, this patch is

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/dvo_ch7xxx.c | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> index 54f58ba44b9f..6d948520e9a6 100644
> --- a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> +++ b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> @@ -50,15 +50,26 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define CH7xxx_INPUT_CLOCK	0x1d
>  #define CH7xxx_GPIO		0x1e
>  #define CH7xxx_GPIO_HPIR	(1<<3)
> +
>  #define CH7xxx_IDF		0x1f
> -
> +#define CH7xxx_IDF_IBS		(1<<7)
> +#define CH7xxx_IDF_DES		(1<<6)
>  #define CH7xxx_IDF_HSP		(1<<3)
>  #define CH7xxx_IDF_VSP		(1<<4)
>  
>  #define CH7xxx_CONNECTION_DETECT 0x20
>  #define CH7xxx_CDET_DVI		(1<<5)
>  
> -#define CH7301_DAC_CNTL		0x21
> +#define CH7xxx_DAC_CNTL		0x21
> +#define CH7xxx_SYNCO_MASK	(3 << 3)
> +#define CH7xxx_SYNCO_VGA_HSYNC	(1 << 3)
> +
> +#define CH7xxx_CLOCK_OUTPUT	0x22
> +#define CH7xxx_BCOEN		(1 << 4)
> +#define CH7xxx_BCOP		(1 << 3)
> +#define CH7xxx_BCO_MASK		(7 << 0)
> +#define CH7xxx_BCO_VGA_VSYNC	(6 << 0)
> +
>  #define CH7301_HOTPLUG		0x23
>  #define CH7xxx_TCTL		0x31
>  #define CH7xxx_TVCO		0x32
> @@ -301,6 +312,8 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
>  
>  	ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
>  
> +	idf |= CH7xxx_IDF_IBS;
> +
>  	idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
>  	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
>  		idf |= CH7xxx_IDF_HSP;
> @@ -309,6 +322,11 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
>  		idf |= CH7xxx_IDF_VSP;
>  
>  	ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
> +
> +	ch7xxx_writeb(dvo, CH7xxx_DAC_CNTL,
> +		      CH7xxx_SYNCO_VGA_HSYNC);
> +	ch7xxx_writeb(dvo, CH7xxx_CLOCK_OUTPUT,
> +		      CH7xxx_BCOEN | CH7xxx_BCO_VGA_VSYNC);
>  }
>  
>  /* set the CH7xxx power state */

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/10] drm/i915/dvo/sil164: Nuke pointless return statements

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the pointless return statements at the end of void
> functions.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/dvo_sil164.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c
> index 0dfa0a0209ff..32dd3b969946 100644
> --- a/drivers/gpu/drm/i915/display/dvo_sil164.c
> +++ b/drivers/gpu/drm/i915/display/dvo_sil164.c
> @@ -205,7 +205,6 @@ static void sil164_mode_set(struct intel_dvo_device *dvo,
>  	  sil164_writeb(sil, 0x0c, 0x89);
>  	  sil164_writeb(sil, 0x08, 0x31);*/
>  	/* don't do much */
> -	return;
>  }
>  
>  /* set the SIL164 power state */
> @@ -224,7 +223,6 @@ static void sil164_dpms(struct intel_dvo_device *dvo, bool enable)
>  		ch &= ~SIL164_8_PD;
>  
>  	sil164_writeb(dvo, SIL164_REG8, ch);
> -	return;
>  }
>  
>  static bool sil164_get_hw_state(struct intel_dvo_device *dvo)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 03/10] drm/i915/dvo/sil164: Fix suspend/resume

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Poke a few more bits into the SiI164 to make it
> recover after S3. HEN/VEN are the important bits,
> the rest PLL filter/HPD detection I just did
> for good measure to match the BIOS programming.
>
> Note that the spec recommended SCNT bit in REGC
> isn't set by the BIOS at least for me, so I left
> it out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/dvo_sil164.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c
> index 32dd3b969946..4acc8ce29c0b 100644
> --- a/drivers/gpu/drm/i915/display/dvo_sil164.c
> +++ b/drivers/gpu/drm/i915/display/dvo_sil164.c
> @@ -58,6 +58,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  #define SIL164_9_MDI (1<<0)
>  
>  #define SIL164_REGC 0x0c
> +#define SIL164_C_SCNT (1<<7)
> +#define SIL164_C_PLLF_MASK (0xf<<1)
> +#define SIL164_C_PLLF_REC (4<<1)
> +#define SIL164_C_PFEN (1<<0)
>  
>  struct sil164_priv {
>  	//I2CDevRec d;
> @@ -205,6 +209,13 @@ static void sil164_mode_set(struct intel_dvo_device *dvo,
>  	  sil164_writeb(sil, 0x0c, 0x89);
>  	  sil164_writeb(sil, 0x08, 0x31);*/
>  	/* don't do much */
> +
> +	sil164_writeb(dvo, SIL164_REG8,
> +		      SIL164_8_VEN | SIL164_8_HEN);
> +	sil164_writeb(dvo, SIL164_REG9,
> +		      SIL164_9_TSEL);
> +	sil164_writeb(dvo, SIL164_REGC,
> +		      SIL164_C_PLLF_REC | SIL164_C_PFEN);
>  }
>  
>  /* set the SIL164 power state */

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/10] drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the dvo_reg/dvo_srcdim_reg stuff by parametrizing
> the DVO port registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c     | 73 ++++++++------------
>  drivers/gpu/drm/i915/display/intel_dvo_dev.h |  7 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 11 ++-
>  3 files changed, 37 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 575cb920bd43..d20334d3394c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -56,48 +56,42 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
>  	{
>  		.type = INTEL_DVO_CHIP_TMDS,
>  		.name = "sil164",
> -		.dvo_reg = DVOC,
> -		.dvo_srcdim_reg = DVOC_SRCDIM,
> +		.port = PORT_C,
>  		.slave_addr = SIL164_ADDR,
>  		.dev_ops = &sil164_ops,
>  	},
>  	{
>  		.type = INTEL_DVO_CHIP_TMDS,
>  		.name = "ch7xxx",
> -		.dvo_reg = DVOC,
> -		.dvo_srcdim_reg = DVOC_SRCDIM,
> +		.port = PORT_C,
>  		.slave_addr = CH7xxx_ADDR,
>  		.dev_ops = &ch7xxx_ops,
>  	},
>  	{
>  		.type = INTEL_DVO_CHIP_TMDS,
>  		.name = "ch7xxx",
> -		.dvo_reg = DVOC,
> -		.dvo_srcdim_reg = DVOC_SRCDIM,
> +		.port = PORT_C,
>  		.slave_addr = 0x75, /* For some ch7010 */
>  		.dev_ops = &ch7xxx_ops,
>  	},
>  	{
>  		.type = INTEL_DVO_CHIP_LVDS,
>  		.name = "ivch",
> -		.dvo_reg = DVOA,
> -		.dvo_srcdim_reg = DVOA_SRCDIM,
> +		.port = PORT_A,
>  		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
>  		.dev_ops = &ivch_ops,
>  	},
>  	{
>  		.type = INTEL_DVO_CHIP_TMDS,
>  		.name = "tfp410",
> -		.dvo_reg = DVOC,
> -		.dvo_srcdim_reg = DVOC_SRCDIM,
> +		.port = PORT_C,
>  		.slave_addr = TFP410_ADDR,
>  		.dev_ops = &tfp410_ops,
>  	},
>  	{
>  		.type = INTEL_DVO_CHIP_LVDS,
>  		.name = "ch7017",
> -		.dvo_reg = DVOC,
> -		.dvo_srcdim_reg = DVOC_SRCDIM,
> +		.port = PORT_C,
>  		.slave_addr = 0x75,
>  		.gpio = GMBUS_PIN_DPB,
>  		.dev_ops = &ch7017_ops,
> @@ -105,8 +99,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
>  	{
>  		.type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
>  		.name = "ns2501",
> -		.dvo_reg = DVOB,
> -		.dvo_srcdim_reg = DVOB_SRCDIM,
> +		.port = PORT_B,
>  		.slave_addr = NS2501_ADDR,
>  		.dev_ops = &ns2501_ops,
>  	},
> @@ -133,10 +126,12 @@ static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector)
>  static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
>  {
>  	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> -	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> +	struct intel_encoder *encoder = intel_attached_encoder(connector);
> +	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> +	enum port port = encoder->port;
>  	u32 tmp;
>  
> -	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
> +	tmp = intel_de_read(i915, DVO(port));
>  
>  	if (!(tmp & DVO_ENABLE))
>  		return false;
> @@ -148,10 +143,10 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
>  				   enum pipe *pipe)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> +	enum port port = encoder->port;
>  	u32 tmp;
>  
> -	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
> +	tmp = intel_de_read(i915, DVO(port));
>  
>  	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
>  
> @@ -162,12 +157,12 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> +	enum port port = encoder->port;
>  	u32 tmp, flags = 0;
>  
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
>  
> -	tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg);
> +	tmp = intel_de_read(i915, DVO(port));
>  	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
>  		flags |= DRM_MODE_FLAG_PHSYNC;
>  	else
> @@ -189,12 +184,12 @@ static void intel_disable_dvo(struct intel_atomic_state *state,
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> -	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
> -	u32 temp = intel_de_read(i915, dvo_reg);
> +	enum port port = encoder->port;
> +	u32 temp = intel_de_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
> -	intel_de_write(i915, dvo_reg, temp & ~DVO_ENABLE);
> -	intel_de_read(i915, dvo_reg);
> +	intel_de_write(i915, DVO(port), temp & ~DVO_ENABLE);
> +	intel_de_read(i915, DVO(port));
>  }
>  
>  static void intel_enable_dvo(struct intel_atomic_state *state,
> @@ -204,15 +199,15 @@ static void intel_enable_dvo(struct intel_atomic_state *state,
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> -	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
> -	u32 temp = intel_de_read(i915, dvo_reg);
> +	enum port port = encoder->port;
> +	u32 temp = intel_de_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
>  					 &pipe_config->hw.mode,
>  					 &pipe_config->hw.adjusted_mode);
>  
> -	intel_de_write(i915, dvo_reg, temp | DVO_ENABLE);
> -	intel_de_read(i915, dvo_reg);
> +	intel_de_write(i915, DVO(port), temp | DVO_ENABLE);
> +	intel_de_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
>  }
> @@ -289,14 +284,12 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> -	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> +	enum port port = encoder->port;
>  	enum pipe pipe = crtc->pipe;
>  	u32 dvo_val;
> -	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
> -	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
>  
>  	/* Save the data order, since I don't know what it should be set to. */
> -	dvo_val = intel_de_read(i915, dvo_reg) &
> +	dvo_val = intel_de_read(i915, DVO(port)) &
>  		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
> @@ -308,9 +301,9 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>  		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
>  
> -	intel_de_write(i915, dvo_srcdim_reg,
> +	intel_de_write(i915, DVO_SRCDIM(port),
>  		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
> -	intel_de_write(i915, dvo_reg, dvo_val);
> +	intel_de_write(i915, DVO(port), dvo_val);
>  }
>  
>  static enum drm_connector_status
> @@ -378,16 +371,6 @@ static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
>  	.destroy = intel_dvo_enc_destroy,
>  };
>  
> -static enum port intel_dvo_port(i915_reg_t dvo_reg)
> -{
> -	if (i915_mmio_reg_equal(dvo_reg, DVOA))
> -		return PORT_A;
> -	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
> -		return PORT_B;
> -	else
> -		return PORT_C;
> -}
> -
>  static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo)
>  {
>  	switch (dvo->type) {
> @@ -528,7 +511,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
>  
>  	encoder->type = INTEL_OUTPUT_DVO;
>  	encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
> -	encoder->port = intel_dvo_port(intel_dvo->dev.dvo_reg);
> +	encoder->port = intel_dvo->dev.port;
>  	encoder->pipe_mask = ~0;
>  
>  	if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS)
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
> index ecff7b190856..ea8eb7dcee38 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
> +++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
> @@ -25,6 +25,8 @@
>  
>  #include "i915_reg_defs.h"
>  
> +#include "intel_display.h"
> +
>  enum drm_connector_status;
>  struct drm_display_mode;
>  struct i2c_adapter;
> @@ -32,9 +34,8 @@ struct i2c_adapter;
>  struct intel_dvo_device {
>  	const char *name;
>  	int type;
> -	/* DVOA/B/C output register */
> -	i915_reg_t dvo_reg;
> -	i915_reg_t dvo_srcdim_reg;
> +	/* DVOA/B/C */
> +	enum port port;
>  	/* GPIO register used for i2c bus to control this device */
>  	u32 gpio;
>  	int slave_addr;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8e1892d14774..f5ae171eaee0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2578,11 +2578,9 @@
>  
>  /* DVO port control */
>  #define _DVOA			0x61120
> -#define DVOA			_MMIO(_DVOA)
>  #define _DVOB			0x61140
> -#define DVOB			_MMIO(_DVOB)
>  #define _DVOC			0x61160
> -#define DVOC			_MMIO(_DVOC)
> +#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
>  #define   DVO_ENABLE			(1 << 31)
>  #define   DVO_PIPE_SEL_SHIFT		30
>  #define   DVO_PIPE_SEL_MASK		(1 << 30)
> @@ -2609,9 +2607,10 @@
>  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
>  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
>  #define   DVO_PRESERVE_MASK		(0x7 << 24)
> -#define DVOA_SRCDIM		_MMIO(0x61124)
> -#define DVOB_SRCDIM		_MMIO(0x61144)
> -#define DVOC_SRCDIM		_MMIO(0x61164)
> +#define _DVOA_SRCDIM		0x61124
> +#define _DVOB_SRCDIM		0x61144
> +#define _DVOC_SRCDIM		0x61164
> +#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
>  #define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
>  #define   DVO_SRCDIM_VERTICAL_SHIFT	0

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 05/10] drm/i915/dvo: Define a few more DVO register bits

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define a few extra interrupt related bits on the DVO register.
> One of these we included in the DVO_PRESERVE_MASK already.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index d20334d3394c..255deb55b932 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -290,7 +290,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  
>  	/* Save the data order, since I don't know what it should be set to. */
>  	dvo_val = intel_de_read(i915, DVO(port)) &
> -		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
> +		  (DVO_DEDICATED_INT_ENABLE |
> +		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5ae171eaee0..89c834d8fff8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2589,6 +2589,9 @@
>  #define   DVO_PIPE_STALL		(1 << 28)
>  #define   DVO_PIPE_STALL_TV		(2 << 28)
>  #define   DVO_PIPE_STALL_MASK		(3 << 28)
> +#define   DVO_INTERRUPT_SELECT		(1 << 27)
> +#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
> +#define   DVO_PRESERVE_MASK		(0x3 << 24)
>  #define   DVO_USE_VGA_SYNC		(1 << 15)
>  #define   DVO_DATA_ORDER_I740		(0 << 14)
>  #define   DVO_DATA_ORDER_FP		(1 << 14)
> @@ -2606,7 +2609,6 @@
>  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
>  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
>  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
> -#define   DVO_PRESERVE_MASK		(0x7 << 24)
>  #define _DVOA_SRCDIM		0x61124
>  #define _DVOB_SRCDIM		0x61144
>  #define _DVOC_SRCDIM		0x61164

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We have two sets of bits for DVO "data order" stuff. Rename
> one set to ACT_DATA_ORDER to make it clear they are separate
> bitfields.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h          | 8 ++++----
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 255deb55b932..b36c3a620250 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -288,10 +288,10 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	enum pipe pipe = crtc->pipe;
>  	u32 dvo_val;
>  
> -	/* Save the data order, since I don't know what it should be set to. */
> +	/* Save the active data order, since I don't know what it should be set to. */
>  	dvo_val = intel_de_read(i915, DVO(port)) &
>  		  (DVO_DEDICATED_INT_ENABLE |
> -		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
> +		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 89c834d8fff8..464be86d6125 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2600,10 +2600,10 @@
>  #define   DVO_VSYNC_TRISTATE		(1 << 9)
>  #define   DVO_HSYNC_TRISTATE		(1 << 8)
>  #define   DVO_BORDER_ENABLE		(1 << 7)
> -#define   DVO_DATA_ORDER_GBRG		(1 << 6)
> -#define   DVO_DATA_ORDER_RGGB		(0 << 6)
> -#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
> -#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
> +#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)
> +#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)
> +#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)
> +#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)
>  #define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
>  #define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
>  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 07/10] drm/i915/dvo: Use REG_BIT() & co. for DVO registers

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Polish the DVO port regisesters with REG_BIT()/etc.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c |  7 +--
>  drivers/gpu/drm/i915/i915_reg.h          | 63 +++++++++++++-----------
>  2 files changed, 37 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index b36c3a620250..a5c464c82e5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -148,7 +148,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
>  
>  	tmp = intel_de_read(i915, DVO(port));
>  
> -	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
> +	*pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp);
>  
>  	return tmp & DVO_ENABLE;
>  }
> @@ -291,7 +291,7 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  	/* Save the active data order, since I don't know what it should be set to. */
>  	dvo_val = intel_de_read(i915, DVO(port)) &
>  		  (DVO_DEDICATED_INT_ENABLE |
> -		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG);
> +		   DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
>  
> @@ -303,7 +303,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
>  
>  	intel_de_write(i915, DVO_SRCDIM(port),
> -		       (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
> +		       DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) |
> +		       DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay));
>  	intel_de_write(i915, DVO(port), dvo_val);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 464be86d6125..08fdc0107212 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2581,40 +2581,43 @@
>  #define _DVOB			0x61140
>  #define _DVOC			0x61160
>  #define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
> -#define   DVO_ENABLE			(1 << 31)
> -#define   DVO_PIPE_SEL_SHIFT		30
> -#define   DVO_PIPE_SEL_MASK		(1 << 30)
> -#define   DVO_PIPE_SEL(pipe)		((pipe) << 30)
> -#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
> -#define   DVO_PIPE_STALL		(1 << 28)
> -#define   DVO_PIPE_STALL_TV		(2 << 28)
> -#define   DVO_PIPE_STALL_MASK		(3 << 28)
> -#define   DVO_INTERRUPT_SELECT		(1 << 27)
> -#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
> -#define   DVO_PRESERVE_MASK		(0x3 << 24)
> -#define   DVO_USE_VGA_SYNC		(1 << 15)
> -#define   DVO_DATA_ORDER_I740		(0 << 14)
> -#define   DVO_DATA_ORDER_FP		(1 << 14)
> -#define   DVO_VSYNC_DISABLE		(1 << 11)
> -#define   DVO_HSYNC_DISABLE		(1 << 10)
> -#define   DVO_VSYNC_TRISTATE		(1 << 9)
> -#define   DVO_HSYNC_TRISTATE		(1 << 8)
> -#define   DVO_BORDER_ENABLE		(1 << 7)
> -#define   DVO_ACT_DATA_ORDER_GBRG		(1 << 6)
> -#define   DVO_ACT_DATA_ORDER_RGGB		(0 << 6)
> -#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	(0 << 6)
> -#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	(1 << 6)
> -#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
> -#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
> -#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
> -#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
> -#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
> +#define   DVO_ENABLE				REG_BIT(31)
> +#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
> +#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
> +#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
> +#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
> +#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
> +#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
> +#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
> +#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
> +#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
> +#define   DVO_USE_VGA_SYNC			REG_BIT(15)
> +#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
> +#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
> +#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_DISABLE			REG_BIT(11)
> +#define   DVO_HSYNC_DISABLE			REG_BIT(10)
> +#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
> +#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
> +#define   DVO_BORDER_ENABLE			REG_BIT(7)
> +#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
> +#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
> +#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
> +#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
> +#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
> +#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
>  #define _DVOA_SRCDIM		0x61124
>  #define _DVOB_SRCDIM		0x61144
>  #define _DVOC_SRCDIM		0x61164
>  #define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
> -#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
> -#define   DVO_SRCDIM_VERTICAL_SHIFT	0
> +#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
> +#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
> +#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
> +#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
>  
>  /* LVDS port control */
>  #define LVDS			_MMIO(0x61180)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 07/10] drm/i915/dvo: Use REG_BIT() & co. for DVO registers

[Jani Nikula]

On Tue, 22 Nov 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Polish the DVO port regisesters with REG_BIT()/etc.

*registers

>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 08/10] drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Replace the hand rolled RMW with intel_de_rmw() in the DVO
> port enable/disable functions. Also switch to intel_de_posting_read()
> for the posting read (though maybe it should be just be nuked...).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I've got an old series adding intel_de_write_post() and
intel_de_rmw_post() that combine the write and the posting read. Wonder
if I should resurrect that. *shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index a5c464c82e5c..c590a92205f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -185,11 +185,11 @@ static void intel_disable_dvo(struct intel_atomic_state *state,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	enum port port = encoder->port;
> -	u32 temp = intel_de_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
> -	intel_de_write(i915, DVO(port), temp & ~DVO_ENABLE);
> -	intel_de_read(i915, DVO(port));
> +
> +	intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0);
> +	intel_de_posting_read(i915, DVO(port));
>  }
>  
>  static void intel_enable_dvo(struct intel_atomic_state *state,
> @@ -200,14 +200,13 @@ static void intel_enable_dvo(struct intel_atomic_state *state,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
>  	enum port port = encoder->port;
> -	u32 temp = intel_de_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
>  					 &pipe_config->hw.mode,
>  					 &pipe_config->hw.adjusted_mode);
>  
> -	intel_de_write(i915, DVO(port), temp | DVO_ENABLE);
> -	intel_de_read(i915, DVO(port));
> +	intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE);
> +	intel_de_posting_read(i915, DVO(port));
>  
>  	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 09/10] drm/i915/dvo: Extract intel_dvo_regs.h

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the DVO port register definitons into their own header
> to declutter i915_reg.h a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c      |  1 +
>  drivers/gpu/drm/i915/display/intel_dvo_regs.h | 54 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 44 ---------------
>  3 files changed, 55 insertions(+), 44 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_dvo_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index c590a92205f0..4a4b98bfce29 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -38,6 +38,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dvo.h"
>  #include "intel_dvo_dev.h"
> +#include "intel_dvo_regs.h"
>  #include "intel_gmbus.h"
>  #include "intel_panel.h"
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo_regs.h b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
> new file mode 100644
> index 000000000000..6f9058462850
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DVO_REGS_H__
> +#define __INTEL_DVO_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _DVOA			0x61120
> +#define _DVOB			0x61140
> +#define _DVOC			0x61160
> +#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
> +#define   DVO_ENABLE				REG_BIT(31)
> +#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
> +#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
> +#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
> +#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
> +#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
> +#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
> +#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
> +#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
> +#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
> +#define   DVO_USE_VGA_SYNC			REG_BIT(15)
> +#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
> +#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
> +#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_DISABLE			REG_BIT(11)
> +#define   DVO_HSYNC_DISABLE			REG_BIT(10)
> +#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
> +#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
> +#define   DVO_BORDER_ENABLE			REG_BIT(7)
> +#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
> +#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
> +#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
> +#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
> +#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
> +#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
> +
> +#define _DVOA_SRCDIM		0x61124
> +#define _DVOB_SRCDIM		0x61144
> +#define _DVOC_SRCDIM		0x61164
> +#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
> +#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
> +#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
> +#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
> +#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
> +
> +#endif /* __INTEL_DVO_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 08fdc0107212..991e2a908314 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2575,50 +2575,6 @@
>  #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
>  #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
>  
> -
> -/* DVO port control */
> -#define _DVOA			0x61120
> -#define _DVOB			0x61140
> -#define _DVOC			0x61160
> -#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
> -#define   DVO_ENABLE				REG_BIT(31)
> -#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
> -#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
> -#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
> -#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
> -#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
> -#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
> -#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
> -#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
> -#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
> -#define   DVO_USE_VGA_SYNC			REG_BIT(15)
> -#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
> -#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
> -#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
> -#define   DVO_VSYNC_DISABLE			REG_BIT(11)
> -#define   DVO_HSYNC_DISABLE			REG_BIT(10)
> -#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
> -#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
> -#define   DVO_BORDER_ENABLE			REG_BIT(7)
> -#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
> -#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> -#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> -#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> -#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> -#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
> -#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
> -#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
> -#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
> -#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
> -#define _DVOA_SRCDIM		0x61124
> -#define _DVOB_SRCDIM		0x61144
> -#define _DVOC_SRCDIM		0x61164
> -#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
> -#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
> -#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
> -#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
> -#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
> -
>  /* LVDS port control */
>  #define LVDS			_MMIO(0x61180)
>  /*

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 10/10] drm/i915/dvo: Log about what was detected on which DVO port

[Jani Nikula]

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently it's not 100% obvious which DVO encoder chip was
> found on which port. Leave a slightly better trace in log.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 4a4b98bfce29..4aeae0f3ac91 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -525,6 +525,10 @@ void intel_dvo_init(struct drm_i915_private *i915)
>  			 intel_dvo_encoder_type(&intel_dvo->dev),
>  			 "DVO %c", port_name(encoder->port));
>  
> +	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] detected %s\n",
> +		    encoder->base.base.id, encoder->base.name,
> +		    intel_dvo->dev.name);
> +
>  	if (intel_dvo->dev.type == INTEL_DVO_CHIP_TMDS)
>  		connector->polled = DRM_CONNECTOR_POLL_CONNECT |
>  			DRM_CONNECTOR_POLL_DISCONNECT;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dvo: Further DVO fixes/cleanups

[Patchwork]

== Series Details ==

Series: drm/i915/dvo: Further DVO fixes/cleanups
URL   : https://patchwork.freedesktop.org/series/111191/
State : warning

== Summary ==

Error: dim checkpatch failed
dcb99cb1b0fc drm/i915/dvo/ch7xxx: Fix suspend/resume
-:31: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#31: FILE: drivers/gpu/drm/i915/display/dvo_ch7xxx.c:55:
+#define CH7xxx_IDF_IBS		(1<<7)
                       		  ^

-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/display/dvo_ch7xxx.c:56:
+#define CH7xxx_IDF_DES		(1<<6)
                       		  ^

total: 0 errors, 0 warnings, 2 checks, 47 lines checked
baba85271cc3 drm/i915/dvo/sil164: Nuke pointless return statements
4ea2f024253a drm/i915/dvo/sil164: Fix suspend/resume
-:29: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#29: FILE: drivers/gpu/drm/i915/display/dvo_sil164.c:61:
+#define SIL164_C_SCNT (1<<7)
                         ^

-:30: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#30: FILE: drivers/gpu/drm/i915/display/dvo_sil164.c:62:
+#define SIL164_C_PLLF_MASK (0xf<<1)
                                ^

-:31: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#31: FILE: drivers/gpu/drm/i915/display/dvo_sil164.c:63:
+#define SIL164_C_PLLF_REC (4<<1)
                             ^

-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/display/dvo_sil164.c:64:
+#define SIL164_C_PFEN (1<<0)
                         ^

total: 0 errors, 0 warnings, 4 checks, 23 lines checked
bf587d1b8efc drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers
cfd4b9ef193f drm/i915/dvo: Define a few more DVO register bits
3737127e81b5 drm/i915/dvo: Rename the "active data order" bits
045559c13484 drm/i915/dvo: Use REG_BIT() & co. for DVO registers
dd974869a2b6 drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable
f2a61e0e895a drm/i915/dvo: Extract intel_dvo_regs.h
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 11, in <module>
    import git
ModuleNotFoundError: No module named 'git'
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 111 lines checked
b464504eb593 drm/i915/dvo: Log about what was detected on which DVO port

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dvo: Further DVO fixes/cleanups

[Patchwork]

== Series Details ==

Series: drm/i915/dvo: Further DVO fixes/cleanups
URL   : https://patchwork.freedesktop.org/series/111191/
State : warning

== Summary ==

Error: make htmldocs had i915 warnings
./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead
./drivers/gpu/drm/i915/gt/intel_gt_mcr.c:739: warning: expecting prototype for intel_gt_mcr_wait_for_reg_fw(). Prototype was for intel_gt_mcr_wait_for_reg() instead

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dvo: Further DVO fixes/cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5695 bytes --]

== Series Details ==

Series: drm/i915/dvo: Further DVO fixes/cleanups
URL   : https://patchwork.freedesktop.org/series/111191/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12417 -> Patchwork_111191v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/index.html

Participating hosts (33 -> 34)
------------------------------

  Additional (1): fi-tgl-dsi 

Known issues
------------

  Here are the changes found in Patchwork_111191v1 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][1] ([i915#7229]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_module_load@reload:
    - {bat-rpls-2}:       [DMESG-WARN][3] ([i915#6434]) -> [PASS][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/bat-rpls-2/igt@i915_module_load@reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/bat-rpls-2/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@migrate:
    - {bat-adlp-6}:       [INCOMPLETE][5] ([i915#7348]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/bat-adlp-6/igt@i915_selftest@live@migrate.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/bat-adlp-6/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@requests:
    - {bat-rpls-2}:       [INCOMPLETE][7] ([i915#6257]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/bat-rpls-2/igt@i915_selftest@live@requests.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/bat-rpls-2/igt@i915_selftest@live@requests.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2:
    - bat-dg1-6:          [FAIL][9] ([fdo#103375]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/bat-dg1-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/bat-dg1-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
  [i915#6471]: https://gitlab.freedesktop.org/drm/intel/issues/6471
  [i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
  [i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
  [i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
  [i915#7058]: https://gitlab.freedesktop.org/drm/intel/issues/7058
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7348]: https://gitlab.freedesktop.org/drm/intel/issues/7348
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561


Build changes
-------------

  * Linux: CI_DRM_12417 -> Patchwork_111191v1

  CI-20190529: 20190529
  CI_DRM_12417: 146bf59b0038cbb0c1665088db64c46c1d420630 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7071: 0801475083ccb938b1d3b358502ff97fdb435585 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111191v1: 146bf59b0038cbb0c1665088db64c46c1d420630 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

5019fd72ff6c drm/i915/dvo: Log about what was detected on which DVO port
affdc89596a0 drm/i915/dvo: Extract intel_dvo_regs.h
35e078e43a2a drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable
a4a6ed9e85aa drm/i915/dvo: Use REG_BIT() & co. for DVO registers
d53f209fe022 drm/i915/dvo: Rename the "active data order" bits
e4f97e43769b drm/i915/dvo: Define a few more DVO register bits
7087e2c6cdca drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers
d56353ecfd44 drm/i915/dvo/sil164: Fix suspend/resume
a8207c7ef918 drm/i915/dvo/sil164: Nuke pointless return statements
7de43839fea0 drm/i915/dvo/ch7xxx: Fix suspend/resume

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/index.html

[-- Attachment #2: Type: text/html, Size: 4848 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dvo: Further DVO fixes/cleanups

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 29755 bytes --]

== Series Details ==

Series: drm/i915/dvo: Further DVO fixes/cleanups
URL   : https://patchwork.freedesktop.org/series/111191/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12417_full -> Patchwork_111191v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in Patchwork_111191v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([i915#4525])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk2/igt@gem_exec_fair@basic-deadline.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk9/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_nop@basic-parallel:
    - shard-glk:          [PASS][5] -> [DMESG-WARN][6] ([i915#118])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk5/igt@gem_exec_nop@basic-parallel.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk2/igt@gem_exec_nop@basic-parallel.html

  * igt@i915_pm_backlight@fade-with-dpms:
    - shard-apl:          NOTRUN -> [SKIP][7] ([fdo#109271]) +19 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl3/igt@i915_pm_backlight@fade-with-dpms.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-skl:          [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl1/igt@i915_selftest@live@gt_heartbeat.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl9/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-b-hdmi-a-1:
    - shard-glk:          [PASS][10] -> [INCOMPLETE][11] ([i915#5584])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-b-hdmi-a-1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-b-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-skl:          NOTRUN -> [SKIP][12] ([fdo#109271])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl9/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-apl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl3/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_color_chamelium@ctm-limited-range:
    - shard-iclb:         NOTRUN -> [SKIP][15] ([fdo#109284] / [fdo#111827])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb8/igt@kms_color_chamelium@ctm-limited-range.html

  * igt@kms_color_chamelium@ctm-negative:
    - shard-skl:          NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl9/igt@kms_color_chamelium@ctm-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][17] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-apl:          [PASS][18] -> [FAIL][19] ([i915#79])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [PASS][20] -> [FAIL][21] ([i915#79])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][22] -> [DMESG-WARN][23] ([i915#180])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-edp1:
    - shard-skl:          [PASS][24] -> [INCOMPLETE][25] ([i915#4839])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl1/igt@kms_flip@flip-vs-suspend@c-edp1.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl1/igt@kms_flip@flip-vs-suspend@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          [PASS][26] -> [FAIL][27] ([i915#2122])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#6375])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#2672]) +8 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([i915#2587] / [i915#2672]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][31] ([i915#3555])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][32] ([i915#2672] / [i915#3555])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([i915#2546])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-skl:          [PASS][35] -> [DMESG-WARN][36] ([i915#1982])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([i915#5176]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109441]) +5 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html

  * igt@perf_pmu@interrupts:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([i915#7318])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl10/igt@perf_pmu@interrupts.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl1/igt@perf_pmu@interrupts.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr1:
    - {shard-rkl}:        [SKIP][43] ([i915#658]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@feature_discovery@psr1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@feature_discovery@psr1.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][45] ([i915#6268]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
    - shard-tglb:         [FAIL][47] ([i915#6268]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-tglb8/igt@gem_ctx_exec@basic-nohangcheck.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [SKIP][49] ([i915#4525]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglb:         [FAIL][51] ([i915#2842]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][53] ([i915#2842]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - {shard-rkl}:        [SKIP][55] ([i915#3281]) -> [PASS][56] +5 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - {shard-rkl}:        [FAIL][57] ([i915#3692]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-5/igt@gem_ppgtt@blt-vs-render-ctxn.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-4/igt@gem_ppgtt@blt-vs-render-ctxn.html

  * igt@gem_set_tiling_vs_pwrite:
    - {shard-rkl}:        [SKIP][59] ([i915#3282]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-1/igt@gem_set_tiling_vs_pwrite.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html

  * igt@gen9_exec_parse@basic-rejected:
    - {shard-rkl}:        [SKIP][61] ([i915#2527]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@gen9_exec_parse@basic-rejected.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-5/igt@gen9_exec_parse@basic-rejected.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [FAIL][63] ([i915#3989] / [i915#454]) -> [PASS][64] +1 similar issue
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [SKIP][65] ([i915#4281]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-skl:          [WARN][67] ([i915#1804]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl1/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - {shard-rkl}:        [SKIP][69] ([i915#1397]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][71] ([i915#72]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [FAIL][73] ([i915#2346]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank@b-dp1:
    - shard-apl:          [FAIL][75] ([i915#79]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-apl:          [DMESG-WARN][77] ([i915#180]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-apl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-ts-check@a-edp1:
    - shard-skl:          [FAIL][79] ([i915#2122]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-skl4/igt@kms_flip@plain-flip-ts-check@a-edp1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-skl4/igt@kms_flip@plain-flip-ts-check@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - {shard-rkl}:        [SKIP][81] ([i915#1849] / [i915#4098]) -> [PASS][82] +13 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_properties@plane-properties-atomic:
    - {shard-rkl}:        [SKIP][83] ([i915#1849]) -> [PASS][84] +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-5/igt@kms_properties@plane-properties-atomic.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html

  * igt@kms_psr@cursor_render:
    - {shard-rkl}:        [SKIP][85] ([i915#1072]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-5/igt@kms_psr@cursor_render.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_psr@cursor_render.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][87] ([fdo#109441]) -> [PASS][88] +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - {shard-rkl}:        [SKIP][89] ([i915#5461]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglb:         [SKIP][91] ([i915#5519]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-tglb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-tglb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b:
    - {shard-rkl}:        [SKIP][93] ([i915#4098]) -> [PASS][94] +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html

  * igt@kms_vblank@pipe-b-query-idle:
    - {shard-rkl}:        [SKIP][95] ([i915#1845] / [i915#4098]) -> [PASS][96] +27 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@kms_vblank@pipe-b-query-idle.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html

  * igt@prime_vgem@basic-fence-flip:
    - {shard-rkl}:        [SKIP][97] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@prime_vgem@basic-fence-flip.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-read:
    - {shard-rkl}:        [SKIP][99] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-rkl-4/igt@prime_vgem@basic-fence-read.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-rkl-5/igt@prime_vgem@basic-fence-read.html

  
#### Warnings ####

  * igt@gem_pread@exhaustion:
    - shard-tglb:         [WARN][101] ([i915#2658]) -> [INCOMPLETE][102] ([i915#7248])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-tglb2/igt@gem_pread@exhaustion.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-tglb6/igt@gem_pread@exhaustion.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
    - shard-iclb:         [SKIP][103] ([i915#658]) -> [SKIP][104] ([i915#2920]) +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-iclb:         [SKIP][105] ([i915#2920]) -> [SKIP][106] ([fdo#111068] / [i915#658])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12417/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/shard-iclb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5584]: https://gitlab.freedesktop.org/drm/intel/issues/5584
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
  [i915#7318]: https://gitlab.freedesktop.org/drm/intel/issues/7318
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12417 -> Patchwork_111191v1

  CI-20190529: 20190529
  CI_DRM_12417: 146bf59b0038cbb0c1665088db64c46c1d420630 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7071: 0801475083ccb938b1d3b358502ff97fdb435585 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111191v1: 146bf59b0038cbb0c1665088db64c46c1d420630 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111191v1/index.html

[-- Attachment #2: Type: text/html, Size: 29523 bytes --]

Re: [Intel-gfx] [PATCH 01/10] drm/i915/dvo/ch7xxx: Fix suspend/resume

[Ville Syrjälä]

On Tue, Nov 22, 2022 at 02:31:55PM +0200, Jani Nikula wrote:
> On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Poke a few more bits into the ch7xxx to make
> > it output a picture after being reset during S3.
> >
> > In particular we need to set the input buffer select (IBS),
> > and enable VGA vsync output on the BCO pin. Selecting
> > VGA hsync on the c/h sync pin doesn't actually seem necessary
> > on my ADD card at least, but the BIOS selects it so why not.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> First things first.
> 
> I'll r-b anything that I've actually reviewed in the series, although
> the subject matter being what it is, I may not have reviewed it as
> thoroughly as I would other code that I review.
> 
> If r-b would require me to look stuff up in the specs, I really couldn't
> be bothered, so I'll just a-b that stuff if it looks reasonable. I don't
> think anyone else is going to show up for review either, and if you end
> up breaking something, I think you're the only one to show up to fix it
> anyway.
> 
> Fair enough?

Yeah, I think acks are good enough for these in general.

> 
> With that, this patch is
> 
> Acked-by: Jani Nikula <jani.nikula@intel.com>

Thanks. Series pushed now.

> 
> > ---
> >  drivers/gpu/drm/i915/display/dvo_ch7xxx.c | 22 ++++++++++++++++++++--
> >  1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> > index 54f58ba44b9f..6d948520e9a6 100644
> > --- a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> > +++ b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c
> > @@ -50,15 +50,26 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> >  #define CH7xxx_INPUT_CLOCK	0x1d
> >  #define CH7xxx_GPIO		0x1e
> >  #define CH7xxx_GPIO_HPIR	(1<<3)
> > +
> >  #define CH7xxx_IDF		0x1f
> > -
> > +#define CH7xxx_IDF_IBS		(1<<7)
> > +#define CH7xxx_IDF_DES		(1<<6)
> >  #define CH7xxx_IDF_HSP		(1<<3)
> >  #define CH7xxx_IDF_VSP		(1<<4)
> >  
> >  #define CH7xxx_CONNECTION_DETECT 0x20
> >  #define CH7xxx_CDET_DVI		(1<<5)
> >  
> > -#define CH7301_DAC_CNTL		0x21
> > +#define CH7xxx_DAC_CNTL		0x21
> > +#define CH7xxx_SYNCO_MASK	(3 << 3)
> > +#define CH7xxx_SYNCO_VGA_HSYNC	(1 << 3)
> > +
> > +#define CH7xxx_CLOCK_OUTPUT	0x22
> > +#define CH7xxx_BCOEN		(1 << 4)
> > +#define CH7xxx_BCOP		(1 << 3)
> > +#define CH7xxx_BCO_MASK		(7 << 0)
> > +#define CH7xxx_BCO_VGA_VSYNC	(6 << 0)
> > +
> >  #define CH7301_HOTPLUG		0x23
> >  #define CH7xxx_TCTL		0x31
> >  #define CH7xxx_TVCO		0x32
> > @@ -301,6 +312,8 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
> >  
> >  	ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
> >  
> > +	idf |= CH7xxx_IDF_IBS;
> > +
> >  	idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
> >  	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> >  		idf |= CH7xxx_IDF_HSP;
> > @@ -309,6 +322,11 @@ static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
> >  		idf |= CH7xxx_IDF_VSP;
> >  
> >  	ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
> > +
> > +	ch7xxx_writeb(dvo, CH7xxx_DAC_CNTL,
> > +		      CH7xxx_SYNCO_VGA_HSYNC);
> > +	ch7xxx_writeb(dvo, CH7xxx_CLOCK_OUTPUT,
> > +		      CH7xxx_BCOEN | CH7xxx_BCO_VGA_VSYNC);
> >  }
> >  
> >  /* set the CH7xxx power state */
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel