* [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
This patch series adds basic device tree support for StarFive JH7110 SoC.
This patch series depends on series [1] and [2]. You can simply get or
review the patches at the link [3].
[1]: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
[2]: https://lore.kernel.org/all/20221220005529.34744-1-hal.feng@starfivetech.com/
[3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Changes since v2:
- Rebased on tag v6.1.
- Dropped patch 8 because it was merged.
Patch 1:
- Made the links into "Link:" tags. (by Conor)
- Corrected the board name to "VisionFive 2" instead of
"VisionFive V2" and added compatibles for version A and
version B of VisionFive 2. (by Emil)
Patch 4:
- Used "sifive,ccache0" compatible string to match. (by Conor)
Patch 5:
- Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
- Dropped "starfive,jh7110-ccache" compatible in
drivers/soc/sifive/sifive_ccache.c.
Patch 6:
- Removed all "clock-frequency = <0>". (by Conor)
- Sorted the nodes after their addresses. (by Emil)
- Renamed "clk_rtc" to "rtc_osc".
- Added "sifive,ccache0" compatible in the cache-controller node.
- Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
renamed "apb_bus_func" to "apb_bus".
Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
- Removed "reg-names" in gpio nodes.
Patch 7:
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
- Renamed jh7110-starfive-visionfive-v2.dts to
jh7110-starfive-visionfive-2.dtsi.
- Added dts for VisionFive 2 version A and version B boards.
- In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
and changed the value of "stdout-path" to "serial0:115200n8".
- Changed the bias of uart0 "rx-pins" to
"bias-disable; /* external pull-up */".
- Renamed "clk_rtc" to "rtc_osc".
- Moved the gpio node behind the uart0 node.
v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
Changes since v1:
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series
should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
Rewrote clock-controller nodes and deleted reset-controller nodes for
using auxiliary bus. Rewrote gpio nodes following generic pinctrl
bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a
chosen node. Removed reserved-memory node. Added fixed frequency clock
nodes for overriding the "clock-frequency" properties. Rewrote the gpio
nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.
v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
Emil Renner Berthing (7):
dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
soc: sifive: ccache: Add StarFive JH7110 support
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
tree
.../sifive,plic-1.0.0.yaml | 1 +
.../bindings/riscv/sifive,ccache0.yaml | 9 +-
.../devicetree/bindings/riscv/starfive.yaml | 6 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-2-va.dts | 13 +
.../jh7110-starfive-visionfive-2-vb.dts | 13 +
.../jh7110-starfive-visionfive-2.dtsi | 111 +++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 ++++++++++++++++++
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
11 files changed, 567 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476
prerequisite-patch-id: 4dc515731ce237184553c1606ffb3afaeb51c3d8
prerequisite-patch-id: 09c98554df52d17ba5fd604125f8cdd62cbe80d1
prerequisite-patch-id: a798370d170dc2bcc79ed86f741c21c1e6d87c78
prerequisite-patch-id: bd9fd8b5cb2376dc7a5e08e1a1fbb969cf475926
prerequisite-patch-id: c57ebb83bc43ccd2a8366ff166eb499da1e1d2cf
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: 94860423c7acc9025249d4bb36652a585bd0a797
prerequisite-patch-id: b5084253283929d9a6d0e66c350400c7c85d034d
prerequisite-patch-id: 6e369dbe9dca2785e4ea7d0b80e525e227a90a6e
prerequisite-patch-id: e08806183c152714c563f3a21c6d7b2f539c4d6e
prerequisite-patch-id: 79db8036abdc48fd36da227652ec62627a6b548b
prerequisite-patch-id: 06971b8e6bddc0e87e63bfdb0ce8bfb653bd73aa
prerequisite-patch-id: 16309a0e23811a2c55d2e56886de3e8eccc51554
prerequisite-patch-id: bf4f7ab0b6cfa90b6e49e66c7d75ed2eaaebbe78
prerequisite-patch-id: 38468d532e87867990055d3320679f18c5f52278
prerequisite-patch-id: 4710f2ac22dca0bdd9ff5d744d2c37cab3c74515
--
2.38.1
^ permalink raw reply [flat|nested] 112+ messages in thread
* [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
This patch series adds basic device tree support for StarFive JH7110 SoC.
This patch series depends on series [1] and [2]. You can simply get or
review the patches at the link [3].
[1]: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
[2]: https://lore.kernel.org/all/20221220005529.34744-1-hal.feng@starfivetech.com/
[3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Changes since v2:
- Rebased on tag v6.1.
- Dropped patch 8 because it was merged.
Patch 1:
- Made the links into "Link:" tags. (by Conor)
- Corrected the board name to "VisionFive 2" instead of
"VisionFive V2" and added compatibles for version A and
version B of VisionFive 2. (by Emil)
Patch 4:
- Used "sifive,ccache0" compatible string to match. (by Conor)
Patch 5:
- Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
- Dropped "starfive,jh7110-ccache" compatible in
drivers/soc/sifive/sifive_ccache.c.
Patch 6:
- Removed all "clock-frequency = <0>". (by Conor)
- Sorted the nodes after their addresses. (by Emil)
- Renamed "clk_rtc" to "rtc_osc".
- Added "sifive,ccache0" compatible in the cache-controller node.
- Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
renamed "apb_bus_func" to "apb_bus".
Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
- Removed "reg-names" in gpio nodes.
Patch 7:
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
- Renamed jh7110-starfive-visionfive-v2.dts to
jh7110-starfive-visionfive-2.dtsi.
- Added dts for VisionFive 2 version A and version B boards.
- In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
and changed the value of "stdout-path" to "serial0:115200n8".
- Changed the bias of uart0 "rx-pins" to
"bias-disable; /* external pull-up */".
- Renamed "clk_rtc" to "rtc_osc".
- Moved the gpio node behind the uart0 node.
v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
Changes since v1:
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series
should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
Rewrote clock-controller nodes and deleted reset-controller nodes for
using auxiliary bus. Rewrote gpio nodes following generic pinctrl
bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a
chosen node. Removed reserved-memory node. Added fixed frequency clock
nodes for overriding the "clock-frequency" properties. Rewrote the gpio
nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.
v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
Emil Renner Berthing (7):
dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
soc: sifive: ccache: Add StarFive JH7110 support
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
tree
.../sifive,plic-1.0.0.yaml | 1 +
.../bindings/riscv/sifive,ccache0.yaml | 9 +-
.../devicetree/bindings/riscv/starfive.yaml | 6 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-2-va.dts | 13 +
.../jh7110-starfive-visionfive-2-vb.dts | 13 +
.../jh7110-starfive-visionfive-2.dtsi | 111 +++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 ++++++++++++++++++
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
11 files changed, 567 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476
prerequisite-patch-id: 4dc515731ce237184553c1606ffb3afaeb51c3d8
prerequisite-patch-id: 09c98554df52d17ba5fd604125f8cdd62cbe80d1
prerequisite-patch-id: a798370d170dc2bcc79ed86f741c21c1e6d87c78
prerequisite-patch-id: bd9fd8b5cb2376dc7a5e08e1a1fbb969cf475926
prerequisite-patch-id: c57ebb83bc43ccd2a8366ff166eb499da1e1d2cf
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: 94860423c7acc9025249d4bb36652a585bd0a797
prerequisite-patch-id: b5084253283929d9a6d0e66c350400c7c85d034d
prerequisite-patch-id: 6e369dbe9dca2785e4ea7d0b80e525e227a90a6e
prerequisite-patch-id: e08806183c152714c563f3a21c6d7b2f539c4d6e
prerequisite-patch-id: 79db8036abdc48fd36da227652ec62627a6b548b
prerequisite-patch-id: 06971b8e6bddc0e87e63bfdb0ce8bfb653bd73aa
prerequisite-patch-id: 16309a0e23811a2c55d2e56886de3e8eccc51554
prerequisite-patch-id: bf4f7ab0b6cfa90b6e49e66c7d75ed2eaaebbe78
prerequisite-patch-id: 38468d532e87867990055d3320679f18c5f52278
prerequisite-patch-id: 4710f2ac22dca0bdd9ff5d744d2c37cab3c74515
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add device tree bindings for the StarFive JH7110 RISC-V SoC
and the VisionFive 2 board equipped with it.
VisionFive 2 board has version A and version B, which are
different in gmac and phy chip. The version A board has one
1000Mbps and one 100Mbps Ethernet ports while the version B
board has two 1000Mbps Ethernet ports.
Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 5b36243fd674..fbe3c012dadf 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -22,6 +22,12 @@ properties:
- const: beagle,beaglev-starlight-jh7100-r0
- const: starfive,jh7100
+ - items:
+ - enum:
+ - starfive,visionfive-2-va
+ - starfive,visionfive-2-vb
+ - const: starfive,jh7110
+
additionalProperties: true
...
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add device tree bindings for the StarFive JH7110 RISC-V SoC
and the VisionFive 2 board equipped with it.
VisionFive 2 board has version A and version B, which are
different in gmac and phy chip. The version A board has one
1000Mbps and one 100Mbps Ethernet ports while the version B
board has two 1000Mbps Ethernet ports.
Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 5b36243fd674..fbe3c012dadf 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -22,6 +22,12 @@ properties:
- const: beagle,beaglev-starlight-jh7100-r0
- const: starfive,jh7100
+ - items:
+ - enum:
+ - starfive,visionfive-2-va
+ - starfive,visionfive-2-vb
+ - const: starfive,jh7110
+
additionalProperties: true
...
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for the StarFive JH7110 clint.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad24165837..a9580191f78b 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -27,6 +27,7 @@ properties:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
+ - starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
- items:
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for the StarFive JH7110 clint.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad24165837..a9580191f78b 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -27,6 +27,7 @@ properties:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
+ - starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
- items:
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for StarFive JH7110 plic.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..571700d5cb9e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for StarFive JH7110 plic.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..571700d5cb9e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
This cache controller is also used on the StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..31d20efaa6d3 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -38,6 +38,10 @@ properties:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
+ - items:
+ - const: starfive,jh7110-ccache
+ - const: sifive,ccache0
+ - const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
@@ -85,6 +89,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
- microchip,mpfs-ccache
then:
@@ -105,7 +110,9 @@ allOf:
properties:
compatible:
contains:
- const: sifive,fu740-c000-ccache
+ enum:
+ - sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
then:
properties:
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
This cache controller is also used on the StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..31d20efaa6d3 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -38,6 +38,10 @@ properties:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
+ - items:
+ - const: starfive,jh7110-ccache
+ - const: sifive,ccache0
+ - const: cache
- items:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
@@ -85,6 +89,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
- microchip,mpfs-ccache
then:
@@ -105,7 +110,9 @@ allOf:
properties:
compatible:
contains:
- const: sifive,fu740-c000-ccache
+ enum:
+ - sifive,fu740-c000-ccache
+ - starfive,jh7110-ccache
then:
properties:
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
-obj-$(CONFIG_SOC_SIFIVE) += sifive/
+obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index ed4c571f8771..e86870be34c9 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
config SIFIVE_CCACHE
bool "Sifive Composable Cache controller"
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/soc/Makefile | 2 +-
drivers/soc/sifive/Kconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508cf2c..534669840858 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -26,7 +26,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
-obj-$(CONFIG_SOC_SIFIVE) += sifive/
+obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index ed4c571f8771..e86870be34c9 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-if SOC_SIFIVE
+if SOC_SIFIVE || SOC_STARFIVE
config SIFIVE_CCACHE
bool "Sifive Composable Cache controller"
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
1 file changed, 411 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..64d260ea1f29
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S76_0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&S76_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+
+ core2 {
+ cpu = <&U74_2>;
+ };
+
+ core3 {
+ cpu = <&U74_3>;
+ };
+
+ core4 {
+ cpu = <&U74_4>;
+ };
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ rtc_osc: rtc_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rmii_refin: gmac1_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2stx_bclk_ext: i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2stx_lrck_ext: i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2srx_bclk_ext: i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2srx_lrck_ext: i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ tdm_ext: tdm_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ mclk_ext: mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: clint@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: plic@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ syscrg: clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpio: gpio@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+ resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+ interrupts = <86>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+ clocks = <&osc>, <&rtc_osc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpioa: gpio@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ resets = <&aoncrg JH7110_AONRST_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
1 file changed, 411 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..64d260ea1f29
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S76_0: cpu@0 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&S76_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+
+ core2 {
+ cpu = <&U74_2>;
+ };
+
+ core3 {
+ cpu = <&U74_3>;
+ };
+
+ core4 {
+ cpu = <&U74_4>;
+ };
+ };
+ };
+ };
+
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ rtc_osc: rtc_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rmii_refin: gmac1_rmii_refin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2stx_bclk_ext: i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2stx_lrck_ext: i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2srx_bclk_ext: i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ i2srx_lrck_ext: i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ tdm_ext: tdm_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ mclk_ext: mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: clint@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: plic@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ syscrg: clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpio: gpio@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+ resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+ interrupts = <86>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+ clocks = <&osc>, <&rtc_osc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpioa: gpio@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ resets = <&aoncrg JH7110_AONRST_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
--
2.38.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 1:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-2-va.dts | 13 ++
.../jh7110-starfive-visionfive-2-vb.dts | 13 ++
.../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
4 files changed, 138 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0ea1bc15ab30..79e925a4a227 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
new file mode 100644
index 000000000000..188d3fddbe88
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 VA";
+ compatible = "starfive,visionfive-2-va", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
new file mode 100644
index 000000000000..f75c10536f84
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 VB";
+ compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
new file mode 100644
index 000000000000..c60280b89c73
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&gpio {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 112+ messages in thread
* [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2022-12-20 1:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-20 1:12 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, Hal Feng,
linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
.../jh7110-starfive-visionfive-2-va.dts | 13 ++
.../jh7110-starfive-visionfive-2-vb.dts | 13 ++
.../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
4 files changed, 138 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 0ea1bc15ab30..79e925a4a227 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
new file mode 100644
index 000000000000..188d3fddbe88
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 VA";
+ compatible = "starfive,visionfive-2-va", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
new file mode 100644
index 000000000000..f75c10536f84
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 VB";
+ compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
new file mode 100644
index 000000000000..c60280b89c73
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&gpio {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+};
--
2.38.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 10:05 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:05 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 20/12/2022 02:12, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC
> and the VisionFive 2 board equipped with it.
>
> VisionFive 2 board has version A and version B, which are
> different in gmac and phy chip. The version A board has one
> 1000Mbps and one 100Mbps Ethernet ports while the version B
> board has two 1000Mbps Ethernet ports.
>
> Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
I assume you did not add my tag because of changes?
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
@ 2022-12-20 10:05 ` Krzysztof Kozlowski
0 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:05 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 20/12/2022 02:12, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC
> and the VisionFive 2 board equipped with it.
>
> VisionFive 2 board has version A and version B, which are
> different in gmac and phy chip. The version A board has one
> 1000Mbps and one 100Mbps Ethernet ports while the version B
> board has two 1000Mbps Ethernet ports.
>
> Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
I assume you did not add my tag because of changes?
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 10:10 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:10 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 20/12/2022 02:12, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..64d260ea1f29
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_2: cpu@2 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <2>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_3: cpu@3 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <3>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_4: cpu@4 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <4>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> +
> + osc: osc {
Node names should be generic, so why this is "osc" and other oscillators
are not "osc"?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + rtc_osc: rtc_osc {
No underscores in node names. Generic node names (so each of them
starting or ending with clock).
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
Same problem... and actually you have way too many fixed clocks which do
nothing. It looks like you avoid to define proper clock controller.
What's the point for all these clocks? These are no-op.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clint: clint@2000000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "starfive,jh7110-clint", "sifive,clint0";
> + reg = <0x0 0x2000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>;
> + };
> +
> + plic: plic@c000000 {
Node names should be generic, so interrupt-controller
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + riscv,ndev = <136>;
> + };
> +
> + ccache: cache-controller@2010000 {
> + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
> + reg = <0x0 0x2010000 0x0 0x4000>;
> + interrupts = <1>, <3>, <4>, <2>;
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + };
> +
> + uart0: serial@10000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART0_APB>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-20 10:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:10 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 20/12/2022 02:12, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..64d260ea1f29
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_2: cpu@2 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <2>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_3: cpu@3 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <3>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_4: cpu@4 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <4>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> +
> + osc: osc {
Node names should be generic, so why this is "osc" and other oscillators
are not "osc"?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + rtc_osc: rtc_osc {
No underscores in node names. Generic node names (so each of them
starting or ending with clock).
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rmii_refin: gmac0_rmii_refin {
Same problem... and actually you have way too many fixed clocks which do
nothing. It looks like you avoid to define proper clock controller.
What's the point for all these clocks? These are no-op.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac1_rmii_refin: gmac1_rmii_refin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2stx_bclk_ext: i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2stx_lrck_ext: i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2srx_bclk_ext: i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + i2srx_lrck_ext: i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + tdm_ext: tdm_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + mclk_ext: mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clint: clint@2000000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "starfive,jh7110-clint", "sifive,clint0";
> + reg = <0x0 0x2000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>;
> + };
> +
> + plic: plic@c000000 {
Node names should be generic, so interrupt-controller
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + riscv,ndev = <136>;
> + };
> +
> + ccache: cache-controller@2010000 {
> + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
> + reg = <0x0 0x2010000 0x0 0x4000>;
> + interrupts = <1>, <3>, <4>, <2>;
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <2097152>;
> + cache-unified;
> + };
> +
> + uart0: serial@10000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x10000000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
> + <&syscrg JH7110_SYSCLK_UART0_APB>;
> + clock-names = "baudclk", "apb_pclk";
> + resets = <&syscrg JH7110_SYSRST_UART0_APB>;
> + interrupts = <32>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 20:21 ` Rob Herring
-1 siblings, 0 replies; 112+ messages in thread
From: Rob Herring @ 2022-12-20 20:21 UTC (permalink / raw)
To: Hal Feng
Cc: Paul Walmsley, Daniel Lezcano, Rob Herring, Stephen Boyd,
Emil Renner Berthing, linux-riscv, Krzysztof Kozlowski,
Thomas Gleixner, Michael Turquette, Philipp Zabel, Marc Zyngier,
Linus Walleij, Ben Dooks, devicetree, linux-kernel, Albert Ou,
Palmer Dabbelt, Conor Dooley
On Tue, 20 Dec 2022 09:12:44 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> This cache controller is also used on the StarFive JH7110 SoC.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
@ 2022-12-20 20:21 ` Rob Herring
0 siblings, 0 replies; 112+ messages in thread
From: Rob Herring @ 2022-12-20 20:21 UTC (permalink / raw)
To: Hal Feng
Cc: Paul Walmsley, Daniel Lezcano, Rob Herring, Stephen Boyd,
Emil Renner Berthing, linux-riscv, Krzysztof Kozlowski,
Thomas Gleixner, Michael Turquette, Philipp Zabel, Marc Zyngier,
Linus Walleij, Ben Dooks, devicetree, linux-kernel, Albert Ou,
Palmer Dabbelt, Conor Dooley
On Tue, 20 Dec 2022 09:12:44 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> This cache controller is also used on the StarFive JH7110 SoC.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 20:58 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 20:58 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Tue, Dec 20, 2022 at 09:12:41AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC
> and the VisionFive 2 board equipped with it.
>
> VisionFive 2 board has version A and version B, which are
> different in gmac and phy chip. The version A board has one
> 1000Mbps and one 100Mbps Ethernet ports while the version B
> board has two 1000Mbps Ethernet ports.
>
> Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Unless Emil objects, I'll queue this for 6.3 once -rc1 has been tagged.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
@ 2022-12-20 20:58 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 20:58 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 792 bytes --]
On Tue, Dec 20, 2022 at 09:12:41AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add device tree bindings for the StarFive JH7110 RISC-V SoC
> and the VisionFive 2 board equipped with it.
>
> VisionFive 2 board has version A and version B, which are
> different in gmac and phy chip. The version A board has one
> 1000Mbps and one 100Mbps Ethernet ports while the version B
> board has two 1000Mbps Ethernet ports.
>
> Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Unless Emil objects, I'll queue this for 6.3 once -rc1 has been tagged.
Thanks,
Conor.
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 21:14 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:14 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Tue, Dec 20, 2022 at 09:12:45AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> This adds support for the StarFive JH7110 SoC which also
> features this SiFive cache controller.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
I'll queue this and the ccache binding for v6.3 once -rc1 is tagged,
once again with the caveat that screaming from Emil with dissuade me.
Ordinarily, I'd wait for his R-b, but he is the author..
Thanks,
Conor.
> ---
> drivers/soc/Makefile | 2 +-
> drivers/soc/sifive/Kconfig | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 69ba6508cf2c..534669840858 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -26,7 +26,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> +obj-y += sifive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index ed4c571f8771..e86870be34c9 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -if SOC_SIFIVE
> +if SOC_SIFIVE || SOC_STARFIVE
>
> config SIFIVE_CCACHE
> bool "Sifive Composable Cache controller"
> --
> 2.38.1
>
>
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support
@ 2022-12-20 21:14 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:14 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1536 bytes --]
On Tue, Dec 20, 2022 at 09:12:45AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> This adds support for the StarFive JH7110 SoC which also
> features this SiFive cache controller.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
I'll queue this and the ccache binding for v6.3 once -rc1 is tagged,
once again with the caveat that screaming from Emil with dissuade me.
Ordinarily, I'd wait for his R-b, but he is the author..
Thanks,
Conor.
> ---
> drivers/soc/Makefile | 2 +-
> drivers/soc/sifive/Kconfig | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 69ba6508cf2c..534669840858 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -26,7 +26,7 @@ obj-y += qcom/
> obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> -obj-$(CONFIG_SOC_SIFIVE) += sifive/
> +obj-y += sifive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
> index ed4c571f8771..e86870be34c9 100644
> --- a/drivers/soc/sifive/Kconfig
> +++ b/drivers/soc/sifive/Kconfig
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -if SOC_SIFIVE
> +if SOC_SIFIVE || SOC_STARFIVE
>
> config SIFIVE_CCACHE
> bool "Sifive Composable Cache controller"
> --
> 2.38.1
>
>
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 21:26 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:26 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3758 bytes --]
On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> which has version A and version B. Support booting and basic
> clock/reset/pinctrl/uart drivers.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> 4 files changed, 138 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 0ea1bc15ab30..79e925a4a227 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
Could you rebase on top of v6.2-rc1 when you submit your next version
squash this in please (unless Emil hates it):
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index c38a9ade7f48..b3744420253a 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
-dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb
I'd rather have more, but easier to read lines than long ones.
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> new file mode 100644
> index 000000000000..c60280b89c73
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
Anyways, I can't review this as I've got neither board nor
documentation, so with the above stuff sorted out:
Acked-by: Conor Dooley <conor.dooley@microchip.com>
I'll not apply it until the clock binding header is in my tree.
Thanks,
Conor.
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^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2022-12-20 21:26 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:26 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3758 bytes --]
On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> which has version A and version B. Support booting and basic
> clock/reset/pinctrl/uart drivers.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> 4 files changed, 138 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 0ea1bc15ab30..79e925a4a227 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
Could you rebase on top of v6.2-rc1 when you submit your next version
squash this in please (unless Emil hates it):
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index c38a9ade7f48..b3744420253a 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
-dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb
I'd rather have more, but easier to read lines than long ones.
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> new file mode 100644
> index 000000000000..c60280b89c73
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
Anyways, I can't review this as I've got neither board nor
documentation, so with the above stuff sorted out:
Acked-by: Conor Dooley <conor.dooley@microchip.com>
I'll not apply it until the clock binding header is in my tree.
Thanks,
Conor.
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-20 21:31 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:31 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2007 bytes --]
On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
FWIW, this cpu-map is now the default in linux, so you no longer *need*
to add it for that purpose - but there's obviously no harm in being
explicit for other operating systems etc. (IOW, don't remove it!)
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> + syscrg: clock-controller@13020000 {
For obvious reasons, I cannot apply this until both the clock & pinctrl
bindings are in my tree - but you know that already.
> + compatible = "starfive,jh7110-syscrg";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> + clocks = <&osc>, <&gmac1_rmii_refin>,
> + <&gmac1_rgmii_rxin>,
> + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> + <&tdm_ext>, <&mclk_ext>;
As Krzk asked - are these clocks really all inputs to the SoC?
> + clock-names = "osc", "gmac1_rmii_refin",
> + "gmac1_rgmii_rxin",
> + "i2stx_bclk_ext", "i2stx_lrck_ext",
> + "i2srx_bclk_ext", "i2srx_lrck_ext",
> + "tdm_ext", "mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + gpio: gpio@13040000 {
> + gpioa: gpio@17020000 {
Out of curiousity, why gpio & gpioa?
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-20 21:31 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-20 21:31 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2007 bytes --]
On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
FWIW, this cpu-map is now the default in linux, so you no longer *need*
to add it for that purpose - but there's obviously no harm in being
explicit for other operating systems etc. (IOW, don't remove it!)
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&S76_0>;
> + };
> +
> + core1 {
> + cpu = <&U74_1>;
> + };
> +
> + core2 {
> + cpu = <&U74_2>;
> + };
> +
> + core3 {
> + cpu = <&U74_3>;
> + };
> +
> + core4 {
> + cpu = <&U74_4>;
> + };
> + };
> + };
> + };
> + syscrg: clock-controller@13020000 {
For obvious reasons, I cannot apply this until both the clock & pinctrl
bindings are in my tree - but you know that already.
> + compatible = "starfive,jh7110-syscrg";
> + reg = <0x0 0x13020000 0x0 0x10000>;
> + clocks = <&osc>, <&gmac1_rmii_refin>,
> + <&gmac1_rgmii_rxin>,
> + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> + <&tdm_ext>, <&mclk_ext>;
As Krzk asked - are these clocks really all inputs to the SoC?
> + clock-names = "osc", "gmac1_rmii_refin",
> + "gmac1_rgmii_rxin",
> + "i2stx_bclk_ext", "i2stx_lrck_ext",
> + "i2srx_bclk_ext", "i2srx_lrck_ext",
> + "tdm_ext", "mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + gpio: gpio@13040000 {
> + gpioa: gpio@17020000 {
Out of curiousity, why gpio & gpioa?
Thanks,
Conor.
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linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
2022-12-20 10:05 ` Krzysztof Kozlowski
@ 2022-12-23 2:05 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 2:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 11:05:51 +0100, Krzysztof Kozlowski wrote:
> On 20/12/2022 02:12, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC
> > and the VisionFive 2 board equipped with it.
> >
> > VisionFive 2 board has version A and version B, which are
> > different in gmac and phy chip. The version A board has one
> > 1000Mbps and one 100Mbps Ethernet ports while the version B
> > board has two 1000Mbps Ethernet ports.
> >
> > Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> I assume you did not add my tag because of changes?
Yes, it might not the original one to which you wanna add the
Acked-by tag.
Best regards,
Hal
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
@ 2022-12-23 2:05 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 2:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 11:05:51 +0100, Krzysztof Kozlowski wrote:
> On 20/12/2022 02:12, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC
> > and the VisionFive 2 board equipped with it.
> >
> > VisionFive 2 board has version A and version B, which are
> > different in gmac and phy chip. The version A board has one
> > 1000Mbps and one 100Mbps Ethernet ports while the version B
> > board has two 1000Mbps Ethernet ports.
> >
> > Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> I assume you did not add my tag because of changes?
Yes, it might not the original one to which you wanna add the
Acked-by tag.
Best regards,
Hal
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
2022-12-20 20:58 ` Conor Dooley
@ 2022-12-23 2:15 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 2:15 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 20:58:38 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:41AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC
> > and the VisionFive 2 board equipped with it.
> >
> > VisionFive 2 board has version A and version B, which are
> > different in gmac and phy chip. The version A board has one
> > 1000Mbps and one 100Mbps Ethernet ports while the version B
> > board has two 1000Mbps Ethernet ports.
> >
> > Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> Unless Emil objects, I'll queue this for 6.3 once -rc1 has been tagged.
Thank you so much.
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
@ 2022-12-23 2:15 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 2:15 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 20:58:38 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:41AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add device tree bindings for the StarFive JH7110 RISC-V SoC
> > and the VisionFive 2 board equipped with it.
> >
> > VisionFive 2 board has version A and version B, which are
> > different in gmac and phy chip. The version A board has one
> > 1000Mbps and one 100Mbps Ethernet ports while the version B
> > board has two 1000Mbps Ethernet ports.
> >
> > Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
> > Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> Unless Emil objects, I'll queue this for 6.3 once -rc1 has been tagged.
Thank you so much.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-20 21:26 ` Conor Dooley
@ 2022-12-23 3:12 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 3:12 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > which has version A and version B. Support booting and basic
> > clock/reset/pinctrl/uart drivers.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/Makefile | 1 +
> > .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> > .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> > .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> > 4 files changed, 138 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > index 0ea1bc15ab30..79e925a4a227 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -1,2 +1,3 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
>
> Could you rebase on top of v6.2-rc1 when you submit your next version
Sure.
> squash this in please (unless Emil hates it):
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index c38a9ade7f48..b3744420253a 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb
>
> I'd rather have more, but easier to read lines than long ones.
I'm fine with this change. If no objection, I will modify it.
Best regards,
Hal
>
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > new file mode 100644
> > index 000000000000..c60280b89c73
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include "jh7110-pinfunc.h"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + cpus {
> > + timebase-frequency = <4000000>;
> > + };
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x40000000 0x1 0x0>;
>
> Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
The VisionFive 2 board only has 4GB version and 8GB version now. Before
linux startup, we will change this property in dtb through u-boot to
make sure the board can boot up with the correct memory size.
Best regards,
Hal
>
> Anyways, I can't review this as I've got neither board nor
> documentation, so with the above stuff sorted out:
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> I'll not apply it until the clock binding header is in my tree.
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2022-12-23 3:12 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-23 3:12 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > which has version A and version B. Support booting and basic
> > clock/reset/pinctrl/uart drivers.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/Makefile | 1 +
> > .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> > .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> > .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> > 4 files changed, 138 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > index 0ea1bc15ab30..79e925a4a227 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -1,2 +1,3 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> > +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
>
> Could you rebase on top of v6.2-rc1 when you submit your next version
Sure.
> squash this in please (unless Emil hates it):
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index c38a9ade7f48..b3744420253a 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-vb.dtb
>
> I'd rather have more, but easier to read lines than long ones.
I'm fine with this change. If no objection, I will modify it.
Best regards,
Hal
>
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > new file mode 100644
> > index 000000000000..c60280b89c73
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include "jh7110-pinfunc.h"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + cpus {
> > + timebase-frequency = <4000000>;
> > + };
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x40000000 0x1 0x0>;
>
> Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
The VisionFive 2 board only has 4GB version and 8GB version now. Before
linux startup, we will change this property in dtb through u-boot to
make sure the board can boot up with the correct memory size.
Best regards,
Hal
>
> Anyways, I can't review this as I've got neither board nor
> documentation, so with the above stuff sorted out:
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> I'll not apply it until the clock binding header is in my tree.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 10:10 ` Krzysztof Kozlowski
@ 2022-12-25 10:31 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-25 10:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 11:10:11 +0100, Krzysztof Kozlowski wrote:
> On 20/12/2022 02:12, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu1_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_2: cpu@2 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <2>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu2_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_3: cpu@3 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <3>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu3_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_4: cpu@4 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <4>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu4_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&S76_0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&U74_1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&U74_2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&U74_3>;
>> + };
>> +
>> + core4 {
>> + cpu = <&U74_4>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + osc: osc {
>
> Node names should be generic, so why this is "osc" and other oscillators
> are not "osc"?
Only "osc" and "rtc_osc" are oscillators, the rest are clock sources provided
through gpio. I will modify the node names according to your link below. So
osc: oscillator {
>
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + rtc_osc: rtc_osc {
>
> No underscores in node names. Generic node names (so each of them
> starting or ending with clock).
Will change this line to
rtc_osc: oscillator {
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rmii_refin: gmac0_rmii_refin {
>
> Same problem... and actually you have way too many fixed clocks which do
Will change the node names as follows.
gmac0_rmii_refin: clock {
...
};
gmac0_rgmii_rxin: clock {
...
};
...
> nothing. It looks like you avoid to define proper clock controller.
> What's the point for all these clocks? These are no-op.
These are all external fixed rate clocks inputted to the SoC. They are the root
clocks of the clock tree made by clock drivers. Their ops are provided in
drivers/clk/clk-fixed-rate.c.
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rmii_refin: gmac1_rmii_refin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_bclk_ext: i2stx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_lrck_ext: i2stx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_bclk_ext: i2srx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_lrck_ext: i2srx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + tdm_ext: tdm_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + mclk_ext: mclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clint: clint@2000000 {
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
clint: timer@2000000 {
>
>> + compatible = "starfive,jh7110-clint", "sifive,clint0";
>> + reg = <0x0 0x2000000 0x0 0x10000>;
>> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
>> + <&cpu1_intc 3>, <&cpu1_intc 7>,
>> + <&cpu2_intc 3>, <&cpu2_intc 7>,
>> + <&cpu3_intc 3>, <&cpu3_intc 7>,
>> + <&cpu4_intc 3>, <&cpu4_intc 7>;
>> + };
>> +
>> + plic: plic@c000000 {
>
> Node names should be generic, so interrupt-controller
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
plic: interrupt-controller@c000000 {
Best regards,
Hal
>
>> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> + <&cpu1_intc 11>, <&cpu1_intc 9>,
>> + <&cpu2_intc 11>, <&cpu2_intc 9>,
>> + <&cpu3_intc 11>, <&cpu3_intc 9>,
>> + <&cpu4_intc 11>, <&cpu4_intc 9>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + #address-cells = <0>;
>> + riscv,ndev = <136>;
>> + };
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-25 10:31 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-25 10:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 11:10:11 +0100, Krzysztof Kozlowski wrote:
> On 20/12/2022 02:12, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu1_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_2: cpu@2 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <2>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu2_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_3: cpu@3 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <3>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu3_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_4: cpu@4 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <4>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu4_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&S76_0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&U74_1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&U74_2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&U74_3>;
>> + };
>> +
>> + core4 {
>> + cpu = <&U74_4>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + osc: osc {
>
> Node names should be generic, so why this is "osc" and other oscillators
> are not "osc"?
Only "osc" and "rtc_osc" are oscillators, the rest are clock sources provided
through gpio. I will modify the node names according to your link below. So
osc: oscillator {
>
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + rtc_osc: rtc_osc {
>
> No underscores in node names. Generic node names (so each of them
> starting or ending with clock).
Will change this line to
rtc_osc: oscillator {
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rmii_refin: gmac0_rmii_refin {
>
> Same problem... and actually you have way too many fixed clocks which do
Will change the node names as follows.
gmac0_rmii_refin: clock {
...
};
gmac0_rgmii_rxin: clock {
...
};
...
> nothing. It looks like you avoid to define proper clock controller.
> What's the point for all these clocks? These are no-op.
These are all external fixed rate clocks inputted to the SoC. They are the root
clocks of the clock tree made by clock drivers. Their ops are provided in
drivers/clk/clk-fixed-rate.c.
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rmii_refin: gmac1_rmii_refin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_bclk_ext: i2stx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_lrck_ext: i2stx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_bclk_ext: i2srx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_lrck_ext: i2srx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + tdm_ext: tdm_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + mclk_ext: mclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clint: clint@2000000 {
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
clint: timer@2000000 {
>
>> + compatible = "starfive,jh7110-clint", "sifive,clint0";
>> + reg = <0x0 0x2000000 0x0 0x10000>;
>> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
>> + <&cpu1_intc 3>, <&cpu1_intc 7>,
>> + <&cpu2_intc 3>, <&cpu2_intc 7>,
>> + <&cpu3_intc 3>, <&cpu3_intc 7>,
>> + <&cpu4_intc 3>, <&cpu4_intc 7>;
>> + };
>> +
>> + plic: plic@c000000 {
>
> Node names should be generic, so interrupt-controller
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
plic: interrupt-controller@c000000 {
Best regards,
Hal
>
>> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> + <&cpu1_intc 11>, <&cpu1_intc 9>,
>> + <&cpu2_intc 11>, <&cpu2_intc 9>,
>> + <&cpu3_intc 11>, <&cpu3_intc 9>,
>> + <&cpu4_intc 11>, <&cpu4_intc 9>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + #address-cells = <0>;
>> + riscv,ndev = <136>;
>> + };
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-25 10:31 ` Hal Feng
@ 2022-12-25 11:56 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-25 11:56 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 25/12/2022 11:31, Hal Feng wrote:
>
> gmac0_rmii_refin: clock {
> ...
> };
>
> gmac0_rgmii_rxin: clock {
> ...
> };
> ...
>
>> nothing. It looks like you avoid to define proper clock controller.
>> What's the point for all these clocks? These are no-op.
>
> These are all external fixed rate clocks inputted to the SoC. They are the root
If they are all external, then it is fine.
>
>>
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-25 11:56 ` Krzysztof Kozlowski
0 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-25 11:56 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On 25/12/2022 11:31, Hal Feng wrote:
>
> gmac0_rmii_refin: clock {
> ...
> };
>
> gmac0_rgmii_rxin: clock {
> ...
> };
> ...
>
>> nothing. It looks like you avoid to define proper clock controller.
>> What's the point for all these clocks? These are no-op.
>
> These are all external fixed rate clocks inputted to the SoC. They are the root
If they are all external, then it is fine.
>
>>
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + };
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 21:31 ` Conor Dooley
@ 2022-12-25 14:31 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-25 14:31 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
>
> FWIW, this cpu-map is now the default in linux, so you no longer *need*
> to add it for that purpose - but there's obviously no harm in being
> explicit for other operating systems etc. (IOW, don't remove it!)
>
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&S76_0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&U74_1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&U74_2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&U74_3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&U74_4>;
> > + };
> > + };
> > + };
> > + };
>
> > + syscrg: clock-controller@13020000 {
>
> For obvious reasons, I cannot apply this until both the clock & pinctrl
> bindings are in my tree - but you know that already.
>
> > + compatible = "starfive,jh7110-syscrg";
> > + reg = <0x0 0x13020000 0x0 0x10000>;
> > + clocks = <&osc>, <&gmac1_rmii_refin>,
> > + <&gmac1_rgmii_rxin>,
> > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> > + <&tdm_ext>, <&mclk_ext>;
>
> As Krzk asked - are these clocks really all inputs to the SoC?
Yes, they are all external clock sources inputted to the SoC. They are
used as root clocks or optional parent clocks in clock tree.
>
> > + clock-names = "osc", "gmac1_rmii_refin",
> > + "gmac1_rgmii_rxin",
> > + "i2stx_bclk_ext", "i2stx_lrck_ext",
> > + "i2srx_bclk_ext", "i2srx_lrck_ext",
> > + "tdm_ext", "mclk_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + gpio: gpio@13040000 {
>
> > + gpioa: gpio@17020000 {
>
> Out of curiousity, why gpio & gpioa?
Oh, is it easier to read if I change "gpio" and "gpioa"
to "sysgpio" and "aongpio"? Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-25 14:31 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2022-12-25 14:31 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
>
> FWIW, this cpu-map is now the default in linux, so you no longer *need*
> to add it for that purpose - but there's obviously no harm in being
> explicit for other operating systems etc. (IOW, don't remove it!)
>
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&S76_0>;
> > + };
> > +
> > + core1 {
> > + cpu = <&U74_1>;
> > + };
> > +
> > + core2 {
> > + cpu = <&U74_2>;
> > + };
> > +
> > + core3 {
> > + cpu = <&U74_3>;
> > + };
> > +
> > + core4 {
> > + cpu = <&U74_4>;
> > + };
> > + };
> > + };
> > + };
>
> > + syscrg: clock-controller@13020000 {
>
> For obvious reasons, I cannot apply this until both the clock & pinctrl
> bindings are in my tree - but you know that already.
>
> > + compatible = "starfive,jh7110-syscrg";
> > + reg = <0x0 0x13020000 0x0 0x10000>;
> > + clocks = <&osc>, <&gmac1_rmii_refin>,
> > + <&gmac1_rgmii_rxin>,
> > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> > + <&tdm_ext>, <&mclk_ext>;
>
> As Krzk asked - are these clocks really all inputs to the SoC?
Yes, they are all external clock sources inputted to the SoC. They are
used as root clocks or optional parent clocks in clock tree.
>
> > + clock-names = "osc", "gmac1_rmii_refin",
> > + "gmac1_rgmii_rxin",
> > + "i2stx_bclk_ext", "i2stx_lrck_ext",
> > + "i2srx_bclk_ext", "i2srx_lrck_ext",
> > + "tdm_ext", "mclk_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + gpio: gpio@13040000 {
>
> > + gpioa: gpio@17020000 {
>
> Out of curiousity, why gpio & gpioa?
Oh, is it easier to read if I change "gpio" and "gpioa"
to "sysgpio" and "aongpio"? Thanks.
Best regards,
Hal
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
2022-12-20 1:12 ` Hal Feng
@ 2022-12-26 23:01 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-26 23:01 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1142 bytes --]
On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> This patch series adds basic device tree support for StarFive JH7110 SoC.
> This patch series depends on series [1] and [2]. You can simply get or
> review the patches at the link [3].
> Emil Renner Berthing (7):
> dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
I've applied this one to riscv-dt-for-next
https://git.kernel.org/conor/c/97b7ed072784
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
> soc: sifive: ccache: Add StarFive JH7110 support
And these two to riscv-soc-for-next
https://git.kernel.org/conor/c/1caf002efa22
https://git.kernel.org/conor/c/6635e91648ce
> riscv: dts: starfive: Add initial StarFive JH7110 device tree
> riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
> tree
The rest I can take with maintainer Acks alongside the DT, or they can
go via subsystem trees.
The DT is waiting for the clock/reset & pinctrl binding headers anyway,
so IDC which it is.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
@ 2022-12-26 23:01 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-26 23:01 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1142 bytes --]
On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> This patch series adds basic device tree support for StarFive JH7110 SoC.
> This patch series depends on series [1] and [2]. You can simply get or
> review the patches at the link [3].
> Emil Renner Berthing (7):
> dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
I've applied this one to riscv-dt-for-next
https://git.kernel.org/conor/c/97b7ed072784
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
> soc: sifive: ccache: Add StarFive JH7110 support
And these two to riscv-soc-for-next
https://git.kernel.org/conor/c/1caf002efa22
https://git.kernel.org/conor/c/6635e91648ce
> riscv: dts: starfive: Add initial StarFive JH7110 device tree
> riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
> tree
The rest I can take with maintainer Acks alongside the DT, or they can
go via subsystem trees.
The DT is waiting for the clock/reset & pinctrl binding headers anyway,
so IDC which it is.
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
2022-12-26 23:01 ` Conor Dooley
@ 2022-12-27 7:58 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-27 7:58 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On 27/12/2022 00:01, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> The DT is waiting for the clock/reset & pinctrl binding headers anyway,
Which were sent with build warnings/errors...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
@ 2022-12-27 7:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 112+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-27 7:58 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On 27/12/2022 00:01, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> The DT is waiting for the clock/reset & pinctrl binding headers anyway,
Which were sent with build warnings/errors...
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
2022-12-27 7:58 ` Krzysztof Kozlowski
@ 2022-12-27 14:20 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-27 14:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Hal Feng, linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 516 bytes --]
On Tue, Dec 27, 2022 at 08:58:01AM +0100, Krzysztof Kozlowski wrote:
> On 27/12/2022 00:01, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> > The DT is waiting for the clock/reset & pinctrl binding headers anyway,
>
> Which were sent with build warnings/errors...
Yah, DW chief - I'm not in a rush. Figure it'll take a few more
iterations.
Errors/warnings aside, responding to the clock series again is in my
todo list, not convinced by the clock binding itself.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
@ 2022-12-27 14:20 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-27 14:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Hal Feng, linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 516 bytes --]
On Tue, Dec 27, 2022 at 08:58:01AM +0100, Krzysztof Kozlowski wrote:
> On 27/12/2022 00:01, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> > The DT is waiting for the clock/reset & pinctrl binding headers anyway,
>
> Which were sent with build warnings/errors...
Yah, DW chief - I'm not in a rush. Figure it'll take a few more
iterations.
Errors/warnings aside, responding to the clock series again is in my
todo list, not convinced by the clock binding itself.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-25 14:31 ` Hal Feng
@ 2022-12-27 20:58 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-27 20:58 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 967 bytes --]
On Sun, Dec 25, 2022 at 10:31:41PM +0800, Hal Feng wrote:
> On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel@esmil.dk>
> > >
> > > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > > Technology Ltd.
> > >
> > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > > + gpio: gpio@13040000 {
> >
> > > + gpioa: gpio@17020000 {
> >
> > Out of curiousity, why gpio & gpioa?
>
> Oh, is it easier to read if I change "gpio" and "gpioa"
> to "sysgpio" and "aongpio"? Thanks.
I think those would be more reader friendly, that's for sure.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-27 20:58 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-27 20:58 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 967 bytes --]
On Sun, Dec 25, 2022 at 10:31:41PM +0800, Hal Feng wrote:
> On Tue, 20 Dec 2022 21:31:43 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel@esmil.dk>
> > >
> > > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > > Technology Ltd.
> > >
> > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > > + gpio: gpio@13040000 {
> >
> > > + gpioa: gpio@17020000 {
> >
> > Out of curiousity, why gpio & gpioa?
>
> Oh, is it easier to read if I change "gpio" and "gpioa"
> to "sysgpio" and "aongpio"? Thanks.
I think those would be more reader friendly, that's for sure.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 1:12 ` Hal Feng
@ 2022-12-28 22:48 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-28 22:48 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3208 bytes --]
Hey,
On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..64d260ea1f29
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
The label here says S76 but the compatible says u74-mc.
Which is correct? Your docs say S7 and S76, so I would imagine that it
is actually an S76?
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
While I was poking around trying to see if there was some logic behind
that compatible, I noticed that SiFive's docs for the S76 say it is
RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
I assume that rv64imac is the correct one here?
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
That also begs the question:
Do your u74s support RV64GBC, as the (current) SiFive documentation
suggests?
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-28 22:48 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-28 22:48 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3208 bytes --]
Hey,
On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> new file mode 100644
> index 000000000000..64d260ea1f29
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +/ {
> + compatible = "starfive,jh7110";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + S76_0: cpu@0 {
> + compatible = "sifive,u74-mc", "riscv";
The label here says S76 but the compatible says u74-mc.
Which is correct? Your docs say S7 and S76, so I would imagine that it
is actually an S76?
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac";
While I was poking around trying to see if there was some logic behind
that compatible, I noticed that SiFive's docs for the S76 say it is
RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
I assume that rv64imac is the correct one here?
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + U74_1: cpu@1 {
> + compatible = "sifive,u74-mc", "riscv";
> + reg = <1>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imafdc";
That also begs the question:
Do your u74s support RV64GBC, as the (current) SiFive documentation
suggests?
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-23 3:12 ` Hal Feng
@ 2022-12-28 22:49 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-28 22:49 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2115 bytes --]
On Fri, Dec 23, 2022 at 11:12:34AM +0800, Hal Feng wrote:
> On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel@esmil.dk>
> > >
> > > Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > > which has version A and version B. Support booting and basic
> > > clock/reset/pinctrl/uart drivers.
> > >
> > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > > new file mode 100644
> > > index 000000000000..c60280b89c73
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > > @@ -0,0 +1,111 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "jh7110.dtsi"
> > > +#include "jh7110-pinfunc.h"
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +/ {
> > > + aliases {
> > > + serial0 = &uart0;
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial0:115200n8";
> > > + };
> > > +
> > > + cpus {
> > > + timebase-frequency = <4000000>;
> > > + };
> > > +
> > > + memory@40000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x40000000 0x1 0x0>;
> >
> > Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
>
> The VisionFive 2 board only has 4GB version and 8GB version now. Before
> linux startup, we will change this property in dtb through u-boot to
> make sure the board can boot up with the correct memory size.
Ah I see. Thanks.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2022-12-28 22:49 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-28 22:49 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2115 bytes --]
On Fri, Dec 23, 2022 at 11:12:34AM +0800, Hal Feng wrote:
> On Tue, 20 Dec 2022 21:26:07 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> > > From: Emil Renner Berthing <kernel@esmil.dk>
> > >
> > > Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > > which has version A and version B. Support booting and basic
> > > clock/reset/pinctrl/uart drivers.
> > >
> > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > > new file mode 100644
> > > index 000000000000..c60280b89c73
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > > @@ -0,0 +1,111 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include "jh7110.dtsi"
> > > +#include "jh7110-pinfunc.h"
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +/ {
> > > + aliases {
> > > + serial0 = &uart0;
> > > + };
> > > +
> > > + chosen {
> > > + stdout-path = "serial0:115200n8";
> > > + };
> > > +
> > > + cpus {
> > > + timebase-frequency = <4000000>;
> > > + };
> > > +
> > > + memory@40000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x40000000 0x1 0x0>;
> >
> > Is this a good idea when you have SKUs with 2, 4 & 8 GiB of DDR?
>
> The VisionFive 2 board only has 4GB version and 8GB version now. Before
> linux startup, we will change this property in dtb through u-boot to
> make sure the board can boot up with the correct memory size.
Ah I see. Thanks.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-28 22:48 ` Conor Dooley
@ 2022-12-29 5:25 ` Icenowy Zheng
-1 siblings, 0 replies; 112+ messages in thread
From: Icenowy Zheng @ 2022-12-29 5:25 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
> Hey,
>
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 411
> > +++++++++++++++++++++++
> > 1 file changed, 411 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..64d260ea1f29
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,411 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> > +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> > +
> > +/ {
> > + compatible = "starfive,jh7110";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + S76_0: cpu@0 {
> > + compatible = "sifive,u74-mc", "riscv";
>
> The label here says S76 but the compatible says u74-mc.
> Which is correct? Your docs say S7 and S76, so I would imagine that
> it
> is actually an S76?
>
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <8192>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <40>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <16384>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <40>;
> > + mmu-type = "riscv,sv39";
> > + next-level-cache = <&ccache>;
> > + riscv,isa = "rv64imac";
>
> While I was poking around trying to see if there was some logic
> behind
> that compatible, I noticed that SiFive's docs for the S76 say it is
> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> I assume that rv64imac is the correct one here?
>
> > + tlb-split;
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + U74_1: cpu@1 {
> > + compatible = "sifive,u74-mc", "riscv";
> > + reg = <1>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <40>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <40>;
> > + mmu-type = "riscv,sv39";
> > + next-level-cache = <&ccache>;
> > + riscv,isa = "rv64imafdc";
>
> That also begs the question:
> Do your u74s support RV64GBC, as the (current) SiFive documentation
> suggests?
It supports RV64GCZbaZbb.
B is not a well-defined thing by specifications, so it should be
prevented here.
>
> Thanks,
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-29 5:25 ` Icenowy Zheng
0 siblings, 0 replies; 112+ messages in thread
From: Icenowy Zheng @ 2022-12-29 5:25 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
> Hey,
>
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> >
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 411
> > +++++++++++++++++++++++
> > 1 file changed, 411 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > new file mode 100644
> > index 000000000000..64d260ea1f29
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -0,0 +1,411 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> > + */
> > +
> > +/dts-v1/;
> > +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> > +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> > +
> > +/ {
> > + compatible = "starfive,jh7110";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + S76_0: cpu@0 {
> > + compatible = "sifive,u74-mc", "riscv";
>
> The label here says S76 but the compatible says u74-mc.
> Which is correct? Your docs say S7 and S76, so I would imagine that
> it
> is actually an S76?
>
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <8192>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <40>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <16384>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <40>;
> > + mmu-type = "riscv,sv39";
> > + next-level-cache = <&ccache>;
> > + riscv,isa = "rv64imac";
>
> While I was poking around trying to see if there was some logic
> behind
> that compatible, I noticed that SiFive's docs for the S76 say it is
> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> I assume that rv64imac is the correct one here?
>
> > + tlb-split;
> > + status = "disabled";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + U74_1: cpu@1 {
> > + compatible = "sifive,u74-mc", "riscv";
> > + reg = <1>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <64>;
> > + d-cache-size = <32768>;
> > + d-tlb-sets = <1>;
> > + d-tlb-size = <40>;
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <64>;
> > + i-cache-size = <32768>;
> > + i-tlb-sets = <1>;
> > + i-tlb-size = <40>;
> > + mmu-type = "riscv,sv39";
> > + next-level-cache = <&ccache>;
> > + riscv,isa = "rv64imafdc";
>
> That also begs the question:
> Do your u74s support RV64GBC, as the (current) SiFive documentation
> suggests?
It supports RV64GCZbaZbb.
B is not a well-defined thing by specifications, so it should be
prevented here.
>
> Thanks,
> Conor.
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-29 5:25 ` Icenowy Zheng
@ 2022-12-29 9:02 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-29 9:02 UTC (permalink / raw)
To: Icenowy Zheng, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
Hey Icenowy, Hal
On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@icenowy.me> wrote:
>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@esmil.dk>
>> >
>> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> > Technology Ltd.
>> >
>> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> > ---
>> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 411
>> > +++++++++++++++++++++++
>> > 1 file changed, 411 insertions(+)
>> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > new file mode 100644
>> > index 000000000000..64d260ea1f29
>> > --- /dev/null
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -0,0 +1,411 @@
>> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> > +/*
>> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> > + */
>> > +
>> > +/dts-v1/;
>> > +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> > +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> > +
>> > +/ {
>> > + compatible = "starfive,jh7110";
>> > + #address-cells = <2>;
>> > + #size-cells = <2>;
>> > +
>> > + cpus {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + S76_0: cpu@0 {
>> > + compatible = "sifive,u74-mc", "riscv";
>>
>> The label here says S76 but the compatible says u74-mc.
>> Which is correct? Your docs say S7 and S76, so I would imagine that
>> it
>> is actually an S76?
>>
>> > + reg = <0>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <8192>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <16384>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imac";
>>
>> While I was poking around trying to see if there was some logic
>> behind
>> that compatible, I noticed that SiFive's docs for the S76 say it is
>> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
>> I assume that rv64imac is the correct one here?
>>
>> > + tlb-split;
>> > + status = "disabled";
>> > +
>> > + cpu0_intc: interrupt-controller {
>> > + compatible = "riscv,cpu-intc";
>> > + interrupt-controller;
>> > + #interrupt-cells = <1>;
>> > + };
>> > + };
>> > +
>> > + U74_1: cpu@1 {
>> > + compatible = "sifive,u74-mc", "riscv";
>> > + reg = <1>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
>It supports RV64GCZbaZbb.
Sweet, thanks.
>B is not a well-defined thing by specifications, so it should be
>prevented here.
Yah, don't worry - my next question was going to be which bits were supported :)
Hal, can you update the isa string in the next version please?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2022-12-29 9:02 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2022-12-29 9:02 UTC (permalink / raw)
To: Icenowy Zheng, Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
Hey Icenowy, Hal
On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@icenowy.me> wrote:
>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@esmil.dk>
>> >
>> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> > Technology Ltd.
>> >
>> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> > ---
>> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 411
>> > +++++++++++++++++++++++
>> > 1 file changed, 411 insertions(+)
>> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > new file mode 100644
>> > index 000000000000..64d260ea1f29
>> > --- /dev/null
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -0,0 +1,411 @@
>> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> > +/*
>> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> > + */
>> > +
>> > +/dts-v1/;
>> > +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> > +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> > +
>> > +/ {
>> > + compatible = "starfive,jh7110";
>> > + #address-cells = <2>;
>> > + #size-cells = <2>;
>> > +
>> > + cpus {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + S76_0: cpu@0 {
>> > + compatible = "sifive,u74-mc", "riscv";
>>
>> The label here says S76 but the compatible says u74-mc.
>> Which is correct? Your docs say S7 and S76, so I would imagine that
>> it
>> is actually an S76?
>>
>> > + reg = <0>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <8192>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <16384>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imac";
>>
>> While I was poking around trying to see if there was some logic
>> behind
>> that compatible, I noticed that SiFive's docs for the S76 say it is
>> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
>> I assume that rv64imac is the correct one here?
>>
>> > + tlb-split;
>> > + status = "disabled";
>> > +
>> > + cpu0_intc: interrupt-controller {
>> > + compatible = "riscv,cpu-intc";
>> > + interrupt-controller;
>> > + #interrupt-cells = <1>;
>> > + };
>> > + };
>> > +
>> > + U74_1: cpu@1 {
>> > + compatible = "sifive,u74-mc", "riscv";
>> > + reg = <1>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
>It supports RV64GCZbaZbb.
Sweet, thanks.
>B is not a well-defined thing by specifications, so it should be
>prevented here.
Yah, don't worry - my next question was going to be which bits were supported :)
Hal, can you update the isa string in the next version please?
Thanks,
Conor.
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-20 1:12 ` Hal Feng
@ 2023-01-10 17:59 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-10 17:59 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
So I think this is wrong, and the stdout-path should be uart3 instead.
Per the QSG [0], GPIO5/6 are the suggested UART Tx/Rx to use.
This appears to map to uart3 rather than uart0.
FWIW, uart3 is also the stdout-path for the v1, see:
arch/riscv/boot/dts/starfive/jh7100-common.dtsi
At least, that change is what I needed to do in order to use the
JH7110_VisionFive2_upstream branch, AFAICT matches what you've got in
this series.
Thanks,
Conor.
0 - https://doc-en.rvspace.org/VisionFive2/PDF/VisionFive2_QSG.pdf
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-01-10 17:59 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-10 17:59 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 682 bytes --]
On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
So I think this is wrong, and the stdout-path should be uart3 instead.
Per the QSG [0], GPIO5/6 are the suggested UART Tx/Rx to use.
This appears to map to uart3 rather than uart0.
FWIW, uart3 is also the stdout-path for the v1, see:
arch/riscv/boot/dts/starfive/jh7100-common.dtsi
At least, that change is what I needed to do in order to use the
JH7110_VisionFive2_upstream branch, AFAICT matches what you've got in
this series.
Thanks,
Conor.
0 - https://doc-en.rvspace.org/VisionFive2/PDF/VisionFive2_QSG.pdf
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-01-10 17:59 ` Conor Dooley
@ 2023-01-18 23:43 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-18 23:43 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1601 bytes --]
On Tue, Jan 10, 2023 at 05:59:09PM +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
>
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
>
> So I think this is wrong, and the stdout-path should be uart3 instead.
> Per the QSG [0], GPIO5/6 are the suggested UART Tx/Rx to use.
> This appears to map to uart3 rather than uart0.
> FWIW, uart3 is also the stdout-path for the v1, see:
> arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>
> At least, that change is what I needed to do in order to use the
> JH7110_VisionFive2_upstream branch, AFAICT matches what you've got in
> this series.
I went and re-tried things again today, but with the clk & pinctrl series
from the ML instead of that branch.
I'd gone and used that branch instead of the patches, as there were some
build issues with the pinctrl driver from the patches.
I fixed the build issues in the pinctrl driver and now uart0 works.
Looking at it again, it makes sense for uart0 to be serial0, given
there's pinconf stuff being done in this DT for pins 5 & 6 for uart0.
Perhaps by using that branch, I was using some older drivers etc given
it seems to mostly contain commits dating from November?
I'm still a bit confused about the whole thing, given I tried out a
whole load of branches to get something booting with ethernet support
that day!
Since this seems to work with the fixed pinctrl driver, I don't think
you need to change anything here.
Apologies for the noise!
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-01-18 23:43 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-18 23:43 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1601 bytes --]
On Tue, Jan 10, 2023 at 05:59:09PM +0000, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:47AM +0800, Hal Feng wrote:
>
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
>
> So I think this is wrong, and the stdout-path should be uart3 instead.
> Per the QSG [0], GPIO5/6 are the suggested UART Tx/Rx to use.
> This appears to map to uart3 rather than uart0.
> FWIW, uart3 is also the stdout-path for the v1, see:
> arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>
> At least, that change is what I needed to do in order to use the
> JH7110_VisionFive2_upstream branch, AFAICT matches what you've got in
> this series.
I went and re-tried things again today, but with the clk & pinctrl series
from the ML instead of that branch.
I'd gone and used that branch instead of the patches, as there were some
build issues with the pinctrl driver from the patches.
I fixed the build issues in the pinctrl driver and now uart0 works.
Looking at it again, it makes sense for uart0 to be serial0, given
there's pinconf stuff being done in this DT for pins 5 & 6 for uart0.
Perhaps by using that branch, I was using some older drivers etc given
it seems to mostly contain commits dating from November?
I'm still a bit confused about the whole thing, given I tried out a
whole load of branches to get something booting with ethernet support
that day!
Since this seems to work with the fixed pinctrl driver, I don't think
you need to change anything here.
Apologies for the noise!
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-20 1:12 ` Hal Feng
@ 2023-01-31 2:00 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-01-31 2:00 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
I wanna add i2c nodes (i2c0-6) in the next version, so someone else
can use them when they submit i2c driver patches.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-01-31 2:00 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-01-31 2:00 UTC (permalink / raw)
To: linux-riscv, devicetree
Cc: Conor Dooley, Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Albert Ou, Ben Dooks, Daniel Lezcano,
Thomas Gleixner, Marc Zyngier, Stephen Boyd, Michael Turquette,
Philipp Zabel, Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add initial device tree for the JH7110 RISC-V SoC by StarFive
> Technology Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
> 1 file changed, 411 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
I wanna add i2c nodes (i2c0-6) in the next version, so someone else
can use them when they submit i2c driver patches.
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-01-31 2:00 ` Hal Feng
@ 2023-01-31 6:17 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-31 6:17 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>can use them when they submit i2c driver patches.
All of the other series depend on this one for enablement,
so unless the binding for i2c is already upstream I'd advise keeping it separate.
Cheers,
Conor.
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-01-31 6:17 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-01-31 6:17 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>
>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>can use them when they submit i2c driver patches.
All of the other series depend on this one for enablement,
so unless the binding for i2c is already upstream I'd advise keeping it separate.
Cheers,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-28 22:48 ` Conor Dooley
@ 2023-02-01 7:21 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:21 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> Hey,
>
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>
> The label here says S76 but the compatible says u74-mc.
U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> Which is correct? Your docs say S7 and S76, so I would imagine that it
> is actually an S76?
I found SiFive website [1] call it S76, but call it S7 in other places.
So I misunderstood this. Considering the ISA difference you described
as below, I think it's proper to change the label to "S7_0".
[1] https://www.sifive.com/cores/essential
>
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>
> While I was poking around trying to see if there was some logic behind
> that compatible, I noticed that SiFive's docs for the S76 say it is
> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> I assume that rv64imac is the correct one here?
Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
S7-series core, not S76.
>
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>
> That also begs the question:
> Do your u74s support RV64GBC, as the (current) SiFive documentation
> suggests?
Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
"IMAFD". "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
[1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-01 7:21 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:21 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> Hey,
>
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>
> The label here says S76 but the compatible says u74-mc.
U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> Which is correct? Your docs say S7 and S76, so I would imagine that it
> is actually an S76?
I found SiFive website [1] call it S76, but call it S7 in other places.
So I misunderstood this. Considering the ISA difference you described
as below, I think it's proper to change the label to "S7_0".
[1] https://www.sifive.com/cores/essential
>
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>
> While I was poking around trying to see if there was some logic behind
> that compatible, I noticed that SiFive's docs for the S76 say it is
> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> I assume that rv64imac is the correct one here?
Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
S7-series core, not S76.
>
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>
> That also begs the question:
> Do your u74s support RV64GBC, as the (current) SiFive documentation
> suggests?
Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
"IMAFD". "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
[1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-29 5:25 ` Icenowy Zheng
@ 2023-02-01 7:31 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:31 UTC (permalink / raw)
To: Icenowy Zheng, Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 29 Dec 2022 13:25:00 +0800, Icenowy Zheng wrote:
> 在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>> > + U74_1: cpu@1 {
>> > + compatible = "sifive,u74-mc", "riscv";
>> > + reg = <1>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
> It supports RV64GCZbaZbb.
>
> B is not a well-defined thing by specifications, so it should be
> prevented here.
Thank you for your kindly reply.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-01 7:31 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:31 UTC (permalink / raw)
To: Icenowy Zheng, Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 29 Dec 2022 13:25:00 +0800, Icenowy Zheng wrote:
> 在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>> > + U74_1: cpu@1 {
>> > + compatible = "sifive,u74-mc", "riscv";
>> > + reg = <1>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
> It supports RV64GCZbaZbb.
>
> B is not a well-defined thing by specifications, so it should be
> prevented here.
Thank you for your kindly reply.
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2022-12-29 9:02 ` Conor Dooley
@ 2023-02-01 7:53 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:53 UTC (permalink / raw)
To: Conor Dooley, Icenowy Zheng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 29 Dec 2022 09:02:15 +0000, Conor Dooley wrote:
> Hey Icenowy, Hal
>
> On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@icenowy.me> wrote:
>>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>>> Hey,
>>>
>>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>>> > + U74_1: cpu@1 {
>>> > + compatible = "sifive,u74-mc", "riscv";
>>> > + reg = <1>;
>>> > + d-cache-block-size = <64>;
>>> > + d-cache-sets = <64>;
>>> > + d-cache-size = <32768>;
>>> > + d-tlb-sets = <1>;
>>> > + d-tlb-size = <40>;
>>> > + device_type = "cpu";
>>> > + i-cache-block-size = <64>;
>>> > + i-cache-sets = <64>;
>>> > + i-cache-size = <32768>;
>>> > + i-tlb-sets = <1>;
>>> > + i-tlb-size = <40>;
>>> > + mmu-type = "riscv,sv39";
>>> > + next-level-cache = <&ccache>;
>>> > + riscv,isa = "rv64imafdc";
>>>
>>> That also begs the question:
>>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>>> suggests?
>>
>>It supports RV64GCZbaZbb.
>
> Sweet, thanks.
>
>>B is not a well-defined thing by specifications, so it should be
>>prevented here.
>
> Yah, don't worry - my next question was going to be which bits were supported :)
>
> Hal, can you update the isa string in the next version please?
The current isa description is correct. Please see my reply [1].
Thank you.
[1] https://lore.kernel.org/all/c507e0b2-5ca3-cffe-55d2-873ed8c24e3d@starfivetech.com/
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-01 7:53 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-01 7:53 UTC (permalink / raw)
To: Conor Dooley, Icenowy Zheng
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 29 Dec 2022 09:02:15 +0000, Conor Dooley wrote:
> Hey Icenowy, Hal
>
> On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@icenowy.me> wrote:
>>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>>> Hey,
>>>
>>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
[...]
>>> > + U74_1: cpu@1 {
>>> > + compatible = "sifive,u74-mc", "riscv";
>>> > + reg = <1>;
>>> > + d-cache-block-size = <64>;
>>> > + d-cache-sets = <64>;
>>> > + d-cache-size = <32768>;
>>> > + d-tlb-sets = <1>;
>>> > + d-tlb-size = <40>;
>>> > + device_type = "cpu";
>>> > + i-cache-block-size = <64>;
>>> > + i-cache-sets = <64>;
>>> > + i-cache-size = <32768>;
>>> > + i-tlb-sets = <1>;
>>> > + i-tlb-size = <40>;
>>> > + mmu-type = "riscv,sv39";
>>> > + next-level-cache = <&ccache>;
>>> > + riscv,isa = "rv64imafdc";
>>>
>>> That also begs the question:
>>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>>> suggests?
>>
>>It supports RV64GCZbaZbb.
>
> Sweet, thanks.
>
>>B is not a well-defined thing by specifications, so it should be
>>prevented here.
>
> Yah, don't worry - my next question was going to be which bits were supported :)
>
> Hal, can you update the isa string in the next version please?
The current isa description is correct. Please see my reply [1].
Thank you.
[1] https://lore.kernel.org/all/c507e0b2-5ca3-cffe-55d2-873ed8c24e3d@starfivetech.com/
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-01 7:21 ` Hal Feng
@ 2023-02-01 8:21 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-01 8:21 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 4648 bytes --]
On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >> +/ {
> >> + compatible = "starfive,jh7110";
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + S76_0: cpu@0 {
> >> + compatible = "sifive,u74-mc", "riscv";
> >
> > The label here says S76 but the compatible says u74-mc.
>
> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>
> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> > is actually an S76?
>
> I found SiFive website [1] call it S76, but call it S7 in other places.
> So I misunderstood this. Considering the ISA difference you described
> as below, I think it's proper to change the label to "S7_0".
I'm less worried about the label & more interested in the compatible.
hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
and using that here instead?
>
> [1] https://www.sifive.com/cores/essential
>
> >
> >> + reg = <0>;
> >> + d-cache-block-size = <64>;
> >> + d-cache-sets = <64>;
> >> + d-cache-size = <8192>;
> >> + d-tlb-sets = <1>;
> >> + d-tlb-size = <40>;
> >> + device_type = "cpu";
> >> + i-cache-block-size = <64>;
> >> + i-cache-sets = <64>;
> >> + i-cache-size = <16384>;
> >> + i-tlb-sets = <1>;
> >> + i-tlb-size = <40>;
> >> + mmu-type = "riscv,sv39";
> >> + next-level-cache = <&ccache>;
> >> + riscv,isa = "rv64imac";
> >
> > While I was poking around trying to see if there was some logic behind
> > that compatible, I noticed that SiFive's docs for the S76 say it is
> > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> > I assume that rv64imac is the correct one here?
>
> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> S7-series core, not S76.
Cool, thanks.
> >> + tlb-split;
> >> + status = "disabled";
> >> +
> >> + cpu0_intc: interrupt-controller {
> >> + compatible = "riscv,cpu-intc";
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> + };
> >> + };
> >> +
> >> + U74_1: cpu@1 {
> >> + compatible = "sifive,u74-mc", "riscv";
> >> + reg = <1>;
> >> + d-cache-block-size = <64>;
> >> + d-cache-sets = <64>;
> >> + d-cache-size = <32768>;
> >> + d-tlb-sets = <1>;
> >> + d-tlb-size = <40>;
> >> + device_type = "cpu";
> >> + i-cache-block-size = <64>;
> >> + i-cache-sets = <64>;
> >> + i-cache-size = <32768>;
> >> + i-tlb-sets = <1>;
> >> + i-tlb-size = <40>;
> >> + mmu-type = "riscv,sv39";
> >> + next-level-cache = <&ccache>;
> >> + riscv,isa = "rv64imafdc";
> >
> > That also begs the question:
> > Do your u74s support RV64GBC, as the (current) SiFive documentation
> > suggests?
>
> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
documentation was using outdated terminology. Also, that is not the doc
for your core complex as far as I can tell. That is the document for
impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
Jess and I had a look one evening but could not find the 21G1.02.00
revision of this document, which is the one corresponding to 0x421_0427.
See Table 92 for more details.
> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
> "IMAFD".
I could not find the 21G1.02.00 version of this document online, but I
was able to find the 21G1.01.00 version of it & that version does not
support the Sscofpmf extension (but does have Zba/Zbb support).
> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
Just because other devicetrees omit them, doesn't mean that you should
too!
This compatible should be an accurate description of your hardware, so
you should add what you actually have.
If you have Zba and Zbb, then add them.
I would double check against your internal documentation for 21G2.02.00
as to whether you do have Sscofpmf, and if you do, add that too!
That way, whenever support for those extensions lands, the jh7110 will
automatically pick it up, rather than needing to have them retrofitted.
> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-01 8:21 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-01 8:21 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 4648 bytes --]
On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >> +/ {
> >> + compatible = "starfive,jh7110";
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + S76_0: cpu@0 {
> >> + compatible = "sifive,u74-mc", "riscv";
> >
> > The label here says S76 but the compatible says u74-mc.
>
> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>
> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> > is actually an S76?
>
> I found SiFive website [1] call it S76, but call it S7 in other places.
> So I misunderstood this. Considering the ISA difference you described
> as below, I think it's proper to change the label to "S7_0".
I'm less worried about the label & more interested in the compatible.
hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
and using that here instead?
>
> [1] https://www.sifive.com/cores/essential
>
> >
> >> + reg = <0>;
> >> + d-cache-block-size = <64>;
> >> + d-cache-sets = <64>;
> >> + d-cache-size = <8192>;
> >> + d-tlb-sets = <1>;
> >> + d-tlb-size = <40>;
> >> + device_type = "cpu";
> >> + i-cache-block-size = <64>;
> >> + i-cache-sets = <64>;
> >> + i-cache-size = <16384>;
> >> + i-tlb-sets = <1>;
> >> + i-tlb-size = <40>;
> >> + mmu-type = "riscv,sv39";
> >> + next-level-cache = <&ccache>;
> >> + riscv,isa = "rv64imac";
> >
> > While I was poking around trying to see if there was some logic behind
> > that compatible, I noticed that SiFive's docs for the S76 say it is
> > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> > I assume that rv64imac is the correct one here?
>
> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> S7-series core, not S76.
Cool, thanks.
> >> + tlb-split;
> >> + status = "disabled";
> >> +
> >> + cpu0_intc: interrupt-controller {
> >> + compatible = "riscv,cpu-intc";
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> + };
> >> + };
> >> +
> >> + U74_1: cpu@1 {
> >> + compatible = "sifive,u74-mc", "riscv";
> >> + reg = <1>;
> >> + d-cache-block-size = <64>;
> >> + d-cache-sets = <64>;
> >> + d-cache-size = <32768>;
> >> + d-tlb-sets = <1>;
> >> + d-tlb-size = <40>;
> >> + device_type = "cpu";
> >> + i-cache-block-size = <64>;
> >> + i-cache-sets = <64>;
> >> + i-cache-size = <32768>;
> >> + i-tlb-sets = <1>;
> >> + i-tlb-size = <40>;
> >> + mmu-type = "riscv,sv39";
> >> + next-level-cache = <&ccache>;
> >> + riscv,isa = "rv64imafdc";
> >
> > That also begs the question:
> > Do your u74s support RV64GBC, as the (current) SiFive documentation
> > suggests?
>
> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
documentation was using outdated terminology. Also, that is not the doc
for your core complex as far as I can tell. That is the document for
impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
Jess and I had a look one evening but could not find the 21G1.02.00
revision of this document, which is the one corresponding to 0x421_0427.
See Table 92 for more details.
> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
> "IMAFD".
I could not find the 21G1.02.00 version of this document online, but I
was able to find the 21G1.01.00 version of it & that version does not
support the Sscofpmf extension (but does have Zba/Zbb support).
> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
Just because other devicetrees omit them, doesn't mean that you should
too!
This compatible should be an accurate description of your hardware, so
you should add what you actually have.
If you have Zba and Zbb, then add them.
I would double check against your internal documentation for 21G2.02.00
as to whether you do have Sscofpmf, and if you do, add that too!
That way, whenever support for those extensions lands, the jh7110 will
automatically pick it up, rather than needing to have them retrofitted.
> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-01-31 6:17 ` Conor Dooley
@ 2023-02-02 2:42 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-02 2:42 UTC (permalink / raw)
To: Conor Dooley, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 31 Jan 2023 06:17:17 +0000, Conor Dooley wrote:
> On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>
>>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>>> Technology Ltd.
>>>
>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>> ---
>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>>> 1 file changed, 411 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>>can use them when they submit i2c driver patches.
>
> All of the other series depend on this one for enablement,
> so unless the binding for i2c is already upstream I'd advise keeping it separate.
The i2c IP of JH7110 is from Synopsys and the same as the i2c IP in JH7100.
The binding and driver for i2c are already upstream. It works as long as we
add the i2c nodes and configure pins for i2c in device tree. It will simplify
the dependency if we do that.
By the way, I am checking the ISA of U74-MC on JH7110 with someone else.
I will reply you today.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-02 2:42 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-02 2:42 UTC (permalink / raw)
To: Conor Dooley, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On Tue, 31 Jan 2023 06:17:17 +0000, Conor Dooley wrote:
> On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>
>>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>>> Technology Ltd.
>>>
>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>> ---
>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>>> 1 file changed, 411 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>>can use them when they submit i2c driver patches.
>
> All of the other series depend on this one for enablement,
> so unless the binding for i2c is already upstream I'd advise keeping it separate.
The i2c IP of JH7110 is from Synopsys and the same as the i2c IP in JH7100.
The binding and driver for i2c are already upstream. It works as long as we
add the i2c nodes and configure pins for i2c in device tree. It will simplify
the dependency if we do that.
By the way, I am checking the ISA of U74-MC on JH7110 with someone else.
I will reply you today.
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-02 2:42 ` Hal Feng
@ 2023-02-02 6:19 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-02 6:19 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On 2 February 2023 02:42:32 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>On Tue, 31 Jan 2023 06:17:17 +0000, Conor Dooley wrote:
>> On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>>>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>>
>>>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>>>> Technology Ltd.
>>>>
>>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>>> ---
>>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>>>> 1 file changed, 411 insertions(+)
>>>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>
>>>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>>>can use them when they submit i2c driver patches.
>>
>> All of the other series depend on this one for enablement,
>> so unless the binding for i2c is already upstream I'd advise keeping it separate.
>
>The i2c IP of JH7110 is from Synopsys and the same as the i2c IP in JH7100.
>The binding and driver for i2c are already upstream. It works as long as we
>add the i2c nodes and configure pins for i2c in device tree. It will simplify
>the dependency if we do that.
Please make sure that you add a device specific compatible for jh7110 then, thanks.
>By the way, I am checking the ISA of U74-MC on JH7110 with someone else.
>I will reply you today.
Cool!
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-02 6:19 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-02 6:19 UTC (permalink / raw)
To: Hal Feng, linux-riscv, devicetree
Cc: Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, Emil Renner Berthing, linux-kernel
On 2 February 2023 02:42:32 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>On Tue, 31 Jan 2023 06:17:17 +0000, Conor Dooley wrote:
>> On 31 January 2023 02:00:26 GMT, Hal Feng <hal.feng@starfivetech.com> wrote:
>>>On Tue, 20 Dec 2022 09:12:46 +0800, Hal Feng wrote:
>>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>>
>>>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>>>> Technology Ltd.
>>>>
>>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>>>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>>> ---
>>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>>>> 1 file changed, 411 insertions(+)
>>>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>
>>>I wanna add i2c nodes (i2c0-6) in the next version, so someone else
>>>can use them when they submit i2c driver patches.
>>
>> All of the other series depend on this one for enablement,
>> so unless the binding for i2c is already upstream I'd advise keeping it separate.
>
>The i2c IP of JH7110 is from Synopsys and the same as the i2c IP in JH7100.
>The binding and driver for i2c are already upstream. It works as long as we
>add the i2c nodes and configure pins for i2c in device tree. It will simplify
>the dependency if we do that.
Please make sure that you add a device specific compatible for jh7110 then, thanks.
>By the way, I am checking the ISA of U74-MC on JH7110 with someone else.
>I will reply you today.
Cool!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-01 8:21 ` Conor Dooley
@ 2023-02-02 18:56 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-02 18:56 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>
>> >> +/ {
>> >> + compatible = "starfive,jh7110";
>> >> + #address-cells = <2>;
>> >> + #size-cells = <2>;
>> >> +
>> >> + cpus {
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + S76_0: cpu@0 {
>> >> + compatible = "sifive,u74-mc", "riscv";
>> >
>> > The label here says S76 but the compatible says u74-mc.
>>
>> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>>
>> > Which is correct? Your docs say S7 and S76, so I would imagine that it
>> > is actually an S76?
>>
>> I found SiFive website [1] call it S76, but call it S7 in other places.
>> So I misunderstood this. Considering the ISA difference you described
>> as below, I think it's proper to change the label to "S7_0".
>
> I'm less worried about the label & more interested in the compatible.
> hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> and using that here instead?
First of all, it's my fault that I didn't check the revision of U74-MC
manual, so most of my previous replies might not make sense.
If we add a new compatible string for S7, should we change the compatibles
of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
I'm not sure about this.
>
>>
>> [1] https://www.sifive.com/cores/essential
>>
>> >
>> >> + reg = <0>;
>> >> + d-cache-block-size = <64>;
>> >> + d-cache-sets = <64>;
>> >> + d-cache-size = <8192>;
>> >> + d-tlb-sets = <1>;
>> >> + d-tlb-size = <40>;
>> >> + device_type = "cpu";
>> >> + i-cache-block-size = <64>;
>> >> + i-cache-sets = <64>;
>> >> + i-cache-size = <16384>;
>> >> + i-tlb-sets = <1>;
>> >> + i-tlb-size = <40>;
>> >> + mmu-type = "riscv,sv39";
>> >> + next-level-cache = <&ccache>;
>> >> + riscv,isa = "rv64imac";
>> >
>> > While I was poking around trying to see if there was some logic behind
>> > that compatible, I noticed that SiFive's docs for the S76 say it is
>> > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
>> > I assume that rv64imac is the correct one here?
>>
>> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
>> S7-series core, not S76.
>
> Cool, thanks.
Now I think it might be another version of S76.
>
>> >> + tlb-split;
>> >> + status = "disabled";
>> >> +
>> >> + cpu0_intc: interrupt-controller {
>> >> + compatible = "riscv,cpu-intc";
>> >> + interrupt-controller;
>> >> + #interrupt-cells = <1>;
>> >> + };
>> >> + };
>> >> +
>> >> + U74_1: cpu@1 {
>> >> + compatible = "sifive,u74-mc", "riscv";
>> >> + reg = <1>;
>> >> + d-cache-block-size = <64>;
>> >> + d-cache-sets = <64>;
>> >> + d-cache-size = <32768>;
>> >> + d-tlb-sets = <1>;
>> >> + d-tlb-size = <40>;
>> >> + device_type = "cpu";
>> >> + i-cache-block-size = <64>;
>> >> + i-cache-sets = <64>;
>> >> + i-cache-size = <32768>;
>> >> + i-tlb-sets = <1>;
>> >> + i-tlb-size = <40>;
>> >> + mmu-type = "riscv,sv39";
>> >> + next-level-cache = <&ccache>;
>> >> + riscv,isa = "rv64imafdc";
>> >
>> > That also begs the question:
>> > Do your u74s support RV64GBC, as the (current) SiFive documentation
>> > suggests?
>>
>> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
>
> Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
> documentation was using outdated terminology. Also, that is not the doc
> for your core complex as far as I can tell. That is the document for
> impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
> Jess and I had a look one evening but could not find the 21G1.02.00
> revision of this document, which is the one corresponding to 0x421_0427.
> See Table 92 for more details.
I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
whether I can make it public and I am checking this. This revision records
that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
"RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
U74 and S7 support the full B extension.
>
>> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
>> "IMAFD".
>
> I could not find the 21G1.02.00 version of this document online, but I
> was able to find the 21G1.01.00 version of it & that version does not
> support the Sscofpmf extension (but does have Zba/Zbb support).
>
>> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
>> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
>
> Just because other devicetrees omit them, doesn't mean that you should
> too!
> This compatible should be an accurate description of your hardware, so
> you should add what you actually have.
Will keep it in mind. Thank you.
Best regards,
Hal
> If you have Zba and Zbb, then add them.
> I would double check against your internal documentation for 21G2.02.00
> as to whether you do have Sscofpmf, and if you do, add that too!
>
> That way, whenever support for those extensions lands, the jh7110 will
> automatically pick it up, rather than needing to have them retrofitted.
>
>> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-02 18:56 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-02 18:56 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>
>> >> +/ {
>> >> + compatible = "starfive,jh7110";
>> >> + #address-cells = <2>;
>> >> + #size-cells = <2>;
>> >> +
>> >> + cpus {
>> >> + #address-cells = <1>;
>> >> + #size-cells = <0>;
>> >> +
>> >> + S76_0: cpu@0 {
>> >> + compatible = "sifive,u74-mc", "riscv";
>> >
>> > The label here says S76 but the compatible says u74-mc.
>>
>> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>>
>> > Which is correct? Your docs say S7 and S76, so I would imagine that it
>> > is actually an S76?
>>
>> I found SiFive website [1] call it S76, but call it S7 in other places.
>> So I misunderstood this. Considering the ISA difference you described
>> as below, I think it's proper to change the label to "S7_0".
>
> I'm less worried about the label & more interested in the compatible.
> hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> and using that here instead?
First of all, it's my fault that I didn't check the revision of U74-MC
manual, so most of my previous replies might not make sense.
If we add a new compatible string for S7, should we change the compatibles
of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
I'm not sure about this.
>
>>
>> [1] https://www.sifive.com/cores/essential
>>
>> >
>> >> + reg = <0>;
>> >> + d-cache-block-size = <64>;
>> >> + d-cache-sets = <64>;
>> >> + d-cache-size = <8192>;
>> >> + d-tlb-sets = <1>;
>> >> + d-tlb-size = <40>;
>> >> + device_type = "cpu";
>> >> + i-cache-block-size = <64>;
>> >> + i-cache-sets = <64>;
>> >> + i-cache-size = <16384>;
>> >> + i-tlb-sets = <1>;
>> >> + i-tlb-size = <40>;
>> >> + mmu-type = "riscv,sv39";
>> >> + next-level-cache = <&ccache>;
>> >> + riscv,isa = "rv64imac";
>> >
>> > While I was poking around trying to see if there was some logic behind
>> > that compatible, I noticed that SiFive's docs for the S76 say it is
>> > RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
>> > I assume that rv64imac is the correct one here?
>>
>> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
>> S7-series core, not S76.
>
> Cool, thanks.
Now I think it might be another version of S76.
>
>> >> + tlb-split;
>> >> + status = "disabled";
>> >> +
>> >> + cpu0_intc: interrupt-controller {
>> >> + compatible = "riscv,cpu-intc";
>> >> + interrupt-controller;
>> >> + #interrupt-cells = <1>;
>> >> + };
>> >> + };
>> >> +
>> >> + U74_1: cpu@1 {
>> >> + compatible = "sifive,u74-mc", "riscv";
>> >> + reg = <1>;
>> >> + d-cache-block-size = <64>;
>> >> + d-cache-sets = <64>;
>> >> + d-cache-size = <32768>;
>> >> + d-tlb-sets = <1>;
>> >> + d-tlb-size = <40>;
>> >> + device_type = "cpu";
>> >> + i-cache-block-size = <64>;
>> >> + i-cache-sets = <64>;
>> >> + i-cache-size = <32768>;
>> >> + i-tlb-sets = <1>;
>> >> + i-tlb-size = <40>;
>> >> + mmu-type = "riscv,sv39";
>> >> + next-level-cache = <&ccache>;
>> >> + riscv,isa = "rv64imafdc";
>> >
>> > That also begs the question:
>> > Do your u74s support RV64GBC, as the (current) SiFive documentation
>> > suggests?
>>
>> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
>
> Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
> documentation was using outdated terminology. Also, that is not the doc
> for your core complex as far as I can tell. That is the document for
> impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
> Jess and I had a look one evening but could not find the 21G1.02.00
> revision of this document, which is the one corresponding to 0x421_0427.
> See Table 92 for more details.
I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
whether I can make it public and I am checking this. This revision records
that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
"RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
U74 and S7 support the full B extension.
>
>> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
>> "IMAFD".
>
> I could not find the 21G1.02.00 version of this document online, but I
> was able to find the 21G1.01.00 version of it & that version does not
> support the Sscofpmf extension (but does have Zba/Zbb support).
>
>> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
>> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
>
> Just because other devicetrees omit them, doesn't mean that you should
> too!
> This compatible should be an accurate description of your hardware, so
> you should add what you actually have.
Will keep it in mind. Thank you.
Best regards,
Hal
> If you have Zba and Zbb, then add them.
> I would double check against your internal documentation for 21G2.02.00
> as to whether you do have Sscofpmf, and if you do, add that too!
>
> That way, whenever support for those extensions lands, the jh7110 will
> automatically pick it up, rather than needing to have them retrofitted.
>
>> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-02 18:56 ` Hal Feng
@ 2023-02-02 19:41 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-02 19:41 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 6844 bytes --]
On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >
> >> >> +/ {
> >> >> + compatible = "starfive,jh7110";
> >> >> + #address-cells = <2>;
> >> >> + #size-cells = <2>;
> >> >> +
> >> >> + cpus {
> >> >> + #address-cells = <1>;
> >> >> + #size-cells = <0>;
> >> >> +
> >> >> + S76_0: cpu@0 {
> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >
> >> > The label here says S76 but the compatible says u74-mc.
> >>
> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> >>
> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> >> > is actually an S76?
> >>
> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> >> So I misunderstood this. Considering the ISA difference you described
> >> as below, I think it's proper to change the label to "S7_0".
> >
> > I'm less worried about the label & more interested in the compatible.
> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> > and using that here instead?
>
> First of all, it's my fault that I didn't check the revision of U74-MC
> manual, so most of my previous replies might not make sense.
No that's fine. The manual stuff confused me too when I went looking
initially, and I still get get mixed up by the fact that there are
core-complex manuals but not core manuals.
> If we add a new compatible string for S7, should we change the compatibles
> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> I'm not sure about this.
[...]
> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> >> S7-series core, not S76.
> >
> > Cool, thanks.
>
> Now I think it might be another version of S76.
The SiFive docs describe the u74-mc core complex, which AFAIU you have,
as being 1x S7 & 4x U7.
I'd be happy with new binding for "sifive,s7" & then we use that here.
If you're sure it's S76, we can also use that. S76 is described, in what
docs I can see, as a core complex containing an S7, so S7 seems likely
to be correct?
u7, u74 & u74-mc are valid compatibles, added by SiFive, in commit
75e6d7248efc ("dt-bindings: riscv: Update DT binding docs to support
SiFive FU740 SoC"). Unfortunately, they never actually *used* those
compatibles for anything, and just used "sifive,bullet0" for the fu740.
I'll accept any of u7, u74 or u74-mc for those harts.
> >> >> + tlb-split;
> >> >> + status = "disabled";
> >> >> +
> >> >> + cpu0_intc: interrupt-controller {
> >> >> + compatible = "riscv,cpu-intc";
> >> >> + interrupt-controller;
> >> >> + #interrupt-cells = <1>;
> >> >> + };
> >> >> + };
> >> >> +
> >> >> + U74_1: cpu@1 {
> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >> + reg = <1>;
> >> >> + d-cache-block-size = <64>;
> >> >> + d-cache-sets = <64>;
> >> >> + d-cache-size = <32768>;
> >> >> + d-tlb-sets = <1>;
> >> >> + d-tlb-size = <40>;
> >> >> + device_type = "cpu";
> >> >> + i-cache-block-size = <64>;
> >> >> + i-cache-sets = <64>;
> >> >> + i-cache-size = <32768>;
> >> >> + i-tlb-sets = <1>;
> >> >> + i-tlb-size = <40>;
> >> >> + mmu-type = "riscv,sv39";
> >> >> + next-level-cache = <&ccache>;
> >> >> + riscv,isa = "rv64imafdc";
> >> >
> >> > That also begs the question:
> >> > Do your u74s support RV64GBC, as the (current) SiFive documentation
> >> > suggests?
> >>
> >> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
> >
> > Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
> > documentation was using outdated terminology. Also, that is not the doc
> > for your core complex as far as I can tell. That is the document for
> > impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
> > Jess and I had a look one evening but could not find the 21G1.02.00
> > revision of this document, which is the one corresponding to 0x421_0427.
> > See Table 92 for more details.
>
> I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
> whether I can make it public and I am checking this.
Yeah, certainly don't do anything without cross-checking!
> This revision records
> that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
> "RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
> U74 and S7 support the full B extension.
Having cross-checked a 21G1.01.00 document against a 21G2.01.00 one, I'm
99% sure that you have _Zba_Zbb.
The G2.01 document says _Zba_Zbb & has the same instructions listed as
supported as the G1.02 one.
I've also tried the Zbb support patches posted by Heiko [2] on a
VisionFive V2 and had them work - which is why a definitive statement on
the version of Zbb supported would be really great to have!
[2] - https://lore.kernel.org/linux-riscv/20230113212301.3534711-1-heiko@sntech.de/
> >> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
> >> "IMAFD".
> >
> > I could not find the 21G1.02.00 version of this document online, but I
> > was able to find the 21G1.01.00 version of it & that version does not
> > support the Sscofpmf extension (but does have Zba/Zbb support).
> >
> >> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
> >> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
> >
> > Just because other devicetrees omit them, doesn't mean that you should
> > too!
> > This compatible should be an accurate description of your hardware, so
> > you should add what you actually have.
>
> Will keep it in mind. Thank you.
FWIW, the deadline for getting material in for v6.3 has already passed,
so you can send the next version of this series without waiting for
clarification on the compatibles & ISA string. We should have plenty of
time to get those fixed up before the series gets applied.
Thanks,
Conor.
> > If you have Zba and Zbb, then add them.
> > I would double check against your internal documentation for 21G2.02.00
> > as to whether you do have Sscofpmf, and if you do, add that too!
> >
> > That way, whenever support for those extensions lands, the jh7110 will
> > automatically pick it up, rather than needing to have them retrofitted.
> >
> >> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-02 19:41 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-02 19:41 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 6844 bytes --]
On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >
> >> >> +/ {
> >> >> + compatible = "starfive,jh7110";
> >> >> + #address-cells = <2>;
> >> >> + #size-cells = <2>;
> >> >> +
> >> >> + cpus {
> >> >> + #address-cells = <1>;
> >> >> + #size-cells = <0>;
> >> >> +
> >> >> + S76_0: cpu@0 {
> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >
> >> > The label here says S76 but the compatible says u74-mc.
> >>
> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> >>
> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> >> > is actually an S76?
> >>
> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> >> So I misunderstood this. Considering the ISA difference you described
> >> as below, I think it's proper to change the label to "S7_0".
> >
> > I'm less worried about the label & more interested in the compatible.
> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> > and using that here instead?
>
> First of all, it's my fault that I didn't check the revision of U74-MC
> manual, so most of my previous replies might not make sense.
No that's fine. The manual stuff confused me too when I went looking
initially, and I still get get mixed up by the fact that there are
core-complex manuals but not core manuals.
> If we add a new compatible string for S7, should we change the compatibles
> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> I'm not sure about this.
[...]
> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> >> S7-series core, not S76.
> >
> > Cool, thanks.
>
> Now I think it might be another version of S76.
The SiFive docs describe the u74-mc core complex, which AFAIU you have,
as being 1x S7 & 4x U7.
I'd be happy with new binding for "sifive,s7" & then we use that here.
If you're sure it's S76, we can also use that. S76 is described, in what
docs I can see, as a core complex containing an S7, so S7 seems likely
to be correct?
u7, u74 & u74-mc are valid compatibles, added by SiFive, in commit
75e6d7248efc ("dt-bindings: riscv: Update DT binding docs to support
SiFive FU740 SoC"). Unfortunately, they never actually *used* those
compatibles for anything, and just used "sifive,bullet0" for the fu740.
I'll accept any of u7, u74 or u74-mc for those harts.
> >> >> + tlb-split;
> >> >> + status = "disabled";
> >> >> +
> >> >> + cpu0_intc: interrupt-controller {
> >> >> + compatible = "riscv,cpu-intc";
> >> >> + interrupt-controller;
> >> >> + #interrupt-cells = <1>;
> >> >> + };
> >> >> + };
> >> >> +
> >> >> + U74_1: cpu@1 {
> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >> + reg = <1>;
> >> >> + d-cache-block-size = <64>;
> >> >> + d-cache-sets = <64>;
> >> >> + d-cache-size = <32768>;
> >> >> + d-tlb-sets = <1>;
> >> >> + d-tlb-size = <40>;
> >> >> + device_type = "cpu";
> >> >> + i-cache-block-size = <64>;
> >> >> + i-cache-sets = <64>;
> >> >> + i-cache-size = <32768>;
> >> >> + i-tlb-sets = <1>;
> >> >> + i-tlb-size = <40>;
> >> >> + mmu-type = "riscv,sv39";
> >> >> + next-level-cache = <&ccache>;
> >> >> + riscv,isa = "rv64imafdc";
> >> >
> >> > That also begs the question:
> >> > Do your u74s support RV64GBC, as the (current) SiFive documentation
> >> > suggests?
> >>
> >> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
> >
> > Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
> > documentation was using outdated terminology. Also, that is not the doc
> > for your core complex as far as I can tell. That is the document for
> > impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
> > Jess and I had a look one evening but could not find the 21G1.02.00
> > revision of this document, which is the one corresponding to 0x421_0427.
> > See Table 92 for more details.
>
> I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
> whether I can make it public and I am checking this.
Yeah, certainly don't do anything without cross-checking!
> This revision records
> that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
> "RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
> U74 and S7 support the full B extension.
Having cross-checked a 21G1.01.00 document against a 21G2.01.00 one, I'm
99% sure that you have _Zba_Zbb.
The G2.01 document says _Zba_Zbb & has the same instructions listed as
supported as the G1.02 one.
I've also tried the Zbb support patches posted by Heiko [2] on a
VisionFive V2 and had them work - which is why a definitive statement on
the version of Zbb supported would be really great to have!
[2] - https://lore.kernel.org/linux-riscv/20230113212301.3534711-1-heiko@sntech.de/
> >> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
> >> "IMAFD".
> >
> > I could not find the 21G1.02.00 version of this document online, but I
> > was able to find the 21G1.01.00 version of it & that version does not
> > support the Sscofpmf extension (but does have Zba/Zbb support).
> >
> >> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
> >> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
> >
> > Just because other devicetrees omit them, doesn't mean that you should
> > too!
> > This compatible should be an accurate description of your hardware, so
> > you should add what you actually have.
>
> Will keep it in mind. Thank you.
FWIW, the deadline for getting material in for v6.3 has already passed,
so you can send the next version of this series without waiting for
clarification on the compatibles & ISA string. We should have plenty of
time to get those fixed up before the series gets applied.
Thanks,
Conor.
> > If you have Zba and Zbb, then add them.
> > I would double check against your internal documentation for 21G2.02.00
> > as to whether you do have Sscofpmf, and if you do, add that too!
> >
> > That way, whenever support for those extensions lands, the jh7110 will
> > automatically pick it up, rather than needing to have them retrofitted.
> >
> >> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-02 19:41 ` Conor Dooley
@ 2023-02-09 11:11 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-09 11:11 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: Hal Feng, linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1188 bytes --]
On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> FWIW, the deadline for getting material in for v6.3 has already passed,
> so you can send the next version of this series without waiting for
> clarification on the compatibles & ISA string. We should have plenty of
> time to get those fixed up before the series gets applied.
Also, as it looks like the pinctrl driver is going to land in time for
v6.3, that leaves just this series and the clock driver required for
base support.
In the original submission, you sent the clock driver and dt in the same
series & I think it might make the process a bit faster if you sent them
both together for the next version again.
That way, both the drivers and dts can go together as their have an
inter dependence.
That's my opinion anyway, will make trying to sequence things between
trees easier.
Cheers,
Conor.
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-09 11:11 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-09 11:11 UTC (permalink / raw)
To: Conor Dooley, Hal Feng
Cc: Hal Feng, linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> FWIW, the deadline for getting material in for v6.3 has already passed,
> so you can send the next version of this series without waiting for
> clarification on the compatibles & ISA string. We should have plenty of
> time to get those fixed up before the series gets applied.
Also, as it looks like the pinctrl driver is going to land in time for
v6.3, that leaves just this series and the clock driver required for
base support.
In the original submission, you sent the clock driver and dt in the same
series & I think it might make the process a bit faster if you sent them
both together for the next version again.
That way, both the drivers and dts can go together as their have an
inter dependence.
That's my opinion anyway, will make trying to sequence things between
trees easier.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-09 11:11 ` Conor Dooley
@ 2023-02-13 9:41 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-13 9:41 UTC (permalink / raw)
To: Conor Dooley, Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
> On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
>> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>
>> FWIW, the deadline for getting material in for v6.3 has already passed,
>> so you can send the next version of this series without waiting for
>> clarification on the compatibles & ISA string. We should have plenty of
>> time to get those fixed up before the series gets applied.
>
> Also, as it looks like the pinctrl driver is going to land in time for
> v6.3, that leaves just this series and the clock driver required for
> base support.
>
> In the original submission, you sent the clock driver and dt in the same
> series & I think it might make the process a bit faster if you sent them
> both together for the next version again.
>
> That way, both the drivers and dts can go together as their have an
> inter dependence.
>
> That's my opinion anyway, will make trying to sequence things between
> trees easier.
Good idea. But how can I write the change log if we do so? Will it make
the history confused? Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-13 9:41 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-13 9:41 UTC (permalink / raw)
To: Conor Dooley, Conor Dooley
Cc: linux-riscv, devicetree, Palmer Dabbelt, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Albert Ou, Ben Dooks,
Daniel Lezcano, Thomas Gleixner, Marc Zyngier, Stephen Boyd,
Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
> On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
>> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>
>> FWIW, the deadline for getting material in for v6.3 has already passed,
>> so you can send the next version of this series without waiting for
>> clarification on the compatibles & ISA string. We should have plenty of
>> time to get those fixed up before the series gets applied.
>
> Also, as it looks like the pinctrl driver is going to land in time for
> v6.3, that leaves just this series and the clock driver required for
> base support.
>
> In the original submission, you sent the clock driver and dt in the same
> series & I think it might make the process a bit faster if you sent them
> both together for the next version again.
>
> That way, both the drivers and dts can go together as their have an
> inter dependence.
>
> That's my opinion anyway, will make trying to sequence things between
> trees easier.
Good idea. But how can I write the change log if we do so? Will it make
the history confused? Thanks.
Best regards,
Hal
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-13 9:41 ` Hal Feng
@ 2023-02-13 10:07 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-13 10:07 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Mon, Feb 13, 2023 at 05:41:02PM +0800, Hal Feng wrote:
> On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
> > On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
> >> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> >> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> >> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >
> >> FWIW, the deadline for getting material in for v6.3 has already passed,
> >> so you can send the next version of this series without waiting for
> >> clarification on the compatibles & ISA string. We should have plenty of
> >> time to get those fixed up before the series gets applied.
> >
> > Also, as it looks like the pinctrl driver is going to land in time for
> > v6.3, that leaves just this series and the clock driver required for
> > base support.
> >
> > In the original submission, you sent the clock driver and dt in the same
> > series & I think it might make the process a bit faster if you sent them
> > both together for the next version again.
> >
> > That way, both the drivers and dts can go together as their have an
> > inter dependence.
> >
> > That's my opinion anyway, will make trying to sequence things between
> > trees easier.
>
> Good idea. But how can I write the change log if we do so? Will it make
> the history confused? Thanks.
I'm not sure what you mean w.r.t. history.
Both series are on V3 I think, so just make the next version v4 title it
something like "Basic clock, reset & dt support..."
For the changelogs, just mention you merged the two series again in
the cover letter & add the changelogs that you would have made for each
series to the cover as a single changelog.
Say somewhere in the cover that I suggested merging the series together
so that they could go via the same tree as the dt-binding headers are
required by both driver & devicetree.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-13 10:07 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-13 10:07 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
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On Mon, Feb 13, 2023 at 05:41:02PM +0800, Hal Feng wrote:
> On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
> > On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
> >> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> >> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> >> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >
> >> FWIW, the deadline for getting material in for v6.3 has already passed,
> >> so you can send the next version of this series without waiting for
> >> clarification on the compatibles & ISA string. We should have plenty of
> >> time to get those fixed up before the series gets applied.
> >
> > Also, as it looks like the pinctrl driver is going to land in time for
> > v6.3, that leaves just this series and the clock driver required for
> > base support.
> >
> > In the original submission, you sent the clock driver and dt in the same
> > series & I think it might make the process a bit faster if you sent them
> > both together for the next version again.
> >
> > That way, both the drivers and dts can go together as their have an
> > inter dependence.
> >
> > That's my opinion anyway, will make trying to sequence things between
> > trees easier.
>
> Good idea. But how can I write the change log if we do so? Will it make
> the history confused? Thanks.
I'm not sure what you mean w.r.t. history.
Both series are on V3 I think, so just make the next version v4 title it
something like "Basic clock, reset & dt support..."
For the changelogs, just mention you merged the two series again in
the cover letter & add the changelogs that you would have made for each
series to the cover as a single changelog.
Say somewhere in the cover that I suggested merging the series together
so that they could go via the same tree as the dt-binding headers are
required by both driver & devicetree.
Cheers,
Conor.
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-13 10:07 ` Conor Dooley
@ 2023-02-14 2:37 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-14 2:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Mon, 13 Feb 2023 10:07:38 +0000, Conor Dooley wrote:
> On Mon, Feb 13, 2023 at 05:41:02PM +0800, Hal Feng wrote:
>> On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
>> > On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
>> >> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> >> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> >> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> >> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> >> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> >
>> >> FWIW, the deadline for getting material in for v6.3 has already passed,
>> >> so you can send the next version of this series without waiting for
>> >> clarification on the compatibles & ISA string. We should have plenty of
>> >> time to get those fixed up before the series gets applied.
>> >
>> > Also, as it looks like the pinctrl driver is going to land in time for
>> > v6.3, that leaves just this series and the clock driver required for
>> > base support.
>> >
>> > In the original submission, you sent the clock driver and dt in the same
>> > series & I think it might make the process a bit faster if you sent them
>> > both together for the next version again.
>> >
>> > That way, both the drivers and dts can go together as their have an
>> > inter dependence.
>> >
>> > That's my opinion anyway, will make trying to sequence things between
>> > trees easier.
>>
>> Good idea. But how can I write the change log if we do so? Will it make
>> the history confused? Thanks.
>
> I'm not sure what you mean w.r.t. history.
> Both series are on V3 I think, so just make the next version v4 title it
> something like "Basic clock, reset & dt support..."
> For the changelogs, just mention you merged the two series again in
> the cover letter & add the changelogs that you would have made for each
> series to the cover as a single changelog.
> Say somewhere in the cover that I suggested merging the series together
> so that they could go via the same tree as the dt-binding headers are
> required by both driver & devicetree.
OK, I see. I will merge the clock patch series [1] and this DT patch
series in v4. Thanks for your suggestions.
[1] https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-14 2:37 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-14 2:37 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Mon, 13 Feb 2023 10:07:38 +0000, Conor Dooley wrote:
> On Mon, Feb 13, 2023 at 05:41:02PM +0800, Hal Feng wrote:
>> On Thu, 9 Feb 2023 11:11:51 +0000, Conor Dooley wrote:
>> > On Thu, Feb 02, 2023 at 07:41:33PM +0000, Conor Dooley wrote:
>> >> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> >> > On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> >> > > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> >> > >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> >> > >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> >
>> >> FWIW, the deadline for getting material in for v6.3 has already passed,
>> >> so you can send the next version of this series without waiting for
>> >> clarification on the compatibles & ISA string. We should have plenty of
>> >> time to get those fixed up before the series gets applied.
>> >
>> > Also, as it looks like the pinctrl driver is going to land in time for
>> > v6.3, that leaves just this series and the clock driver required for
>> > base support.
>> >
>> > In the original submission, you sent the clock driver and dt in the same
>> > series & I think it might make the process a bit faster if you sent them
>> > both together for the next version again.
>> >
>> > That way, both the drivers and dts can go together as their have an
>> > inter dependence.
>> >
>> > That's my opinion anyway, will make trying to sequence things between
>> > trees easier.
>>
>> Good idea. But how can I write the change log if we do so? Will it make
>> the history confused? Thanks.
>
> I'm not sure what you mean w.r.t. history.
> Both series are on V3 I think, so just make the next version v4 title it
> something like "Basic clock, reset & dt support..."
> For the changelogs, just mention you merged the two series again in
> the cover letter & add the changelogs that you would have made for each
> series to the cover as a single changelog.
> Say somewhere in the cover that I suggested merging the series together
> so that they could go via the same tree as the dt-binding headers are
> required by both driver & devicetree.
OK, I see. I will merge the clock patch series [1] and this DT patch
series in v4. Thanks for your suggestions.
[1] https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2022-12-20 1:12 ` Hal Feng
@ 2023-02-14 9:53 ` Emil Renner Berthing
-1 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-14 9:53 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> which has version A and version B. Support booting and basic
> clock/reset/pinctrl/uart drivers.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> 4 files changed, 138 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 0ea1bc15ab30..79e925a4a227 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> new file mode 100644
> index 000000000000..188d3fddbe88
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 VA";
> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> new file mode 100644
> index 000000000000..f75c10536f84
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 VB";
> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Hi Hal,
I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
still think having these names match what is printed on the silkscreen
makes it a lot easier for everybody. Even your own releases calls the
boards "v1.2A" and "v1.3B":
https://github.com/starfive-tech/VisionFive2/releases/
So I'd suggest
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
I haven't seen these "VA" and "VB" anywhere else, so if you don't want
the version numbers and can promise that there will be no incompatible
future revisions of the boards then maybe just drop the "V". Eg.
model = "StarFive VisionFive 2 B";
compatible = "starfive,visionfive-2-b", "starfive,jh7110";
/Emil
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> new file mode 100644
> index 000000000000..c60280b89c73
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> + clock-frequency = <32768>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&gpio {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
> + bias-disable; /* external pull-up */
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-14 9:53 ` Emil Renner Berthing
0 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-14 9:53 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> which has version A and version B. Support booting and basic
> clock/reset/pinctrl/uart drivers.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 1 +
> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> 4 files changed, 138 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 0ea1bc15ab30..79e925a4a227 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> new file mode 100644
> index 000000000000..188d3fddbe88
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 VA";
> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> new file mode 100644
> index 000000000000..f75c10536f84
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 VB";
> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Hi Hal,
I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
still think having these names match what is printed on the silkscreen
makes it a lot easier for everybody. Even your own releases calls the
boards "v1.2A" and "v1.3B":
https://github.com/starfive-tech/VisionFive2/releases/
So I'd suggest
model = "StarFive VisionFive 2 v1.3B";
compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
I haven't seen these "VA" and "VB" anywhere else, so if you don't want
the version numbers and can promise that there will be no incompatible
future revisions of the boards then maybe just drop the "V". Eg.
model = "StarFive VisionFive 2 B";
compatible = "starfive,visionfive-2-b", "starfive,jh7110";
/Emil
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> new file mode 100644
> index 000000000000..c60280b89c73
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> + clock-frequency = <32768>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&gpio {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
> + bias-disable; /* external pull-up */
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +};
> --
> 2.38.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-02 19:41 ` Conor Dooley
@ 2023-02-15 3:07 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-15 3:07 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> >
>> >> >> +/ {
>> >> >> + compatible = "starfive,jh7110";
>> >> >> + #address-cells = <2>;
>> >> >> + #size-cells = <2>;
>> >> >> +
>> >> >> + cpus {
>> >> >> + #address-cells = <1>;
>> >> >> + #size-cells = <0>;
>> >> >> +
>> >> >> + S76_0: cpu@0 {
>> >> >> + compatible = "sifive,u74-mc", "riscv";
>> >> >
>> >> > The label here says S76 but the compatible says u74-mc.
>> >>
>> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>> >>
>> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
>> >> > is actually an S76?
>> >>
>> >> I found SiFive website [1] call it S76, but call it S7 in other places.
>> >> So I misunderstood this. Considering the ISA difference you described
>> >> as below, I think it's proper to change the label to "S7_0".
>> >
>> > I'm less worried about the label & more interested in the compatible.
>> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
>> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
>> > and using that here instead?
>>
>> First of all, it's my fault that I didn't check the revision of U74-MC
>> manual, so most of my previous replies might not make sense.
>
> No that's fine. The manual stuff confused me too when I went looking
> initially, and I still get get mixed up by the fact that there are
> core-complex manuals but not core manuals.
>
>> If we add a new compatible string for S7, should we change the compatibles
>> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
>> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
>> I'm not sure about this.
>
> [...]
>
>> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
>> >> S7-series core, not S76.
>> >
>> > Cool, thanks.
>>
>> Now I think it might be another version of S76.
>
> The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> as being 1x S7 & 4x U7.
>
> I'd be happy with new binding for "sifive,s7" & then we use that here.
> If you're sure it's S76, we can also use that. S76 is described, in what
> docs I can see, as a core complex containing an S7, so S7 seems likely
> to be correct?
I will add a new binding for "sifive,s7" and modify the code as follows.
S7_0: cpu@0 {
compatible = "sifive,s7", "riscv";
...
riscv,isa = "rv64imac_zicsr_zba_zbb";
...
};
>
> u7, u74 & u74-mc are valid compatibles, added by SiFive, in commit
> 75e6d7248efc ("dt-bindings: riscv: Update DT binding docs to support
> SiFive FU740 SoC"). Unfortunately, they never actually *used* those
> compatibles for anything, and just used "sifive,bullet0" for the fu740.
>
> I'll accept any of u7, u74 or u74-mc for those harts.
>
>> >> >> + tlb-split;
>> >> >> + status = "disabled";
>> >> >> +
>> >> >> + cpu0_intc: interrupt-controller {
>> >> >> + compatible = "riscv,cpu-intc";
>> >> >> + interrupt-controller;
>> >> >> + #interrupt-cells = <1>;
>> >> >> + };
>> >> >> + };
>> >> >> +
>> >> >> + U74_1: cpu@1 {
>> >> >> + compatible = "sifive,u74-mc", "riscv";
>> >> >> + reg = <1>;
>> >> >> + d-cache-block-size = <64>;
>> >> >> + d-cache-sets = <64>;
>> >> >> + d-cache-size = <32768>;
>> >> >> + d-tlb-sets = <1>;
>> >> >> + d-tlb-size = <40>;
>> >> >> + device_type = "cpu";
>> >> >> + i-cache-block-size = <64>;
>> >> >> + i-cache-sets = <64>;
>> >> >> + i-cache-size = <32768>;
>> >> >> + i-tlb-sets = <1>;
>> >> >> + i-tlb-size = <40>;
>> >> >> + mmu-type = "riscv,sv39";
>> >> >> + next-level-cache = <&ccache>;
>> >> >> + riscv,isa = "rv64imafdc";
>> >> >
>> >> > That also begs the question:
>> >> > Do your u74s support RV64GBC, as the (current) SiFive documentation
>> >> > suggests?
>> >>
>> >> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
>> >
>> > Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
>> > documentation was using outdated terminology. Also, that is not the doc
>> > for your core complex as far as I can tell. That is the document for
>> > impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
>> > Jess and I had a look one evening but could not find the 21G1.02.00
>> > revision of this document, which is the one corresponding to 0x421_0427.
>> > See Table 92 for more details.
>>
>> I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
>> whether I can make it public and I am checking this.
>
> Yeah, certainly don't do anything without cross-checking!
>
>> This revision records
>> that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
>> "RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
>> U74 and S7 support the full B extension.
>
> Having cross-checked a 21G1.01.00 document against a 21G2.01.00 one, I'm
> 99% sure that you have _Zba_Zbb.
> The G2.01 document says _Zba_Zbb & has the same instructions listed as
> supported as the G1.02 one.
> I've also tried the Zbb support patches posted by Heiko [2] on a
> VisionFive V2 and had them work - which is why a definitive statement on
> the version of Zbb supported would be really great to have!
>
> [2] - https://lore.kernel.org/linux-riscv/20230113212301.3534711-1-heiko@sntech.de/
The 21G1.02.00 document is still not allowed to be public so far. By
comparing with instructions included in b extensions [1], I can confirm
that the 21G1.02.00 only supports Zba and Zbb.
[1] https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc#
Zicsr is also supported as described in 21G1.02.00 document. So I will
modify as follows.
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
...
riscv,isa = "rv64imafdc_zicsr_zba_zbb";
...
};
Best regards,
Hal
>
>> >> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
>> >> "IMAFD".
>> >
>> > I could not find the 21G1.02.00 version of this document online, but I
>> > was able to find the 21G1.01.00 version of it & that version does not
>> > support the Sscofpmf extension (but does have Zba/Zbb support).
>> >
>> >> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
>> >> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
>> >
>> > Just because other devicetrees omit them, doesn't mean that you should
>> > too!
>> > This compatible should be an accurate description of your hardware, so
>> > you should add what you actually have.
>>
>> Will keep it in mind. Thank you.
>
> FWIW, the deadline for getting material in for v6.3 has already passed,
> so you can send the next version of this series without waiting for
> clarification on the compatibles & ISA string. We should have plenty of
> time to get those fixed up before the series gets applied.
>
> Thanks,
> Conor.
>
>> > If you have Zba and Zbb, then add them.
>> > I would double check against your internal documentation for 21G2.02.00
>> > as to whether you do have Sscofpmf, and if you do, add that too!
>> >
>> > That way, whenever support for those extensions lands, the jh7110 will
>> > automatically pick it up, rather than needing to have them retrofitted.
>> >
>> >> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-15 3:07 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-15 3:07 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
>> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
>> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
>> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
>> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> >
>> >> >> +/ {
>> >> >> + compatible = "starfive,jh7110";
>> >> >> + #address-cells = <2>;
>> >> >> + #size-cells = <2>;
>> >> >> +
>> >> >> + cpus {
>> >> >> + #address-cells = <1>;
>> >> >> + #size-cells = <0>;
>> >> >> +
>> >> >> + S76_0: cpu@0 {
>> >> >> + compatible = "sifive,u74-mc", "riscv";
>> >> >
>> >> > The label here says S76 but the compatible says u74-mc.
>> >>
>> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
>> >>
>> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
>> >> > is actually an S76?
>> >>
>> >> I found SiFive website [1] call it S76, but call it S7 in other places.
>> >> So I misunderstood this. Considering the ISA difference you described
>> >> as below, I think it's proper to change the label to "S7_0".
>> >
>> > I'm less worried about the label & more interested in the compatible.
>> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
>> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
>> > and using that here instead?
>>
>> First of all, it's my fault that I didn't check the revision of U74-MC
>> manual, so most of my previous replies might not make sense.
>
> No that's fine. The manual stuff confused me too when I went looking
> initially, and I still get get mixed up by the fact that there are
> core-complex manuals but not core manuals.
>
>> If we add a new compatible string for S7, should we change the compatibles
>> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
>> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
>> I'm not sure about this.
>
> [...]
>
>> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
>> >> S7-series core, not S76.
>> >
>> > Cool, thanks.
>>
>> Now I think it might be another version of S76.
>
> The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> as being 1x S7 & 4x U7.
>
> I'd be happy with new binding for "sifive,s7" & then we use that here.
> If you're sure it's S76, we can also use that. S76 is described, in what
> docs I can see, as a core complex containing an S7, so S7 seems likely
> to be correct?
I will add a new binding for "sifive,s7" and modify the code as follows.
S7_0: cpu@0 {
compatible = "sifive,s7", "riscv";
...
riscv,isa = "rv64imac_zicsr_zba_zbb";
...
};
>
> u7, u74 & u74-mc are valid compatibles, added by SiFive, in commit
> 75e6d7248efc ("dt-bindings: riscv: Update DT binding docs to support
> SiFive FU740 SoC"). Unfortunately, they never actually *used* those
> compatibles for anything, and just used "sifive,bullet0" for the fu740.
>
> I'll accept any of u7, u74 or u74-mc for those harts.
>
>> >> >> + tlb-split;
>> >> >> + status = "disabled";
>> >> >> +
>> >> >> + cpu0_intc: interrupt-controller {
>> >> >> + compatible = "riscv,cpu-intc";
>> >> >> + interrupt-controller;
>> >> >> + #interrupt-cells = <1>;
>> >> >> + };
>> >> >> + };
>> >> >> +
>> >> >> + U74_1: cpu@1 {
>> >> >> + compatible = "sifive,u74-mc", "riscv";
>> >> >> + reg = <1>;
>> >> >> + d-cache-block-size = <64>;
>> >> >> + d-cache-sets = <64>;
>> >> >> + d-cache-size = <32768>;
>> >> >> + d-tlb-sets = <1>;
>> >> >> + d-tlb-size = <40>;
>> >> >> + device_type = "cpu";
>> >> >> + i-cache-block-size = <64>;
>> >> >> + i-cache-sets = <64>;
>> >> >> + i-cache-size = <32768>;
>> >> >> + i-tlb-sets = <1>;
>> >> >> + i-tlb-size = <40>;
>> >> >> + mmu-type = "riscv,sv39";
>> >> >> + next-level-cache = <&ccache>;
>> >> >> + riscv,isa = "rv64imafdc";
>> >> >
>> >> > That also begs the question:
>> >> > Do your u74s support RV64GBC, as the (current) SiFive documentation
>> >> > suggests?
>> >>
>> >> Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
>> >
>> > Yeah, I knew asking that question that the "RV64GBC" in SiFive's online
>> > documentation was using outdated terminology. Also, that is not the doc
>> > for your core complex as far as I can tell. That is the document for
>> > impid 0x0621_1222, whereas (IIRC) your core is 0x0421_0427.
>> > Jess and I had a look one evening but could not find the 21G1.02.00
>> > revision of this document, which is the one corresponding to 0x421_0427.
>> > See Table 92 for more details.
>>
>> I found the 21G1.02.00 revision on StarFive internal net, but I'm not sure
>> whether I can make it public and I am checking this.
>
> Yeah, certainly don't do anything without cross-checking!
>
>> This revision records
>> that the ISA of 21G1.02.00 U74 is "RV64GCB" and ISA of 21G1.02.00 S7 is
>> "RV64IMACB". I am asking someone to check with SiFive whether both 21G1.02.00
>> U74 and S7 support the full B extension.
>
> Having cross-checked a 21G1.01.00 document against a 21G2.01.00 one, I'm
> 99% sure that you have _Zba_Zbb.
> The G2.01 document says _Zba_Zbb & has the same instructions listed as
> supported as the G1.02 one.
> I've also tried the Zbb support patches posted by Heiko [2] on a
> VisionFive V2 and had them work - which is why a definitive statement on
> the version of Zbb supported would be really great to have!
>
> [2] - https://lore.kernel.org/linux-riscv/20230113212301.3534711-1-heiko@sntech.de/
The 21G1.02.00 document is still not allowed to be public so far. By
comparing with instructions included in b extensions [1], I can confirm
that the 21G1.02.00 only supports Zba and Zbb.
[1] https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc#
Zicsr is also supported as described in 21G1.02.00 document. So I will
modify as follows.
U74_1: cpu@1 {
compatible = "sifive,u74-mc", "riscv";
...
riscv,isa = "rv64imafdc_zicsr_zba_zbb";
...
};
Best regards,
Hal
>
>> >> describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
>> >> "IMAFD".
>> >
>> > I could not find the 21G1.02.00 version of this document online, but I
>> > was able to find the 21G1.01.00 version of it & that version does not
>> > support the Sscofpmf extension (but does have Zba/Zbb support).
>> >
>> >> "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
>> >> jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
>> >
>> > Just because other devicetrees omit them, doesn't mean that you should
>> > too!
>> > This compatible should be an accurate description of your hardware, so
>> > you should add what you actually have.
>>
>> Will keep it in mind. Thank you.
>
> FWIW, the deadline for getting material in for v6.3 has already passed,
> so you can send the next version of this series without waiting for
> clarification on the compatibles & ISA string. We should have plenty of
> time to get those fixed up before the series gets applied.
>
> Thanks,
> Conor.
>
>> > If you have Zba and Zbb, then add them.
>> > I would double check against your internal documentation for 21G2.02.00
>> > as to whether you do have Sscofpmf, and if you do, add that too!
>> >
>> > That way, whenever support for those extensions lands, the jh7110 will
>> > automatically pick it up, rather than needing to have them retrofitted.
>> >
>> >> [1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-15 3:07 ` Hal Feng
@ 2023-02-15 7:42 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-15 7:42 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3544 bytes --]
Hey Hal!
On Wed, Feb 15, 2023 at 11:07:15AM +0800, Hal Feng wrote:
> On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> > On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> >> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> >> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >> >
> >> >> >> +/ {
> >> >> >> + compatible = "starfive,jh7110";
> >> >> >> + #address-cells = <2>;
> >> >> >> + #size-cells = <2>;
> >> >> >> +
> >> >> >> + cpus {
> >> >> >> + #address-cells = <1>;
> >> >> >> + #size-cells = <0>;
> >> >> >> +
> >> >> >> + S76_0: cpu@0 {
> >> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >> >
> >> >> > The label here says S76 but the compatible says u74-mc.
> >> >>
> >> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> >> >>
> >> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> >> >> > is actually an S76?
> >> >>
> >> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> >> >> So I misunderstood this. Considering the ISA difference you described
> >> >> as below, I think it's proper to change the label to "S7_0".
> >> >
> >> > I'm less worried about the label & more interested in the compatible.
> >> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> >> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> >> > and using that here instead?
> >>
> >> First of all, it's my fault that I didn't check the revision of U74-MC
> >> manual, so most of my previous replies might not make sense.
> >
> > No that's fine. The manual stuff confused me too when I went looking
> > initially, and I still get get mixed up by the fact that there are
> > core-complex manuals but not core manuals.
> >
> >> If we add a new compatible string for S7, should we change the compatibles
> >> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> >> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> >> I'm not sure about this.
> >
> > [...]
> >
> >> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> >> >> S7-series core, not S76.
> >> >
> >> > Cool, thanks.
> >>
> >> Now I think it might be another version of S76.
> >
> > The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> > as being 1x S7 & 4x U7.
> >
> > I'd be happy with new binding for "sifive,s7" & then we use that here.
> > If you're sure it's S76, we can also use that. S76 is described, in what
> > docs I can see, as a core complex containing an S7, so S7 seems likely
> > to be correct?
>
> I will add a new binding for "sifive,s7" and modify the code as follows.
>
> S7_0: cpu@0 {
> compatible = "sifive,s7", "riscv";
> ...
> riscv,isa = "rv64imac_zicsr_zba_zbb";
I'm not sure that I'd bother with the zicsr, it gets added automagically
by the Makefile if needed:
| # Newer binutils versions default to ISA spec version 20191213 which moves some
| # instructions from the I extension to the Zicsr and Zifencei extensions.
| toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
| riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
Otherwise, thanks for the actual confirmation of zba/zbb!
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-15 7:42 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-15 7:42 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3544 bytes --]
Hey Hal!
On Wed, Feb 15, 2023 at 11:07:15AM +0800, Hal Feng wrote:
> On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> > On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> >> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> >> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> >> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> >> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> >> >
> >> >> >> +/ {
> >> >> >> + compatible = "starfive,jh7110";
> >> >> >> + #address-cells = <2>;
> >> >> >> + #size-cells = <2>;
> >> >> >> +
> >> >> >> + cpus {
> >> >> >> + #address-cells = <1>;
> >> >> >> + #size-cells = <0>;
> >> >> >> +
> >> >> >> + S76_0: cpu@0 {
> >> >> >> + compatible = "sifive,u74-mc", "riscv";
> >> >> >
> >> >> > The label here says S76 but the compatible says u74-mc.
> >> >>
> >> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> >> >>
> >> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> >> >> > is actually an S76?
> >> >>
> >> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> >> >> So I misunderstood this. Considering the ISA difference you described
> >> >> as below, I think it's proper to change the label to "S7_0".
> >> >
> >> > I'm less worried about the label & more interested in the compatible.
> >> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> >> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> >> > and using that here instead?
> >>
> >> First of all, it's my fault that I didn't check the revision of U74-MC
> >> manual, so most of my previous replies might not make sense.
> >
> > No that's fine. The manual stuff confused me too when I went looking
> > initially, and I still get get mixed up by the fact that there are
> > core-complex manuals but not core manuals.
> >
> >> If we add a new compatible string for S7, should we change the compatibles
> >> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> >> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> >> I'm not sure about this.
> >
> > [...]
> >
> >> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> >> >> S7-series core, not S76.
> >> >
> >> > Cool, thanks.
> >>
> >> Now I think it might be another version of S76.
> >
> > The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> > as being 1x S7 & 4x U7.
> >
> > I'd be happy with new binding for "sifive,s7" & then we use that here.
> > If you're sure it's S76, we can also use that. S76 is described, in what
> > docs I can see, as a core complex containing an S7, so S7 seems likely
> > to be correct?
>
> I will add a new binding for "sifive,s7" and modify the code as follows.
>
> S7_0: cpu@0 {
> compatible = "sifive,s7", "riscv";
> ...
> riscv,isa = "rv64imac_zicsr_zba_zbb";
I'm not sure that I'd bother with the zicsr, it gets added automagically
by the Makefile if needed:
| # Newer binutils versions default to ISA spec version 20191213 which moves some
| # instructions from the I extension to the Zicsr and Zifencei extensions.
| toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
| riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
Otherwise, thanks for the actual confirmation of zba/zbb!
Thanks,
Conor.
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_______________________________________________
linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-15 7:42 ` Conor Dooley
@ 2023-02-15 7:59 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-15 7:59 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 4327 bytes --]
On Wed, Feb 15, 2023 at 07:42:32AM +0000, Conor Dooley wrote:
> Hey Hal!
>
> On Wed, Feb 15, 2023 at 11:07:15AM +0800, Hal Feng wrote:
> > On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> > > On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> > >> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > >> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> > >> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > >> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > >> >
> > >> >> >> +/ {
> > >> >> >> + compatible = "starfive,jh7110";
> > >> >> >> + #address-cells = <2>;
> > >> >> >> + #size-cells = <2>;
> > >> >> >> +
> > >> >> >> + cpus {
> > >> >> >> + #address-cells = <1>;
> > >> >> >> + #size-cells = <0>;
> > >> >> >> +
> > >> >> >> + S76_0: cpu@0 {
> > >> >> >> + compatible = "sifive,u74-mc", "riscv";
> > >> >> >
> > >> >> > The label here says S76 but the compatible says u74-mc.
> > >> >>
> > >> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> > >> >>
> > >> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> > >> >> > is actually an S76?
> > >> >>
> > >> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> > >> >> So I misunderstood this. Considering the ISA difference you described
> > >> >> as below, I think it's proper to change the label to "S7_0".
> > >> >
> > >> > I'm less worried about the label & more interested in the compatible.
> > >> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> > >> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> > >> > and using that here instead?
> > >>
> > >> First of all, it's my fault that I didn't check the revision of U74-MC
> > >> manual, so most of my previous replies might not make sense.
> > >
> > > No that's fine. The manual stuff confused me too when I went looking
> > > initially, and I still get get mixed up by the fact that there are
> > > core-complex manuals but not core manuals.
> > >
> > >> If we add a new compatible string for S7, should we change the compatibles
> > >> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> > >> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> > >> I'm not sure about this.
> > >
> > > [...]
> > >
> > >> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> > >> >> S7-series core, not S76.
> > >> >
> > >> > Cool, thanks.
> > >>
> > >> Now I think it might be another version of S76.
> > >
> > > The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> > > as being 1x S7 & 4x U7.
> > >
> > > I'd be happy with new binding for "sifive,s7" & then we use that here.
> > > If you're sure it's S76, we can also use that. S76 is described, in what
> > > docs I can see, as a core complex containing an S7, so S7 seems likely
> > > to be correct?
> >
> > I will add a new binding for "sifive,s7" and modify the code as follows.
> >
> > S7_0: cpu@0 {
> > compatible = "sifive,s7", "riscv";
> > ...
> > riscv,isa = "rv64imac_zicsr_zba_zbb";
>
> I'm not sure that I'd bother with the zicsr, it gets added automagically
> by the Makefile if needed:
Meh, I probably shouldn't have replied to this first thing in the
morning as this comment of mine doesn't really make sense.
I skipped the middle part of my point here...
What I meant was that you can avoid zicsr & zifencei because when the
binding was defined they were included in i. I meant to use the
following as a kinda explanation of it depending on the version of the
ISA spec & that we just assume that zicsr & zifencei are present.
I suppose you can add them to the isa string if you like, dtbs_check
shouldn't complain!
> | # Newer binutils versions default to ISA spec version 20191213 which moves some
> | # instructions from the I extension to the Zicsr and Zifencei extensions.
> | toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> | riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
>
> Otherwise, thanks for the actual confirmation of zba/zbb!
>
> Thanks,
> Conor.
>
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree
@ 2023-02-15 7:59 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-15 7:59 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
Emil Renner Berthing, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 4327 bytes --]
On Wed, Feb 15, 2023 at 07:42:32AM +0000, Conor Dooley wrote:
> Hey Hal!
>
> On Wed, Feb 15, 2023 at 11:07:15AM +0800, Hal Feng wrote:
> > On Thu, 2 Feb 2023 19:41:33 +0000, Conor Dooley wrote:
> > > On Fri, Feb 03, 2023 at 02:56:41AM +0800, Hal Feng wrote:
> > >> On Wed, 1 Feb 2023 08:21:05 +0000, Conor Dooley wrote:
> > >> > On Wed, Feb 01, 2023 at 03:21:48PM +0800, Hal Feng wrote:
> > >> >> On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> > >> >> > On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
> > >> >
> > >> >> >> +/ {
> > >> >> >> + compatible = "starfive,jh7110";
> > >> >> >> + #address-cells = <2>;
> > >> >> >> + #size-cells = <2>;
> > >> >> >> +
> > >> >> >> + cpus {
> > >> >> >> + #address-cells = <1>;
> > >> >> >> + #size-cells = <0>;
> > >> >> >> +
> > >> >> >> + S76_0: cpu@0 {
> > >> >> >> + compatible = "sifive,u74-mc", "riscv";
> > >> >> >
> > >> >> > The label here says S76 but the compatible says u74-mc.
> > >> >>
> > >> >> U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> > >> >>
> > >> >> > Which is correct? Your docs say S7 and S76, so I would imagine that it
> > >> >> > is actually an S76?
> > >> >>
> > >> >> I found SiFive website [1] call it S76, but call it S7 in other places.
> > >> >> So I misunderstood this. Considering the ISA difference you described
> > >> >> as below, I think it's proper to change the label to "S7_0".
> > >> >
> > >> > I'm less worried about the label & more interested in the compatible.
> > >> > hart0 is, as you say, not a u74. Should we not be adding a "sifive,s7"
> > >> > compatible string to Documentation/devicetree/bindings/riscv/cpus.yaml
> > >> > and using that here instead?
> > >>
> > >> First of all, it's my fault that I didn't check the revision of U74-MC
> > >> manual, so most of my previous replies might not make sense.
> > >
> > > No that's fine. The manual stuff confused me too when I went looking
> > > initially, and I still get get mixed up by the fact that there are
> > > core-complex manuals but not core manuals.
> > >
> > >> If we add a new compatible string for S7, should we change the compatibles
> > >> of hart1~3 to "sifive,u74" also? And then, there may be no point keeping some
> > >> compatible strings of core complex like "sifive,u74-mc" and "sifive,u54-mc".
> > >> I'm not sure about this.
> > >
> > > [...]
> > >
> > >> >> Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
> > >> >> S7-series core, not S76.
> > >> >
> > >> > Cool, thanks.
> > >>
> > >> Now I think it might be another version of S76.
> > >
> > > The SiFive docs describe the u74-mc core complex, which AFAIU you have,
> > > as being 1x S7 & 4x U7.
> > >
> > > I'd be happy with new binding for "sifive,s7" & then we use that here.
> > > If you're sure it's S76, we can also use that. S76 is described, in what
> > > docs I can see, as a core complex containing an S7, so S7 seems likely
> > > to be correct?
> >
> > I will add a new binding for "sifive,s7" and modify the code as follows.
> >
> > S7_0: cpu@0 {
> > compatible = "sifive,s7", "riscv";
> > ...
> > riscv,isa = "rv64imac_zicsr_zba_zbb";
>
> I'm not sure that I'd bother with the zicsr, it gets added automagically
> by the Makefile if needed:
Meh, I probably shouldn't have replied to this first thing in the
morning as this comment of mine doesn't really make sense.
I skipped the middle part of my point here...
What I meant was that you can avoid zicsr & zifencei because when the
binding was defined they were included in i. I meant to use the
following as a kinda explanation of it depending on the version of the
ISA spec & that we just assume that zicsr & zifencei are present.
I suppose you can add them to the isa string if you like, dtbs_check
shouldn't complain!
> | # Newer binutils versions default to ISA spec version 20191213 which moves some
> | # instructions from the I extension to the Zicsr and Zifencei extensions.
> | toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
> | riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
>
> Otherwise, thanks for the actual confirmation of zba/zbb!
>
> Thanks,
> Conor.
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-14 9:53 ` Emil Renner Berthing
@ 2023-02-15 14:03 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-15 14:03 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>>
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
>> which has version A and version B. Support booting and basic
>> clock/reset/pinctrl/uart drivers.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/Makefile | 1 +
>> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
>> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
>> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
>> 4 files changed, 138 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
>> index 0ea1bc15ab30..79e925a4a227 100644
>> --- a/arch/riscv/boot/dts/starfive/Makefile
>> +++ b/arch/riscv/boot/dts/starfive/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> new file mode 100644
>> index 000000000000..188d3fddbe88
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 VA";
>> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
>> +};
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> new file mode 100644
>> index 000000000000..f75c10536f84
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 VB";
>> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>
> Hi Hal,
>
> I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> still think having these names match what is printed on the silkscreen
> makes it a lot easier for everybody. Even your own releases calls the
> boards "v1.2A" and "v1.3B":
> https://github.com/starfive-tech/VisionFive2/releases/
>
> So I'd suggest
> model = "StarFive VisionFive 2 v1.3B";
> compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
>
> I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> the version numbers and can promise that there will be no incompatible
> future revisions of the boards then maybe just drop the "V". Eg.
> model = "StarFive VisionFive 2 B";
> compatible = "starfive,visionfive-2-b", "starfive,jh7110";
The version A board has reached the end of life. As far as I know, the
version B board will not update also unless there are some important
requirements and StarFive decides to update. Furthermore, it's too late
to change the compatible as patch 1 was already accepted. Will it be
easier to read if I modify it as below?
model = "StarFive VisionFive 2 vB";
compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Best regards,
Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-15 14:03 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-15 14:03 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>>
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
>> which has version A and version B. Support booting and basic
>> clock/reset/pinctrl/uart drivers.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/Makefile | 1 +
>> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
>> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
>> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
>> 4 files changed, 138 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
>> index 0ea1bc15ab30..79e925a4a227 100644
>> --- a/arch/riscv/boot/dts/starfive/Makefile
>> +++ b/arch/riscv/boot/dts/starfive/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> new file mode 100644
>> index 000000000000..188d3fddbe88
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 VA";
>> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
>> +};
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> new file mode 100644
>> index 000000000000..f75c10536f84
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 VB";
>> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>
> Hi Hal,
>
> I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> still think having these names match what is printed on the silkscreen
> makes it a lot easier for everybody. Even your own releases calls the
> boards "v1.2A" and "v1.3B":
> https://github.com/starfive-tech/VisionFive2/releases/
>
> So I'd suggest
> model = "StarFive VisionFive 2 v1.3B";
> compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
>
> I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> the version numbers and can promise that there will be no incompatible
> future revisions of the boards then maybe just drop the "V". Eg.
> model = "StarFive VisionFive 2 B";
> compatible = "starfive,visionfive-2-b", "starfive,jh7110";
The version A board has reached the end of life. As far as I know, the
version B board will not update also unless there are some important
requirements and StarFive decides to update. Furthermore, it's too late
to change the compatible as patch 1 was already accepted. Will it be
easier to read if I modify it as below?
model = "StarFive VisionFive 2 vB";
compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Best regards,
Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-15 14:03 ` Hal Feng
@ 2023-02-16 9:27 ` Emil Renner Berthing
-1 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-16 9:27 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> >>
> >> From: Emil Renner Berthing <kernel@esmil.dk>
> >>
> >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> >> which has version A and version B. Support booting and basic
> >> clock/reset/pinctrl/uart drivers.
> >>
> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> >> ---
> >> arch/riscv/boot/dts/starfive/Makefile | 1 +
> >> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> >> 4 files changed, 138 insertions(+)
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> >> index 0ea1bc15ab30..79e925a4a227 100644
> >> --- a/arch/riscv/boot/dts/starfive/Makefile
> >> +++ b/arch/riscv/boot/dts/starfive/Makefile
> >> @@ -1,2 +1,3 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> new file mode 100644
> >> index 000000000000..188d3fddbe88
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >> +/*
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include "jh7110-starfive-visionfive-2.dtsi"
> >> +
> >> +/ {
> >> + model = "StarFive VisionFive 2 VA";
> >> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
> >> +};
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> new file mode 100644
> >> index 000000000000..f75c10536f84
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >> +/*
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include "jh7110-starfive-visionfive-2.dtsi"
> >> +
> >> +/ {
> >> + model = "StarFive VisionFive 2 VB";
> >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> >
> > Hi Hal,
> >
> > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > still think having these names match what is printed on the silkscreen
> > makes it a lot easier for everybody. Even your own releases calls the
> > boards "v1.2A" and "v1.3B":
> > https://github.com/starfive-tech/VisionFive2/releases/
> >
> > So I'd suggest
> > model = "StarFive VisionFive 2 v1.3B";
> > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> >
> > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > the version numbers and can promise that there will be no incompatible
> > future revisions of the boards then maybe just drop the "V". Eg.
> > model = "StarFive VisionFive 2 B";
> > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
>
> The version A board has reached the end of life. As far as I know, the
> version B board will not update also unless there are some important
> requirements and StarFive decides to update. Furthermore, it's too late
> to change the compatible as patch 1 was already accepted. Will it be
> easier to read if I modify it as below?
>
> model = "StarFive VisionFive 2 vB";
> compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Oh, that's sad that the kernel will now end up calling the boards
something that's used nowhere else, even by StarFive :/
But yeah, I guess vA and vB are a little easier to read.
> Best regards,
> Hal
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 9:27 ` Emil Renner Berthing
0 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-16 9:27 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> >>
> >> From: Emil Renner Berthing <kernel@esmil.dk>
> >>
> >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> >> which has version A and version B. Support booting and basic
> >> clock/reset/pinctrl/uart drivers.
> >>
> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> >> ---
> >> arch/riscv/boot/dts/starfive/Makefile | 1 +
> >> .../jh7110-starfive-visionfive-2-va.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2-vb.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 111 ++++++++++++++++++
> >> 4 files changed, 138 insertions(+)
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> >> index 0ea1bc15ab30..79e925a4a227 100644
> >> --- a/arch/riscv/boot/dts/starfive/Makefile
> >> +++ b/arch/riscv/boot/dts/starfive/Makefile
> >> @@ -1,2 +1,3 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-va.dtb jh7110-starfive-visionfive-2-vb.dtb
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> new file mode 100644
> >> index 000000000000..188d3fddbe88
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-va.dts
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >> +/*
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include "jh7110-starfive-visionfive-2.dtsi"
> >> +
> >> +/ {
> >> + model = "StarFive VisionFive 2 VA";
> >> + compatible = "starfive,visionfive-2-va", "starfive,jh7110";
> >> +};
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> new file mode 100644
> >> index 000000000000..f75c10536f84
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-vb.dts
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >> +/*
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> >> + */
> >> +
> >> +/dts-v1/;
> >> +#include "jh7110-starfive-visionfive-2.dtsi"
> >> +
> >> +/ {
> >> + model = "StarFive VisionFive 2 VB";
> >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> >
> > Hi Hal,
> >
> > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > still think having these names match what is printed on the silkscreen
> > makes it a lot easier for everybody. Even your own releases calls the
> > boards "v1.2A" and "v1.3B":
> > https://github.com/starfive-tech/VisionFive2/releases/
> >
> > So I'd suggest
> > model = "StarFive VisionFive 2 v1.3B";
> > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> >
> > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > the version numbers and can promise that there will be no incompatible
> > future revisions of the boards then maybe just drop the "V". Eg.
> > model = "StarFive VisionFive 2 B";
> > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
>
> The version A board has reached the end of life. As far as I know, the
> version B board will not update also unless there are some important
> requirements and StarFive decides to update. Furthermore, it's too late
> to change the compatible as patch 1 was already accepted. Will it be
> easier to read if I modify it as below?
>
> model = "StarFive VisionFive 2 vB";
> compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
Oh, that's sad that the kernel will now end up calling the boards
something that's used nowhere else, even by StarFive :/
But yeah, I guess vA and vB are a little easier to read.
> Best regards,
> Hal
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-16 9:27 ` Emil Renner Berthing
@ 2023-02-16 9:50 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 9:50 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2282 bytes --]
On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> > >> + model = "StarFive VisionFive 2 VB";
> > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > >
> > > Hi Hal,
> > >
> > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > still think having these names match what is printed on the silkscreen
> > > makes it a lot easier for everybody. Even your own releases calls the
> > > boards "v1.2A" and "v1.3B":
> > > https://github.com/starfive-tech/VisionFive2/releases/
> > >
> > > So I'd suggest
> > > model = "StarFive VisionFive 2 v1.3B";
> > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > >
> > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > the version numbers and can promise that there will be no incompatible
> > > future revisions of the boards then maybe just drop the "V". Eg.
> > > model = "StarFive VisionFive 2 B";
> > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> >
> > The version A board has reached the end of life. As far as I know, the
> > version B board will not update also unless there are some important
> > requirements and StarFive decides to update. Furthermore, it's too late
> > to change the compatible as patch 1 was already accepted. Will it be
> > easier to read if I modify it as below?
> >
> > model = "StarFive VisionFive 2 vB";
> > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>
> Oh, that's sad that the kernel will now end up calling the boards
> something that's used nowhere else, even by StarFive :/
> But yeah, I guess vA and vB are a little easier to read.
Nothing has been released with that name so AFAIU we can change it
still. If you sort it out today/tomorrow I'll try get it to Arnd before
the merge window opens...
I might've jumped the gun a bit here, I thought that it'd been changed
to what you (Emil) had suggested.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 9:50 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 9:50 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2282 bytes --]
On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> > >> + model = "StarFive VisionFive 2 VB";
> > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > >
> > > Hi Hal,
> > >
> > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > still think having these names match what is printed on the silkscreen
> > > makes it a lot easier for everybody. Even your own releases calls the
> > > boards "v1.2A" and "v1.3B":
> > > https://github.com/starfive-tech/VisionFive2/releases/
> > >
> > > So I'd suggest
> > > model = "StarFive VisionFive 2 v1.3B";
> > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > >
> > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > the version numbers and can promise that there will be no incompatible
> > > future revisions of the boards then maybe just drop the "V". Eg.
> > > model = "StarFive VisionFive 2 B";
> > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> >
> > The version A board has reached the end of life. As far as I know, the
> > version B board will not update also unless there are some important
> > requirements and StarFive decides to update. Furthermore, it's too late
> > to change the compatible as patch 1 was already accepted. Will it be
> > easier to read if I modify it as below?
> >
> > model = "StarFive VisionFive 2 vB";
> > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>
> Oh, that's sad that the kernel will now end up calling the boards
> something that's used nowhere else, even by StarFive :/
> But yeah, I guess vA and vB are a little easier to read.
Nothing has been released with that name so AFAIU we can change it
still. If you sort it out today/tomorrow I'll try get it to Arnd before
the merge window opens...
I might've jumped the gun a bit here, I thought that it'd been changed
to what you (Emil) had suggested.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-16 9:50 ` Conor Dooley
@ 2023-02-16 10:09 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 10:09 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3928 bytes --]
On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
> On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> > > >> + model = "StarFive VisionFive 2 VB";
> > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > > >
> > > > Hi Hal,
> > > >
> > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > > still think having these names match what is printed on the silkscreen
> > > > makes it a lot easier for everybody. Even your own releases calls the
> > > > boards "v1.2A" and "v1.3B":
> > > > https://github.com/starfive-tech/VisionFive2/releases/
> > > >
> > > > So I'd suggest
> > > > model = "StarFive VisionFive 2 v1.3B";
> > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > > >
> > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > > the version numbers and can promise that there will be no incompatible
> > > > future revisions of the boards then maybe just drop the "V". Eg.
> > > > model = "StarFive VisionFive 2 B";
> > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> > >
> > > The version A board has reached the end of life. As far as I know, the
> > > version B board will not update also unless there are some important
> > > requirements and StarFive decides to update. Furthermore, it's too late
> > > to change the compatible as patch 1 was already accepted. Will it be
> > > easier to read if I modify it as below?
> > >
> > > model = "StarFive VisionFive 2 vB";
> > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> >
> > Oh, that's sad that the kernel will now end up calling the boards
> > something that's used nowhere else, even by StarFive :/
> > But yeah, I guess vA and vB are a little easier to read.
>
> Nothing has been released with that name so AFAIU we can change it
> still. If you sort it out today/tomorrow I'll try get it to Arnd before
> the merge window opens...
>
> I might've jumped the gun a bit here, I thought that it'd been changed
> to what you (Emil) had suggested.
?
-- >8 --
From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
From: Conor Dooley <conor.dooley@microchip.com>
Date: Thu, 16 Feb 2023 09:58:22 +0000
Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
Using "va" and "vb" doesn't match what's written on the board, or the
communications from StarFive.
Switching to using the silkscreened version number will ease confusion &
the risk of another spin of the board containing a "conflicting" version
identifier.
Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 60c7c03fcdce..cc4d92f0a1bf 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -26,8 +26,8 @@ properties:
- items:
- enum:
- - starfive,visionfive-2-va
- - starfive,visionfive-2-vb
+ - starfive,visionfive-2-v1.2a
+ - starfive,visionfive-2-v1.3b
- const: starfive,jh7110
additionalProperties: true
--
2.39.0
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^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 10:09 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 10:09 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3928 bytes --]
On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
> On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> > > >> + model = "StarFive VisionFive 2 VB";
> > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > > >
> > > > Hi Hal,
> > > >
> > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > > still think having these names match what is printed on the silkscreen
> > > > makes it a lot easier for everybody. Even your own releases calls the
> > > > boards "v1.2A" and "v1.3B":
> > > > https://github.com/starfive-tech/VisionFive2/releases/
> > > >
> > > > So I'd suggest
> > > > model = "StarFive VisionFive 2 v1.3B";
> > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > > >
> > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > > the version numbers and can promise that there will be no incompatible
> > > > future revisions of the boards then maybe just drop the "V". Eg.
> > > > model = "StarFive VisionFive 2 B";
> > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> > >
> > > The version A board has reached the end of life. As far as I know, the
> > > version B board will not update also unless there are some important
> > > requirements and StarFive decides to update. Furthermore, it's too late
> > > to change the compatible as patch 1 was already accepted. Will it be
> > > easier to read if I modify it as below?
> > >
> > > model = "StarFive VisionFive 2 vB";
> > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> >
> > Oh, that's sad that the kernel will now end up calling the boards
> > something that's used nowhere else, even by StarFive :/
> > But yeah, I guess vA and vB are a little easier to read.
>
> Nothing has been released with that name so AFAIU we can change it
> still. If you sort it out today/tomorrow I'll try get it to Arnd before
> the merge window opens...
>
> I might've jumped the gun a bit here, I thought that it'd been changed
> to what you (Emil) had suggested.
?
-- >8 --
From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
From: Conor Dooley <conor.dooley@microchip.com>
Date: Thu, 16 Feb 2023 09:58:22 +0000
Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
Using "va" and "vb" doesn't match what's written on the board, or the
communications from StarFive.
Switching to using the silkscreened version number will ease confusion &
the risk of another spin of the board containing a "conflicting" version
identifier.
Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 60c7c03fcdce..cc4d92f0a1bf 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -26,8 +26,8 @@ properties:
- items:
- enum:
- - starfive,visionfive-2-va
- - starfive,visionfive-2-vb
+ - starfive,visionfive-2-v1.2a
+ - starfive,visionfive-2-v1.3b
- const: starfive,jh7110
additionalProperties: true
--
2.39.0
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-16 10:09 ` Conor Dooley
@ 2023-02-16 10:32 ` Emil Renner Berthing
-1 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-16 10:32 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
> > On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> > > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> >
> > > > >> + model = "StarFive VisionFive 2 VB";
> > > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > > > >
> > > > > Hi Hal,
> > > > >
> > > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > > > still think having these names match what is printed on the silkscreen
> > > > > makes it a lot easier for everybody. Even your own releases calls the
> > > > > boards "v1.2A" and "v1.3B":
> > > > > https://github.com/starfive-tech/VisionFive2/releases/
> > > > >
> > > > > So I'd suggest
> > > > > model = "StarFive VisionFive 2 v1.3B";
> > > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > > > >
> > > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > > > the version numbers and can promise that there will be no incompatible
> > > > > future revisions of the boards then maybe just drop the "V". Eg.
> > > > > model = "StarFive VisionFive 2 B";
> > > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> > > >
> > > > The version A board has reached the end of life. As far as I know, the
> > > > version B board will not update also unless there are some important
> > > > requirements and StarFive decides to update. Furthermore, it's too late
> > > > to change the compatible as patch 1 was already accepted. Will it be
> > > > easier to read if I modify it as below?
> > > >
> > > > model = "StarFive VisionFive 2 vB";
> > > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > >
> > > Oh, that's sad that the kernel will now end up calling the boards
> > > something that's used nowhere else, even by StarFive :/
> > > But yeah, I guess vA and vB are a little easier to read.
> >
> > Nothing has been released with that name so AFAIU we can change it
> > still. If you sort it out today/tomorrow I'll try get it to Arnd before
> > the merge window opens...
> >
> > I might've jumped the gun a bit here, I thought that it'd been changed
> > to what you (Emil) had suggested.
No, I'm sorry for being late here. The below definitely looks better to me.
Hal, would you be fine with this change?
/Emil
>
> -- >8 --
> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
> From: Conor Dooley <conor.dooley@microchip.com>
> Date: Thu, 16 Feb 2023 09:58:22 +0000
> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
>
> Using "va" and "vb" doesn't match what's written on the board, or the
> communications from StarFive.
> Switching to using the silkscreened version number will ease confusion &
> the risk of another spin of the board containing a "conflicting" version
> identifier.
>
> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 60c7c03fcdce..cc4d92f0a1bf 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -26,8 +26,8 @@ properties:
>
> - items:
> - enum:
> - - starfive,visionfive-2-va
> - - starfive,visionfive-2-vb
> + - starfive,visionfive-2-v1.2a
> + - starfive,visionfive-2-v1.3b
> - const: starfive,jh7110
>
> additionalProperties: true
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 10:32 ` Emil Renner Berthing
0 siblings, 0 replies; 112+ messages in thread
From: Emil Renner Berthing @ 2023-02-16 10:32 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
> > On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
> > > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
> > > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
> > > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
> >
> > > > >> + model = "StarFive VisionFive 2 VB";
> > > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > > > >
> > > > > Hi Hal,
> > > > >
> > > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
> > > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
> > > > > still think having these names match what is printed on the silkscreen
> > > > > makes it a lot easier for everybody. Even your own releases calls the
> > > > > boards "v1.2A" and "v1.3B":
> > > > > https://github.com/starfive-tech/VisionFive2/releases/
> > > > >
> > > > > So I'd suggest
> > > > > model = "StarFive VisionFive 2 v1.3B";
> > > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> > > > >
> > > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
> > > > > the version numbers and can promise that there will be no incompatible
> > > > > future revisions of the boards then maybe just drop the "V". Eg.
> > > > > model = "StarFive VisionFive 2 B";
> > > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
> > > >
> > > > The version A board has reached the end of life. As far as I know, the
> > > > version B board will not update also unless there are some important
> > > > requirements and StarFive decides to update. Furthermore, it's too late
> > > > to change the compatible as patch 1 was already accepted. Will it be
> > > > easier to read if I modify it as below?
> > > >
> > > > model = "StarFive VisionFive 2 vB";
> > > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
> > >
> > > Oh, that's sad that the kernel will now end up calling the boards
> > > something that's used nowhere else, even by StarFive :/
> > > But yeah, I guess vA and vB are a little easier to read.
> >
> > Nothing has been released with that name so AFAIU we can change it
> > still. If you sort it out today/tomorrow I'll try get it to Arnd before
> > the merge window opens...
> >
> > I might've jumped the gun a bit here, I thought that it'd been changed
> > to what you (Emil) had suggested.
No, I'm sorry for being late here. The below definitely looks better to me.
Hal, would you be fine with this change?
/Emil
>
> -- >8 --
> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
> From: Conor Dooley <conor.dooley@microchip.com>
> Date: Thu, 16 Feb 2023 09:58:22 +0000
> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
>
> Using "va" and "vb" doesn't match what's written on the board, or the
> communications from StarFive.
> Switching to using the silkscreened version number will ease confusion &
> the risk of another spin of the board containing a "conflicting" version
> identifier.
>
> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 60c7c03fcdce..cc4d92f0a1bf 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -26,8 +26,8 @@ properties:
>
> - items:
> - enum:
> - - starfive,visionfive-2-va
> - - starfive,visionfive-2-vb
> + - starfive,visionfive-2-v1.2a
> + - starfive,visionfive-2-v1.3b
> - const: starfive,jh7110
>
> additionalProperties: true
> --
> 2.39.0
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-16 10:32 ` Emil Renner Berthing
@ 2023-02-16 12:27 ` Hal Feng
-1 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-16 12:27 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Thu, 16 Feb 2023 11:32:31 +0100, Emil Renner Berthing wrote:
> On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
>> > On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
>> > > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
>> > > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
>> > > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>> >
>> > > > >> + model = "StarFive VisionFive 2 VB";
>> > > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>> > > > >
>> > > > > Hi Hal,
>> > > > >
>> > > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
>> > > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
>> > > > > still think having these names match what is printed on the silkscreen
>> > > > > makes it a lot easier for everybody. Even your own releases calls the
>> > > > > boards "v1.2A" and "v1.3B":
>> > > > > https://github.com/starfive-tech/VisionFive2/releases/
>> > > > >
>> > > > > So I'd suggest
>> > > > > model = "StarFive VisionFive 2 v1.3B";
>> > > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
>> > > > >
>> > > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
>> > > > > the version numbers and can promise that there will be no incompatible
>> > > > > future revisions of the boards then maybe just drop the "V". Eg.
>> > > > > model = "StarFive VisionFive 2 B";
>> > > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
>> > > >
>> > > > The version A board has reached the end of life. As far as I know, the
>> > > > version B board will not update also unless there are some important
>> > > > requirements and StarFive decides to update. Furthermore, it's too late
>> > > > to change the compatible as patch 1 was already accepted. Will it be
>> > > > easier to read if I modify it as below?
>> > > >
>> > > > model = "StarFive VisionFive 2 vB";
>> > > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>> > >
>> > > Oh, that's sad that the kernel will now end up calling the boards
>> > > something that's used nowhere else, even by StarFive :/
>> > > But yeah, I guess vA and vB are a little easier to read.
>> >
>> > Nothing has been released with that name so AFAIU we can change it
>> > still. If you sort it out today/tomorrow I'll try get it to Arnd before
>> > the merge window opens...
>> >
>> > I might've jumped the gun a bit here, I thought that it'd been changed
>> > to what you (Emil) had suggested.
>
> No, I'm sorry for being late here. The below definitely looks better to me.
>
> Hal, would you be fine with this change?
I'm fine with this. It will be more exact. Thanks.
Best regards,
Hal
>
>>
>> -- >8 --
>> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
>> From: Conor Dooley <conor.dooley@microchip.com>
>> Date: Thu, 16 Feb 2023 09:58:22 +0000
>> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
>>
>> Using "va" and "vb" doesn't match what's written on the board, or the
>> communications from StarFive.
>> Switching to using the silkscreened version number will ease confusion &
>> the risk of another spin of the board containing a "conflicting" version
>> identifier.
>>
>> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> index 60c7c03fcdce..cc4d92f0a1bf 100644
>> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> @@ -26,8 +26,8 @@ properties:
>>
>> - items:
>> - enum:
>> - - starfive,visionfive-2-va
>> - - starfive,visionfive-2-vb
>> + - starfive,visionfive-2-v1.2a
>> + - starfive,visionfive-2-v1.3b
>> - const: starfive,jh7110
>>
>> additionalProperties: true
>> --
>> 2.39.0
>>
>>
^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 12:27 ` Hal Feng
0 siblings, 0 replies; 112+ messages in thread
From: Hal Feng @ 2023-02-16 12:27 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley
Cc: linux-riscv, devicetree, Conor Dooley, Palmer Dabbelt,
Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Stephen Boyd, Michael Turquette, Philipp Zabel, Linus Walleij,
linux-kernel
On Thu, 16 Feb 2023 11:32:31 +0100, Emil Renner Berthing wrote:
> On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> On Thu, Feb 16, 2023 at 09:50:37AM +0000, Conor Dooley wrote:
>> > On Thu, Feb 16, 2023 at 10:27:17AM +0100, Emil Renner Berthing wrote:
>> > > On Wed, 15 Feb 2023 at 15:04, Hal Feng <hal.feng@starfivetech.com> wrote:
>> > > > On 2/14/2023 5:53 PM, Emil Renner Berthing wrote:
>> > > > > On Tue, 20 Dec 2022 at 02:12, Hal Feng <hal.feng@starfivetech.com> wrote:
>> >
>> > > > >> + model = "StarFive VisionFive 2 VB";
>> > > > >> + compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>> > > > >
>> > > > > Hi Hal,
>> > > > >
>> > > > > I just want to double check, is "VisionFive 2 VA" / "visoinfive-2-va"
>> > > > > and "VisionFive 2 VB" / "visionfive-2-vb" really what you want? I
>> > > > > still think having these names match what is printed on the silkscreen
>> > > > > makes it a lot easier for everybody. Even your own releases calls the
>> > > > > boards "v1.2A" and "v1.3B":
>> > > > > https://github.com/starfive-tech/VisionFive2/releases/
>> > > > >
>> > > > > So I'd suggest
>> > > > > model = "StarFive VisionFive 2 v1.3B";
>> > > > > compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
>> > > > >
>> > > > > I haven't seen these "VA" and "VB" anywhere else, so if you don't want
>> > > > > the version numbers and can promise that there will be no incompatible
>> > > > > future revisions of the boards then maybe just drop the "V". Eg.
>> > > > > model = "StarFive VisionFive 2 B";
>> > > > > compatible = "starfive,visionfive-2-b", "starfive,jh7110";
>> > > >
>> > > > The version A board has reached the end of life. As far as I know, the
>> > > > version B board will not update also unless there are some important
>> > > > requirements and StarFive decides to update. Furthermore, it's too late
>> > > > to change the compatible as patch 1 was already accepted. Will it be
>> > > > easier to read if I modify it as below?
>> > > >
>> > > > model = "StarFive VisionFive 2 vB";
>> > > > compatible = "starfive,visionfive-2-vb", "starfive,jh7110";
>> > >
>> > > Oh, that's sad that the kernel will now end up calling the boards
>> > > something that's used nowhere else, even by StarFive :/
>> > > But yeah, I guess vA and vB are a little easier to read.
>> >
>> > Nothing has been released with that name so AFAIU we can change it
>> > still. If you sort it out today/tomorrow I'll try get it to Arnd before
>> > the merge window opens...
>> >
>> > I might've jumped the gun a bit here, I thought that it'd been changed
>> > to what you (Emil) had suggested.
>
> No, I'm sorry for being late here. The below definitely looks better to me.
>
> Hal, would you be fine with this change?
I'm fine with this. It will be more exact. Thanks.
Best regards,
Hal
>
>>
>> -- >8 --
>> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
>> From: Conor Dooley <conor.dooley@microchip.com>
>> Date: Thu, 16 Feb 2023 09:58:22 +0000
>> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
>>
>> Using "va" and "vb" doesn't match what's written on the board, or the
>> communications from StarFive.
>> Switching to using the silkscreened version number will ease confusion &
>> the risk of another spin of the board containing a "conflicting" version
>> identifier.
>>
>> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> index 60c7c03fcdce..cc4d92f0a1bf 100644
>> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> @@ -26,8 +26,8 @@ properties:
>>
>> - items:
>> - enum:
>> - - starfive,visionfive-2-va
>> - - starfive,visionfive-2-vb
>> + - starfive,visionfive-2-v1.2a
>> + - starfive,visionfive-2-v1.3b
>> - const: starfive,jh7110
>>
>> additionalProperties: true
>> --
>> 2.39.0
>>
>>
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-16 12:27 ` Hal Feng
@ 2023-02-16 13:02 ` Conor Dooley
-1 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 13:02 UTC (permalink / raw)
To: Hal Feng
Cc: Emil Renner Berthing, linux-riscv, devicetree, Conor Dooley,
Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, linux-kernel
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On Thu, Feb 16, 2023 at 08:27:42PM +0800, Hal Feng wrote:
> On Thu, 16 Feb 2023 11:32:31 +0100, Emil Renner Berthing wrote:
> > On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
> >
> > No, I'm sorry for being late here. The below definitely looks better to me.
> >
> > Hal, would you be fine with this change?
>
> I'm fine with this. It will be more exact. Thanks.
I'll convert these both to Acked-by & send this as a real patch then.
Thanks!
> >> -- >8 --
> >> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >> Date: Thu, 16 Feb 2023 09:58:22 +0000
> >> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
> >>
> >> Using "va" and "vb" doesn't match what's written on the board, or the
> >> communications from StarFive.
> >> Switching to using the silkscreened version number will ease confusion &
> >> the risk of another spin of the board containing a "conflicting" version
> >> identifier.
> >>
> >> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> index 60c7c03fcdce..cc4d92f0a1bf 100644
> >> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> @@ -26,8 +26,8 @@ properties:
> >>
> >> - items:
> >> - enum:
> >> - - starfive,visionfive-2-va
> >> - - starfive,visionfive-2-vb
> >> + - starfive,visionfive-2-v1.2a
> >> + - starfive,visionfive-2-v1.3b
> >> - const: starfive,jh7110
> >>
> >> additionalProperties: true
> >> --
> >> 2.39.0
> >>
> >>
>
>
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^ permalink raw reply [flat|nested] 112+ messages in thread
* Re: [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
@ 2023-02-16 13:02 ` Conor Dooley
0 siblings, 0 replies; 112+ messages in thread
From: Conor Dooley @ 2023-02-16 13:02 UTC (permalink / raw)
To: Hal Feng
Cc: Emil Renner Berthing, linux-riscv, devicetree, Conor Dooley,
Palmer Dabbelt, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Stephen Boyd, Michael Turquette, Philipp Zabel,
Linus Walleij, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 2165 bytes --]
On Thu, Feb 16, 2023 at 08:27:42PM +0800, Hal Feng wrote:
> On Thu, 16 Feb 2023 11:32:31 +0100, Emil Renner Berthing wrote:
> > On Thu, 16 Feb 2023 at 11:09, Conor Dooley <conor.dooley@microchip.com> wrote:
> >
> > No, I'm sorry for being late here. The below definitely looks better to me.
> >
> > Hal, would you be fine with this change?
>
> I'm fine with this. It will be more exact. Thanks.
I'll convert these both to Acked-by & send this as a real patch then.
Thanks!
> >> -- >8 --
> >> From 4d44e8a83716d1caa314f25a95bd21ac8904909e Mon Sep 17 00:00:00 2001
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >> Date: Thu, 16 Feb 2023 09:58:22 +0000
> >> Subject: [PATCH] dt-bindings: riscv: correct starfive visionfive 2 compatibles
> >>
> >> Using "va" and "vb" doesn't match what's written on the board, or the
> >> communications from StarFive.
> >> Switching to using the silkscreened version number will ease confusion &
> >> the risk of another spin of the board containing a "conflicting" version
> >> identifier.
> >>
> >> Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >> Fixes: 97b7ed072784 ("dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board")
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> Documentation/devicetree/bindings/riscv/starfive.yaml | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> index 60c7c03fcdce..cc4d92f0a1bf 100644
> >> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> >> @@ -26,8 +26,8 @@ properties:
> >>
> >> - items:
> >> - enum:
> >> - - starfive,visionfive-2-va
> >> - - starfive,visionfive-2-vb
> >> + - starfive,visionfive-2-v1.2a
> >> + - starfive,visionfive-2-v1.3b
> >> - const: starfive,jh7110
> >>
> >> additionalProperties: true
> >> --
> >> 2.39.0
> >>
> >>
>
>
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_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 112+ messages in thread
end of thread, other threads:[~2023-02-16 13:03 UTC | newest]
Thread overview: 112+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-20 1:12 [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 1:12 ` [PATCH v3 1/7] dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 10:05 ` Krzysztof Kozlowski
2022-12-20 10:05 ` Krzysztof Kozlowski
2022-12-23 2:05 ` Hal Feng
2022-12-23 2:05 ` Hal Feng
2022-12-20 20:58 ` Conor Dooley
2022-12-20 20:58 ` Conor Dooley
2022-12-23 2:15 ` Hal Feng
2022-12-23 2:15 ` Hal Feng
2022-12-20 1:12 ` [PATCH v3 2/7] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 1:12 ` [PATCH v3 3/7] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 1:12 ` [PATCH v3 4/7] dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 20:21 ` Rob Herring
2022-12-20 20:21 ` Rob Herring
2022-12-20 1:12 ` [PATCH v3 5/7] soc: sifive: ccache: Add StarFive JH7110 support Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 21:14 ` Conor Dooley
2022-12-20 21:14 ` Conor Dooley
2022-12-20 1:12 ` [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 10:10 ` Krzysztof Kozlowski
2022-12-20 10:10 ` Krzysztof Kozlowski
2022-12-25 10:31 ` Hal Feng
2022-12-25 10:31 ` Hal Feng
2022-12-25 11:56 ` Krzysztof Kozlowski
2022-12-25 11:56 ` Krzysztof Kozlowski
2022-12-20 21:31 ` Conor Dooley
2022-12-20 21:31 ` Conor Dooley
2022-12-25 14:31 ` Hal Feng
2022-12-25 14:31 ` Hal Feng
2022-12-27 20:58 ` Conor Dooley
2022-12-27 20:58 ` Conor Dooley
2022-12-28 22:48 ` Conor Dooley
2022-12-28 22:48 ` Conor Dooley
2022-12-29 5:25 ` Icenowy Zheng
2022-12-29 5:25 ` Icenowy Zheng
2022-12-29 9:02 ` Conor Dooley
2022-12-29 9:02 ` Conor Dooley
2023-02-01 7:53 ` Hal Feng
2023-02-01 7:53 ` Hal Feng
2023-02-01 7:31 ` Hal Feng
2023-02-01 7:31 ` Hal Feng
2023-02-01 7:21 ` Hal Feng
2023-02-01 7:21 ` Hal Feng
2023-02-01 8:21 ` Conor Dooley
2023-02-01 8:21 ` Conor Dooley
2023-02-02 18:56 ` Hal Feng
2023-02-02 18:56 ` Hal Feng
2023-02-02 19:41 ` Conor Dooley
2023-02-02 19:41 ` Conor Dooley
2023-02-09 11:11 ` Conor Dooley
2023-02-09 11:11 ` Conor Dooley
2023-02-13 9:41 ` Hal Feng
2023-02-13 9:41 ` Hal Feng
2023-02-13 10:07 ` Conor Dooley
2023-02-13 10:07 ` Conor Dooley
2023-02-14 2:37 ` Hal Feng
2023-02-14 2:37 ` Hal Feng
2023-02-15 3:07 ` Hal Feng
2023-02-15 3:07 ` Hal Feng
2023-02-15 7:42 ` Conor Dooley
2023-02-15 7:42 ` Conor Dooley
2023-02-15 7:59 ` Conor Dooley
2023-02-15 7:59 ` Conor Dooley
2023-01-31 2:00 ` Hal Feng
2023-01-31 2:00 ` Hal Feng
2023-01-31 6:17 ` Conor Dooley
2023-01-31 6:17 ` Conor Dooley
2023-02-02 2:42 ` Hal Feng
2023-02-02 2:42 ` Hal Feng
2023-02-02 6:19 ` Conor Dooley
2023-02-02 6:19 ` Conor Dooley
2022-12-20 1:12 ` [PATCH v3 7/7] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board " Hal Feng
2022-12-20 1:12 ` Hal Feng
2022-12-20 21:26 ` Conor Dooley
2022-12-20 21:26 ` Conor Dooley
2022-12-23 3:12 ` Hal Feng
2022-12-23 3:12 ` Hal Feng
2022-12-28 22:49 ` Conor Dooley
2022-12-28 22:49 ` Conor Dooley
2023-01-10 17:59 ` Conor Dooley
2023-01-10 17:59 ` Conor Dooley
2023-01-18 23:43 ` Conor Dooley
2023-01-18 23:43 ` Conor Dooley
2023-02-14 9:53 ` Emil Renner Berthing
2023-02-14 9:53 ` Emil Renner Berthing
2023-02-15 14:03 ` Hal Feng
2023-02-15 14:03 ` Hal Feng
2023-02-16 9:27 ` Emil Renner Berthing
2023-02-16 9:27 ` Emil Renner Berthing
2023-02-16 9:50 ` Conor Dooley
2023-02-16 9:50 ` Conor Dooley
2023-02-16 10:09 ` Conor Dooley
2023-02-16 10:09 ` Conor Dooley
2023-02-16 10:32 ` Emil Renner Berthing
2023-02-16 10:32 ` Emil Renner Berthing
2023-02-16 12:27 ` Hal Feng
2023-02-16 12:27 ` Hal Feng
2023-02-16 13:02 ` Conor Dooley
2023-02-16 13:02 ` Conor Dooley
2022-12-26 23:01 ` [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2022-12-26 23:01 ` Conor Dooley
2022-12-27 7:58 ` Krzysztof Kozlowski
2022-12-27 7:58 ` Krzysztof Kozlowski
2022-12-27 14:20 ` Conor Dooley
2022-12-27 14:20 ` Conor Dooley
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