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* [PATCH v5 0/2] Add MNT Reform 2 board support
@ 2022-06-26 21:41 Patrick Wildt
  2022-06-26 21:42 ` [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 Patrick Wildt
                   ` (2 more replies)
  0 siblings, 3 replies; 17+ messages in thread
From: Patrick Wildt @ 2022-06-26 21:41 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

This U-Boot patchset supports the serial console, the SD card and
eMMC, Gigabit Ethernet and USB.

Changes since v4:
- Adjusted to Kconfig conversions.
- Removed U-Boot-specific device tree changes.
- Synced device tree to Linux v5.19-rc3.
Changes since v3:
- Adjusted to Binman changes in main branch.
- Cleaned up environment variables akin to i.MX8MM.
- Added vendor-prefix to device tree filename.
- Provided ramdisk_addr_r.
Changes since v2:
- Switched to Binman.
Changes since v1:
- Synced DTS with files in Linux git repo.
- Added support for USB host ports.

Patrick Wildt (2):
  arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3
  board: mntre: imx8mq: Add MNT Reform 2 board support

 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/dts/imx8mq-mnt-reform2.dts           |  145 ++-
 arch/arm/dts/imx8mq-nitrogen-som.dtsi         |   15 +-
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  213 ++++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |   94 ++
 include/configs/imx8mq_reform2.h              |   86 ++
 13 files changed, 1966 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

-- 
2.36.1


^ permalink raw reply	[flat|nested] 17+ messages in thread
* [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3
  2022-06-26 21:41 [PATCH v5 0/2] Add MNT Reform 2 board support Patrick Wildt
@ 2022-06-26 21:42 ` Patrick Wildt
  2022-06-27  1:51   ` Fabio Estevam
  2022-06-26 21:42 ` [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support Patrick Wildt
  2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
  2 siblings, 1 reply; 17+ messages in thread
From: Patrick Wildt @ 2022-06-26 21:42 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

---
 arch/arm/dts/imx8mq-mnt-reform2.dts   | 145 +++++++++++++++++++++++++-
 arch/arm/dts/imx8mq-nitrogen-som.dtsi |  15 +--
 2 files changed, 152 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts
index 4f2db6197b..8956a46788 100644
--- a/arch/arm/dts/imx8mq-mnt-reform2.dts
+++ b/arch/arm/dts/imx8mq-mnt-reform2.dts
@@ -12,6 +12,31 @@
 / {
 	model = "MNT Reform 2";
 	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
+	chassis-type = "laptop";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_backlight>;
+		pwms = <&pwm2 0 10000 0>;
+		power-supply = <&reg_main_usb>;
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <0 32 64 128 160 200 255>;
+		default-brightness-level = <6>;
+	};
+
+	panel {
+		compatible = "innolux,n125hce-gn1", "simple-panel";
+		power-supply = <&reg_main_3v3>;
+		backlight = <&backlight>;
+		no-hpd;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&edp_bridge_out>;
+			};
+		};
+	};
 
 	pcie1_refclk: clock-pcie1-refclk {
 		compatible = "fixed-clock";
@@ -41,6 +66,22 @@
 		vin-supply = <&reg_main_5v>;
 	};
 
+	reg_main_1v8: regulator-main-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&reg_main_3v3>;
+	};
+
+	reg_main_1v2: regulator-main-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "1V2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&reg_main_5v>;
+	};
+
 	sound {
 		compatible = "fsl,imx-audio-wm8960";
 		audio-cpu = <&sai2>;
@@ -60,6 +101,13 @@
 	};
 };
 
+&dphy {
+	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+	assigned-clock-rates = <25000000>;
+	status = "okay";
+};
+
 &fec1 {
 	status = "okay";
 };
@@ -83,6 +131,67 @@
 	};
 };
 
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	edp_bridge: bridge@2c {
+		compatible = "ti,sn65dsi86";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_edp_bridge>;
+		reg = <0x2c>;
+		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+		vccio-supply = <&reg_main_1v8>;
+		vpll-supply = <&reg_main_1v8>;
+		vcca-supply = <&reg_main_1v2>;
+		vcc-supply = <&reg_main_1v2>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				edp_bridge_in: endpoint {
+					remote-endpoint = <&mipi_dsi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				edp_bridge_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+		};
+	};
+};
+
+&lcdif {
+	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
+	/delete-property/assigned-clock-rates;
+	status = "okay";
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			mipi_dsi_out: endpoint {
+				remote-endpoint = <&edp_bridge_in>;
+			};
+		};
+	};
+};
+
 &pcie1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie1>;
@@ -95,6 +204,13 @@
 	status = "okay";
 };
 
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+
 &reg_1p8v {
 	vin-supply = <&reg_main_5v>;
 };
@@ -168,10 +284,29 @@
 };
 
 &iomuxc {
+	pinctrl_backlight: backlightgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3
+		>;
+	};
+
+	pinctrl_edp_bridge: edpbridgegrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000022
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
 		>;
 	};
 
@@ -181,6 +316,12 @@
 		>;
 	};
 
+	pinctrl_pwm2: pwm2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3
+		>;
+	};
+
 	pinctrl_sai2: sai2grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi
index 36fc428ebe..395f77b5ac 100644
--- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi
+++ b/arch/arm/dts/imx8mq-nitrogen-som.dtsi
@@ -69,6 +69,9 @@
 			reg = <4>;
 			interrupt-parent = <&gpio1>;
 			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <300>;
 		};
 	};
 };
@@ -191,20 +194,20 @@
 			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
 			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
 			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1
 			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
 			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
 			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
-			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x59
+			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1
+			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1
+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x41
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000022
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000022
 		>;
 	};
 
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support
  2022-06-26 21:41 [PATCH v5 0/2] Add MNT Reform 2 board support Patrick Wildt
  2022-06-26 21:42 ` [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 Patrick Wildt
@ 2022-06-26 21:42 ` Patrick Wildt
  2022-06-27  1:57   ` Fabio Estevam
  2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
  2 siblings, 1 reply; 17+ messages in thread
From: Patrick Wildt @ 2022-06-26 21:42 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
---
 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  213 ++++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |   94 ++
 include/configs/imx8mq_reform2.h              |   86 ++
 11 files changed, 1814 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 0000000000..7efd82214d
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index ef8518c06b..b1a8c30e80 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -50,6 +50,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -284,6 +290,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
 source "board/kontron/pitx_imx8m/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/ronetix/imx8mq-cm/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 0000000000..f9260cb7f5
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 0000000000..946f287ecf
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 0000000000..2efd56bb4a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 0000000000..f7cb32dd98
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	int val;
+
+	/*
+	 * Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8));
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~0x11c;
+	val |= 0x80; /* 1/2 drive strength */
+	val |= 0x18; /* 125 MHz */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val | 0x0100);
+
+	phydev->supported = phydev->drv->features;
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 0000000000..e5303db0f8
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 0000000000..7dcc9a7db7
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CONFIG_DDR_MB 4096
+#define CONFIG_DDR_RANK_BITS 1
+#define CONFIG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CONFIG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CONFIG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CONFIG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CONFIG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CONFIG_DDR_CHANNEL_CNT == 2)
+#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 0000000000..c0885e422c
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 0000000000..56e229e7ef
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_HAB=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 0000000000..f5ee97035b
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR	0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000	/* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE	0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_FEC_MXC_PHYADDR		4
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_addr_r=0x43000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	ENV_MEM_LAYOUT_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"console=ttymxc0,115200\0" \
+	"stdin=serial,usbkbd\0" \
+	BOOTENV
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CONFIG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#endif
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* Re: [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3
  2022-06-26 21:42 ` [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 Patrick Wildt
@ 2022-06-27  1:51   ` Fabio Estevam
  0 siblings, 0 replies; 17+ messages in thread
From: Fabio Estevam @ 2022-06-27  1:51 UTC (permalink / raw)
  To: Patrick Wildt; +Cc: Stefano Babic, U-Boot-Denx, Lukas F. Hartmann

On Sun, Jun 26, 2022 at 6:41 PM Patrick Wildt <patrick@blueri.se> wrote:
>
> ---

Commit log and Signed-off-by are missing.

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support
  2022-06-26 21:42 ` [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support Patrick Wildt
@ 2022-06-27  1:57   ` Fabio Estevam
  0 siblings, 0 replies; 17+ messages in thread
From: Fabio Estevam @ 2022-06-27  1:57 UTC (permalink / raw)
  To: Patrick Wildt; +Cc: Stefano Babic, U-Boot-Denx, Lukas F. Hartmann

On Sun, Jun 26, 2022 at 6:42 PM Patrick Wildt <patrick@blueri.se> wrote:

> +static iomux_v3_cfg_t const uart_pads[] = {
> +       IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +       IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};

As you use DM_SERIAL, this is no longer necessary.

> +int board_phy_config(struct phy_device *phydev)
> +{
> +       int val;
> +
> +       /*
> +        * Ar803x phy SmartEEE feature cause link status generates glitch,
> +        * which cause ethernet link down/up issue, so disable SmartEEE
> +        */
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
> +       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8));
> +
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> +       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> +       val &= ~0x11c;
> +       val |= 0x80; /* 1/2 drive strength */
> +       val |= 0x18; /* 125 MHz */
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> +
> +       /* rgmii tx clock delay enable */
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
> +       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> +       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val | 0x0100);

It seems the PHY code could be removed in favor of DM.

> +#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(1)

With DM, this is not needed.

^ permalink raw reply	[flat|nested] 17+ messages in thread
* [PATCH v6] board: mntre: imx8mq: Add MNT Reform 2 board support
  2022-06-26 21:41 [PATCH v5 0/2] Add MNT Reform 2 board support Patrick Wildt
  2022-06-26 21:42 ` [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 Patrick Wildt
  2022-06-26 21:42 ` [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support Patrick Wildt
@ 2023-01-19 19:56 ` Patrick Wildt
  2023-01-31 17:00   ` Stefano Babic
                     ` (2 more replies)
  2 siblings, 3 replies; 17+ messages in thread
From: Patrick Wildt @ 2023-01-19 19:56 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
---
Changes since v5:
- Adjusted to further Binman changes.
- Adjusted to further Kconfig conversions.
- Removed some phy init in favor of DM.
- Removed some pinmux which are now handled by DM_SERIAL.
- Compared with Librem5/EVK and adjusted for similarity.
Changes since v4:
- Adjusted to Kconfig conversions.
- Removed U-Boot-specific device tree changes.
- Synced device tree to Linux v5.19-rc3.
Changes since v3:
- Adjusted to Binman changes in main branch.
- Cleaned up environment variables akin to i.MX8MM.
- Added vendor-prefix to device tree filename.
- Provided ramdisk_addr_r.
Changes since v2:
- Switched to Binman.
Changes since v1:
- Synced DTS with files in Linux git repo.
- Added support for USB host ports.

 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |  107 ++
 include/configs/imx8mq_reform2.h              |   66 ++
 11 files changed, 1765 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 0000000000..e0a6fc5470
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 { /* console */
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a0715e8091..2049efb131 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -51,6 +51,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -320,6 +326,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/purism/librem5/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 0000000000..f9260cb7f5
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 0000000000..946f287ecf
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 0000000000..2efd56bb4a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 0000000000..be5c5060a2
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 0000000000..e5303db0f8
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 0000000000..7dcc9a7db7
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CONFIG_DDR_MB 4096
+#define CONFIG_DDR_RANK_BITS 1
+#define CONFIG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CONFIG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CONFIG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CONFIG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CONFIG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CONFIG_DDR_CHANNEL_CNT == 2)
+#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 0000000000..21fad4972a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 0000000000..9b14a1bca1
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x180000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x187ff0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1050
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 0000000000..bc380850e3
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif
-- 
2.39.0


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* Re: [PATCH v6] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
@ 2023-01-31 17:00   ` Stefano Babic
  2023-01-31 23:53     ` Patrick Wildt
  2023-01-31 23:57   ` [PATCH v7] " Patrick Wildt
  2023-02-05 23:24   ` [PATCH v6] " Vagrant Cascadian
  2 siblings, 1 reply; 17+ messages in thread
From: Stefano Babic @ 2023-01-31 17:00 UTC (permalink / raw)
  To: Patrick Wildt, Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

On 19.01.23 20:56, Patrick Wildt wrote:
> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
> lifted from BoundaryDevices official U-Boot downstream project.
> 
> Signed-off-by: Patrick Wildt <patrick@blueri.se>
> ---
> Changes since v5:
> - Adjusted to further Binman changes.
> - Adjusted to further Kconfig conversions.
> - Removed some phy init in favor of DM.
> - Removed some pinmux which are now handled by DM_SERIAL.
> - Compared with Librem5/EVK and adjusted for similarity.
> Changes since v4:
> - Adjusted to Kconfig conversions.
> - Removed U-Boot-specific device tree changes.
> - Synced device tree to Linux v5.19-rc3.
> Changes since v3:
> - Adjusted to Binman changes in main branch.
> - Cleaned up environment variables akin to i.MX8MM.
> - Added vendor-prefix to device tree filename.
> - Provided ramdisk_addr_r.
> Changes since v2:
> - Switched to Binman.
> Changes since v1:
> - Synced DTS with files in Linux git repo.
> - Added support for USB host ports.
> 
>   arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>   arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>   board/mntre/imx8mq_reform2/Kconfig            |   15 +
>   board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>   board/mntre/imx8mq_reform2/Makefile           |   12 +
>   board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>   board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
>   .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>   board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>   configs/imx8mq_reform2_defconfig              |  107 ++
>   include/configs/imx8mq_reform2.h              |   66 ++
>   11 files changed, 1765 insertions(+)
>   create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>   create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>   create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>   create mode 100644 board/mntre/imx8mq_reform2/Makefile
>   create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>   create mode 100644 board/mntre/imx8mq_reform2/spl.c
>   create mode 100644 configs/imx8mq_reform2_defconfig
>   create mode 100644 include/configs/imx8mq_reform2.h
> 
> diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
> new file mode 100644
> index 0000000000..e0a6fc5470
> --- /dev/null
> +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
> @@ -0,0 +1,11 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#include "imx8mq-u-boot.dtsi"
> +
> +&pinctrl_uart1 {
> +	u-boot,dm-spl;
> +};
> +
> +&uart1 { /* console */
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index a0715e8091..2049efb131 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -51,6 +51,12 @@ config TARGET_IMX8MQ_PHANBELL
>   	select IMX8MQ
>   	select IMX8M_LPDDR4
>   
> +config TARGET_IMX8MQ_REFORM2
> +	bool "imx8mq_reform2"
> +	select BINMAN
> +	select IMX8MQ
> +	select IMX8M_LPDDR4
> +
>   config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
>   	bool "Data Modul eDM SBC i.MX8M Mini"
>   	select BINMAN
> @@ -320,6 +326,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
>   source "board/kontron/sl-mx8mm/Kconfig"
>   source "board/menlo/mx8menlo/Kconfig"
>   source "board/msc/sm2s_imx8mp/Kconfig"
> +source "board/mntre/imx8mq_reform2/Kconfig"
>   source "board/phytec/phycore_imx8mm/Kconfig"
>   source "board/phytec/phycore_imx8mp/Kconfig"
>   source "board/purism/librem5/Kconfig"
> diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
> new file mode 100644
> index 0000000000..f9260cb7f5
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_IMX8MQ_REFORM2
> +
> +config SYS_BOARD
> +	default "imx8mq_reform2"
> +
> +config SYS_VENDOR
> +	default "mntre"
> +
> +config SYS_CONFIG_NAME
> +	default "imx8mq_reform2"
> +
> +config IMX_CONFIG
> +	default "arch/arm/mach-imx/imx8m/imximage.cfg"
> +
> +endif
> diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
> new file mode 100644
> index 0000000000..946f287ecf
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/MAINTAINERS
> @@ -0,0 +1,7 @@
> +REFORM2 IMX8MQ BOARD
> +M:	Lukas F. Hartmann <lukas@mntre.com>
> +M:	Patrick Wildt <patrick@blueri.se>
> +S:	Maintained
> +F:	board/mntre/imx8mq_reform2/
> +F:	include/configs/imx8mq_reform2.h
> +F:	configs/imx8mq_reform2_defconfig
> diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
> new file mode 100644
> index 0000000000..2efd56bb4a
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright 2017 NXP
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +obj-y += imx8mq_reform2.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> +endif
> diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
> new file mode 100644
> index 0000000000..be5c5060a2
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
> @@ -0,0 +1,171 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
> + */
> +
> +#include <common.h>
> +#include <env.h>
> +#include <init.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/global_data.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <fsl_esdhc_imx.h>
> +#include <mmc.h>
> +#include <asm/arch/imx8mq_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/clock.h>
> +#include <spl.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <power/pmic.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +
> +#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> +	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +
> +int board_early_init_f(void)
> +{
> +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> +	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +	set_wdog_reset(wdog);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_FEC_MXC
> +
> +#define PHY_RESET	IMX_GPIO_NR(1, 9)
> +#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
> +#define PHY_RXC		IMX_GPIO_NR(1, 25)
> +#define PHY_RD0		IMX_GPIO_NR(1, 26)
> +#define PHY_RD1		IMX_GPIO_NR(1, 27)
> +#define PHY_RD2		IMX_GPIO_NR(1, 28)
> +#define PHY_RD3		IMX_GPIO_NR(1, 29)
> +
> +#define STRAP_AR8035	(0x28) // 0010 1000
> +
> +static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
> +	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
> +	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
> +	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
> +	/* 1.8V(1)/1.5V select(0) */
> +	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
> +};
> +
> +static const iomux_v3_cfg_t enet_ar8035_pads[] = {
> +	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
> +	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
> +};
> +
> +static void setup_fec(void)
> +{
> +	struct iomuxc_gpr_base_regs *gpr =
> +		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> +	/* Pull PHY into reset */
> +	gpio_request(PHY_RESET, "fec_rst");
> +	gpio_direction_output(PHY_RESET, 0);
> +
> +	/* Configure ethernet pins value as GPIOs */
> +	gpio_request(PHY_RD0, "fec_rd0");
> +	gpio_direction_output(PHY_RD0, 0);
> +	gpio_request(PHY_RD1, "fec_rd1");
> +	gpio_direction_output(PHY_RD1, 0);
> +	gpio_request(PHY_RD2, "fec_rd2");
> +	gpio_direction_output(PHY_RD2, 0);
> +	gpio_request(PHY_RD3, "fec_rd3");
> +	gpio_direction_output(PHY_RD3, 1);
> +	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
> +	gpio_direction_output(PHY_RX_CTL, 0);
> +	gpio_request(PHY_RXC, "fec_rxc");
> +	gpio_direction_output(PHY_RXC, 1);
> +
> +	/* Set ethernet pins to GPIO to bootstrap PHY */
> +	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
> +	    ARRAY_SIZE(enet_ar8035_gpio_pads));
> +
> +	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
> +	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
> +	/* Enable RGMII TX clk output */
> +	setbits_le32(&gpr->gpr[1], BIT(22));
> +	set_clk_enet(ENET_125MHZ);
> +
> +	/* 1 ms minimum reset pulse for ar8035 */
> +	mdelay(1);
> +
> +	/* Release PHY from reset */
> +	gpio_set_value(PHY_RESET, 1);
> +
> +	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
> +	udelay(12);
> +
> +	/* Change ethernet pins back to normal function */
> +	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
> +	    ARRAY_SIZE(enet_ar8035_pads));
> +}
> +#endif
> +
> +#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> +#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
> +
> +static void setup_usb(void)
> +{
> +	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
> +	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
> +	gpio_request(USB1_HUB_RESET, "usb1_rst");
> +	gpio_direction_output(USB1_HUB_RESET, 0);
> +	mdelay(10);
> +	gpio_set_value(USB1_HUB_RESET, 1);
> +}
> +
> +int board_init(void)
> +{
> +#ifdef CONFIG_FEC_MXC
> +	setup_fec();
> +#endif
> +
> +	setup_usb();
> +
> +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
> +	init_usb_clk();
> +#endif
> +
> +	return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno;
> +}
> +
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +	env_set("board_name", "Reform2");
> +	env_set("board_rev", "iMX8MQ");
> +#endif
> +
> +	return 0;
> +}
> diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
> new file mode 100644
> index 0000000000..e5303db0f8
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
> @@ -0,0 +1,1014 @@
> +/*
> + * Copyright 2019 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot version:
> + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
> + */
> +#include "lpddr4_timing_ch2.h"
> +
> +static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{ DDRC_DBG1(0), 1 },
> +	/* selfref_en=1, SDRAM enter self-refresh state */
> +	{ DDRC_PWRCTL(0), 1 },
> +	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
> +	{ DDRC_MSTR2(0), 0 },
> +	{ DDRC_DERATEEN(0), 0x0203 },
> +	{ DDRC_DERATEINT(0), 0x0003e800 },
> +	{ DDRC_RFSHTMG(0), 0x006100e0 },
> +	{ DDRC_INIT0(0), 0xc003061c },
> +	{ DDRC_INIT1(0), 0x009e0000 },
> +	{ DDRC_INIT3(0), 0x00d4002d },
> +	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
> +	{ DDRC_INIT6(0), 0x0066004a },
> +	{ DDRC_INIT7(0), 0x0016004a },
> +	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
> +	{ DDRC_DRAMTMG1(0), 0x00060633 },
> +	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
> +	{ DDRC_DRAMTMG4(0), 0x0f04080f },
> +	{ DDRC_DRAMTMG5(0), 0x02040c0c },
> +	{ DDRC_DRAMTMG6(0), 0x01010007 },
> +	{ DDRC_DRAMTMG7(0), 0x0401 },
> +	{ DDRC_DRAMTMG12(0), 0x00020600 },
> +	{ DDRC_DRAMTMG13(0), 0x0c100002 },
> +	{ DDRC_DRAMTMG14(0), 0xe6 },
> +	{ DDRC_DRAMTMG17(0), 0x00a00050 },
> +	{ DDRC_ZQCTL0(0), 0xc3200018 },
> +	{ DDRC_ZQCTL1(0), 0x028061a8 },
> +	{ DDRC_ZQCTL2(0), 0 },
> +	{ DDRC_DFITMG0(0), 0x0497820a },
> +	{ DDRC_DFITMG1(0), 0x00080303 },
> +	{ DDRC_DFIUPD0(0), 0xe0400018 },
> +	{ DDRC_DFIUPD1(0), 0x00df00e4 },
> +	{ DDRC_DFIUPD2(0), 0x80000000 },
> +	{ DDRC_DFIMISC(0), 0x11 },
> +	{ DDRC_DFITMG2(0), 0x170a },
> +	{ DDRC_DBICTL(0), 1 },
> +	{ DDRC_DFIPHYMSTR(0), 1 },
> +	{ DDRC_RANKCTL(0), 0x0639 },
> +	{ DDRC_DRAMTMG2(0), 0x070e1617 },
> +
> +	/* address mapping */
> +	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
> +	{ DDRC_ADDRMAP3(0), 0 },
> +	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
> +	{ DDRC_ADDRMAP4(0), 0x1f1f },
> +	/* bank interleave */
> +	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
> +	{ DDRC_ADDRMAP1(0), 0x00080808 },
> +	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
> +	{ DDRC_ADDRMAP5(0), 0x07070707 },
> +	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
> +	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
> +	{ DDRC_ADDRMAP7(0), 0x0f0f },
> +	{ DDRC_FREQ1_DERATEEN(0), 1 },
> +	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
> +	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
> +	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
> +	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
> +	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
> +	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
> +	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
> +	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
> +	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
> +	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
> +	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
> +	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
> +	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
> +	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
> +	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
> +	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
> +	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
> +	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
> +	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
> +	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
> +	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
> +	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
> +	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
> +	{ DDRC_ODTMAP(0), 0 },
> +	{ DDRC_SCHED(0), 0x29001505 },
> +	{ DDRC_SCHED1(0), 0x2c },
> +	{ DDRC_PERFHPR1(0), 0x5900575b },
> +	{ DDRC_PERFLPR1(0), 0x90000096 },
> +	{ DDRC_PERFWR1(0), 0x1000012c },
> +	{ DDRC_DBG0(0), 0x16 },
> +	{ DDRC_DBG1(0), 0 },
> +	{ DDRC_DBGCMD(0), 0 },
> +	{ DDRC_SWCTL(0), 1 },
> +	{ DDRC_POISONCFG(0), 0x11 },
> +	{ DDRC_PCCFG(0), 0x0111 },
> +	{ DDRC_PCFGR_0(0), 0x10f3 },
> +	{ DDRC_PCFGW_0(0), 0x72ff },
> +	{ DDRC_PCTRL_0(0), 1 },
> +	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
> +	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
> +	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
> +	{ DDRC_PCFGWQOS1_0(0), 0xffff },
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> +	{ 0x100a0, 0 },
> +	{ 0x100a1, 1 },
> +	{ 0x100a2, 2 },
> +	{ 0x100a3, 3 },
> +	{ 0x100a4, 4 },
> +	{ 0x100a5, 5 },
> +	{ 0x100a6, 6 },
> +	{ 0x100a7, 7 },
> +	{ 0x110a0, 0 },
> +	{ 0x110a1, 1 },
> +	{ 0x110a2, 2 },
> +	{ 0x110a3, 3 },
> +	{ 0x110a4, 4 },
> +	{ 0x110a5, 5 },
> +	{ 0x110a6, 6 },
> +	{ 0x110a7, 7 },
> +	{ 0x120a0, 0 },
> +	{ 0x120a1, 1 },
> +	{ 0x120a2, 2 },
> +	{ 0x120a3, 3 },
> +	{ 0x120a4, 4 },
> +	{ 0x120a5, 5 },
> +	{ 0x120a6, 6 },
> +	{ 0x120a7, 7 },
> +	{ 0x130a0, 0 },
> +	{ 0x130a1, 1 },
> +	{ 0x130a2, 2 },
> +	{ 0x130a3, 3 },
> +	{ 0x130a4, 4 },
> +	{ 0x130a5, 5 },
> +	{ 0x130a6, 6 },
> +	{ 0x130a7, 7 },
> +	{ 0x1005f, 0x01ff },
> +	{ 0x1015f, 0x01ff },
> +	{ 0x1105f, 0x01ff },
> +	{ 0x1115f, 0x01ff },
> +	{ 0x1205f, 0x01ff },
> +	{ 0x1215f, 0x01ff },
> +	{ 0x1305f, 0x01ff },
> +	{ 0x1315f, 0x01ff },
> +	{ 0x11005f, 0x01ff },
> +	{ 0x11015f, 0x01ff },
> +	{ 0x11105f, 0x01ff },
> +	{ 0x11115f, 0x01ff },
> +	{ 0x11205f, 0x01ff },
> +	{ 0x11215f, 0x01ff },
> +	{ 0x11305f, 0x01ff },
> +	{ 0x11315f, 0x01ff },
> +	{ 0x0055, 0x01ff },
> +	{ 0x1055, 0x01ff },
> +	{ 0x2055, 0x01ff },
> +	{ 0x3055, 0x01ff },
> +	{ 0x4055, 0x01ff },
> +	{ 0x5055, 0x01ff },
> +	{ 0x6055, 0x01ff },
> +	{ 0x7055, 0x01ff },
> +	{ 0x8055, 0x01ff },
> +	{ 0x9055, 0x01ff },
> +	{ 0x200c5, 0x19 },
> +	{ 0x1200c5, 7 },
> +	{ 0x2002e, 2 },
> +	{ 0x12002e, 1 },
> +	{ 0x90204, 0 },
> +	{ 0x190204, 0 },
> +	{ 0x20024, 0x01ab },
> +	{ 0x2003a, 0 },
> +	{ 0x120024, 0x01ab },
> +	{ 0x2003a, 0 },
> +	{ 0x20056, 3 },
> +	{ 0x120056, 3 },
> +	{ 0x1004d, 0x0e00 },
> +	{ 0x1014d, 0x0e00 },
> +	{ 0x1104d, 0x0e00 },
> +	{ 0x1114d, 0x0e00 },
> +	{ 0x1204d, 0x0e00 },
> +	{ 0x1214d, 0x0e00 },
> +	{ 0x1304d, 0x0e00 },
> +	{ 0x1314d, 0x0e00 },
> +	{ 0x11004d, 0x0e00 },
> +	{ 0x11014d, 0x0e00 },
> +	{ 0x11104d, 0x0e00 },
> +	{ 0x11114d, 0x0e00 },
> +	{ 0x11204d, 0x0e00 },
> +	{ 0x11214d, 0x0e00 },
> +	{ 0x11304d, 0x0e00 },
> +	{ 0x11314d, 0x0e00 },
> +	{ 0x10049, 0x0eba },
> +	{ 0x10149, 0x0eba },
> +	{ 0x11049, 0x0eba },
> +	{ 0x11149, 0x0eba },
> +	{ 0x12049, 0x0eba },
> +	{ 0x12149, 0x0eba },
> +	{ 0x13049, 0x0eba },
> +	{ 0x13149, 0x0eba },
> +	{ 0x110049, 0x0eba },
> +	{ 0x110149, 0x0eba },
> +	{ 0x111049, 0x0eba },
> +	{ 0x111149, 0x0eba },
> +	{ 0x112049, 0x0eba },
> +	{ 0x112149, 0x0eba },
> +	{ 0x113049, 0x0eba },
> +	{ 0x113149, 0x0eba },
> +	{ 0x0043, 0x63 },
> +	{ 0x1043, 0x63 },
> +	{ 0x2043, 0x63 },
> +	{ 0x3043, 0x63 },
> +	{ 0x4043, 0x63 },
> +	{ 0x5043, 0x63 },
> +	{ 0x6043, 0x63 },
> +	{ 0x7043, 0x63 },
> +	{ 0x8043, 0x63 },
> +	{ 0x9043, 0x63 },
> +	{ 0x20018, 3 },
> +	{ 0x20075, 4 },
> +	{ 0x20050, 0 },
> +	{ 0x20008, 0x0320 },
> +	{ 0x120008, 0xa7 },
> +	{ 0x20088, 9 },
> +	{ 0x200b2, 0xdc },
> +	{ 0x10043, 0x05a1 },
> +	{ 0x10143, 0x05a1 },
> +	{ 0x11043, 0x05a1 },
> +	{ 0x11143, 0x05a1 },
> +	{ 0x12043, 0x05a1 },
> +	{ 0x12143, 0x05a1 },
> +	{ 0x13043, 0x05a1 },
> +	{ 0x13143, 0x05a1 },
> +	{ 0x1200b2, 0xdc },
> +	{ 0x110043, 0x05a1 },
> +	{ 0x110143, 0x05a1 },
> +	{ 0x111043, 0x05a1 },
> +	{ 0x111143, 0x05a1 },
> +	{ 0x112043, 0x05a1 },
> +	{ 0x112143, 0x05a1 },
> +	{ 0x113043, 0x05a1 },
> +	{ 0x113143, 0x05a1 },
> +	{ 0x200fa, 1 },
> +	{ 0x1200fa, 1 },
> +	{ 0x20019, 1 },
> +	{ 0x120019, 1 },
> +	{ 0x200f0, 0 },
> +	{ 0x200f1, 0 },
> +	{ 0x200f2, 0x4444 },
> +	{ 0x200f3, 0x8888 },
> +	{ 0x200f4, 0x5555 },
> +	{ 0x200f5, 0 },
> +	{ 0x200f6, 0 },
> +	{ 0x200f7, 0xf000 },
> +	{ 0x20025, 0 },
> +	{ 0x2002d, 0 },
> +	{ 0x12002d, 0 },
> +	{ 0x200c7, 0x80 },
> +	{ 0x1200c7, 0x80 },
> +	{ 0x200ca, 0x0106 },
> +	{ 0x1200ca, 0x0106 },
> +	{ 0x20110, 2 },
> +	{ 0x20111, 3 },
> +	{ 0x20112, 4 },
> +	{ 0x20113, 5 },
> +	{ 0x20114, 0 },
> +	{ 0x20115, 1 },
> +};
> +
> +/* P0 message block parameter for training firmware */
> +static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> +	{ 0xd0000, 0 },
> +	{ 0x54003, 0x0c80 },
> +	{ 0x54004, 2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> +	{ 0x54008, 0x131f },
> +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> +	{ 0x5400b, 2 },
> +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> +	{ 0x54019, 0x2dd4 },
> +	{ 0x5401a, 0x31 },
> +	{ 0x5401b, 0x4a66 },
> +	{ 0x5401c, 0x4a08 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x2dd4 },
> +	{ 0x54020, 0x31 },
> +	{ 0x54021, 0x4a66 },
> +	{ 0x54022, 0x4a08 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, CH2_LPDDR4_CS },
> +	{ 0x54032, 0xd400 },
> +	{ 0x54033, 0x312d },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x084a },
> +	{ 0x54036, 0x4a },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xd400 },
> +	{ 0x54039, 0x312d },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x084a },
> +	{ 0x5403c, 0x4a },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 1 },
> +};
> +
> +
> +/* P1 message block parameter for training firmware */
> +static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> +	{ 0xd0000, 0 },
> +	{ 0x54002, 1 },
> +	{ 0x54003, 0x029c },
> +	{ 0x54004, 2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> +	{ 0x5400b, 2 },
> +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> +	{ 0x54019, 0x0994 },
> +	{ 0x5401a, 0x31 },
> +	{ 0x5401b, 0x4a66 },
> +	{ 0x5401c, 0x4a08 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x0994 },
> +	{ 0x54020, 0x31 },
> +	{ 0x54021, 0x4a66 },
> +	{ 0x54022, 0x4a08 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, CH2_LPDDR4_CS },
> +	{ 0x54032, 0x9400 },
> +	{ 0x54033, 0x3109 },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x084a },
> +	{ 0x54036, 0x4a },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0x9400 },
> +	{ 0x54039, 0x3109 },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x084a },
> +	{ 0x5403c, 0x4a },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 1 },
> +};
> +
> +
> +/* P0 2D message block parameter for training firmware */
> +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> +	{ 0xd0000, 0 },
> +	{ 0x54003, 0x0c80 },
> +	{ 0x54004, 2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> +	{ 0x54008, 0x61 },
> +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> +	{ 0x5400b, 2 },
> +	{ 0x5400d, 0x0100 },
> +	{ 0x5400f, 0x0100 },
> +	{ 0x54010, 0x1f7f },
> +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> +	{ 0x54019, 0x2dd4 },
> +	{ 0x5401a, 0x31 },
> +	{ 0x5401b, 0x4a66 },
> +	{ 0x5401c, 0x4a08 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x2dd4 },
> +	{ 0x54020, 0x31 },
> +	{ 0x54021, 0x4a66 },
> +	{ 0x54022, 0x4a08 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, CH2_LPDDR4_CS },
> +	{ 0x54032, 0xd400 },
> +	{ 0x54033, 0x312d },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x084a },
> +	{ 0x54036, 0x4a },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xd400 },
> +	{ 0x54039, 0x312d },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x084a },
> +	{ 0x5403c, 0x4a },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param lpddr4_phy_pie[] = {
> +	{ 0xd0000, 0 },
> +	{ 0x90000, 0x10 },
> +	{ 0x90001, 0x0400 },
> +	{ 0x90002, 0x010e },
> +	{ 0x90003, 0 },
> +	{ 0x90004, 0 },
> +	{ 0x90005, 8 },
> +	{ 0x90029, 0x0b },
> +	{ 0x9002a, 0x0480 },
> +	{ 0x9002b, 0x0109 },
> +	{ 0x9002c, 8 },
> +	{ 0x9002d, 0x0448 },
> +	{ 0x9002e, 0x0139 },
> +	{ 0x9002f, 8 },
> +	{ 0x90030, 0x0478 },
> +	{ 0x90031, 0x0109 },
> +	{ 0x90032, 0 },
> +	{ 0x90033, 0xe8 },
> +	{ 0x90034, 0x0109 },
> +	{ 0x90035, 2 },
> +	{ 0x90036, 0x10 },
> +	{ 0x90037, 0x0139 },
> +	{ 0x90038, 0x0f },
> +	{ 0x90039, 0x07c0 },
> +	{ 0x9003a, 0x0139 },
> +	{ 0x9003b, 0x44 },
> +	{ 0x9003c, 0x0630 },
> +	{ 0x9003d, 0x0159 },
> +	{ 0x9003e, 0x014f },
> +	{ 0x9003f, 0x0630 },
> +	{ 0x90040, 0x0159 },
> +	{ 0x90041, 0x47 },
> +	{ 0x90042, 0x0630 },
> +	{ 0x90043, 0x0149 },
> +	{ 0x90044, 0x4f },
> +	{ 0x90045, 0x0630 },
> +	{ 0x90046, 0x0179 },
> +	{ 0x90047, 8 },
> +	{ 0x90048, 0xe0 },
> +	{ 0x90049, 0x0109 },
> +	{ 0x9004a, 0 },
> +	{ 0x9004b, 0x07c8 },
> +	{ 0x9004c, 0x0109 },
> +	{ 0x9004d, 0 },
> +	{ 0x9004e, 1 },
> +	{ 0x9004f, 8 },
> +	{ 0x90050, 0 },
> +	{ 0x90051, 0x045a },
> +	{ 0x90052, 9 },
> +	{ 0x90053, 0 },
> +	{ 0x90054, 0x0448 },
> +	{ 0x90055, 0x0109 },
> +	{ 0x90056, 0x40 },
> +	{ 0x90057, 0x0630 },
> +	{ 0x90058, 0x0179 },
> +	{ 0x90059, 1 },
> +	{ 0x9005a, 0x0618 },
> +	{ 0x9005b, 0x0109 },
> +	{ 0x9005c, 0x40c0 },
> +	{ 0x9005d, 0x0630 },
> +	{ 0x9005e, 0x0149 },
> +	{ 0x9005f, 8 },
> +	{ 0x90060, 4 },
> +	{ 0x90061, 0x48 },
> +	{ 0x90062, 0x4040 },
> +	{ 0x90063, 0x0630 },
> +	{ 0x90064, 0x0149 },
> +	{ 0x90065, 0 },
> +	{ 0x90066, 4 },
> +	{ 0x90067, 0x48 },
> +	{ 0x90068, 0x40 },
> +	{ 0x90069, 0x0630 },
> +	{ 0x9006a, 0x0149 },
> +	{ 0x9006b, 0x10 },
> +	{ 0x9006c, 4 },
> +	{ 0x9006d, 0x18 },
> +	{ 0x9006e, 0 },
> +	{ 0x9006f, 4 },
> +	{ 0x90070, 0x78 },
> +	{ 0x90071, 0x0549 },
> +	{ 0x90072, 0x0630 },
> +	{ 0x90073, 0x0159 },
> +	{ 0x90074, 0x0d49 },
> +	{ 0x90075, 0x0630 },
> +	{ 0x90076, 0x0159 },
> +	{ 0x90077, 0x094a },
> +	{ 0x90078, 0x0630 },
> +	{ 0x90079, 0x0159 },
> +	{ 0x9007a, 0x0441 },
> +	{ 0x9007b, 0x0630 },
> +	{ 0x9007c, 0x0149 },
> +	{ 0x9007d, 0x42 },
> +	{ 0x9007e, 0x0630 },
> +	{ 0x9007f, 0x0149 },
> +	{ 0x90080, 1 },
> +	{ 0x90081, 0x0630 },
> +	{ 0x90082, 0x0149 },
> +	{ 0x90083, 0 },
> +	{ 0x90084, 0xe0 },
> +	{ 0x90085, 0x0109 },
> +	{ 0x90086, 0x0a },
> +	{ 0x90087, 0x10 },
> +	{ 0x90088, 0x0109 },
> +	{ 0x90089, 9 },
> +	{ 0x9008a, 0x03c0 },
> +	{ 0x9008b, 0x0149 },
> +	{ 0x9008c, 9 },
> +	{ 0x9008d, 0x03c0 },
> +	{ 0x9008e, 0x0159 },
> +	{ 0x9008f, 0x18 },
> +	{ 0x90090, 0x10 },
> +	{ 0x90091, 0x0109 },
> +	{ 0x90092, 0 },
> +	{ 0x90093, 0x03c0 },
> +	{ 0x90094, 0x0109 },
> +	{ 0x90095, 0x18 },
> +	{ 0x90096, 4 },
> +	{ 0x90097, 0x48 },
> +	{ 0x90098, 0x18 },
> +	{ 0x90099, 4 },
> +	{ 0x9009a, 0x58 },
> +	{ 0x9009b, 0x0a },
> +	{ 0x9009c, 0x10 },
> +	{ 0x9009d, 0x0109 },
> +	{ 0x9009e, 2 },
> +	{ 0x9009f, 0x10 },
> +	{ 0x900a0, 0x0109 },
> +	{ 0x900a1, 5 },
> +	{ 0x900a2, 0x07c0 },
> +	{ 0x900a3, 0x0109 },
> +	{ 0x900a4, 0x10 },
> +	{ 0x900a5, 0x10 },
> +	{ 0x900a6, 0x0109 },
> +	{ 0x40000, 0x0811 },
> +	{ 0x40020, 0x0880 },
> +	{ 0x40040, 0 },
> +	{ 0x40060, 0 },
> +	{ 0x40001, 0x4008 },
> +	{ 0x40021, 0x83 },
> +	{ 0x40041, 0x4f },
> +	{ 0x40061, 0 },
> +	{ 0x40002, 0x4040 },
> +	{ 0x40022, 0x83 },
> +	{ 0x40042, 0x51 },
> +	{ 0x40062, 0 },
> +	{ 0x40003, 0x0811 },
> +	{ 0x40023, 0x0880 },
> +	{ 0x40043, 0 },
> +	{ 0x40063, 0 },
> +	{ 0x40004, 0x0720 },
> +	{ 0x40024, 0x0f },
> +	{ 0x40044, 0x1740 },
> +	{ 0x40064, 0 },
> +	{ 0x40005, 0x16 },
> +	{ 0x40025, 0x83 },
> +	{ 0x40045, 0x4b },
> +	{ 0x40065, 0 },
> +	{ 0x40006, 0x0716 },
> +	{ 0x40026, 0x0f },
> +	{ 0x40046, 0x2001 },
> +	{ 0x40066, 0 },
> +	{ 0x40007, 0x0716 },
> +	{ 0x40027, 0x0f },
> +	{ 0x40047, 0x2800 },
> +	{ 0x40067, 0 },
> +	{ 0x40008, 0x0716 },
> +	{ 0x40028, 0x0f },
> +	{ 0x40048, 0x0f00 },
> +	{ 0x40068, 0 },
> +	{ 0x40009, 0x0720 },
> +	{ 0x40029, 0x0f },
> +	{ 0x40049, 0x1400 },
> +	{ 0x40069, 0 },
> +	{ 0x4000a, 0x0e08 },
> +	{ 0x4002a, 0x0c15 },
> +	{ 0x4004a, 0 },
> +	{ 0x4006a, 0 },
> +	{ 0x4000b, 0x0623 },
> +	{ 0x4002b, 0x15 },
> +	{ 0x4004b, 0 },
> +	{ 0x4006b, 0 },
> +	{ 0x4000c, 0x4028 },
> +	{ 0x4002c, 0x80 },
> +	{ 0x4004c, 0 },
> +	{ 0x4006c, 0 },
> +	{ 0x4000d, 0x0e08 },
> +	{ 0x4002d, 0x0c1a },
> +	{ 0x4004d, 0 },
> +	{ 0x4006d, 0 },
> +	{ 0x4000e, 0x0623 },
> +	{ 0x4002e, 0x1a },
> +	{ 0x4004e, 0 },
> +	{ 0x4006e, 0 },
> +	{ 0x4000f, 0x4040 },
> +	{ 0x4002f, 0x80 },
> +	{ 0x4004f, 0 },
> +	{ 0x4006f, 0 },
> +	{ 0x40010, 0x2604 },
> +	{ 0x40030, 0x15 },
> +	{ 0x40050, 0 },
> +	{ 0x40070, 0 },
> +	{ 0x40011, 0x0708 },
> +	{ 0x40031, 5 },
> +	{ 0x40051, 0 },
> +	{ 0x40071, 0x2002 },
> +	{ 0x40012, 8 },
> +	{ 0x40032, 0x80 },
> +	{ 0x40052, 0 },
> +	{ 0x40072, 0 },
> +	{ 0x40013, 0x2604 },
> +	{ 0x40033, 0x1a },
> +	{ 0x40053, 0 },
> +	{ 0x40073, 0 },
> +	{ 0x40014, 0x0708 },
> +	{ 0x40034, 0x0a },
> +	{ 0x40054, 0 },
> +	{ 0x40074, 0x2002 },
> +	{ 0x40015, 0x4040 },
> +	{ 0x40035, 0x80 },
> +	{ 0x40055, 0 },
> +	{ 0x40075, 0 },
> +	{ 0x40016, 0x060a },
> +	{ 0x40036, 0x15 },
> +	{ 0x40056, 0x1200 },
> +	{ 0x40076, 0 },
> +	{ 0x40017, 0x061a },
> +	{ 0x40037, 0x15 },
> +	{ 0x40057, 0x1300 },
> +	{ 0x40077, 0 },
> +	{ 0x40018, 0x060a },
> +	{ 0x40038, 0x1a },
> +	{ 0x40058, 0x1200 },
> +	{ 0x40078, 0 },
> +	{ 0x40019, 0x0642 },
> +	{ 0x40039, 0x1a },
> +	{ 0x40059, 0x1300 },
> +	{ 0x40079, 0 },
> +	{ 0x4001a, 0x4808 },
> +	{ 0x4003a, 0x0880 },
> +	{ 0x4005a, 0 },
> +	{ 0x4007a, 0 },
> +	{ 0x900a7, 0 },
> +	{ 0x900a8, 0x0790 },
> +	{ 0x900a9, 0x011a },
> +	{ 0x900aa, 8 },
> +	{ 0x900ab, 0x07aa },
> +	{ 0x900ac, 0x2a },
> +	{ 0x900ad, 0x10 },
> +	{ 0x900ae, 0x07b2 },
> +	{ 0x900af, 0x2a },
> +	{ 0x900b0, 0 },
> +	{ 0x900b1, 0x07c8 },
> +	{ 0x900b2, 0x0109 },
> +	{ 0x900b3, 0x10 },
> +	{ 0x900b4, 0x02a8 },
> +	{ 0x900b5, 0x0129 },
> +	{ 0x900b6, 8 },
> +	{ 0x900b7, 0x0370 },
> +	{ 0x900b8, 0x0129 },
> +	{ 0x900b9, 0x0a },
> +	{ 0x900ba, 0x03c8 },
> +	{ 0x900bb, 0x01a9 },
> +	{ 0x900bc, 0x0c },
> +	{ 0x900bd, 0x0408 },
> +	{ 0x900be, 0x0199 },
> +	{ 0x900bf, 0x14 },
> +	{ 0x900c0, 0x0790 },
> +	{ 0x900c1, 0x011a },
> +	{ 0x900c2, 8 },
> +	{ 0x900c3, 4 },
> +	{ 0x900c4, 0x18 },
> +	{ 0x900c5, 0x0e },
> +	{ 0x900c6, 0x0408 },
> +	{ 0x900c7, 0x0199 },
> +	{ 0x900c8, 8 },
> +	{ 0x900c9, 0x8568 },
> +	{ 0x900ca, 0x0108 },
> +	{ 0x900cb, 0x18 },
> +	{ 0x900cc, 0x0790 },
> +	{ 0x900cd, 0x016a },
> +	{ 0x900ce, 8 },
> +	{ 0x900cf, 0x01d8 },
> +	{ 0x900d0, 0x0169 },
> +	{ 0x900d1, 0x10 },
> +	{ 0x900d2, 0x8558 },
> +	{ 0x900d3, 0x0168 },
> +	{ 0x900d4, 0x70 },
> +	{ 0x900d5, 0x0788 },
> +	{ 0x900d6, 0x016a },
> +	{ 0x900d7, 0x1ff8 },
> +	{ 0x900d8, 0x85a8 },
> +	{ 0x900d9, 0x01e8 },
> +	{ 0x900da, 0x50 },
> +	{ 0x900db, 0x0798 },
> +	{ 0x900dc, 0x016a },
> +	{ 0x900dd, 0x60 },
> +	{ 0x900de, 0x07a0 },
> +	{ 0x900df, 0x016a },
> +	{ 0x900e0, 8 },
> +	{ 0x900e1, 0x8310 },
> +	{ 0x900e2, 0x0168 },
> +	{ 0x900e3, 8 },
> +	{ 0x900e4, 0xa310 },
> +	{ 0x900e5, 0x0168 },
> +	{ 0x900e6, 0x0a },
> +	{ 0x900e7, 0x0408 },
> +	{ 0x900e8, 0x0169 },
> +	{ 0x900e9, 0x6e },
> +	{ 0x900ea, 0 },
> +	{ 0x900eb, 0x68 },
> +	{ 0x900ec, 0 },
> +	{ 0x900ed, 0x0408 },
> +	{ 0x900ee, 0x0169 },
> +	{ 0x900ef, 0 },
> +	{ 0x900f0, 0x8310 },
> +	{ 0x900f1, 0x0168 },
> +	{ 0x900f2, 0 },
> +	{ 0x900f3, 0xa310 },
> +	{ 0x900f4, 0x0168 },
> +	{ 0x900f5, 0x1ff8 },
> +	{ 0x900f6, 0x85a8 },
> +	{ 0x900f7, 0x01e8 },
> +	{ 0x900f8, 0x68 },
> +	{ 0x900f9, 0x0798 },
> +	{ 0x900fa, 0x016a },
> +	{ 0x900fb, 0x78 },
> +	{ 0x900fc, 0x07a0 },
> +	{ 0x900fd, 0x016a },
> +	{ 0x900fe, 0x68 },
> +	{ 0x900ff, 0x0790 },
> +	{ 0x90100, 0x016a },
> +	{ 0x90101, 8 },
> +	{ 0x90102, 0x8b10 },
> +	{ 0x90103, 0x0168 },
> +	{ 0x90104, 8 },
> +	{ 0x90105, 0xab10 },
> +	{ 0x90106, 0x0168 },
> +	{ 0x90107, 0x0a },
> +	{ 0x90108, 0x0408 },
> +	{ 0x90109, 0x0169 },
> +	{ 0x9010a, 0x58 },
> +	{ 0x9010b, 0 },
> +	{ 0x9010c, 0x68 },
> +	{ 0x9010d, 0 },
> +	{ 0x9010e, 0x0408 },
> +	{ 0x9010f, 0x0169 },
> +	{ 0x90110, 0 },
> +	{ 0x90111, 0x8b10 },
> +	{ 0x90112, 0x0168 },
> +	{ 0x90113, 0 },
> +	{ 0x90114, 0xab10 },
> +	{ 0x90115, 0x0168 },
> +	{ 0x90116, 0 },
> +	{ 0x90117, 0x01d8 },
> +	{ 0x90118, 0x0169 },
> +	{ 0x90119, 0x80 },
> +	{ 0x9011a, 0x0790 },
> +	{ 0x9011b, 0x016a },
> +	{ 0x9011c, 0x18 },
> +	{ 0x9011d, 0x07aa },
> +	{ 0x9011e, 0x6a },
> +	{ 0x9011f, 0x0a },
> +	{ 0x90120, 0 },
> +	{ 0x90121, 0x01e9 },
> +	{ 0x90122, 8 },
> +	{ 0x90123, 0x8080 },
> +	{ 0x90124, 0x0108 },
> +	{ 0x90125, 0x0f },
> +	{ 0x90126, 0x0408 },
> +	{ 0x90127, 0x0169 },
> +	{ 0x90128, 0x0c },
> +	{ 0x90129, 0 },
> +	{ 0x9012a, 0x68 },
> +	{ 0x9012b, 9 },
> +	{ 0x9012c, 0 },
> +	{ 0x9012d, 0x01a9 },
> +	{ 0x9012e, 0 },
> +	{ 0x9012f, 0x0408 },
> +	{ 0x90130, 0x0169 },
> +	{ 0x90131, 0 },
> +	{ 0x90132, 0x8080 },
> +	{ 0x90133, 0x0108 },
> +	{ 0x90134, 8 },
> +	{ 0x90135, 0x07aa },
> +	{ 0x90136, 0x6a },
> +	{ 0x90137, 0 },
> +	{ 0x90138, 0x8568 },
> +	{ 0x90139, 0x0108 },
> +	{ 0x9013a, 0xb7 },
> +	{ 0x9013b, 0x0790 },
> +	{ 0x9013c, 0x016a },
> +	{ 0x9013d, 0x1f },
> +	{ 0x9013e, 0 },
> +	{ 0x9013f, 0x68 },
> +	{ 0x90140, 8 },
> +	{ 0x90141, 0x8558 },
> +	{ 0x90142, 0x0168 },
> +	{ 0x90143, 0x0f },
> +	{ 0x90144, 0x0408 },
> +	{ 0x90145, 0x0169 },
> +	{ 0x90146, 0x0c },
> +	{ 0x90147, 0 },
> +	{ 0x90148, 0x68 },
> +	{ 0x90149, 0 },
> +	{ 0x9014a, 0x0408 },
> +	{ 0x9014b, 0x0169 },
> +	{ 0x9014c, 0 },
> +	{ 0x9014d, 0x8558 },
> +	{ 0x9014e, 0x0168 },
> +	{ 0x9014f, 8 },
> +	{ 0x90150, 0x03c8 },
> +	{ 0x90151, 0x01a9 },
> +	{ 0x90152, 3 },
> +	{ 0x90153, 0x0370 },
> +	{ 0x90154, 0x0129 },
> +	{ 0x90155, 0x20 },
> +	{ 0x90156, 0x02aa },
> +	{ 0x90157, 9 },
> +	{ 0x90158, 0 },
> +	{ 0x90159, 0x0400 },
> +	{ 0x9015a, 0x010e },
> +	{ 0x9015b, 8 },
> +	{ 0x9015c, 0xe8 },
> +	{ 0x9015d, 0x0109 },
> +	{ 0x9015e, 0 },
> +	{ 0x9015f, 0x8140 },
> +	{ 0x90160, 0x010c },
> +	{ 0x90161, 0x10 },
> +	{ 0x90162, 0x8138 },
> +	{ 0x90163, 0x010c },
> +	{ 0x90164, 8 },
> +	{ 0x90165, 0x07c8 },
> +	{ 0x90166, 0x0101 },
> +	{ 0x90167, 8 },
> +	{ 0x90168, 0 },
> +	{ 0x90169, 8 },
> +	{ 0x9016a, 8 },
> +	{ 0x9016b, 0x0448 },
> +	{ 0x9016c, 0x0109 },
> +	{ 0x9016d, 0x0f },
> +	{ 0x9016e, 0x07c0 },
> +	{ 0x9016f, 0x0109 },
> +	{ 0x90170, 0 },
> +	{ 0x90171, 0xe8 },
> +	{ 0x90172, 0x0109 },
> +	{ 0x90173, 0x47 },
> +	{ 0x90174, 0x0630 },
> +	{ 0x90175, 0x0109 },
> +	{ 0x90176, 8 },
> +	{ 0x90177, 0x0618 },
> +	{ 0x90178, 0x0109 },
> +	{ 0x90179, 8 },
> +	{ 0x9017a, 0xe0 },
> +	{ 0x9017b, 0x0109 },
> +	{ 0x9017c, 0 },
> +	{ 0x9017d, 0x07c8 },
> +	{ 0x9017e, 0x0109 },
> +	{ 0x9017f, 8 },
> +	{ 0x90180, 0x8140 },
> +	{ 0x90181, 0x010c },
> +	{ 0x90182, 0 },
> +	{ 0x90183, 1 },
> +	{ 0x90184, 8 },
> +	{ 0x90185, 8 },
> +	{ 0x90186, 4 },
> +	{ 0x90187, 8 },
> +	{ 0x90188, 8 },
> +	{ 0x90189, 0x07c8 },
> +	{ 0x9018a, 0x0101 },
> +	{ 0x90006, 0 },
> +	{ 0x90007, 0 },
> +	{ 0x90008, 8 },
> +	{ 0x90009, 0 },
> +	{ 0x9000a, 0 },
> +	{ 0x9000b, 0 },
> +	{ 0xd00e7, 0x0400 },
> +	{ 0x90017, 0 },
> +	{ 0x9001f, 0x2a },
> +	{ 0x90026, 0x6a },
> +	{ 0x400d0, 0 },
> +	{ 0x400d1, 0x0101 },
> +	{ 0x400d2, 0x0105 },
> +	{ 0x400d3, 0x0107 },
> +	{ 0x400d4, 0x010f },
> +	{ 0x400d5, 0x0202 },
> +	{ 0x400d6, 0x020a },
> +	{ 0x400d7, 0x020b },
> +	{ 0x2003a, 2 },
> +	{ 0x2000b, 0x64 },
> +	{ 0x2000c, 0xc8 },
> +	{ 0x2000d, 0x07d0 },
> +	{ 0x2000e, 0x2c },
> +	{ 0x12000b, 0x14 },
> +	{ 0x12000c, 0x29 },
> +	{ 0x12000d, 0x01a1 },
> +	{ 0x12000e, 0x10 },
> +	{ 0x9000c, 0 },
> +	{ 0x9000d, 0x0173 },
> +	{ 0x9000e, 0x60 },
> +	{ 0x9000f, 0x6110 },
> +	{ 0x90010, 0x2152 },
> +	{ 0x90011, 0xdfbd },
> +	{ 0x90012, 0x60 },
> +	{ 0x90013, 0x6152 },
> +	{ 0x20010, 0x5a },
> +	{ 0x20011, 3 },
> +	{ 0x40080, 0xe0 },
> +	{ 0x40081, 0x12 },
> +	{ 0x40082, 0xe0 },
> +	{ 0x40083, 0x12 },
> +	{ 0x40084, 0xe0 },
> +	{ 0x40085, 0x12 },
> +	{ 0x140080, 0xe0 },
> +	{ 0x140081, 0x12 },
> +	{ 0x140082, 0xe0 },
> +	{ 0x140083, 0x12 },
> +	{ 0x140084, 0xe0 },
> +	{ 0x140085, 0x12 },
> +	{ 0x400fd, 0x0f },
> +	{ 0x10011, 1 },
> +	{ 0x10012, 1 },
> +	{ 0x10013, 0x0180 },
> +	{ 0x10018, 1 },
> +	{ 0x10002, 0x6209 },
> +	{ 0x100b2, 1 },
> +	{ 0x101b4, 1 },
> +	{ 0x102b4, 1 },
> +	{ 0x103b4, 1 },
> +	{ 0x104b4, 1 },
> +	{ 0x105b4, 1 },
> +	{ 0x106b4, 1 },
> +	{ 0x107b4, 1 },
> +	{ 0x108b4, 1 },
> +	{ 0x11011, 1 },
> +	{ 0x11012, 1 },
> +	{ 0x11013, 0x0180 },
> +	{ 0x11018, 1 },
> +	{ 0x11002, 0x6209 },
> +	{ 0x110b2, 1 },
> +	{ 0x111b4, 1 },
> +	{ 0x112b4, 1 },
> +	{ 0x113b4, 1 },
> +	{ 0x114b4, 1 },
> +	{ 0x115b4, 1 },
> +	{ 0x116b4, 1 },
> +	{ 0x117b4, 1 },
> +	{ 0x118b4, 1 },
> +	{ 0x12011, 1 },
> +	{ 0x12012, 1 },
> +	{ 0x12013, 0x0180 },
> +	{ 0x12018, 1 },
> +	{ 0x12002, 0x6209 },
> +	{ 0x120b2, 1 },
> +	{ 0x121b4, 1 },
> +	{ 0x122b4, 1 },
> +	{ 0x123b4, 1 },
> +	{ 0x124b4, 1 },
> +	{ 0x125b4, 1 },
> +	{ 0x126b4, 1 },
> +	{ 0x127b4, 1 },
> +	{ 0x128b4, 1 },
> +	{ 0x13011, 1 },
> +	{ 0x13012, 1 },
> +	{ 0x13013, 0x0180 },
> +	{ 0x13018, 1 },
> +	{ 0x13002, 0x6209 },
> +	{ 0x130b2, 1 },
> +	{ 0x131b4, 1 },
> +	{ 0x132b4, 1 },
> +	{ 0x133b4, 1 },
> +	{ 0x134b4, 1 },
> +	{ 0x135b4, 1 },
> +	{ 0x136b4, 1 },
> +	{ 0x137b4, 1 },
> +	{ 0x138b4, 1 },
> +	{ 0x2003a, 2 },
> +	{ 0xc0080, 2 },
> +	{ 0xd0000, 1 }
> +};
> +
> +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> +	{
> +		/* P0 3200mts 1D */
> +		.drate = 3200,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = lpddr4_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> +	},
> +	{
> +		/* P1 667mts 1D */
> +		.drate = 667,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = lpddr4_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> +	},
> +	{
> +		/* P0 3200mts 2D */
> +		.drate = 3200,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = lpddr4_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info dram_timing_ch2 = {
> +	.ddrc_cfg = lpddr4_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> +	.ddrphy_cfg = lpddr4_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> +	.fsp_msg = lpddr4_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> +	.ddrphy_pie = lpddr4_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> +	.fsp_table = { 3200, 667, },
> +};
> diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
> new file mode 100644
> index 0000000000..7dcc9a7db7
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright Boundary Devices
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#include <config.h>
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/arch/lpddr4_define.h>
> +
> +/* MNT Reform2 */
> +#define CONFIG_DDR_MB 4096
> +#define CONFIG_DDR_RANK_BITS 1
> +#define CONFIG_DDR_CHANNEL_CNT 2

These are not allowed anymore - any new CONFIG_ should flow into Kbuild.

See:

	https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/565798

CONFIG_DDR_MB  is already in Kbuild, just move the value in defconfig.

Best regards,
Stefano Babic

> +
> +#ifdef WR_POST_EXT_3200
> +#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
> +#else
> +#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
> +#endif
> +
> +#if CONFIG_DDR_MB == 1024
> +	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
> +#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
> +#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
> +
> +#elif CONFIG_DDR_MB == 2048
> +	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
> +#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
> +#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
> +	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
> +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
> +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
> +
> +#elif CONFIG_DDR_MB == 3072
> +	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
> +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
> +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
> +
> +#elif CONFIG_DDR_MB == 4096
> +	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
> +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
> +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
> +#else
> +#error unsupported memory size
> +#endif
> +
> +#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
> +#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
> +
> +#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> +#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
> +#define CH2_LPDDR4_CS			LPDDR4_CS_R0
> +#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
> +#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
> +#else
> +#error unsupported memory rank/size
> +#endif
> +/*
> + * rank0 will succeed, even if really rank 1, so we need
> + * to probe memory if rank0 succeeds
> + */
> +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> +#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
> +#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
> +#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
> +#endif
> +
> +#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
> +#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
> +#define CH2_LPDDR4_CS			LPDDR4_CS_R1
> +#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
> +#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
> +#else
> +#error unsupported memory rank/size
> +#endif
> +
> +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> +#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
> +#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
> +#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
> +#endif
> +
> +#else
> +#error unsupported rank bits
> +#endif
> +
> +#if (CONFIG_DDR_CHANNEL_CNT == 2)
> +#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
> +#error unsupported options
> +#endif
> +#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> +#error unsupported options
> +#endif
> +#endif
> diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
> new file mode 100644
> index 0000000000..21fad4972a
> --- /dev/null
> +++ b/board/mntre/imx8mq_reform2/spl.c
> @@ -0,0 +1,260 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <hang.h>
> +#include <image.h>
> +#include <init.h>
> +#include <log.h>
> +#include <asm/global_data.h>
> +#include <asm/io.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/arch/imx8mq_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/arch/clock.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <fsl_esdhc_imx.h>
> +#include <mmc.h>
> +#include <linux/delay.h>
> +#include <power/pmic.h>
> +#include <spl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +extern struct dram_timing_info dram_timing_ch2;
> +
> +static void spl_dram_init(void)
> +{
> +	ddr_init(&dram_timing_ch2);
> +}
> +
> +#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +static struct i2c_pads_info i2c_pad_info1 = {
> +	.scl = {
> +		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
> +		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> +		.gp = IMX_GPIO_NR(5, 14),
> +	},
> +	.sda = {
> +		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
> +		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> +		.gp = IMX_GPIO_NR(5, 15),
> +	},
> +};
> +
> +#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
> +#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
> +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret = 0;
> +
> +	switch (cfg->esdhc_base) {
> +	case USDHC1_BASE_ADDR:
> +		ret = 1;
> +		break;
> +	case USDHC2_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> +		return ret;
> +	}
> +
> +	return 1;
> +}
> +
> +#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
> +			 PAD_CTL_FSEL2)
> +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
> +
> +static iomux_v3_cfg_t const usdhc1_pads[] = {
> +	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> +	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> +	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> +	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> +	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> +	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> +	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
> +	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> +	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
> +	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
> +};
> +
> +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> +	{USDHC1_BASE_ADDR, 0, 8},
> +	{USDHC2_BASE_ADDR, 0, 4},
> +};
> +
> +int board_mmc_init(struct bd_info *bis)
> +{
> +	int i, ret;
> +	/*
> +	 * According to the board_mmc_init() the following map is done:
> +	 * (U-Boot device node)    (Physical Port)
> +	 * mmc0                    USDHC1
> +	 * mmc1                    USDHC2
> +	 */
> +	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
> +		switch (i) {
> +		case 0:
> +			init_clk_usdhc(0);
> +			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
> +			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
> +							 ARRAY_SIZE(usdhc1_pads));
> +			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
> +			gpio_direction_output(USDHC1_PWR_GPIO, 0);
> +			udelay(500);
> +			gpio_direction_output(USDHC1_PWR_GPIO, 1);
> +			break;
> +		case 1:
> +			init_clk_usdhc(1);
> +			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
> +			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
> +							 ARRAY_SIZE(usdhc2_pads));
> +			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
> +			gpio_direction_output(USDHC2_VSEL, 0);
> +			break;
> +		default:
> +			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
> +			return -EINVAL;
> +		}
> +
> +		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
> +#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
> +#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
> +#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
> +
> +#define I2C_MUX_ADDR		0x70
> +#define I2C_FAN53555_ADDR	0x60
> +
> +static iomux_v3_cfg_t const power_pads[] = {
> +	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
> +};
> +
> +int power_init_board(void)
> +{
> +	uint8_t val;
> +
> +	imx_iomux_v3_setup_multiple_pads(power_pads,
> +					 ARRAY_SIZE(usdhc2_pads));
> +
> +	/* Release I2C multiplexer reset */
> +	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
> +	gpio_direction_output(I2C1_PCA9546_RESET, 1);
> +
> +	/* Select VSEL0 on voltage regulators */
> +	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
> +	gpio_direction_output(ARM_DRAM_VSEL, 0);
> +	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
> +	gpio_direction_output(DRAM_1P1_VSEL, 0);
> +	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
> +	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
> +
> +	/* Set mux to target ARM/DRAM regulator */
> +	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
> +	/* .6 + .40 = 1.00 */
> +	val = 0x80 + 40;
> +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> +
> +	/* Set mux to target DRAM regulator */
> +	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
> +	/* .6 + .50 = 1.10 */
> +	val = 0x80 + 50;
> +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> +
> +	/* Set mux to target SoC/GPU/VPU regulator */
> +	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
> +	/*  .6 + .30 = .90 */
> +	val = 0x80 + 30;
> +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> +
> +	/* Set mux to target peripherals */
> +	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
> +
> +	return 0;
> +}
> +
> +void spl_board_init(void)
> +{
> +	puts("Normal Boot\n");
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> +	int ret;
> +
> +	/* Clear global data */
> +	memset((void *)gd, 0, sizeof(gd_t));
> +
> +	arch_cpu_init();
> +
> +	init_uart_clk(0);
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	ret = spl_init();
> +	if (ret) {
> +		debug("spl_init() failed: %d\n", ret);
> +		hang();
> +	}
> +
> +	enable_tzc380();
> +
> +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> +	power_init_board();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +
> +	board_init_r(NULL, 0);
> +}
> diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
> new file mode 100644
> index 0000000000..9b14a1bca1
> --- /dev/null
> +++ b/configs/imx8mq_reform2_defconfig
> @@ -0,0 +1,107 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_TEXT_BASE=0x40200000
> +CONFIG_SYS_MALLOC_LEN=0x600000
> +CONFIG_SPL_GPIO=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
> +CONFIG_SPL_TEXT_BASE=0x7E1000
> +CONFIG_TARGET_IMX8MQ_REFORM2=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +CONFIG_SPL_MMC=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_SPL=y
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_SYS_LOAD_ADDR=0x40480000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_REMAKE_ELF=y
> +CONFIG_SYS_MONITOR_LEN=524288
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_USE_PREBOOT=y
> +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
> +CONFIG_CONSOLE_MUX=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_SPL_MAX_SIZE=0x1f000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x180000
> +CONFIG_SPL_BSS_MAX_SIZE=0x2000
> +CONFIG_SPL_BOARD_INIT=y
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_STACK=0x187ff0
> +CONFIG_SYS_SPL_MALLOC=y
> +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
> +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
> +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
> +CONFIG_SPL_I2C=y
> +CONFIG_SPL_POWER=y
> +CONFIG_SPL_WATCHDOG=y
> +CONFIG_SYS_MAXARGS=64
> +CONFIG_SYS_PBSIZE=1050
> +# CONFIG_BOOTM_NETBSD is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_MDIO is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SYS_MMC_ENV_DEV=1
> +CONFIG_USE_ETHPRIME=y
> +CONFIG_ETHPRIME="FEC"
> +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SPL_SYS_I2C_LEGACY=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_DM_ETH=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_FEC_MXC=y
> +CONFIG_MII=y
> +CONFIG_PHY=y
> +CONFIG_PHY_IMX8MQ_USB=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_SPL_POWER_LEGACY=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8M_POWER_DOMAIN=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_POWER_I2C=y
> +CONFIG_DM_RESET=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_MXC_UART=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_KEYBOARD=y
> diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
> new file mode 100644
> index 0000000000..bc380850e3
> --- /dev/null
> +++ b/include/configs/imx8mq_reform2.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef __IMX8M_REFORM2_H
> +#define __IMX8M_REFORM2_H
> +
> +#include <linux/sizes.h>
> +#include <linux/stringify.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SPL_BUILD
> +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> +
> +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> +#define CFG_MALLOC_F_ADDR		0x182000
> +/* For RAW image gives a error info not panic */
> +#endif
> +
> +/* ENET Config */
> +/* ENET1 */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_FEC_MXC_PHYADDR		4
> +#endif
> +
> +#define BOOT_TARGET_DEVICES(func) \
> +	func(MMC, mmc, 1) \
> +	func(MMC, mmc, 0) \
> +	func(USB, usb, 0) \
> +	func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +/* Initial environment variables */
> +#define CFG_EXTRA_ENV_SETTINGS		\
> +	BOOTENV \
> +	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> +	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> +	"image=Image\0" \
> +	"console=ttymxc0,115200\0" \
> +	"fdt_addr_r=0x43000000\0" \
> +	"boot_fdt=try\0" \
> +	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
> +	"initrd_addr=0x43800000\0" \
> +	"bootm_size=0x10000000\0" \
> +	"mmcpart=1\0" \
> +	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
> +	"stdin=serial,usbkbd\0"
> +
> +/* Link Definitions */
> +
> +#define CFG_SYS_INIT_RAM_ADDR		0x40000000
> +#define CFG_SYS_INIT_RAM_SIZE		0x80000
> +
> +
> +#define CFG_SYS_SDRAM_BASE		0x40000000
> +#define PHYS_SDRAM			0x40000000
> +#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
> +
> +#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
> +
> +#define CFG_SYS_FSL_USDHC_NUM		2
> +#define CFG_SYS_FSL_ESDHC_ADDR		0
> +
> +#endif

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================


^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v6] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-31 17:00   ` Stefano Babic
@ 2023-01-31 23:53     ` Patrick Wildt
  0 siblings, 0 replies; 17+ messages in thread
From: Patrick Wildt @ 2023-01-31 23:53 UTC (permalink / raw)
  To: Stefano Babic; +Cc: Fabio Estevam, u-boot, Lukas F. Hartmann

Am Tue, Jan 31, 2023 at 06:00:31PM +0100 schrieb Stefano Babic:
> On 19.01.23 20:56, Patrick Wildt wrote:
> > The MNT Reform 2 is a modular DIY laptop.  In its initial version it
> > is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
> > lifted from BoundaryDevices official U-Boot downstream project.
> > 
> > Signed-off-by: Patrick Wildt <patrick@blueri.se>
> > ---
> > Changes since v5:
> > - Adjusted to further Binman changes.
> > - Adjusted to further Kconfig conversions.
> > - Removed some phy init in favor of DM.
> > - Removed some pinmux which are now handled by DM_SERIAL.
> > - Compared with Librem5/EVK and adjusted for similarity.
> > Changes since v4:
> > - Adjusted to Kconfig conversions.
> > - Removed U-Boot-specific device tree changes.
> > - Synced device tree to Linux v5.19-rc3.
> > Changes since v3:
> > - Adjusted to Binman changes in main branch.
> > - Cleaned up environment variables akin to i.MX8MM.
> > - Added vendor-prefix to device tree filename.
> > - Provided ramdisk_addr_r.
> > Changes since v2:
> > - Switched to Binman.
> > Changes since v1:
> > - Synced DTS with files in Linux git repo.
> > - Added support for USB host ports.
> > 
> >   arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
> >   arch/arm/mach-imx/imx8m/Kconfig               |    7 +
> >   board/mntre/imx8mq_reform2/Kconfig            |   15 +
> >   board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
> >   board/mntre/imx8mq_reform2/Makefile           |   12 +
> >   board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
> >   board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
> >   .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
> >   board/mntre/imx8mq_reform2/spl.c              |  260 +++++
> >   configs/imx8mq_reform2_defconfig              |  107 ++
> >   include/configs/imx8mq_reform2.h              |   66 ++
> >   11 files changed, 1765 insertions(+)
> >   create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
> >   create mode 100644 board/mntre/imx8mq_reform2/Kconfig
> >   create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
> >   create mode 100644 board/mntre/imx8mq_reform2/Makefile
> >   create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
> >   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
> >   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
> >   create mode 100644 board/mntre/imx8mq_reform2/spl.c
> >   create mode 100644 configs/imx8mq_reform2_defconfig
> >   create mode 100644 include/configs/imx8mq_reform2.h
> > 
> > diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..e0a6fc5470
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
> > @@ -0,0 +1,11 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +
> > +#include "imx8mq-u-boot.dtsi"
> > +
> > +&pinctrl_uart1 {
> > +	u-boot,dm-spl;
> > +};
> > +
> > +&uart1 { /* console */
> > +	u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> > index a0715e8091..2049efb131 100644
> > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > @@ -51,6 +51,12 @@ config TARGET_IMX8MQ_PHANBELL
> >   	select IMX8MQ
> >   	select IMX8M_LPDDR4
> > +config TARGET_IMX8MQ_REFORM2
> > +	bool "imx8mq_reform2"
> > +	select BINMAN
> > +	select IMX8MQ
> > +	select IMX8M_LPDDR4
> > +
> >   config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
> >   	bool "Data Modul eDM SBC i.MX8M Mini"
> >   	select BINMAN
> > @@ -320,6 +326,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
> >   source "board/kontron/sl-mx8mm/Kconfig"
> >   source "board/menlo/mx8menlo/Kconfig"
> >   source "board/msc/sm2s_imx8mp/Kconfig"
> > +source "board/mntre/imx8mq_reform2/Kconfig"
> >   source "board/phytec/phycore_imx8mm/Kconfig"
> >   source "board/phytec/phycore_imx8mp/Kconfig"
> >   source "board/purism/librem5/Kconfig"
> > diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
> > new file mode 100644
> > index 0000000000..f9260cb7f5
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/Kconfig
> > @@ -0,0 +1,15 @@
> > +if TARGET_IMX8MQ_REFORM2
> > +
> > +config SYS_BOARD
> > +	default "imx8mq_reform2"
> > +
> > +config SYS_VENDOR
> > +	default "mntre"
> > +
> > +config SYS_CONFIG_NAME
> > +	default "imx8mq_reform2"
> > +
> > +config IMX_CONFIG
> > +	default "arch/arm/mach-imx/imx8m/imximage.cfg"
> > +
> > +endif
> > diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
> > new file mode 100644
> > index 0000000000..946f287ecf
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +REFORM2 IMX8MQ BOARD
> > +M:	Lukas F. Hartmann <lukas@mntre.com>
> > +M:	Patrick Wildt <patrick@blueri.se>
> > +S:	Maintained
> > +F:	board/mntre/imx8mq_reform2/
> > +F:	include/configs/imx8mq_reform2.h
> > +F:	configs/imx8mq_reform2_defconfig
> > diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
> > new file mode 100644
> > index 0000000000..2efd56bb4a
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/Makefile
> > @@ -0,0 +1,12 @@
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# SPDX-License-Identifier:      GPL-2.0+
> > +#
> > +
> > +obj-y += imx8mq_reform2.o
> > +
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> > +endif
> > diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
> > new file mode 100644
> > index 0000000000..be5c5060a2
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
> > @@ -0,0 +1,171 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 NXP
> > + * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <env.h>
> > +#include <init.h>
> > +#include <malloc.h>
> > +#include <errno.h>
> > +#include <asm/global_data.h>
> > +#include <asm/io.h>
> > +#include <miiphy.h>
> > +#include <netdev.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm-generic/gpio.h>
> > +#include <fsl_esdhc_imx.h>
> > +#include <mmc.h>
> > +#include <asm/arch/imx8mq_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <asm/arch/clock.h>
> > +#include <spl.h>
> > +#include <linux/bitops.h>
> > +#include <linux/delay.h>
> > +#include <power/pmic.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +
> > +#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> > +
> > +static iomux_v3_cfg_t const wdog_pads[] = {
> > +	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> > +};
> > +
> > +
> > +int board_early_init_f(void)
> > +{
> > +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> > +
> > +	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> > +	set_wdog_reset(wdog);
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_FEC_MXC
> > +
> > +#define PHY_RESET	IMX_GPIO_NR(1, 9)
> > +#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
> > +#define PHY_RXC		IMX_GPIO_NR(1, 25)
> > +#define PHY_RD0		IMX_GPIO_NR(1, 26)
> > +#define PHY_RD1		IMX_GPIO_NR(1, 27)
> > +#define PHY_RD2		IMX_GPIO_NR(1, 28)
> > +#define PHY_RD3		IMX_GPIO_NR(1, 29)
> > +
> > +#define STRAP_AR8035	(0x28) // 0010 1000
> > +
> > +static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
> > +	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
> > +	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
> > +	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
> > +	/* 1.8V(1)/1.5V select(0) */
> > +	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
> > +};
> > +
> > +static const iomux_v3_cfg_t enet_ar8035_pads[] = {
> > +	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
> > +	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
> > +};
> > +
> > +static void setup_fec(void)
> > +{
> > +	struct iomuxc_gpr_base_regs *gpr =
> > +		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> > +
> > +	/* Pull PHY into reset */
> > +	gpio_request(PHY_RESET, "fec_rst");
> > +	gpio_direction_output(PHY_RESET, 0);
> > +
> > +	/* Configure ethernet pins value as GPIOs */
> > +	gpio_request(PHY_RD0, "fec_rd0");
> > +	gpio_direction_output(PHY_RD0, 0);
> > +	gpio_request(PHY_RD1, "fec_rd1");
> > +	gpio_direction_output(PHY_RD1, 0);
> > +	gpio_request(PHY_RD2, "fec_rd2");
> > +	gpio_direction_output(PHY_RD2, 0);
> > +	gpio_request(PHY_RD3, "fec_rd3");
> > +	gpio_direction_output(PHY_RD3, 1);
> > +	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
> > +	gpio_direction_output(PHY_RX_CTL, 0);
> > +	gpio_request(PHY_RXC, "fec_rxc");
> > +	gpio_direction_output(PHY_RXC, 1);
> > +
> > +	/* Set ethernet pins to GPIO to bootstrap PHY */
> > +	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
> > +	    ARRAY_SIZE(enet_ar8035_gpio_pads));
> > +
> > +	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
> > +	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
> > +	/* Enable RGMII TX clk output */
> > +	setbits_le32(&gpr->gpr[1], BIT(22));
> > +	set_clk_enet(ENET_125MHZ);
> > +
> > +	/* 1 ms minimum reset pulse for ar8035 */
> > +	mdelay(1);
> > +
> > +	/* Release PHY from reset */
> > +	gpio_set_value(PHY_RESET, 1);
> > +
> > +	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
> > +	udelay(12);
> > +
> > +	/* Change ethernet pins back to normal function */
> > +	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
> > +	    ARRAY_SIZE(enet_ar8035_pads));
> > +}
> > +#endif
> > +
> > +#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> > +#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
> > +
> > +static void setup_usb(void)
> > +{
> > +	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
> > +	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
> > +	gpio_request(USB1_HUB_RESET, "usb1_rst");
> > +	gpio_direction_output(USB1_HUB_RESET, 0);
> > +	mdelay(10);
> > +	gpio_set_value(USB1_HUB_RESET, 1);
> > +}
> > +
> > +int board_init(void)
> > +{
> > +#ifdef CONFIG_FEC_MXC
> > +	setup_fec();
> > +#endif
> > +
> > +	setup_usb();
> > +
> > +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
> > +	init_usb_clk();
> > +#endif
> > +
> > +	return 0;
> > +}
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > +	return devno;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > +	env_set("board_name", "Reform2");
> > +	env_set("board_rev", "iMX8MQ");
> > +#endif
> > +
> > +	return 0;
> > +}
> > diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
> > new file mode 100644
> > index 0000000000..e5303db0f8
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
> > @@ -0,0 +1,1014 @@
> > +/*
> > + * Copyright 2019 NXP
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + *
> > + * Generated code from MX8M_DDR_tool
> > + * Align with uboot version:
> > + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
> > + */
> > +#include "lpddr4_timing_ch2.h"
> > +
> > +static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
> > +	/** Initialize DDRC registers **/
> > +	{ DDRC_DBG1(0), 1 },
> > +	/* selfref_en=1, SDRAM enter self-refresh state */
> > +	{ DDRC_PWRCTL(0), 1 },
> > +	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
> > +	{ DDRC_MSTR2(0), 0 },
> > +	{ DDRC_DERATEEN(0), 0x0203 },
> > +	{ DDRC_DERATEINT(0), 0x0003e800 },
> > +	{ DDRC_RFSHTMG(0), 0x006100e0 },
> > +	{ DDRC_INIT0(0), 0xc003061c },
> > +	{ DDRC_INIT1(0), 0x009e0000 },
> > +	{ DDRC_INIT3(0), 0x00d4002d },
> > +	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
> > +	{ DDRC_INIT6(0), 0x0066004a },
> > +	{ DDRC_INIT7(0), 0x0016004a },
> > +	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
> > +	{ DDRC_DRAMTMG1(0), 0x00060633 },
> > +	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
> > +	{ DDRC_DRAMTMG4(0), 0x0f04080f },
> > +	{ DDRC_DRAMTMG5(0), 0x02040c0c },
> > +	{ DDRC_DRAMTMG6(0), 0x01010007 },
> > +	{ DDRC_DRAMTMG7(0), 0x0401 },
> > +	{ DDRC_DRAMTMG12(0), 0x00020600 },
> > +	{ DDRC_DRAMTMG13(0), 0x0c100002 },
> > +	{ DDRC_DRAMTMG14(0), 0xe6 },
> > +	{ DDRC_DRAMTMG17(0), 0x00a00050 },
> > +	{ DDRC_ZQCTL0(0), 0xc3200018 },
> > +	{ DDRC_ZQCTL1(0), 0x028061a8 },
> > +	{ DDRC_ZQCTL2(0), 0 },
> > +	{ DDRC_DFITMG0(0), 0x0497820a },
> > +	{ DDRC_DFITMG1(0), 0x00080303 },
> > +	{ DDRC_DFIUPD0(0), 0xe0400018 },
> > +	{ DDRC_DFIUPD1(0), 0x00df00e4 },
> > +	{ DDRC_DFIUPD2(0), 0x80000000 },
> > +	{ DDRC_DFIMISC(0), 0x11 },
> > +	{ DDRC_DFITMG2(0), 0x170a },
> > +	{ DDRC_DBICTL(0), 1 },
> > +	{ DDRC_DFIPHYMSTR(0), 1 },
> > +	{ DDRC_RANKCTL(0), 0x0639 },
> > +	{ DDRC_DRAMTMG2(0), 0x070e1617 },
> > +
> > +	/* address mapping */
> > +	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
> > +	{ DDRC_ADDRMAP3(0), 0 },
> > +	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
> > +	{ DDRC_ADDRMAP4(0), 0x1f1f },
> > +	/* bank interleave */
> > +	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
> > +	{ DDRC_ADDRMAP1(0), 0x00080808 },
> > +	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
> > +	{ DDRC_ADDRMAP5(0), 0x07070707 },
> > +	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
> > +	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
> > +	{ DDRC_ADDRMAP7(0), 0x0f0f },
> > +	{ DDRC_FREQ1_DERATEEN(0), 1 },
> > +	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
> > +	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
> > +	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
> > +	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
> > +	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
> > +	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
> > +	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
> > +	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
> > +	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
> > +	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
> > +	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
> > +	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
> > +	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
> > +	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
> > +	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
> > +	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
> > +	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
> > +	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
> > +	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
> > +	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
> > +	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
> > +	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
> > +	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
> > +	{ DDRC_ODTMAP(0), 0 },
> > +	{ DDRC_SCHED(0), 0x29001505 },
> > +	{ DDRC_SCHED1(0), 0x2c },
> > +	{ DDRC_PERFHPR1(0), 0x5900575b },
> > +	{ DDRC_PERFLPR1(0), 0x90000096 },
> > +	{ DDRC_PERFWR1(0), 0x1000012c },
> > +	{ DDRC_DBG0(0), 0x16 },
> > +	{ DDRC_DBG1(0), 0 },
> > +	{ DDRC_DBGCMD(0), 0 },
> > +	{ DDRC_SWCTL(0), 1 },
> > +	{ DDRC_POISONCFG(0), 0x11 },
> > +	{ DDRC_PCCFG(0), 0x0111 },
> > +	{ DDRC_PCFGR_0(0), 0x10f3 },
> > +	{ DDRC_PCFGW_0(0), 0x72ff },
> > +	{ DDRC_PCTRL_0(0), 1 },
> > +	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
> > +	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
> > +	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
> > +	{ DDRC_PCFGWQOS1_0(0), 0xffff },
> > +};
> > +
> > +/* PHY Initialize Configuration */
> > +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
> > +	{ 0x100a0, 0 },
> > +	{ 0x100a1, 1 },
> > +	{ 0x100a2, 2 },
> > +	{ 0x100a3, 3 },
> > +	{ 0x100a4, 4 },
> > +	{ 0x100a5, 5 },
> > +	{ 0x100a6, 6 },
> > +	{ 0x100a7, 7 },
> > +	{ 0x110a0, 0 },
> > +	{ 0x110a1, 1 },
> > +	{ 0x110a2, 2 },
> > +	{ 0x110a3, 3 },
> > +	{ 0x110a4, 4 },
> > +	{ 0x110a5, 5 },
> > +	{ 0x110a6, 6 },
> > +	{ 0x110a7, 7 },
> > +	{ 0x120a0, 0 },
> > +	{ 0x120a1, 1 },
> > +	{ 0x120a2, 2 },
> > +	{ 0x120a3, 3 },
> > +	{ 0x120a4, 4 },
> > +	{ 0x120a5, 5 },
> > +	{ 0x120a6, 6 },
> > +	{ 0x120a7, 7 },
> > +	{ 0x130a0, 0 },
> > +	{ 0x130a1, 1 },
> > +	{ 0x130a2, 2 },
> > +	{ 0x130a3, 3 },
> > +	{ 0x130a4, 4 },
> > +	{ 0x130a5, 5 },
> > +	{ 0x130a6, 6 },
> > +	{ 0x130a7, 7 },
> > +	{ 0x1005f, 0x01ff },
> > +	{ 0x1015f, 0x01ff },
> > +	{ 0x1105f, 0x01ff },
> > +	{ 0x1115f, 0x01ff },
> > +	{ 0x1205f, 0x01ff },
> > +	{ 0x1215f, 0x01ff },
> > +	{ 0x1305f, 0x01ff },
> > +	{ 0x1315f, 0x01ff },
> > +	{ 0x11005f, 0x01ff },
> > +	{ 0x11015f, 0x01ff },
> > +	{ 0x11105f, 0x01ff },
> > +	{ 0x11115f, 0x01ff },
> > +	{ 0x11205f, 0x01ff },
> > +	{ 0x11215f, 0x01ff },
> > +	{ 0x11305f, 0x01ff },
> > +	{ 0x11315f, 0x01ff },
> > +	{ 0x0055, 0x01ff },
> > +	{ 0x1055, 0x01ff },
> > +	{ 0x2055, 0x01ff },
> > +	{ 0x3055, 0x01ff },
> > +	{ 0x4055, 0x01ff },
> > +	{ 0x5055, 0x01ff },
> > +	{ 0x6055, 0x01ff },
> > +	{ 0x7055, 0x01ff },
> > +	{ 0x8055, 0x01ff },
> > +	{ 0x9055, 0x01ff },
> > +	{ 0x200c5, 0x19 },
> > +	{ 0x1200c5, 7 },
> > +	{ 0x2002e, 2 },
> > +	{ 0x12002e, 1 },
> > +	{ 0x90204, 0 },
> > +	{ 0x190204, 0 },
> > +	{ 0x20024, 0x01ab },
> > +	{ 0x2003a, 0 },
> > +	{ 0x120024, 0x01ab },
> > +	{ 0x2003a, 0 },
> > +	{ 0x20056, 3 },
> > +	{ 0x120056, 3 },
> > +	{ 0x1004d, 0x0e00 },
> > +	{ 0x1014d, 0x0e00 },
> > +	{ 0x1104d, 0x0e00 },
> > +	{ 0x1114d, 0x0e00 },
> > +	{ 0x1204d, 0x0e00 },
> > +	{ 0x1214d, 0x0e00 },
> > +	{ 0x1304d, 0x0e00 },
> > +	{ 0x1314d, 0x0e00 },
> > +	{ 0x11004d, 0x0e00 },
> > +	{ 0x11014d, 0x0e00 },
> > +	{ 0x11104d, 0x0e00 },
> > +	{ 0x11114d, 0x0e00 },
> > +	{ 0x11204d, 0x0e00 },
> > +	{ 0x11214d, 0x0e00 },
> > +	{ 0x11304d, 0x0e00 },
> > +	{ 0x11314d, 0x0e00 },
> > +	{ 0x10049, 0x0eba },
> > +	{ 0x10149, 0x0eba },
> > +	{ 0x11049, 0x0eba },
> > +	{ 0x11149, 0x0eba },
> > +	{ 0x12049, 0x0eba },
> > +	{ 0x12149, 0x0eba },
> > +	{ 0x13049, 0x0eba },
> > +	{ 0x13149, 0x0eba },
> > +	{ 0x110049, 0x0eba },
> > +	{ 0x110149, 0x0eba },
> > +	{ 0x111049, 0x0eba },
> > +	{ 0x111149, 0x0eba },
> > +	{ 0x112049, 0x0eba },
> > +	{ 0x112149, 0x0eba },
> > +	{ 0x113049, 0x0eba },
> > +	{ 0x113149, 0x0eba },
> > +	{ 0x0043, 0x63 },
> > +	{ 0x1043, 0x63 },
> > +	{ 0x2043, 0x63 },
> > +	{ 0x3043, 0x63 },
> > +	{ 0x4043, 0x63 },
> > +	{ 0x5043, 0x63 },
> > +	{ 0x6043, 0x63 },
> > +	{ 0x7043, 0x63 },
> > +	{ 0x8043, 0x63 },
> > +	{ 0x9043, 0x63 },
> > +	{ 0x20018, 3 },
> > +	{ 0x20075, 4 },
> > +	{ 0x20050, 0 },
> > +	{ 0x20008, 0x0320 },
> > +	{ 0x120008, 0xa7 },
> > +	{ 0x20088, 9 },
> > +	{ 0x200b2, 0xdc },
> > +	{ 0x10043, 0x05a1 },
> > +	{ 0x10143, 0x05a1 },
> > +	{ 0x11043, 0x05a1 },
> > +	{ 0x11143, 0x05a1 },
> > +	{ 0x12043, 0x05a1 },
> > +	{ 0x12143, 0x05a1 },
> > +	{ 0x13043, 0x05a1 },
> > +	{ 0x13143, 0x05a1 },
> > +	{ 0x1200b2, 0xdc },
> > +	{ 0x110043, 0x05a1 },
> > +	{ 0x110143, 0x05a1 },
> > +	{ 0x111043, 0x05a1 },
> > +	{ 0x111143, 0x05a1 },
> > +	{ 0x112043, 0x05a1 },
> > +	{ 0x112143, 0x05a1 },
> > +	{ 0x113043, 0x05a1 },
> > +	{ 0x113143, 0x05a1 },
> > +	{ 0x200fa, 1 },
> > +	{ 0x1200fa, 1 },
> > +	{ 0x20019, 1 },
> > +	{ 0x120019, 1 },
> > +	{ 0x200f0, 0 },
> > +	{ 0x200f1, 0 },
> > +	{ 0x200f2, 0x4444 },
> > +	{ 0x200f3, 0x8888 },
> > +	{ 0x200f4, 0x5555 },
> > +	{ 0x200f5, 0 },
> > +	{ 0x200f6, 0 },
> > +	{ 0x200f7, 0xf000 },
> > +	{ 0x20025, 0 },
> > +	{ 0x2002d, 0 },
> > +	{ 0x12002d, 0 },
> > +	{ 0x200c7, 0x80 },
> > +	{ 0x1200c7, 0x80 },
> > +	{ 0x200ca, 0x0106 },
> > +	{ 0x1200ca, 0x0106 },
> > +	{ 0x20110, 2 },
> > +	{ 0x20111, 3 },
> > +	{ 0x20112, 4 },
> > +	{ 0x20113, 5 },
> > +	{ 0x20114, 0 },
> > +	{ 0x20115, 1 },
> > +};
> > +
> > +/* P0 message block parameter for training firmware */
> > +static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
> > +	{ 0xd0000, 0 },
> > +	{ 0x54003, 0x0c80 },
> > +	{ 0x54004, 2 },
> > +	{ 0x54005, 0x2228 },
> > +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> > +	{ 0x54008, 0x131f },
> > +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> > +	{ 0x5400b, 2 },
> > +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> > +	{ 0x54019, 0x2dd4 },
> > +	{ 0x5401a, 0x31 },
> > +	{ 0x5401b, 0x4a66 },
> > +	{ 0x5401c, 0x4a08 },
> > +	{ 0x5401e, 0x16 },
> > +	{ 0x5401f, 0x2dd4 },
> > +	{ 0x54020, 0x31 },
> > +	{ 0x54021, 0x4a66 },
> > +	{ 0x54022, 0x4a08 },
> > +	{ 0x54024, 0x16 },
> > +	{ 0x5402b, 0x1000 },
> > +	{ 0x5402c, CH2_LPDDR4_CS },
> > +	{ 0x54032, 0xd400 },
> > +	{ 0x54033, 0x312d },
> > +	{ 0x54034, 0x6600 },
> > +	{ 0x54035, 0x084a },
> > +	{ 0x54036, 0x4a },
> > +	{ 0x54037, 0x1600 },
> > +	{ 0x54038, 0xd400 },
> > +	{ 0x54039, 0x312d },
> > +	{ 0x5403a, 0x6600 },
> > +	{ 0x5403b, 0x084a },
> > +	{ 0x5403c, 0x4a },
> > +	{ 0x5403d, 0x1600 },
> > +	{ 0xd0000, 1 },
> > +};
> > +
> > +
> > +/* P1 message block parameter for training firmware */
> > +static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
> > +	{ 0xd0000, 0 },
> > +	{ 0x54002, 1 },
> > +	{ 0x54003, 0x029c },
> > +	{ 0x54004, 2 },
> > +	{ 0x54005, 0x2228 },
> > +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> > +	{ 0x54008, 0x121f },
> > +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> > +	{ 0x5400b, 2 },
> > +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> > +	{ 0x54019, 0x0994 },
> > +	{ 0x5401a, 0x31 },
> > +	{ 0x5401b, 0x4a66 },
> > +	{ 0x5401c, 0x4a08 },
> > +	{ 0x5401e, 0x16 },
> > +	{ 0x5401f, 0x0994 },
> > +	{ 0x54020, 0x31 },
> > +	{ 0x54021, 0x4a66 },
> > +	{ 0x54022, 0x4a08 },
> > +	{ 0x54024, 0x16 },
> > +	{ 0x5402b, 0x1000 },
> > +	{ 0x5402c, CH2_LPDDR4_CS },
> > +	{ 0x54032, 0x9400 },
> > +	{ 0x54033, 0x3109 },
> > +	{ 0x54034, 0x6600 },
> > +	{ 0x54035, 0x084a },
> > +	{ 0x54036, 0x4a },
> > +	{ 0x54037, 0x1600 },
> > +	{ 0x54038, 0x9400 },
> > +	{ 0x54039, 0x3109 },
> > +	{ 0x5403a, 0x6600 },
> > +	{ 0x5403b, 0x084a },
> > +	{ 0x5403c, 0x4a },
> > +	{ 0x5403d, 0x1600 },
> > +	{ 0xd0000, 1 },
> > +};
> > +
> > +
> > +/* P0 2D message block parameter for training firmware */
> > +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
> > +	{ 0xd0000, 0 },
> > +	{ 0x54003, 0x0c80 },
> > +	{ 0x54004, 2 },
> > +	{ 0x54005, 0x2228 },
> > +	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
> > +	{ 0x54008, 0x61 },
> > +	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
> > +	{ 0x5400b, 2 },
> > +	{ 0x5400d, 0x0100 },
> > +	{ 0x5400f, 0x0100 },
> > +	{ 0x54010, 0x1f7f },
> > +	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
> > +	{ 0x54019, 0x2dd4 },
> > +	{ 0x5401a, 0x31 },
> > +	{ 0x5401b, 0x4a66 },
> > +	{ 0x5401c, 0x4a08 },
> > +	{ 0x5401e, 0x16 },
> > +	{ 0x5401f, 0x2dd4 },
> > +	{ 0x54020, 0x31 },
> > +	{ 0x54021, 0x4a66 },
> > +	{ 0x54022, 0x4a08 },
> > +	{ 0x54024, 0x16 },
> > +	{ 0x5402b, 0x1000 },
> > +	{ 0x5402c, CH2_LPDDR4_CS },
> > +	{ 0x54032, 0xd400 },
> > +	{ 0x54033, 0x312d },
> > +	{ 0x54034, 0x6600 },
> > +	{ 0x54035, 0x084a },
> > +	{ 0x54036, 0x4a },
> > +	{ 0x54037, 0x1600 },
> > +	{ 0x54038, 0xd400 },
> > +	{ 0x54039, 0x312d },
> > +	{ 0x5403a, 0x6600 },
> > +	{ 0x5403b, 0x084a },
> > +	{ 0x5403c, 0x4a },
> > +	{ 0x5403d, 0x1600 },
> > +	{ 0xd0000, 1 },
> > +};
> > +
> > +/* DRAM PHY init engine image */
> > +static struct dram_cfg_param lpddr4_phy_pie[] = {
> > +	{ 0xd0000, 0 },
> > +	{ 0x90000, 0x10 },
> > +	{ 0x90001, 0x0400 },
> > +	{ 0x90002, 0x010e },
> > +	{ 0x90003, 0 },
> > +	{ 0x90004, 0 },
> > +	{ 0x90005, 8 },
> > +	{ 0x90029, 0x0b },
> > +	{ 0x9002a, 0x0480 },
> > +	{ 0x9002b, 0x0109 },
> > +	{ 0x9002c, 8 },
> > +	{ 0x9002d, 0x0448 },
> > +	{ 0x9002e, 0x0139 },
> > +	{ 0x9002f, 8 },
> > +	{ 0x90030, 0x0478 },
> > +	{ 0x90031, 0x0109 },
> > +	{ 0x90032, 0 },
> > +	{ 0x90033, 0xe8 },
> > +	{ 0x90034, 0x0109 },
> > +	{ 0x90035, 2 },
> > +	{ 0x90036, 0x10 },
> > +	{ 0x90037, 0x0139 },
> > +	{ 0x90038, 0x0f },
> > +	{ 0x90039, 0x07c0 },
> > +	{ 0x9003a, 0x0139 },
> > +	{ 0x9003b, 0x44 },
> > +	{ 0x9003c, 0x0630 },
> > +	{ 0x9003d, 0x0159 },
> > +	{ 0x9003e, 0x014f },
> > +	{ 0x9003f, 0x0630 },
> > +	{ 0x90040, 0x0159 },
> > +	{ 0x90041, 0x47 },
> > +	{ 0x90042, 0x0630 },
> > +	{ 0x90043, 0x0149 },
> > +	{ 0x90044, 0x4f },
> > +	{ 0x90045, 0x0630 },
> > +	{ 0x90046, 0x0179 },
> > +	{ 0x90047, 8 },
> > +	{ 0x90048, 0xe0 },
> > +	{ 0x90049, 0x0109 },
> > +	{ 0x9004a, 0 },
> > +	{ 0x9004b, 0x07c8 },
> > +	{ 0x9004c, 0x0109 },
> > +	{ 0x9004d, 0 },
> > +	{ 0x9004e, 1 },
> > +	{ 0x9004f, 8 },
> > +	{ 0x90050, 0 },
> > +	{ 0x90051, 0x045a },
> > +	{ 0x90052, 9 },
> > +	{ 0x90053, 0 },
> > +	{ 0x90054, 0x0448 },
> > +	{ 0x90055, 0x0109 },
> > +	{ 0x90056, 0x40 },
> > +	{ 0x90057, 0x0630 },
> > +	{ 0x90058, 0x0179 },
> > +	{ 0x90059, 1 },
> > +	{ 0x9005a, 0x0618 },
> > +	{ 0x9005b, 0x0109 },
> > +	{ 0x9005c, 0x40c0 },
> > +	{ 0x9005d, 0x0630 },
> > +	{ 0x9005e, 0x0149 },
> > +	{ 0x9005f, 8 },
> > +	{ 0x90060, 4 },
> > +	{ 0x90061, 0x48 },
> > +	{ 0x90062, 0x4040 },
> > +	{ 0x90063, 0x0630 },
> > +	{ 0x90064, 0x0149 },
> > +	{ 0x90065, 0 },
> > +	{ 0x90066, 4 },
> > +	{ 0x90067, 0x48 },
> > +	{ 0x90068, 0x40 },
> > +	{ 0x90069, 0x0630 },
> > +	{ 0x9006a, 0x0149 },
> > +	{ 0x9006b, 0x10 },
> > +	{ 0x9006c, 4 },
> > +	{ 0x9006d, 0x18 },
> > +	{ 0x9006e, 0 },
> > +	{ 0x9006f, 4 },
> > +	{ 0x90070, 0x78 },
> > +	{ 0x90071, 0x0549 },
> > +	{ 0x90072, 0x0630 },
> > +	{ 0x90073, 0x0159 },
> > +	{ 0x90074, 0x0d49 },
> > +	{ 0x90075, 0x0630 },
> > +	{ 0x90076, 0x0159 },
> > +	{ 0x90077, 0x094a },
> > +	{ 0x90078, 0x0630 },
> > +	{ 0x90079, 0x0159 },
> > +	{ 0x9007a, 0x0441 },
> > +	{ 0x9007b, 0x0630 },
> > +	{ 0x9007c, 0x0149 },
> > +	{ 0x9007d, 0x42 },
> > +	{ 0x9007e, 0x0630 },
> > +	{ 0x9007f, 0x0149 },
> > +	{ 0x90080, 1 },
> > +	{ 0x90081, 0x0630 },
> > +	{ 0x90082, 0x0149 },
> > +	{ 0x90083, 0 },
> > +	{ 0x90084, 0xe0 },
> > +	{ 0x90085, 0x0109 },
> > +	{ 0x90086, 0x0a },
> > +	{ 0x90087, 0x10 },
> > +	{ 0x90088, 0x0109 },
> > +	{ 0x90089, 9 },
> > +	{ 0x9008a, 0x03c0 },
> > +	{ 0x9008b, 0x0149 },
> > +	{ 0x9008c, 9 },
> > +	{ 0x9008d, 0x03c0 },
> > +	{ 0x9008e, 0x0159 },
> > +	{ 0x9008f, 0x18 },
> > +	{ 0x90090, 0x10 },
> > +	{ 0x90091, 0x0109 },
> > +	{ 0x90092, 0 },
> > +	{ 0x90093, 0x03c0 },
> > +	{ 0x90094, 0x0109 },
> > +	{ 0x90095, 0x18 },
> > +	{ 0x90096, 4 },
> > +	{ 0x90097, 0x48 },
> > +	{ 0x90098, 0x18 },
> > +	{ 0x90099, 4 },
> > +	{ 0x9009a, 0x58 },
> > +	{ 0x9009b, 0x0a },
> > +	{ 0x9009c, 0x10 },
> > +	{ 0x9009d, 0x0109 },
> > +	{ 0x9009e, 2 },
> > +	{ 0x9009f, 0x10 },
> > +	{ 0x900a0, 0x0109 },
> > +	{ 0x900a1, 5 },
> > +	{ 0x900a2, 0x07c0 },
> > +	{ 0x900a3, 0x0109 },
> > +	{ 0x900a4, 0x10 },
> > +	{ 0x900a5, 0x10 },
> > +	{ 0x900a6, 0x0109 },
> > +	{ 0x40000, 0x0811 },
> > +	{ 0x40020, 0x0880 },
> > +	{ 0x40040, 0 },
> > +	{ 0x40060, 0 },
> > +	{ 0x40001, 0x4008 },
> > +	{ 0x40021, 0x83 },
> > +	{ 0x40041, 0x4f },
> > +	{ 0x40061, 0 },
> > +	{ 0x40002, 0x4040 },
> > +	{ 0x40022, 0x83 },
> > +	{ 0x40042, 0x51 },
> > +	{ 0x40062, 0 },
> > +	{ 0x40003, 0x0811 },
> > +	{ 0x40023, 0x0880 },
> > +	{ 0x40043, 0 },
> > +	{ 0x40063, 0 },
> > +	{ 0x40004, 0x0720 },
> > +	{ 0x40024, 0x0f },
> > +	{ 0x40044, 0x1740 },
> > +	{ 0x40064, 0 },
> > +	{ 0x40005, 0x16 },
> > +	{ 0x40025, 0x83 },
> > +	{ 0x40045, 0x4b },
> > +	{ 0x40065, 0 },
> > +	{ 0x40006, 0x0716 },
> > +	{ 0x40026, 0x0f },
> > +	{ 0x40046, 0x2001 },
> > +	{ 0x40066, 0 },
> > +	{ 0x40007, 0x0716 },
> > +	{ 0x40027, 0x0f },
> > +	{ 0x40047, 0x2800 },
> > +	{ 0x40067, 0 },
> > +	{ 0x40008, 0x0716 },
> > +	{ 0x40028, 0x0f },
> > +	{ 0x40048, 0x0f00 },
> > +	{ 0x40068, 0 },
> > +	{ 0x40009, 0x0720 },
> > +	{ 0x40029, 0x0f },
> > +	{ 0x40049, 0x1400 },
> > +	{ 0x40069, 0 },
> > +	{ 0x4000a, 0x0e08 },
> > +	{ 0x4002a, 0x0c15 },
> > +	{ 0x4004a, 0 },
> > +	{ 0x4006a, 0 },
> > +	{ 0x4000b, 0x0623 },
> > +	{ 0x4002b, 0x15 },
> > +	{ 0x4004b, 0 },
> > +	{ 0x4006b, 0 },
> > +	{ 0x4000c, 0x4028 },
> > +	{ 0x4002c, 0x80 },
> > +	{ 0x4004c, 0 },
> > +	{ 0x4006c, 0 },
> > +	{ 0x4000d, 0x0e08 },
> > +	{ 0x4002d, 0x0c1a },
> > +	{ 0x4004d, 0 },
> > +	{ 0x4006d, 0 },
> > +	{ 0x4000e, 0x0623 },
> > +	{ 0x4002e, 0x1a },
> > +	{ 0x4004e, 0 },
> > +	{ 0x4006e, 0 },
> > +	{ 0x4000f, 0x4040 },
> > +	{ 0x4002f, 0x80 },
> > +	{ 0x4004f, 0 },
> > +	{ 0x4006f, 0 },
> > +	{ 0x40010, 0x2604 },
> > +	{ 0x40030, 0x15 },
> > +	{ 0x40050, 0 },
> > +	{ 0x40070, 0 },
> > +	{ 0x40011, 0x0708 },
> > +	{ 0x40031, 5 },
> > +	{ 0x40051, 0 },
> > +	{ 0x40071, 0x2002 },
> > +	{ 0x40012, 8 },
> > +	{ 0x40032, 0x80 },
> > +	{ 0x40052, 0 },
> > +	{ 0x40072, 0 },
> > +	{ 0x40013, 0x2604 },
> > +	{ 0x40033, 0x1a },
> > +	{ 0x40053, 0 },
> > +	{ 0x40073, 0 },
> > +	{ 0x40014, 0x0708 },
> > +	{ 0x40034, 0x0a },
> > +	{ 0x40054, 0 },
> > +	{ 0x40074, 0x2002 },
> > +	{ 0x40015, 0x4040 },
> > +	{ 0x40035, 0x80 },
> > +	{ 0x40055, 0 },
> > +	{ 0x40075, 0 },
> > +	{ 0x40016, 0x060a },
> > +	{ 0x40036, 0x15 },
> > +	{ 0x40056, 0x1200 },
> > +	{ 0x40076, 0 },
> > +	{ 0x40017, 0x061a },
> > +	{ 0x40037, 0x15 },
> > +	{ 0x40057, 0x1300 },
> > +	{ 0x40077, 0 },
> > +	{ 0x40018, 0x060a },
> > +	{ 0x40038, 0x1a },
> > +	{ 0x40058, 0x1200 },
> > +	{ 0x40078, 0 },
> > +	{ 0x40019, 0x0642 },
> > +	{ 0x40039, 0x1a },
> > +	{ 0x40059, 0x1300 },
> > +	{ 0x40079, 0 },
> > +	{ 0x4001a, 0x4808 },
> > +	{ 0x4003a, 0x0880 },
> > +	{ 0x4005a, 0 },
> > +	{ 0x4007a, 0 },
> > +	{ 0x900a7, 0 },
> > +	{ 0x900a8, 0x0790 },
> > +	{ 0x900a9, 0x011a },
> > +	{ 0x900aa, 8 },
> > +	{ 0x900ab, 0x07aa },
> > +	{ 0x900ac, 0x2a },
> > +	{ 0x900ad, 0x10 },
> > +	{ 0x900ae, 0x07b2 },
> > +	{ 0x900af, 0x2a },
> > +	{ 0x900b0, 0 },
> > +	{ 0x900b1, 0x07c8 },
> > +	{ 0x900b2, 0x0109 },
> > +	{ 0x900b3, 0x10 },
> > +	{ 0x900b4, 0x02a8 },
> > +	{ 0x900b5, 0x0129 },
> > +	{ 0x900b6, 8 },
> > +	{ 0x900b7, 0x0370 },
> > +	{ 0x900b8, 0x0129 },
> > +	{ 0x900b9, 0x0a },
> > +	{ 0x900ba, 0x03c8 },
> > +	{ 0x900bb, 0x01a9 },
> > +	{ 0x900bc, 0x0c },
> > +	{ 0x900bd, 0x0408 },
> > +	{ 0x900be, 0x0199 },
> > +	{ 0x900bf, 0x14 },
> > +	{ 0x900c0, 0x0790 },
> > +	{ 0x900c1, 0x011a },
> > +	{ 0x900c2, 8 },
> > +	{ 0x900c3, 4 },
> > +	{ 0x900c4, 0x18 },
> > +	{ 0x900c5, 0x0e },
> > +	{ 0x900c6, 0x0408 },
> > +	{ 0x900c7, 0x0199 },
> > +	{ 0x900c8, 8 },
> > +	{ 0x900c9, 0x8568 },
> > +	{ 0x900ca, 0x0108 },
> > +	{ 0x900cb, 0x18 },
> > +	{ 0x900cc, 0x0790 },
> > +	{ 0x900cd, 0x016a },
> > +	{ 0x900ce, 8 },
> > +	{ 0x900cf, 0x01d8 },
> > +	{ 0x900d0, 0x0169 },
> > +	{ 0x900d1, 0x10 },
> > +	{ 0x900d2, 0x8558 },
> > +	{ 0x900d3, 0x0168 },
> > +	{ 0x900d4, 0x70 },
> > +	{ 0x900d5, 0x0788 },
> > +	{ 0x900d6, 0x016a },
> > +	{ 0x900d7, 0x1ff8 },
> > +	{ 0x900d8, 0x85a8 },
> > +	{ 0x900d9, 0x01e8 },
> > +	{ 0x900da, 0x50 },
> > +	{ 0x900db, 0x0798 },
> > +	{ 0x900dc, 0x016a },
> > +	{ 0x900dd, 0x60 },
> > +	{ 0x900de, 0x07a0 },
> > +	{ 0x900df, 0x016a },
> > +	{ 0x900e0, 8 },
> > +	{ 0x900e1, 0x8310 },
> > +	{ 0x900e2, 0x0168 },
> > +	{ 0x900e3, 8 },
> > +	{ 0x900e4, 0xa310 },
> > +	{ 0x900e5, 0x0168 },
> > +	{ 0x900e6, 0x0a },
> > +	{ 0x900e7, 0x0408 },
> > +	{ 0x900e8, 0x0169 },
> > +	{ 0x900e9, 0x6e },
> > +	{ 0x900ea, 0 },
> > +	{ 0x900eb, 0x68 },
> > +	{ 0x900ec, 0 },
> > +	{ 0x900ed, 0x0408 },
> > +	{ 0x900ee, 0x0169 },
> > +	{ 0x900ef, 0 },
> > +	{ 0x900f0, 0x8310 },
> > +	{ 0x900f1, 0x0168 },
> > +	{ 0x900f2, 0 },
> > +	{ 0x900f3, 0xa310 },
> > +	{ 0x900f4, 0x0168 },
> > +	{ 0x900f5, 0x1ff8 },
> > +	{ 0x900f6, 0x85a8 },
> > +	{ 0x900f7, 0x01e8 },
> > +	{ 0x900f8, 0x68 },
> > +	{ 0x900f9, 0x0798 },
> > +	{ 0x900fa, 0x016a },
> > +	{ 0x900fb, 0x78 },
> > +	{ 0x900fc, 0x07a0 },
> > +	{ 0x900fd, 0x016a },
> > +	{ 0x900fe, 0x68 },
> > +	{ 0x900ff, 0x0790 },
> > +	{ 0x90100, 0x016a },
> > +	{ 0x90101, 8 },
> > +	{ 0x90102, 0x8b10 },
> > +	{ 0x90103, 0x0168 },
> > +	{ 0x90104, 8 },
> > +	{ 0x90105, 0xab10 },
> > +	{ 0x90106, 0x0168 },
> > +	{ 0x90107, 0x0a },
> > +	{ 0x90108, 0x0408 },
> > +	{ 0x90109, 0x0169 },
> > +	{ 0x9010a, 0x58 },
> > +	{ 0x9010b, 0 },
> > +	{ 0x9010c, 0x68 },
> > +	{ 0x9010d, 0 },
> > +	{ 0x9010e, 0x0408 },
> > +	{ 0x9010f, 0x0169 },
> > +	{ 0x90110, 0 },
> > +	{ 0x90111, 0x8b10 },
> > +	{ 0x90112, 0x0168 },
> > +	{ 0x90113, 0 },
> > +	{ 0x90114, 0xab10 },
> > +	{ 0x90115, 0x0168 },
> > +	{ 0x90116, 0 },
> > +	{ 0x90117, 0x01d8 },
> > +	{ 0x90118, 0x0169 },
> > +	{ 0x90119, 0x80 },
> > +	{ 0x9011a, 0x0790 },
> > +	{ 0x9011b, 0x016a },
> > +	{ 0x9011c, 0x18 },
> > +	{ 0x9011d, 0x07aa },
> > +	{ 0x9011e, 0x6a },
> > +	{ 0x9011f, 0x0a },
> > +	{ 0x90120, 0 },
> > +	{ 0x90121, 0x01e9 },
> > +	{ 0x90122, 8 },
> > +	{ 0x90123, 0x8080 },
> > +	{ 0x90124, 0x0108 },
> > +	{ 0x90125, 0x0f },
> > +	{ 0x90126, 0x0408 },
> > +	{ 0x90127, 0x0169 },
> > +	{ 0x90128, 0x0c },
> > +	{ 0x90129, 0 },
> > +	{ 0x9012a, 0x68 },
> > +	{ 0x9012b, 9 },
> > +	{ 0x9012c, 0 },
> > +	{ 0x9012d, 0x01a9 },
> > +	{ 0x9012e, 0 },
> > +	{ 0x9012f, 0x0408 },
> > +	{ 0x90130, 0x0169 },
> > +	{ 0x90131, 0 },
> > +	{ 0x90132, 0x8080 },
> > +	{ 0x90133, 0x0108 },
> > +	{ 0x90134, 8 },
> > +	{ 0x90135, 0x07aa },
> > +	{ 0x90136, 0x6a },
> > +	{ 0x90137, 0 },
> > +	{ 0x90138, 0x8568 },
> > +	{ 0x90139, 0x0108 },
> > +	{ 0x9013a, 0xb7 },
> > +	{ 0x9013b, 0x0790 },
> > +	{ 0x9013c, 0x016a },
> > +	{ 0x9013d, 0x1f },
> > +	{ 0x9013e, 0 },
> > +	{ 0x9013f, 0x68 },
> > +	{ 0x90140, 8 },
> > +	{ 0x90141, 0x8558 },
> > +	{ 0x90142, 0x0168 },
> > +	{ 0x90143, 0x0f },
> > +	{ 0x90144, 0x0408 },
> > +	{ 0x90145, 0x0169 },
> > +	{ 0x90146, 0x0c },
> > +	{ 0x90147, 0 },
> > +	{ 0x90148, 0x68 },
> > +	{ 0x90149, 0 },
> > +	{ 0x9014a, 0x0408 },
> > +	{ 0x9014b, 0x0169 },
> > +	{ 0x9014c, 0 },
> > +	{ 0x9014d, 0x8558 },
> > +	{ 0x9014e, 0x0168 },
> > +	{ 0x9014f, 8 },
> > +	{ 0x90150, 0x03c8 },
> > +	{ 0x90151, 0x01a9 },
> > +	{ 0x90152, 3 },
> > +	{ 0x90153, 0x0370 },
> > +	{ 0x90154, 0x0129 },
> > +	{ 0x90155, 0x20 },
> > +	{ 0x90156, 0x02aa },
> > +	{ 0x90157, 9 },
> > +	{ 0x90158, 0 },
> > +	{ 0x90159, 0x0400 },
> > +	{ 0x9015a, 0x010e },
> > +	{ 0x9015b, 8 },
> > +	{ 0x9015c, 0xe8 },
> > +	{ 0x9015d, 0x0109 },
> > +	{ 0x9015e, 0 },
> > +	{ 0x9015f, 0x8140 },
> > +	{ 0x90160, 0x010c },
> > +	{ 0x90161, 0x10 },
> > +	{ 0x90162, 0x8138 },
> > +	{ 0x90163, 0x010c },
> > +	{ 0x90164, 8 },
> > +	{ 0x90165, 0x07c8 },
> > +	{ 0x90166, 0x0101 },
> > +	{ 0x90167, 8 },
> > +	{ 0x90168, 0 },
> > +	{ 0x90169, 8 },
> > +	{ 0x9016a, 8 },
> > +	{ 0x9016b, 0x0448 },
> > +	{ 0x9016c, 0x0109 },
> > +	{ 0x9016d, 0x0f },
> > +	{ 0x9016e, 0x07c0 },
> > +	{ 0x9016f, 0x0109 },
> > +	{ 0x90170, 0 },
> > +	{ 0x90171, 0xe8 },
> > +	{ 0x90172, 0x0109 },
> > +	{ 0x90173, 0x47 },
> > +	{ 0x90174, 0x0630 },
> > +	{ 0x90175, 0x0109 },
> > +	{ 0x90176, 8 },
> > +	{ 0x90177, 0x0618 },
> > +	{ 0x90178, 0x0109 },
> > +	{ 0x90179, 8 },
> > +	{ 0x9017a, 0xe0 },
> > +	{ 0x9017b, 0x0109 },
> > +	{ 0x9017c, 0 },
> > +	{ 0x9017d, 0x07c8 },
> > +	{ 0x9017e, 0x0109 },
> > +	{ 0x9017f, 8 },
> > +	{ 0x90180, 0x8140 },
> > +	{ 0x90181, 0x010c },
> > +	{ 0x90182, 0 },
> > +	{ 0x90183, 1 },
> > +	{ 0x90184, 8 },
> > +	{ 0x90185, 8 },
> > +	{ 0x90186, 4 },
> > +	{ 0x90187, 8 },
> > +	{ 0x90188, 8 },
> > +	{ 0x90189, 0x07c8 },
> > +	{ 0x9018a, 0x0101 },
> > +	{ 0x90006, 0 },
> > +	{ 0x90007, 0 },
> > +	{ 0x90008, 8 },
> > +	{ 0x90009, 0 },
> > +	{ 0x9000a, 0 },
> > +	{ 0x9000b, 0 },
> > +	{ 0xd00e7, 0x0400 },
> > +	{ 0x90017, 0 },
> > +	{ 0x9001f, 0x2a },
> > +	{ 0x90026, 0x6a },
> > +	{ 0x400d0, 0 },
> > +	{ 0x400d1, 0x0101 },
> > +	{ 0x400d2, 0x0105 },
> > +	{ 0x400d3, 0x0107 },
> > +	{ 0x400d4, 0x010f },
> > +	{ 0x400d5, 0x0202 },
> > +	{ 0x400d6, 0x020a },
> > +	{ 0x400d7, 0x020b },
> > +	{ 0x2003a, 2 },
> > +	{ 0x2000b, 0x64 },
> > +	{ 0x2000c, 0xc8 },
> > +	{ 0x2000d, 0x07d0 },
> > +	{ 0x2000e, 0x2c },
> > +	{ 0x12000b, 0x14 },
> > +	{ 0x12000c, 0x29 },
> > +	{ 0x12000d, 0x01a1 },
> > +	{ 0x12000e, 0x10 },
> > +	{ 0x9000c, 0 },
> > +	{ 0x9000d, 0x0173 },
> > +	{ 0x9000e, 0x60 },
> > +	{ 0x9000f, 0x6110 },
> > +	{ 0x90010, 0x2152 },
> > +	{ 0x90011, 0xdfbd },
> > +	{ 0x90012, 0x60 },
> > +	{ 0x90013, 0x6152 },
> > +	{ 0x20010, 0x5a },
> > +	{ 0x20011, 3 },
> > +	{ 0x40080, 0xe0 },
> > +	{ 0x40081, 0x12 },
> > +	{ 0x40082, 0xe0 },
> > +	{ 0x40083, 0x12 },
> > +	{ 0x40084, 0xe0 },
> > +	{ 0x40085, 0x12 },
> > +	{ 0x140080, 0xe0 },
> > +	{ 0x140081, 0x12 },
> > +	{ 0x140082, 0xe0 },
> > +	{ 0x140083, 0x12 },
> > +	{ 0x140084, 0xe0 },
> > +	{ 0x140085, 0x12 },
> > +	{ 0x400fd, 0x0f },
> > +	{ 0x10011, 1 },
> > +	{ 0x10012, 1 },
> > +	{ 0x10013, 0x0180 },
> > +	{ 0x10018, 1 },
> > +	{ 0x10002, 0x6209 },
> > +	{ 0x100b2, 1 },
> > +	{ 0x101b4, 1 },
> > +	{ 0x102b4, 1 },
> > +	{ 0x103b4, 1 },
> > +	{ 0x104b4, 1 },
> > +	{ 0x105b4, 1 },
> > +	{ 0x106b4, 1 },
> > +	{ 0x107b4, 1 },
> > +	{ 0x108b4, 1 },
> > +	{ 0x11011, 1 },
> > +	{ 0x11012, 1 },
> > +	{ 0x11013, 0x0180 },
> > +	{ 0x11018, 1 },
> > +	{ 0x11002, 0x6209 },
> > +	{ 0x110b2, 1 },
> > +	{ 0x111b4, 1 },
> > +	{ 0x112b4, 1 },
> > +	{ 0x113b4, 1 },
> > +	{ 0x114b4, 1 },
> > +	{ 0x115b4, 1 },
> > +	{ 0x116b4, 1 },
> > +	{ 0x117b4, 1 },
> > +	{ 0x118b4, 1 },
> > +	{ 0x12011, 1 },
> > +	{ 0x12012, 1 },
> > +	{ 0x12013, 0x0180 },
> > +	{ 0x12018, 1 },
> > +	{ 0x12002, 0x6209 },
> > +	{ 0x120b2, 1 },
> > +	{ 0x121b4, 1 },
> > +	{ 0x122b4, 1 },
> > +	{ 0x123b4, 1 },
> > +	{ 0x124b4, 1 },
> > +	{ 0x125b4, 1 },
> > +	{ 0x126b4, 1 },
> > +	{ 0x127b4, 1 },
> > +	{ 0x128b4, 1 },
> > +	{ 0x13011, 1 },
> > +	{ 0x13012, 1 },
> > +	{ 0x13013, 0x0180 },
> > +	{ 0x13018, 1 },
> > +	{ 0x13002, 0x6209 },
> > +	{ 0x130b2, 1 },
> > +	{ 0x131b4, 1 },
> > +	{ 0x132b4, 1 },
> > +	{ 0x133b4, 1 },
> > +	{ 0x134b4, 1 },
> > +	{ 0x135b4, 1 },
> > +	{ 0x136b4, 1 },
> > +	{ 0x137b4, 1 },
> > +	{ 0x138b4, 1 },
> > +	{ 0x2003a, 2 },
> > +	{ 0xc0080, 2 },
> > +	{ 0xd0000, 1 }
> > +};
> > +
> > +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
> > +	{
> > +		/* P0 3200mts 1D */
> > +		.drate = 3200,
> > +		.fw_type = FW_1D_IMAGE,
> > +		.fsp_cfg = lpddr4_fsp0_cfg,
> > +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
> > +	},
> > +	{
> > +		/* P1 667mts 1D */
> > +		.drate = 667,
> > +		.fw_type = FW_1D_IMAGE,
> > +		.fsp_cfg = lpddr4_fsp1_cfg,
> > +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
> > +	},
> > +	{
> > +		/* P0 3200mts 2D */
> > +		.drate = 3200,
> > +		.fw_type = FW_2D_IMAGE,
> > +		.fsp_cfg = lpddr4_fsp0_2d_cfg,
> > +		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
> > +	},
> > +};
> > +
> > +/* ddr timing config params */
> > +struct dram_timing_info dram_timing_ch2 = {
> > +	.ddrc_cfg = lpddr4_ddrc_cfg,
> > +	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
> > +	.ddrphy_cfg = lpddr4_ddrphy_cfg,
> > +	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
> > +	.fsp_msg = lpddr4_dram_fsp_msg,
> > +	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
> > +	.ddrphy_pie = lpddr4_phy_pie,
> > +	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
> > +	.fsp_table = { 3200, 667, },
> > +};
> > diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
> > new file mode 100644
> > index 0000000000..7dcc9a7db7
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
> > @@ -0,0 +1,95 @@
> > +/*
> > + * Copyright Boundary Devices
> > + *
> > + * SPDX-License-Identifier: GPL-2.0+
> > + */
> > +#include <config.h>
> > +#include <linux/kernel.h>
> > +#include <asm/arch/ddr.h>
> > +#include <asm/arch/lpddr4_define.h>
> > +
> > +/* MNT Reform2 */
> > +#define CONFIG_DDR_MB 4096
> > +#define CONFIG_DDR_RANK_BITS 1
> > +#define CONFIG_DDR_CHANNEL_CNT 2
> 
> These are not allowed anymore - any new CONFIG_ should flow into Kbuild.
> 
> See:
> 
> 	https://source.denx.de/u-boot/custodians/u-boot-imx/-/jobs/565798
> 
> CONFIG_DDR_MB  is already in Kbuild, just move the value in defconfig.

But only in the nitrogen6x board config, not for any other board or any
of the i.MX8Ms:

board/boundary/nitrogen6x/Kconfig:config DDR_MB

I guess I'll just rename the define like the others.

Thanks,
Patrick

> Best regards,
> Stefano Babic
> 
> > +
> > +#ifdef WR_POST_EXT_3200
> > +#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
> > +#else
> > +#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
> > +#endif
> > +
> > +#if CONFIG_DDR_MB == 1024
> > +	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
> > +#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
> > +#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
> > +
> > +#elif CONFIG_DDR_MB == 2048
> > +	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
> > +#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
> > +#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
> > +	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
> > +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
> > +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
> > +
> > +#elif CONFIG_DDR_MB == 3072
> > +	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
> > +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
> > +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
> > +
> > +#elif CONFIG_DDR_MB == 4096
> > +	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
> > +#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
> > +#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
> > +#else
> > +#error unsupported memory size
> > +#endif
> > +
> > +#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
> > +#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
> > +
> > +#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> > +#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
> > +#define CH2_LPDDR4_CS			LPDDR4_CS_R0
> > +#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
> > +#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
> > +#else
> > +#error unsupported memory rank/size
> > +#endif
> > +/*
> > + * rank0 will succeed, even if really rank 1, so we need
> > + * to probe memory if rank0 succeeds
> > + */
> > +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> > +#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
> > +#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
> > +#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
> > +#endif
> > +
> > +#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
> > +#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
> > +#define CH2_LPDDR4_CS			LPDDR4_CS_R1
> > +#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
> > +#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
> > +#else
> > +#error unsupported memory rank/size
> > +#endif
> > +
> > +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> > +#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
> > +#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
> > +#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
> > +#endif
> > +
> > +#else
> > +#error unsupported rank bits
> > +#endif
> > +
> > +#if (CONFIG_DDR_CHANNEL_CNT == 2)
> > +#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
> > +#error unsupported options
> > +#endif
> > +#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
> > +#error unsupported options
> > +#endif
> > +#endif
> > diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
> > new file mode 100644
> > index 0000000000..21fad4972a
> > --- /dev/null
> > +++ b/board/mntre/imx8mq_reform2/spl.c
> > @@ -0,0 +1,260 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2018 NXP
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +
> > +#include <common.h>
> > +#include <hang.h>
> > +#include <image.h>
> > +#include <init.h>
> > +#include <log.h>
> > +#include <asm/global_data.h>
> > +#include <asm/io.h>
> > +#include <errno.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/ddr.h>
> > +#include <asm/arch/imx8mq_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <fsl_esdhc_imx.h>
> > +#include <mmc.h>
> > +#include <linux/delay.h>
> > +#include <power/pmic.h>
> > +#include <spl.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +extern struct dram_timing_info dram_timing_ch2;
> > +
> > +static void spl_dram_init(void)
> > +{
> > +	ddr_init(&dram_timing_ch2);
> > +}
> > +
> > +#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
> > +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> > +static struct i2c_pads_info i2c_pad_info1 = {
> > +	.scl = {
> > +		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
> > +		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> > +		.gp = IMX_GPIO_NR(5, 14),
> > +	},
> > +	.sda = {
> > +		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
> > +		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> > +		.gp = IMX_GPIO_NR(5, 15),
> > +	},
> > +};
> > +
> > +#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
> > +#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
> > +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
> > +
> > +int board_mmc_getcd(struct mmc *mmc)
> > +{
> > +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> > +	int ret = 0;
> > +
> > +	switch (cfg->esdhc_base) {
> > +	case USDHC1_BASE_ADDR:
> > +		ret = 1;
> > +		break;
> > +	case USDHC2_BASE_ADDR:
> > +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> > +		return ret;
> > +	}
> > +
> > +	return 1;
> > +}
> > +
> > +#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
> > +			 PAD_CTL_FSEL2)
> > +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
> > +
> > +static iomux_v3_cfg_t const usdhc1_pads[] = {
> > +	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> > +	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > +};
> > +
> > +static iomux_v3_cfg_t const usdhc2_pads[] = {
> > +	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> > +	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> > +	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> > +	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> > +	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
> > +	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
> > +	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
> > +	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
> > +};
> > +
> > +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
> > +	{USDHC1_BASE_ADDR, 0, 8},
> > +	{USDHC2_BASE_ADDR, 0, 4},
> > +};
> > +
> > +int board_mmc_init(struct bd_info *bis)
> > +{
> > +	int i, ret;
> > +	/*
> > +	 * According to the board_mmc_init() the following map is done:
> > +	 * (U-Boot device node)    (Physical Port)
> > +	 * mmc0                    USDHC1
> > +	 * mmc1                    USDHC2
> > +	 */
> > +	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
> > +		switch (i) {
> > +		case 0:
> > +			init_clk_usdhc(0);
> > +			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
> > +			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
> > +							 ARRAY_SIZE(usdhc1_pads));
> > +			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
> > +			gpio_direction_output(USDHC1_PWR_GPIO, 0);
> > +			udelay(500);
> > +			gpio_direction_output(USDHC1_PWR_GPIO, 1);
> > +			break;
> > +		case 1:
> > +			init_clk_usdhc(1);
> > +			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
> > +			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
> > +							 ARRAY_SIZE(usdhc2_pads));
> > +			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
> > +			gpio_direction_output(USDHC2_VSEL, 0);
> > +			break;
> > +		default:
> > +			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
> > +			return -EINVAL;
> > +		}
> > +
> > +		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> > +		if (ret)
> > +			return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
> > +#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
> > +#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
> > +#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
> > +
> > +#define I2C_MUX_ADDR		0x70
> > +#define I2C_FAN53555_ADDR	0x60
> > +
> > +static iomux_v3_cfg_t const power_pads[] = {
> > +	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
> > +};
> > +
> > +int power_init_board(void)
> > +{
> > +	uint8_t val;
> > +
> > +	imx_iomux_v3_setup_multiple_pads(power_pads,
> > +					 ARRAY_SIZE(usdhc2_pads));
> > +
> > +	/* Release I2C multiplexer reset */
> > +	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
> > +	gpio_direction_output(I2C1_PCA9546_RESET, 1);
> > +
> > +	/* Select VSEL0 on voltage regulators */
> > +	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
> > +	gpio_direction_output(ARM_DRAM_VSEL, 0);
> > +	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
> > +	gpio_direction_output(DRAM_1P1_VSEL, 0);
> > +	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
> > +	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
> > +
> > +	/* Set mux to target ARM/DRAM regulator */
> > +	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
> > +	/* .6 + .40 = 1.00 */
> > +	val = 0x80 + 40;
> > +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> > +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> > +
> > +	/* Set mux to target DRAM regulator */
> > +	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
> > +	/* .6 + .50 = 1.10 */
> > +	val = 0x80 + 50;
> > +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> > +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> > +
> > +	/* Set mux to target SoC/GPU/VPU regulator */
> > +	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
> > +	/*  .6 + .30 = .90 */
> > +	val = 0x80 + 30;
> > +	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
> > +	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
> > +
> > +	/* Set mux to target peripherals */
> > +	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
> > +
> > +	return 0;
> > +}
> > +
> > +void spl_board_init(void)
> > +{
> > +	puts("Normal Boot\n");
> > +}
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > +	/* Just empty function now - can't decide what to choose */
> > +	debug("%s: %s\n", __func__, name);
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +void board_init_f(ulong dummy)
> > +{
> > +	int ret;
> > +
> > +	/* Clear global data */
> > +	memset((void *)gd, 0, sizeof(gd_t));
> > +
> > +	arch_cpu_init();
> > +
> > +	init_uart_clk(0);
> > +
> > +	board_early_init_f();
> > +
> > +	timer_init();
> > +
> > +	preloader_console_init();
> > +
> > +	/* Clear the BSS. */
> > +	memset(__bss_start, 0, __bss_end - __bss_start);
> > +
> > +	ret = spl_init();
> > +	if (ret) {
> > +		debug("spl_init() failed: %d\n", ret);
> > +		hang();
> > +	}
> > +
> > +	enable_tzc380();
> > +
> > +	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> > +
> > +	power_init_board();
> > +
> > +	/* DDR initialization */
> > +	spl_dram_init();
> > +
> > +	board_init_r(NULL, 0);
> > +}
> > diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
> > new file mode 100644
> > index 0000000000..9b14a1bca1
> > --- /dev/null
> > +++ b/configs/imx8mq_reform2_defconfig
> > @@ -0,0 +1,107 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_IMX8M=y
> > +CONFIG_TEXT_BASE=0x40200000
> > +CONFIG_SYS_MALLOC_LEN=0x600000
> > +CONFIG_SPL_GPIO=y
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_ENV_SIZE=0x1000
> > +CONFIG_ENV_OFFSET=0x400000
> > +CONFIG_SYS_I2C_MXC_I2C1=y
> > +CONFIG_SYS_I2C_MXC_I2C2=y
> > +CONFIG_SYS_I2C_MXC_I2C3=y
> > +CONFIG_DM_GPIO=y
> > +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
> > +CONFIG_SPL_TEXT_BASE=0x7E1000
> > +CONFIG_TARGET_IMX8MQ_REFORM2=y
> > +CONFIG_SYS_PROMPT="u-boot=> "
> > +CONFIG_SPL_MMC=y
> > +CONFIG_SPL_SERIAL=y
> > +CONFIG_SPL_DRIVERS_MISC=y
> > +CONFIG_SPL=y
> > +CONFIG_IMX_BOOTAUX=y
> > +CONFIG_SYS_LOAD_ADDR=0x40480000
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_REMAKE_ELF=y
> > +CONFIG_SYS_MONITOR_LEN=524288
> > +CONFIG_FIT=y
> > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > +CONFIG_SPL_LOAD_FIT=y
> > +# CONFIG_USE_SPL_FIT_GENERATOR is not set
> > +CONFIG_OF_SYSTEM_SETUP=y
> > +CONFIG_USE_PREBOOT=y
> > +CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
> > +CONFIG_CONSOLE_MUX=y
> > +CONFIG_BOARD_EARLY_INIT_F=y
> > +CONFIG_BOARD_LATE_INIT=y
> > +CONFIG_SPL_MAX_SIZE=0x1f000
> > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> > +CONFIG_SPL_BSS_START_ADDR=0x180000
> > +CONFIG_SPL_BSS_MAX_SIZE=0x2000
> > +CONFIG_SPL_BOARD_INIT=y
> > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> > +CONFIG_SPL_STACK=0x187ff0
> > +CONFIG_SYS_SPL_MALLOC=y
> > +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
> > +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
> > +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
> > +CONFIG_SPL_I2C=y
> > +CONFIG_SPL_POWER=y
> > +CONFIG_SPL_WATCHDOG=y
> > +CONFIG_SYS_MAXARGS=64
> > +CONFIG_SYS_PBSIZE=1050
> > +# CONFIG_BOOTM_NETBSD is not set
> > +# CONFIG_CMD_EXPORTENV is not set
> > +# CONFIG_CMD_IMPORTENV is not set
> > +# CONFIG_CMD_CRC32 is not set
> > +CONFIG_CMD_CLK=y
> > +CONFIG_CMD_FUSE=y
> > +CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_MDIO is not set
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_REGULATOR=y
> > +CONFIG_CMD_EXT4_WRITE=y
> > +CONFIG_OF_CONTROL=y
> > +CONFIG_ENV_OVERWRITE=y
> > +CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > +CONFIG_SYS_MMC_ENV_DEV=1
> > +CONFIG_USE_ETHPRIME=y
> > +CONFIG_ETHPRIME="FEC"
> > +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
> > +CONFIG_MXC_GPIO=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SPL_SYS_I2C_LEGACY=y
> > +CONFIG_SUPPORT_EMMC_BOOT=y
> > +CONFIG_FSL_USDHC=y
> > +CONFIG_PHYLIB=y
> > +CONFIG_PHY_ATHEROS=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_PHY_GIGE=y
> > +CONFIG_FEC_MXC=y
> > +CONFIG_MII=y
> > +CONFIG_PHY=y
> > +CONFIG_PHY_IMX8MQ_USB=y
> > +CONFIG_PINCTRL=y
> > +CONFIG_PINCTRL_IMX8M=y
> > +CONFIG_SPL_POWER_LEGACY=y
> > +CONFIG_POWER_DOMAIN=y
> > +CONFIG_IMX8M_POWER_DOMAIN=y
> > +CONFIG_DM_REGULATOR=y
> > +CONFIG_DM_REGULATOR_FIXED=y
> > +CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_SPL_POWER_I2C=y
> > +CONFIG_DM_RESET=y
> > +CONFIG_DM_SERIAL=y
> > +CONFIG_MXC_UART=y
> > +CONFIG_DM_THERMAL=y
> > +CONFIG_USB=y
> > +CONFIG_USB_XHCI_HCD=y
> > +CONFIG_USB_XHCI_DWC3=y
> > +CONFIG_USB_DWC3=y
> > +CONFIG_USB_KEYBOARD=y
> > diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
> > new file mode 100644
> > index 0000000000..bc380850e3
> > --- /dev/null
> > +++ b/include/configs/imx8mq_reform2.h
> > @@ -0,0 +1,66 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright 2018 NXP
> > + */
> > +
> > +#ifndef __IMX8M_REFORM2_H
> > +#define __IMX8M_REFORM2_H
> > +
> > +#include <linux/sizes.h>
> > +#include <linux/stringify.h>
> > +#include <asm/arch/imx-regs.h>
> > +
> > +#ifdef CONFIG_SPL_BUILD
> > +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
> > +
> > +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> > +#define CFG_MALLOC_F_ADDR		0x182000
> > +/* For RAW image gives a error info not panic */
> > +#endif
> > +
> > +/* ENET Config */
> > +/* ENET1 */
> > +#if defined(CONFIG_CMD_NET)
> > +#define CONFIG_FEC_MXC_PHYADDR		4
> > +#endif
> > +
> > +#define BOOT_TARGET_DEVICES(func) \
> > +	func(MMC, mmc, 1) \
> > +	func(MMC, mmc, 0) \
> > +	func(USB, usb, 0) \
> > +	func(DHCP, dhcp, na)
> > +
> > +#include <config_distro_bootcmd.h>
> > +
> > +/* Initial environment variables */
> > +#define CFG_EXTRA_ENV_SETTINGS		\
> > +	BOOTENV \
> > +	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> > +	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> > +	"image=Image\0" \
> > +	"console=ttymxc0,115200\0" \
> > +	"fdt_addr_r=0x43000000\0" \
> > +	"boot_fdt=try\0" \
> > +	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
> > +	"initrd_addr=0x43800000\0" \
> > +	"bootm_size=0x10000000\0" \
> > +	"mmcpart=1\0" \
> > +	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
> > +	"stdin=serial,usbkbd\0"
> > +
> > +/* Link Definitions */
> > +
> > +#define CFG_SYS_INIT_RAM_ADDR		0x40000000
> > +#define CFG_SYS_INIT_RAM_SIZE		0x80000
> > +
> > +
> > +#define CFG_SYS_SDRAM_BASE		0x40000000
> > +#define PHYS_SDRAM			0x40000000
> > +#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
> > +
> > +#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
> > +
> > +#define CFG_SYS_FSL_USDHC_NUM		2
> > +#define CFG_SYS_FSL_ESDHC_ADDR		0
> > +
> > +#endif
> 
> -- 
> =====================================================================
> DENX Software Engineering GmbH,        Managing Director: Erika Unter
> HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
> =====================================================================
> 

^ permalink raw reply	[flat|nested] 17+ messages in thread
* [PATCH v7] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
  2023-01-31 17:00   ` Stefano Babic
@ 2023-01-31 23:57   ` Patrick Wildt
  2023-02-04 10:50     ` Dominique Martinet
  2023-02-05 23:48     ` [PATCH v8] " Patrick Wildt
  2023-02-05 23:24   ` [PATCH v6] " Vagrant Cascadian
  2 siblings, 2 replies; 17+ messages in thread
From: Patrick Wildt @ 2023-01-31 23:57 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
---
Changes since v6:
- Cleaned up some CONFIG_* pollution.
Changes since v5:
- Adjusted to further Binman changes.
- Adjusted to further Kconfig conversions.
- Removed some phy init in favor of DM.
- Removed some pinmux which are now handled by DM_SERIAL.
- Compared with Librem5/EVK and adjusted for similarity.
Changes since v4:
- Adjusted to Kconfig conversions.
- Removed U-Boot-specific device tree changes.
- Synced device tree to Linux v5.19-rc3.
Changes since v3:
- Adjusted to Binman changes in main branch.
- Cleaned up environment variables akin to i.MX8MM.
- Added vendor-prefix to device tree filename.
- Provided ramdisk_addr_r.
Changes since v2:
- Switched to Binman.
Changes since v1:
- Synced DTS with files in Linux git repo.
- Added support for USB host ports.

 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |  107 ++
 include/configs/imx8mq_reform2.h              |   66 ++
 11 files changed, 1765 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 0000000000..e0a6fc5470
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 { /* console */
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a0715e8091..2049efb131 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -51,6 +51,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -320,6 +326,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/purism/librem5/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 0000000000..f9260cb7f5
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 0000000000..946f287ecf
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 0000000000..2efd56bb4a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 0000000000..be5c5060a2
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 0000000000..e5303db0f8
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 0000000000..a55086bb5e
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CFG_DDR_MB 4096
+#define CFG_DDR_RANK_BITS 1
+#define CFG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CFG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CFG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CFG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CFG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CFG_DDR_CHANNEL_CNT == 2)
+#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 0000000000..21fad4972a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 0000000000..9b14a1bca1
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x180000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x187ff0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1050
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 0000000000..28793056cb
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif
-- 
2.39.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* Re: [PATCH v7] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-31 23:57   ` [PATCH v7] " Patrick Wildt
@ 2023-02-04 10:50     ` Dominique Martinet
  2023-02-05 23:48     ` [PATCH v8] " Patrick Wildt
  1 sibling, 0 replies; 17+ messages in thread
From: Dominique Martinet @ 2023-02-04 10:50 UTC (permalink / raw)
  To: Patrick Wildt; +Cc: Stefano Babic, Fabio Estevam, u-boot, Lukas F. Hartmann

Patrick Wildt wrote on Wed, Feb 01, 2023 at 12:57:47AM +0100:
> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
> lifted from BoundaryDevices official U-Boot downstream project.
> 
> Signed-off-by: Patrick Wildt <patrick@blueri.se>

Thanks for this patch!

(a bit late but I see checkpatch has a few things to say about this
(multiple blank lines, const position, SPDX comment position,
and 'if (IS_ENABLED) instead of #ifdef' to name a few)... But most if
not all of these come from the "source" evk files so it's probably best
to ignore and roll with it to keep differences minimal if a backport is
required)

I've reviewed the following:
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
arch/arm/mach-imx/imx8m/Kconfig
git diff --no-index board/freescale/imx8mq_evk/Kconfig board/mntre/imx8mq_reform2/Kconfig
git diff --no-index board/freescale/imx8mq_evk/MAINTAINERS board/mntre/imx8mq_reform2/MAINTAINERS
git diff --no-index board/freescale/imx8mq_evk/Makefile board/mntre/imx8mq_reform2/Makefile
git diff --no-index board/freescale/imx8mq_evk/imx8mq_evk.c board/mntre/imx8mq_reform2/imx8mq_reform2.c
git diff --no-index board/freescale/imx8mq_evk/spl.c board/mntre/imx8mq_reform2/spl.c
git diff --no-index configs/imx8mq_evk_defconfig configs/imx8mq_reform2_defconfig
git diff --no-index include/configs/imx8mq_evk.h include/configs/imx8mq_reform2.h
and board/mntre/imx8mq_reform2/lpddr4_timing* are autogenerated?

which covers everything, and it looks good to me:
Reviewed-by: Dominique Martinet <asmadeus@codewreck.org>


Thanks!
-- 
Dominique Martinet

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v6] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
  2023-01-31 17:00   ` Stefano Babic
  2023-01-31 23:57   ` [PATCH v7] " Patrick Wildt
@ 2023-02-05 23:24   ` Vagrant Cascadian
  2 siblings, 0 replies; 17+ messages in thread
From: Vagrant Cascadian @ 2023-02-05 23:24 UTC (permalink / raw)
  To: Patrick Wildt, Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

[-- Attachment #1: Type: text/plain, Size: 1097 bytes --]

On 2023-01-19, Patrick Wildt wrote:
> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
> lifted from BoundaryDevices official U-Boot downstream project.
>
> Signed-off-by: Patrick Wildt <patrick@blueri.se>
> ---
> Changes since v3:
> - Adjusted to Binman changes in main branch.
> - Cleaned up environment variables akin to i.MX8MM.
> - Added vendor-prefix to device tree filename.
> - Provided ramdisk_addr_r.

ramdisk_addr_r no longer appears to be set.

> +++ b/include/configs/imx8mq_reform2.h
...
> +#include <config_distro_bootcmd.h>
> +
> +/* Initial environment variables */
> +#define CFG_EXTRA_ENV_SETTINGS		\
> +	BOOTENV \
> +	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> +	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

Maybe put "ramdisk_addr_r=0x44000000\0" here?

I had proposed 0x44000000 as a valid value before.

Other than that, seems to work well enough for me, thanks for working on
this!


Would love to be CCed on future patch series. :)


live well,
  vagrant

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 227 bytes --]

^ permalink raw reply	[flat|nested] 17+ messages in thread
* [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-01-31 23:57   ` [PATCH v7] " Patrick Wildt
  2023-02-04 10:50     ` Dominique Martinet
@ 2023-02-05 23:48     ` Patrick Wildt
  2023-02-06  5:27       ` Vagrant Cascadian
  1 sibling, 1 reply; 17+ messages in thread
From: Patrick Wildt @ 2023-02-05 23:48 UTC (permalink / raw)
  To: Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann, Vagrant Cascadian

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
---
Changes since v7:
- Re-added lost ramdisk_addr_r.
Changes since v6:
- Cleaned up some CONFIG_* pollution.
Changes since v5:
- Adjusted to further Binman changes.
- Adjusted to further Kconfig conversions.
- Removed some phy init in favor of DM.
- Removed some pinmux which are now handled by DM_SERIAL.
- Compared with Librem5/EVK and adjusted for similarity.
Changes since v4:
- Adjusted to Kconfig conversions.
- Removed U-Boot-specific device tree changes.
- Synced device tree to Linux v5.19-rc3.
Changes since v3:
- Adjusted to Binman changes in main branch.
- Cleaned up environment variables akin to i.MX8MM.
- Added vendor-prefix to device tree filename.
- Provided ramdisk_addr_r.
Changes since v2:
- Switched to Binman.
Changes since v1:
- Synced DTS with files in Linux git repo.
- Added support for USB host ports.

 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |  107 ++
 include/configs/imx8mq_reform2.h              |   67 ++
 11 files changed, 1766 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 0000000000..e0a6fc5470
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&uart1 { /* console */
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 5e4836b02f..3133e0a009 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -343,6 +349,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/purism/librem5/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 0000000000..f9260cb7f5
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 0000000000..946f287ecf
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 0000000000..2efd56bb4a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 0000000000..be5c5060a2
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 0000000000..e5303db0f8
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 0000000000..a55086bb5e
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CFG_DDR_MB 4096
+#define CFG_DDR_RANK_BITS 1
+#define CFG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CFG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CFG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CFG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CFG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CFG_DDR_CHANNEL_CNT == 2)
+#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 0000000000..21fad4972a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 0000000000..9b14a1bca1
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x180000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x187ff0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1050
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 0000000000..3148e8622e
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif
-- 
2.39.1


^ permalink raw reply related	[flat|nested] 17+ messages in thread
* Re: [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-02-05 23:48     ` [PATCH v8] " Patrick Wildt
@ 2023-02-06  5:27       ` Vagrant Cascadian
  2023-04-28 18:38         ` Vagrant Cascadian
  0 siblings, 1 reply; 17+ messages in thread
From: Vagrant Cascadian @ 2023-02-06  5:27 UTC (permalink / raw)
  To: Patrick Wildt, Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

[-- Attachment #1: Type: text/plain, Size: 2758 bytes --]

On 2023-02-06, Patrick Wildt wrote:
> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
> lifted from BoundaryDevices official U-Boot downstream project.
>
> Signed-off-by: Patrick Wildt <patrick@blueri.se>

Tested booting Debian with a 6.1.x linux kernel on a mnt/reform2 using
nvme rootfs and microsd /boot. Some oddities with video and wifi that do
not occur with the vendor u-boot, but seems like huge progress.

Thanks!

Tested-by: Vagrant Cascadian <vagrant@debian.org>

> ---
> Changes since v7:
> - Re-added lost ramdisk_addr_r.
> Changes since v6:
> - Cleaned up some CONFIG_* pollution.
> Changes since v5:
> - Adjusted to further Binman changes.
> - Adjusted to further Kconfig conversions.
> - Removed some phy init in favor of DM.
> - Removed some pinmux which are now handled by DM_SERIAL.
> - Compared with Librem5/EVK and adjusted for similarity.
> Changes since v4:
> - Adjusted to Kconfig conversions.
> - Removed U-Boot-specific device tree changes.
> - Synced device tree to Linux v5.19-rc3.
> Changes since v3:
> - Adjusted to Binman changes in main branch.
> - Cleaned up environment variables akin to i.MX8MM.
> - Added vendor-prefix to device tree filename.
> - Provided ramdisk_addr_r.
> Changes since v2:
> - Switched to Binman.
> Changes since v1:
> - Synced DTS with files in Linux git repo.
> - Added support for USB host ports.
>
>  arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>  arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>  board/mntre/imx8mq_reform2/Kconfig            |   15 +
>  board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>  board/mntre/imx8mq_reform2/Makefile           |   12 +
>  board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>  board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
>  .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>  board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>  configs/imx8mq_reform2_defconfig              |  107 ++
>  include/configs/imx8mq_reform2.h              |   67 ++
>  11 files changed, 1766 insertions(+)
>  create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>  create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>  create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>  create mode 100644 board/mntre/imx8mq_reform2/Makefile
>  create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>  create mode 100644 board/mntre/imx8mq_reform2/spl.c
>  create mode 100644 configs/imx8mq_reform2_defconfig
>  create mode 100644 include/configs/imx8mq_reform2.h

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-02-06  5:27       ` Vagrant Cascadian
@ 2023-04-28 18:38         ` Vagrant Cascadian
  2023-04-28 21:39           ` Vagrant Cascadian
  0 siblings, 1 reply; 17+ messages in thread
From: Vagrant Cascadian @ 2023-04-28 18:38 UTC (permalink / raw)
  To: Patrick Wildt, Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

[-- Attachment #1: Type: text/plain, Size: 2902 bytes --]

On 2023-02-05, Vagrant Cascadian wrote:
> On 2023-02-06, Patrick Wildt wrote:
>> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
>> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
>> lifted from BoundaryDevices official U-Boot downstream project.
>>
>> Signed-off-by: Patrick Wildt <patrick@blueri.se>
>
> Tested booting Debian with a 6.1.x linux kernel on a mnt/reform2 using
> nvme rootfs and microsd /boot. Some oddities with video and wifi that do
> not occur with the vendor u-boot, but seems like huge progress.

The patch still applies to master; could this be considered for merging
soon?


live well,
  vagrant

>> ---
>> Changes since v7:
>> - Re-added lost ramdisk_addr_r.
>> Changes since v6:
>> - Cleaned up some CONFIG_* pollution.
>> Changes since v5:
>> - Adjusted to further Binman changes.
>> - Adjusted to further Kconfig conversions.
>> - Removed some phy init in favor of DM.
>> - Removed some pinmux which are now handled by DM_SERIAL.
>> - Compared with Librem5/EVK and adjusted for similarity.
>> Changes since v4:
>> - Adjusted to Kconfig conversions.
>> - Removed U-Boot-specific device tree changes.
>> - Synced device tree to Linux v5.19-rc3.
>> Changes since v3:
>> - Adjusted to Binman changes in main branch.
>> - Cleaned up environment variables akin to i.MX8MM.
>> - Added vendor-prefix to device tree filename.
>> - Provided ramdisk_addr_r.
>> Changes since v2:
>> - Switched to Binman.
>> Changes since v1:
>> - Synced DTS with files in Linux git repo.
>> - Added support for USB host ports.
>>
>>  arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>>  arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>>  board/mntre/imx8mq_reform2/Kconfig            |   15 +
>>  board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>>  board/mntre/imx8mq_reform2/Makefile           |   12 +
>>  board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>>  board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
>>  .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>>  board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>>  configs/imx8mq_reform2_defconfig              |  107 ++
>>  include/configs/imx8mq_reform2.h              |   67 ++
>>  11 files changed, 1766 insertions(+)
>>  create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>>  create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>>  create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>>  create mode 100644 board/mntre/imx8mq_reform2/Makefile
>>  create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>>  create mode 100644 board/mntre/imx8mq_reform2/spl.c
>>  create mode 100644 configs/imx8mq_reform2_defconfig
>>  create mode 100644 include/configs/imx8mq_reform2.h

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-04-28 18:38         ` Vagrant Cascadian
@ 2023-04-28 21:39           ` Vagrant Cascadian
  2023-05-02  8:39             ` Stefano Babic
  0 siblings, 1 reply; 17+ messages in thread
From: Vagrant Cascadian @ 2023-04-28 21:39 UTC (permalink / raw)
  To: Patrick Wildt, Stefano Babic, Fabio Estevam; +Cc: u-boot, Lukas F. Hartmann

[-- Attachment #1: Type: text/plain, Size: 3240 bytes --]

On 2023-04-28, Vagrant Cascadian wrote:
> On 2023-02-05, Vagrant Cascadian wrote:
>> On 2023-02-06, Patrick Wildt wrote:
>>> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
>>> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
>>> lifted from BoundaryDevices official U-Boot downstream project.
>>>
>>> Signed-off-by: Patrick Wildt <patrick@blueri.se>
>>
>> Tested booting Debian with a 6.1.x linux kernel on a mnt/reform2 using
>> nvme rootfs and microsd /boot. Some oddities with video and wifi that do
>> not occur with the vendor u-boot, but seems like huge progress.
>
> The patch still applies to master; could this be considered for merging
> soon?

I've also verified that the patch not only builds, but actually boots,
based on git commit c9c2c95d4cd27fe0cd41fe13a863899d268f973c (and also
works on v2023.04, for good measure)...

Tested-by: Vagrant Cascadian <vagrant@debian.org>

live well,
  vagrant

>>> ---
>>> Changes since v7:
>>> - Re-added lost ramdisk_addr_r.
>>> Changes since v6:
>>> - Cleaned up some CONFIG_* pollution.
>>> Changes since v5:
>>> - Adjusted to further Binman changes.
>>> - Adjusted to further Kconfig conversions.
>>> - Removed some phy init in favor of DM.
>>> - Removed some pinmux which are now handled by DM_SERIAL.
>>> - Compared with Librem5/EVK and adjusted for similarity.
>>> Changes since v4:
>>> - Adjusted to Kconfig conversions.
>>> - Removed U-Boot-specific device tree changes.
>>> - Synced device tree to Linux v5.19-rc3.
>>> Changes since v3:
>>> - Adjusted to Binman changes in main branch.
>>> - Cleaned up environment variables akin to i.MX8MM.
>>> - Added vendor-prefix to device tree filename.
>>> - Provided ramdisk_addr_r.
>>> Changes since v2:
>>> - Switched to Binman.
>>> Changes since v1:
>>> - Synced DTS with files in Linux git repo.
>>> - Added support for USB host ports.
>>>
>>>  arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>>>  arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>>>  board/mntre/imx8mq_reform2/Kconfig            |   15 +
>>>  board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>>>  board/mntre/imx8mq_reform2/Makefile           |   12 +
>>>  board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>>>  board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
>>>  .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>>>  board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>>>  configs/imx8mq_reform2_defconfig              |  107 ++
>>>  include/configs/imx8mq_reform2.h              |   67 ++
>>>  11 files changed, 1766 insertions(+)
>>>  create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>>>  create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>>>  create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>>>  create mode 100644 board/mntre/imx8mq_reform2/Makefile
>>>  create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>>>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>>>  create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>>>  create mode 100644 board/mntre/imx8mq_reform2/spl.c
>>>  create mode 100644 configs/imx8mq_reform2_defconfig
>>>  create mode 100644 include/configs/imx8mq_reform2.h

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-04-28 21:39           ` Vagrant Cascadian
@ 2023-05-02  8:39             ` Stefano Babic
  2023-05-02 12:44               ` Stefano Babic
  0 siblings, 1 reply; 17+ messages in thread
From: Stefano Babic @ 2023-05-02  8:39 UTC (permalink / raw)
  To: Vagrant Cascadian, Patrick Wildt, Stefano Babic, Fabio Estevam
  Cc: u-boot, Lukas F. Hartmann

On 28.04.23 23:39, Vagrant Cascadian wrote:
> On 2023-04-28, Vagrant Cascadian wrote:
>> On 2023-02-05, Vagrant Cascadian wrote:
>>> On 2023-02-06, Patrick Wildt wrote:
>>>> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
>>>> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
>>>> lifted from BoundaryDevices official U-Boot downstream project.
>>>>
>>>> Signed-off-by: Patrick Wildt <patrick@blueri.se>
>>>
>>> Tested booting Debian with a 6.1.x linux kernel on a mnt/reform2 using
>>> nvme rootfs and microsd /boot. Some oddities with video and wifi that do
>>> not occur with the vendor u-boot, but seems like huge progress.
>>
>> The patch still applies to master; could this be considered for merging
>> soon?
> 
> I've also verified that the patch not only builds, but actually boots,
> based on git commit c9c2c95d4cd27fe0cd41fe13a863899d268f973c (and also
> works on v2023.04, for good measure)...
> 
> Tested-by: Vagrant Cascadian <vagrant@debian.org>
> 

Thanks, I apply it and CI is running, if no issues are found it will 
part of my next PR.

Regards,
Stefano

> live well,
>    vagrant
> 
>>>> ---
>>>> Changes since v7:
>>>> - Re-added lost ramdisk_addr_r.
>>>> Changes since v6:
>>>> - Cleaned up some CONFIG_* pollution.
>>>> Changes since v5:
>>>> - Adjusted to further Binman changes.
>>>> - Adjusted to further Kconfig conversions.
>>>> - Removed some phy init in favor of DM.
>>>> - Removed some pinmux which are now handled by DM_SERIAL.
>>>> - Compared with Librem5/EVK and adjusted for similarity.
>>>> Changes since v4:
>>>> - Adjusted to Kconfig conversions.
>>>> - Removed U-Boot-specific device tree changes.
>>>> - Synced device tree to Linux v5.19-rc3.
>>>> Changes since v3:
>>>> - Adjusted to Binman changes in main branch.
>>>> - Cleaned up environment variables akin to i.MX8MM.
>>>> - Added vendor-prefix to device tree filename.
>>>> - Provided ramdisk_addr_r.
>>>> Changes since v2:
>>>> - Switched to Binman.
>>>> Changes since v1:
>>>> - Synced DTS with files in Linux git repo.
>>>> - Added support for USB host ports.
>>>>
>>>>   arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>>>>   arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>>>>   board/mntre/imx8mq_reform2/Kconfig            |   15 +
>>>>   board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>>>>   board/mntre/imx8mq_reform2/Makefile           |   12 +
>>>>   board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>>>>   board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
>>>>   .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>>>>   board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>>>>   configs/imx8mq_reform2_defconfig              |  107 ++
>>>>   include/configs/imx8mq_reform2.h              |   67 ++
>>>>   11 files changed, 1766 insertions(+)
>>>>   create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>>>>   create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>>>>   create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>>>>   create mode 100644 board/mntre/imx8mq_reform2/Makefile
>>>>   create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>>>>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>>>>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>>>>   create mode 100644 board/mntre/imx8mq_reform2/spl.c
>>>>   create mode 100644 configs/imx8mq_reform2_defconfig
>>>>   create mode 100644 include/configs/imx8mq_reform2.h

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================


^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v8] board: mntre: imx8mq: Add MNT Reform 2 board support
  2023-05-02  8:39             ` Stefano Babic
@ 2023-05-02 12:44               ` Stefano Babic
  0 siblings, 0 replies; 17+ messages in thread
From: Stefano Babic @ 2023-05-02 12:44 UTC (permalink / raw)
  To: Stefano Babic, Vagrant Cascadian, Patrick Wildt, Fabio Estevam
  Cc: u-boot, Lukas F. Hartmann

On 02.05.23 10:39, Stefano Babic wrote:
> On 28.04.23 23:39, Vagrant Cascadian wrote:
>> On 2023-04-28, Vagrant Cascadian wrote:
>>> On 2023-02-05, Vagrant Cascadian wrote:
>>>> On 2023-02-06, Patrick Wildt wrote:
>>>>> The MNT Reform 2 is a modular DIY laptop.  In its initial version it
>>>>> is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
>>>>> lifted from BoundaryDevices official U-Boot downstream project.
>>>>>
>>>>> Signed-off-by: Patrick Wildt <patrick@blueri.se>
>>>>
>>>> Tested booting Debian with a 6.1.x linux kernel on a mnt/reform2 using
>>>> nvme rootfs and microsd /boot. Some oddities with video and wifi 
>>>> that do
>>>> not occur with the vendor u-boot, but seems like huge progress.
>>>
>>> The patch still applies to master; could this be considered for merging
>>> soon?
>>
>> I've also verified that the patch not only builds, but actually boots,
>> based on git commit c9c2c95d4cd27fe0cd41fe13a863899d268f973c (and also
>> works on v2023.04, for good measure)...
>>
>> Tested-by: Vagrant Cascadian <vagrant@debian.org>
>>
> 
> Thanks, I apply it and CI is running, if no issues are found it will 
> part of my next PR.
> 

Just FYI: CI stoppt because u-boot,dm-spl is not valid anymore. I have 
replaced it with "bootph-pre-ram" in dtsi and Ci is successful, I merge 
it now into u-boot-imx.

Regards,
Stefano

> Regards,
> Stefano
> 
>> live well,
>>    vagrant
>>
>>>>> ---
>>>>> Changes since v7:
>>>>> - Re-added lost ramdisk_addr_r.
>>>>> Changes since v6:
>>>>> - Cleaned up some CONFIG_* pollution.
>>>>> Changes since v5:
>>>>> - Adjusted to further Binman changes.
>>>>> - Adjusted to further Kconfig conversions.
>>>>> - Removed some phy init in favor of DM.
>>>>> - Removed some pinmux which are now handled by DM_SERIAL.
>>>>> - Compared with Librem5/EVK and adjusted for similarity.
>>>>> Changes since v4:
>>>>> - Adjusted to Kconfig conversions.
>>>>> - Removed U-Boot-specific device tree changes.
>>>>> - Synced device tree to Linux v5.19-rc3.
>>>>> Changes since v3:
>>>>> - Adjusted to Binman changes in main branch.
>>>>> - Cleaned up environment variables akin to i.MX8MM.
>>>>> - Added vendor-prefix to device tree filename.
>>>>> - Provided ramdisk_addr_r.
>>>>> Changes since v2:
>>>>> - Switched to Binman.
>>>>> Changes since v1:
>>>>> - Synced DTS with files in Linux git repo.
>>>>> - Added support for USB host ports.
>>>>>
>>>>>   arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
>>>>>   arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>>>>>   board/mntre/imx8mq_reform2/Kconfig            |   15 +
>>>>>   board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
>>>>>   board/mntre/imx8mq_reform2/Makefile           |   12 +
>>>>>   board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
>>>>>   board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 
>>>>> +++++++++++++++++
>>>>>   .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
>>>>>   board/mntre/imx8mq_reform2/spl.c              |  260 +++++
>>>>>   configs/imx8mq_reform2_defconfig              |  107 ++
>>>>>   include/configs/imx8mq_reform2.h              |   67 ++
>>>>>   11 files changed, 1766 insertions(+)
>>>>>   create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/Kconfig
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/Makefile
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
>>>>>   create mode 100644 board/mntre/imx8mq_reform2/spl.c
>>>>>   create mode 100644 configs/imx8mq_reform2_defconfig
>>>>>   create mode 100644 include/configs/imx8mq_reform2.h
> 

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================


^ permalink raw reply	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-05-02 12:44 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-26 21:41 [PATCH v5 0/2] Add MNT Reform 2 board support Patrick Wildt
2022-06-26 21:42 ` [PATCH v5 1/2] arm: dts: imx8mq: update MNT Reform 2 to Linux v5.19-rc3 Patrick Wildt
2022-06-27  1:51   ` Fabio Estevam
2022-06-26 21:42 ` [PATCH v5 2/2] board: mntre: imx8mq: Add MNT Reform 2 board support Patrick Wildt
2022-06-27  1:57   ` Fabio Estevam
2023-01-19 19:56 ` [PATCH v6] " Patrick Wildt
2023-01-31 17:00   ` Stefano Babic
2023-01-31 23:53     ` Patrick Wildt
2023-01-31 23:57   ` [PATCH v7] " Patrick Wildt
2023-02-04 10:50     ` Dominique Martinet
2023-02-05 23:48     ` [PATCH v8] " Patrick Wildt
2023-02-06  5:27       ` Vagrant Cascadian
2023-04-28 18:38         ` Vagrant Cascadian
2023-04-28 21:39           ` Vagrant Cascadian
2023-05-02  8:39             ` Stefano Babic
2023-05-02 12:44               ` Stefano Babic
2023-02-05 23:24   ` [PATCH v6] " Vagrant Cascadian

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