* [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-03-29 13:55 ` Michal Wajdeczko
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
` (21 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
v2: rename the component struct (Rodrigo)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..09b8389152af
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component - Used for communication between i915 and TEE
+ * drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_component {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
@ 2021-03-29 13:55 ` Michal Wajdeczko
2021-04-08 21:38 ` Rodrigo Vivi
0 siblings, 1 reply; 62+ messages in thread
From: Michal Wajdeczko @ 2021-03-29 13:55 UTC (permalink / raw)
To: intel-gfx
On 29.03.2021 00:56, Daniele Ceraolo Spurio wrote:
> This will be used for communication between the i915 driver and the mei
> one. Defining it in a stand-alone patch to avoid circualr dependedencies
typos
> between the patches modifying the 2 drivers.
>
> Split out from an original patch from Huang, Sean Z
>
> v2: rename the component struct (Rodrigo)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index 000000000000..09b8389152af
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
shouldn't be at least on cc: ?
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
typo
> + */
> + struct module *owner;
hmm, usually ops structs have only function pointers, why do we need
owner here ? and are you sure is it a right place if still needed ?
> +
> + int (*send)(struct device *dev, const void *message, size_t size);
> + int (*recv)(struct device *dev, void *buffer, size_t size);
> +};
> +
> +/**
> + * struct i915_pxp_component - Used for communication between i915 and TEE
> + * drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_component {
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface
2021-03-29 13:55 ` Michal Wajdeczko
@ 2021-04-08 21:38 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-08 21:38 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx, Vitaly Lubart
On Mon, Mar 29, 2021 at 03:55:03PM +0200, Michal Wajdeczko wrote:
>
>
> On 29.03.2021 00:56, Daniele Ceraolo Spurio wrote:
> > This will be used for communication between the i915 driver and the mei
> > one. Defining it in a stand-alone patch to avoid circualr dependedencies
>
> typos
>
> > between the patches modifying the 2 drivers.
> >
> > Split out from an original patch from Huang, Sean Z
> >
> > v2: rename the component struct (Rodrigo)
> >
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > include/drm/i915_component.h | 1 +
> > include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++
> > 2 files changed, 46 insertions(+)
> > create mode 100644 include/drm/i915_pxp_tee_interface.h
> >
> > diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> > index 55c3b123581b..c1e2a43d2d1e 100644
> > --- a/include/drm/i915_component.h
> > +++ b/include/drm/i915_component.h
> > @@ -29,6 +29,7 @@
> > enum i915_component_type {
> > I915_COMPONENT_AUDIO = 1,
> > I915_COMPONENT_HDCP,
> > + I915_COMPONENT_PXP
> > };
> >
> > /* MAX_PORT is the number of port
> > diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
> > new file mode 100644
> > index 000000000000..09b8389152af
> > --- /dev/null
> > +++ b/include/drm/i915_pxp_tee_interface.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2020 Intel Corporation
> > + *
> > + * Authors:
> > + * Vitaly Lubart <vitaly.lubart@intel.com>
>
> shouldn't be at least on cc: ?
yeap, good idea...
let's start cc'ing now...
>
> > + */
> > +
> > +#ifndef _I915_PXP_TEE_INTERFACE_H_
> > +#define _I915_PXP_TEE_INTERFACE_H_
> > +
> > +#include <linux/mutex.h>
> > +#include <linux/device.h>
> > +
> > +/**
> > + * struct i915_pxp_component_ops - ops for PXP services.
> > + * @owner: Module providing the ops
> > + * @send: sends data to PXP
> > + * @receive: receives data from PXP
> > + */
> > +struct i915_pxp_component_ops {
> > + /**
> > + * @owner: owner of the module provding the ops
>
> typo
>
> > + */
> > + struct module *owner;
>
> hmm, usually ops structs have only function pointers, why do we need
> owner here ? and are you sure is it a right place if still needed ?
it is indeed not used here and for this series it could be removed.
I haven't considered this earlier because this came from TEE directly,
but for now, let's remove if not used.
>
> > +
> > + int (*send)(struct device *dev, const void *message, size_t size);
> > + int (*recv)(struct device *dev, void *buffer, size_t size);
> > +};
> > +
> > +/**
> > + * struct i915_pxp_component - Used for communication between i915 and TEE
> > + * drivers for the PXP services
> > + * @tee_dev: device that provide the PXP service from TEE Bus.
> > + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> > + */
> > +struct i915_pxp_component {
> > + struct device *tee_dev;
> > + const struct i915_pxp_component_ops *ops;
> > +
> > + /* To protect the above members. */
> > + struct mutex mutex;
> > +};
> > +
> > +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-03-29 14:15 ` Michal Wajdeczko
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
` (20 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915 driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 233 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 274 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..cacfbedb640a
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_component *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static void mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ ret = mei_cldev_disable(cldev);
+ if (ret)
+ dev_warn(&cldev->dev, "mei_cldev_disable() failed\n");
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
@ 2021-03-29 14:15 ` Michal Wajdeczko
0 siblings, 0 replies; 62+ messages in thread
From: Michal Wajdeczko @ 2021-03-29 14:15 UTC (permalink / raw)
To: intel-gfx
On 29.03.2021 00:56, Daniele Ceraolo Spurio wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Export PAVP client to work with i915 driver,
> for binding it uses kernel component framework.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 ++
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 233 +++++++++++++++++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 +++
> 6 files changed, 274 insertions(+)
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>
> diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
> index f5fd5b786607..0e0bcd0da852 100644
> --- a/drivers/misc/mei/Kconfig
> +++ b/drivers/misc/mei/Kconfig
> @@ -47,3 +47,5 @@ config INTEL_MEI_TXE
> Intel Bay Trail
>
> source "drivers/misc/mei/hdcp/Kconfig"
> +source "drivers/misc/mei/pxp/Kconfig"
> +
> diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
> index f1c76f7ee804..d8e5165917f2 100644
> --- a/drivers/misc/mei/Makefile
> +++ b/drivers/misc/mei/Makefile
> @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
> CFLAGS_mei-trace.o = -I$(src)
>
> obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
> +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
> diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
> new file mode 100644
> index 000000000000..4029b96afc04
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Kconfig
> @@ -0,0 +1,13 @@
> +
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +config INTEL_MEI_PXP
> + tristate "Intel PXP services of ME Interface"
> + select INTEL_MEI_ME
> + depends on DRM_I915
> + help
> + MEI Support for PXP Services on Intel platforms.
> +
> + Enables the ME FW services required for PXP support through
> + I915 display driver of Intel.
> diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
> new file mode 100644
> index 000000000000..0329950d5794
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +# Makefile - PXP client driver for Intel MEI Bus Driver.
> +
> +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
> diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
> new file mode 100644
> index 000000000000..cacfbedb640a
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/mei_pxp.c
> @@ -0,0 +1,233 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +/**
> + * DOC: MEI_PXP Client Driver
> + *
> + * The mei_pxp driver acts as a translation layer between PXP
> + * protocol implementer (I915) and ME FW by translating PXP
> + * negotiation messages to ME FW command payloads and vice versa.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/uuid.h>
> +#include <linux/mei_cl_bus.h>
> +#include <linux/component.h>
> +#include <drm/drm_connector.h>
> +#include <drm/i915_component.h>
> +#include <drm/i915_pxp_tee_interface.h>
> +
> +#include "mei_pxp.h"
> +
> +/**
> + * mei_pxp_send_message() - Sends a PXP message to ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @message: a message buffer to send
> + * @size: size of the message
> + * Return: 0 on Success, <0 on Failure
> + */
> +static int
> +mei_pxp_send_message(struct device *dev, const void *message, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !message)
> + return -EINVAL;
can't we just require valid dev and message and then BUG_ON ?
> +
> + cldev = to_mei_cl_device(dev);
> +
> + /* temporary drop const qualifier till the API is fixed */
> + byte = mei_cldev_send(cldev, (u8 *)message, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * mei_pxp_receive_message() - Receives a PXP message from ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @buffer: a message buffer to contain the received message
> + * @size: size of the buffer
> + * Return: bytes sent on Success, <0 on Failure
bytes received ?
> + */
> +static int
> +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !buffer)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + byte = mei_cldev_recv(cldev, buffer, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return byte;
> +}
> +
> +static const struct i915_pxp_component_ops mei_pxp_ops = {
> + .owner = THIS_MODULE,
> + .send = mei_pxp_send_message,
> + .recv = mei_pxp_receive_message,
> +};
> +
> +static int mei_component_master_bind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> + int ret;
> +
> + dev_dbg(dev, "%s\n", __func__);
> + comp_master->ops = &mei_pxp_ops;
> + comp_master->tee_dev = dev;
> + ret = component_bind_all(dev, comp_master);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void mei_component_master_unbind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> +
> + dev_dbg(dev, "%s\n", __func__);
> + component_unbind_all(dev, comp_master);
> +}
> +
> +static const struct component_master_ops mei_component_master_ops = {
> + .bind = mei_component_master_bind,
> + .unbind = mei_component_master_unbind,
> +};
> +
> +/**
> + * mei_pxp_component_match - compare function for matching mei pxp.
> + *
> + * The function checks if the driver is i915, the subcomponent is PXP
> + * and the grand parent of pxp and the parent of i915 are the same
> + * PCH device.
> + *
> + * @dev: master device
> + * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
> + * @data: compare data (mei pxp device)
> + *
> + * Return:
> + * * 1 - if components match
> + * * 0 - otherwise
> + */
> +static int mei_pxp_component_match(struct device *dev, int subcomponent,
> + void *data)
> +{
> + struct device *base = data;
> +
> + if (subcomponent != I915_COMPONENT_PXP)
> + return 0;
> +
> + if (strcmp(dev->driver->name, "i915") == 0) {
> + base = base->parent;
> + if (!base)
> + return 0;
> +
> + base = base->parent;
> + dev = dev->parent;
> + return (base && dev && dev == base);
> + }
> +
> + return 0;
> +}
> +
> +static int mei_pxp_probe(struct mei_cl_device *cldev,
> + const struct mei_cl_device_id *id)
> +{
> + struct i915_pxp_component *comp_master;
> + struct component_match *master_match;
> + int ret;
> +
> + ret = mei_cldev_enable(cldev);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
> + goto enable_err_exit;
> + }
> +
> + comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
> + if (!comp_master) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> +
> + master_match = NULL;
> + component_match_add_typed(&cldev->dev, &master_match,
> + mei_pxp_component_match, &cldev->dev);
> + if (IS_ERR_OR_NULL(master_match)) {
> + ret = -ENOMEM;
why ENOMEM again ? it should be different than kzalloc failure
> + goto err_exit;
> + }
> +
> + mei_cldev_set_drvdata(cldev, comp_master);
> + ret = component_master_add_with_match(&cldev->dev,
> + &mei_component_master_ops,
> + master_match);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
> + goto err_exit;
> + }
> +
> + return 0;
> +
> +err_exit:
> + mei_cldev_set_drvdata(cldev, NULL);
> + kfree(comp_master);
> + mei_cldev_disable(cldev);
> +enable_err_exit:
> + return ret;
> +}
> +
> +static void mei_pxp_remove(struct mei_cl_device *cldev)
> +{
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> + int ret;
> +
> + component_master_del(&cldev->dev, &mei_component_master_ops);
> + kfree(comp_master);
> + mei_cldev_set_drvdata(cldev, NULL);
shouldn't we first set drvdata to null and then kfree ?
> +
> + ret = mei_cldev_disable(cldev);
> + if (ret)
> + dev_warn(&cldev->dev, "mei_cldev_disable() failed\n");
printing "%d" with ret might be useful to find out why it failed
> +}
> +
> +/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
> +#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
> + 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
> +
> +static struct mei_cl_device_id mei_pxp_tbl[] = {
> + { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
> + { }
> +};
> +MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
> +
> +static struct mei_cl_driver mei_pxp_driver = {
> + .id_table = mei_pxp_tbl,
> + .name = KBUILD_MODNAME,
> + .probe = mei_pxp_probe,
> + .remove = mei_pxp_remove,
> +};
> +
> +module_mei_cl_driver(mei_pxp_driver);
> +
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("MEI PXP");
> diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
> new file mode 100644
> index 000000000000..e7b15373fefd
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/mei_pxp.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
> + */
> +
> +#ifndef __MEI_PXP_H__
> +#define __MEI_PXP_H__
> +
> +/* me_pxp_status: Enumeration of all PXP Status Codes */
where exactly this status will be used ?
can't spot it in this patch
> +enum me_pxp_status {
in other places "mei" prefix is used, why "me" here ?
> + ME_PXP_STATUS_SUCCESS = 0x0000,
or "ME" here ?
> +
> +};
> +
> +#endif /* __MEI_PXP_H__ */
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 03/16] drm/i915/pxp: define PXP device flag and kconfig
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 02/16] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
` (19 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 11 +++++++++++
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..c55e58bdbe0b 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,17 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ depends on INTEL_MEI && INTEL_MEI_PXP
+ default y
+ help
+ PXP (Protected Xe Path) is an i915 component, available on GEN12+
+ GPUs, that helps to establish the hardware protected session and
+ manage the status of the alive software session, as well as its life
+ cycle.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fa596dace490..5bf50778d3c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1733,6 +1733,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
+
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 90acbaf800d5..1d8181045885 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -126,6 +126,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_master_unit_irq); \
func(has_pooled_eu); \
+ func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
--
2.29.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-04-08 21:47 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
` (18 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
v2: use perma-pinned context (Chris)
v3: rename pinned_context functions (Chris)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 12 +++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 +++++++----
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 62 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 ++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
8 files changed, 159 insertions(+), 9 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 14f1ab399ad0..a797c6e5830c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -270,6 +270,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 47ee8578e511..ff53cdb847f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -19,6 +19,7 @@
struct drm_printer;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -185,6 +186,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
+#define I915_GEM_HWS_PXP 0x60
+#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX 0x10
@@ -256,6 +259,15 @@ intel_engine_find_active_request(struct intel_engine_cs *engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ unsigned int hwsp,
+ u64 ring_size,
+ struct i915_address_space *vm,
+ struct lock_class_key *key,
+ const char *name);
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
+
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
#define ENGINE_PHYSICAL 0
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index efe935f80c1a..a8e7468b9261 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
#endif
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ unsigned int hwsp,
+ u64 ring_size,
+ struct i915_address_space *vm,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -817,6 +819,14 @@ create_pinned_context(struct intel_engine_cs *engine,
__set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
ce->timeline = page_pack_bits(NULL, hwsp);
+ if (ring_size)
+ ce->ring = __intel_context_ring_size(ring_size);
+
+ if (vm) {
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
+ }
+
err = intel_context_pin(ce); /* perma-pin so it is always available */
if (err) {
intel_context_put(ce);
@@ -834,7 +844,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -854,8 +864,12 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
- &kernel, "kernel_context");
+ return intel_engine_create_pinned_context(engine,
+ I915_GEM_HWS_SEQNO_ADDR,
+ SZ_4K,
+ NULL,
+ &kernel,
+ "kernel_context");
}
/**
@@ -956,7 +970,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
fput(engine->default_state);
if (engine->kernel_context)
- destroy_pinned_context(engine->kernel_context);
+ intel_engine_destroy_pinned_context(engine->kernel_context);
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
cleanup_status_page(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8d77dcbad059..68f42fabc151 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -20,6 +20,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -627,6 +628,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -661,6 +664,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
intel_rps_driver_unregister(>->rps);
+ intel_pxp_fini(>->pxp);
+
/*
* Upon unregistering the device to prevent any new users, cancel
* all in-flight requests so that we can quickly unbind the active
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 0caf6ca0a784..53f44fd4a974 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -25,6 +25,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -148,6 +149,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..7a4258c8f6a1
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "intel_pxp.h"
+#include "gt/intel_context.h"
+#include "i915_drv.h"
+
+static int create_vcs_context(struct intel_pxp *pxp)
+{
+ static struct lock_class_key pxp_lock;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+
+ /*
+ * Find the first VCS engine present. We're guaranteed there is one
+ * if we're in this function due to the check in has_pxp
+ */
+ for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++);
+ GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);
+
+ ce = intel_engine_create_pinned_context(engine, I915_GEM_HWS_PXP_ADDR,
+ SZ_4K, NULL, &pxp_lock,
+ "pxp_context");
+ if (IS_ERR(ce)) {
+ drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
+ return PTR_ERR(ce);
+ }
+
+ pxp->ce = ce;
+
+ return 0;
+}
+
+static void destroy_vcs_context(struct intel_pxp *pxp)
+{
+ intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));
+}
+
+void intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret;
+
+ if (!HAS_PXP(gt->i915))
+ return;
+
+ ret = create_vcs_context(pxp);
+ if (ret)
+ return;
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ destroy_vcs_context(pxp);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..e87550fb9821
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "gt/intel_gt_types.h"
+#include "intel_pxp_types.h"
+
+static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
+{
+ return container_of(pxp, struct intel_gt, pxp);
+}
+
+static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
+{
+ return pxp->ce;
+}
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_fini(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_fini(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
new file mode 100644
index 000000000000..bd12c520e60a
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TYPES_H__
+#define __INTEL_PXP_TYPES_H__
+
+struct intel_context;
+
+struct intel_pxp {
+ struct intel_context *ce;
+};
+
+#endif /* __INTEL_PXP_TYPES_H__ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
@ 2021-04-08 21:47 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-08 21:47 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Chris Wilson
On Sun, Mar 28, 2021 at 03:56:56PM -0700, Daniele Ceraolo Spurio wrote:
> The context is required to send the session termination commands to the
> VCS, which will be implemented in a follow-up patch. We can also use the
> presence of the context as a check of pxp initialization completion.
>
> v2: use perma-pinned context (Chris)
this makes sense...
> v3: rename pinned_context functions (Chris)
this is a good idea...
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 4 ++
> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +++++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 +++++++----
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 62 ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 ++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
> 8 files changed, 159 insertions(+), 9 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 14f1ab399ad0..a797c6e5830c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -270,6 +270,10 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 47ee8578e511..ff53cdb847f2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -19,6 +19,7 @@
>
> struct drm_printer;
> struct intel_gt;
> +struct lock_class_key;
>
> /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
> * but keeps the logic simple. Indeed, the whole purpose of this macro is just
> @@ -185,6 +186,8 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
> +#define I915_GEM_HWS_PXP 0x60
> +#define I915_GEM_HWS_PXP_ADDR (I915_GEM_HWS_PXP * sizeof(u32))
> #define I915_GEM_HWS_SCRATCH 0x80
>
> #define I915_HWS_CSB_BUF0_INDEX 0x10
> @@ -256,6 +259,15 @@ intel_engine_find_active_request(struct intel_engine_cs *engine);
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
>
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> + unsigned int hwsp,
> + u64 ring_size,
> + struct i915_address_space *vm,
> + struct lock_class_key *key,
> + const char *name);
> +void intel_engine_destroy_pinned_context(struct intel_context *ce);
> +
> void intel_engine_init_active(struct intel_engine_cs *engine,
> unsigned int subclass);
> #define ENGINE_PHYSICAL 0
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index efe935f80c1a..a8e7468b9261 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
> #endif
> }
>
> -static struct intel_context *
> -create_pinned_context(struct intel_engine_cs *engine,
> - unsigned int hwsp,
> - struct lock_class_key *key,
> - const char *name)
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> + unsigned int hwsp,
> + u64 ring_size,
> + struct i915_address_space *vm,
> + struct lock_class_key *key,
> + const char *name)
> {
> struct intel_context *ce;
> int err;
> @@ -817,6 +819,14 @@ create_pinned_context(struct intel_engine_cs *engine,
> __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> ce->timeline = page_pack_bits(NULL, hwsp);
>
> + if (ring_size)
> + ce->ring = __intel_context_ring_size(ring_size);
... but I'm afraid I couldn't understand why you are doing this...
> +
> + if (vm) {
> + i915_vm_put(ce->vm);
> + ce->vm = i915_vm_get(vm);
> + }
nor this...
So I believe that a separated patch for this and the rename is more appropriated...
> +
> err = intel_context_pin(ce); /* perma-pin so it is always available */
> if (err) {
> intel_context_put(ce);
> @@ -834,7 +844,7 @@ create_pinned_context(struct intel_engine_cs *engine,
> return ce;
> }
>
> -static void destroy_pinned_context(struct intel_context *ce)
> +void intel_engine_destroy_pinned_context(struct intel_context *ce)
> {
> struct intel_engine_cs *engine = ce->engine;
> struct i915_vma *hwsp = engine->status_page.vma;
> @@ -854,8 +864,12 @@ create_kernel_context(struct intel_engine_cs *engine)
> {
> static struct lock_class_key kernel;
>
> - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
> - &kernel, "kernel_context");
> + return intel_engine_create_pinned_context(engine,
> + I915_GEM_HWS_SEQNO_ADDR,
> + SZ_4K,
> + NULL,
> + &kernel,
> + "kernel_context");
> }
>
> /**
> @@ -956,7 +970,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> fput(engine->default_state);
>
> if (engine->kernel_context)
> - destroy_pinned_context(engine->kernel_context);
> + intel_engine_destroy_pinned_context(engine->kernel_context);
>
> GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
> cleanup_status_page(engine);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 8d77dcbad059..68f42fabc151 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -20,6 +20,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> @@ -627,6 +628,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -661,6 +664,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
>
> intel_rps_driver_unregister(>->rps);
>
> + intel_pxp_fini(>->pxp);
> +
> /*
> * Upon unregistering the device to prevent any new users, cancel
> * all in-flight requests so that we can quickly unbind the active
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 0caf6ca0a784..53f44fd4a974 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -25,6 +25,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -148,6 +149,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..7a4258c8f6a1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: MIT
oh! this reminded me that on the first patch we need to change to use //
instead of /**/
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "intel_pxp.h"
> +#include "gt/intel_context.h"
> +#include "i915_drv.h"
> +
> +static int create_vcs_context(struct intel_pxp *pxp)
> +{
> + static struct lock_class_key pxp_lock;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_engine_cs *engine;
> + struct intel_context *ce;
> +
> + /*
> + * Find the first VCS engine present. We're guaranteed there is one
> + * if we're in this function due to the check in has_pxp
> + */
> + for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++);
> + GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);
> +
> + ce = intel_engine_create_pinned_context(engine, I915_GEM_HWS_PXP_ADDR,
> + SZ_4K, NULL, &pxp_lock,
> + "pxp_context");
> + if (IS_ERR(ce)) {
> + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
> + return PTR_ERR(ce);
> + }
> +
> + pxp->ce = ce;
> +
> + return 0;
> +}
> +
> +static void destroy_vcs_context(struct intel_pxp *pxp)
> +{
> + intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));
> +}
> +
> +void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + if (!HAS_PXP(gt->i915))
> + return;
> +
> + ret = create_vcs_context(pxp);
> + if (ret)
> + return;
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + destroy_vcs_context(pxp);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..e87550fb9821
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "gt/intel_gt_types.h"
> +#include "intel_pxp_types.h"
> +
> +static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> +{
> + return container_of(pxp, struct intel_gt, pxp);
> +}
> +
> +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> +{
> + return pxp->ce;
> +}
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_fini(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_init(struct intel_pxp *pxp)
> +{
> +}
> +
> +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> new file mode 100644
> index 000000000000..bd12c520e60a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TYPES_H__
> +#define __INTEL_PXP_TYPES_H__
> +
> +struct intel_context;
> +
> +struct intel_pxp {
> + struct intel_context *ce;
> +};
> +
> +#endif /* __INTEL_PXP_TYPES_H__ */
everything else looks good to me here...
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-04-08 21:50 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
` (17 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang, Chris Wilson
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
v2: fix locking, don't pollute dev_priv (Chris)
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 77 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 ++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
5 files changed, 109 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a797c6e5830c..14795f6a3c86 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -272,7 +272,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 7a4258c8f6a1..a0fc43f72cad 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -50,7 +51,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
return;
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ goto out_context;
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+
+ return;
+
+out_context:
+ destroy_vcs_context(pxp);
}
void intel_pxp_fini(struct intel_pxp *pxp)
@@ -58,5 +68,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_tee_component_fini(pxp);
+
destroy_vcs_context(pxp);
+
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..21916ec0f6ff
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
+{
+ return &kdev_to_i915(i915_kdev)->gt.pxp;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = data;
+ pxp->pxp_component->tee_dev = tee_kdev;
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+
+ pxp->pxp_component = NULL;
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (!pxp->pxp_component)
+ return;
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..23d050a5d3e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index bd12c520e60a..3e95d21513e8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -7,8 +7,11 @@
#define __INTEL_PXP_TYPES_H__
struct intel_context;
+struct i915_pxp_component;
struct intel_pxp {
+ struct i915_pxp_component *pxp_component;
+
struct intel_context *ce;
};
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
@ 2021-04-08 21:50 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-08 21:50 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Huang, Sean Z, Chris Wilson
On Sun, Mar 28, 2021 at 03:56:57PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (default) session.
>
> v2: fix locking, don't pollute dev_priv (Chris)
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 13 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 77 ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
> 5 files changed, 109 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index a797c6e5830c..14795f6a3c86 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -272,7 +272,8 @@ i915-y += i915_perf.o
>
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> - pxp/intel_pxp.o
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 7a4258c8f6a1..a0fc43f72cad 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -50,7 +51,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (ret)
> return;
>
> + ret = intel_pxp_tee_component_init(pxp);
> + if (ret)
> + goto out_context;
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +
> + return;
> +
> +out_context:
> + destroy_vcs_context(pxp);
> }
>
> void intel_pxp_fini(struct intel_pxp *pxp)
> @@ -58,5 +68,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> destroy_vcs_context(pxp);
> +
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index 000000000000..21916ec0f6ff
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> +{
> + return &kdev_to_i915(i915_kdev)->gt.pxp;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume from system sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = data;
> + pxp->pxp_component->tee_dev = tee_kdev;
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = NULL;
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind,
> +};
> +
> +int intel_pxp_tee_component_init(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + if (!pxp->pxp_component)
> + return;
> +
> + component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> new file mode 100644
> index 000000000000..23d050a5d3e7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
> +
> +int intel_pxp_tee_component_init(struct intel_pxp *pxp);
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index bd12c520e60a..3e95d21513e8 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -7,8 +7,11 @@
> #define __INTEL_PXP_TYPES_H__
>
> struct intel_context;
> +struct i915_pxp_component;
>
> struct intel_pxp {
> + struct i915_pxp_component *pxp_component;
> +
> struct intel_context *ce;
> };
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-04-08 21:52 ` Rodrigo Vivi
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
` (16 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Sean Z, Huang
The setting is required by hardware to allow us doing further protection
operation such as sending commands to GPU or TEE. The register needs to
be re-programmed on resume, so for simplicitly we bundle the programming
with the component binding, which is automatically called on resume.
Further HW set-up operations will be added in the same location in
follow-up patches, so get ready for them by using a couple of
init/fini_hw wrappers instead of calling the KCR funcs directly.
v3: move programming to component binding function, rework commit msg
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +++++
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index a0fc43f72cad..c1ad0cf2c664 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,24 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
+
+static void kcr_pxp_enable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+ _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
+static void kcr_pxp_disable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+ _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
static int create_vcs_context(struct intel_pxp *pxp)
{
static struct lock_class_key pxp_lock;
@@ -71,5 +89,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
+}
+
+void intel_pxp_init_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_enable(pxp_to_gt(pxp));
+}
+void intel_pxp_fini_hw(struct intel_pxp *pxp)
+{
+ kcr_pxp_disable(pxp_to_gt(pxp));
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e87550fb9821..5427c3b28aa9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -22,6 +22,9 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
+
+void intel_pxp_init_hw(struct intel_pxp *pxp);
+void intel_pxp_fini_hw(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
{
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 21916ec0f6ff..33130fb7113b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
pxp->pxp_component = data;
pxp->pxp_component->tee_dev = tee_kdev;
+ /* the component is required to fully start the PXP HW */
+ intel_pxp_init_hw(pxp);
+
return 0;
}
@@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
{
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+ intel_pxp_fini_hw(pxp);
+
pxp->pxp_component = NULL;
}
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
@ 2021-04-08 21:52 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-08 21:52 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Sean Z
On Sun, Mar 28, 2021 at 03:56:58PM -0700, Daniele Ceraolo Spurio wrote:
> The setting is required by hardware to allow us doing further protection
> operation such as sending commands to GPU or TEE. The register needs to
> be re-programmed on resume, so for simplicitly we bundle the programming
> with the component binding, which is automatically called on resume.
>
> Further HW set-up operations will be added in the same location in
> follow-up patches, so get ready for them by using a couple of
> init/fini_hw wrappers instead of calling the KCR funcs directly.
>
> v3: move programming to component binding function, rework commit msg
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +++++
> 3 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index a0fc43f72cad..c1ad0cf2c664 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -7,6 +7,24 @@
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
defining registers outside of i915_reg.h is so wrong imo...
but I'm afraid I have lost this fight :/
> +
> +static void kcr_pxp_enable(struct intel_gt *gt)
> +{
> + intel_uncore_write(gt->uncore, KCR_INIT,
> + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> +}
> +
> +static void kcr_pxp_disable(struct intel_gt *gt)
> +{
> + intel_uncore_write(gt->uncore, KCR_INIT,
> + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> +}
> +
> static int create_vcs_context(struct intel_pxp *pxp)
> {
> static struct lock_class_key pxp_lock;
> @@ -71,5 +89,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> intel_pxp_tee_component_fini(pxp);
>
> destroy_vcs_context(pxp);
> +}
> +
> +void intel_pxp_init_hw(struct intel_pxp *pxp)
> +{
> + kcr_pxp_enable(pxp_to_gt(pxp));
> +}
>
> +void intel_pxp_fini_hw(struct intel_pxp *pxp)
> +{
> + kcr_pxp_disable(pxp_to_gt(pxp));
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index e87550fb9821..5427c3b28aa9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -22,6 +22,9 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> +
> +void intel_pxp_init_hw(struct intel_pxp *pxp);
> +void intel_pxp_fini_hw(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 21916ec0f6ff..33130fb7113b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -33,6 +33,9 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> pxp->pxp_component = data;
> pxp->pxp_component->tee_dev = tee_kdev;
>
> + /* the component is required to fully start the PXP HW */
> + intel_pxp_init_hw(pxp);
> +
> return 0;
> }
>
> @@ -41,6 +44,8 @@ static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> {
> struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
>
> + intel_pxp_fini_hw(pxp);
> +
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> pxp->pxp_component = NULL;
> }
>
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
@ 2021-03-28 22:56 ` Daniele Ceraolo Spurio
2021-04-08 22:01 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
` (15 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang, Chris Wilson
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session will need to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
The session ID is exposed as part of the uapi so it can be used as part
of userspace commands.
v2: use gt->uncore->rpm (Chris)
v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
init_hw function
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74 ++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15 ++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 92 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 10 +++
include/uapi/drm/i915_drm.h | 3 +
9 files changed, 206 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 14795f6a3c86..219095d9b42c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c1ad0cf2c664..e496fc4ccf0a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -94,6 +95,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
kcr_pxp_enable(pxp_to_gt(pxp));
+
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 5427c3b28aa9..8eeb65af78b1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
return pxp->ce;
}
+static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
+{
+ return pxp->arb_is_valid;
+}
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
new file mode 100644
index 000000000000..3331868f354c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+
+#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 sip = 0;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
+ return sip & BIT(id);
+}
+
+static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 mask = BIT(id);
+ int ret;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ ret = intel_wait_for_register(gt->uncore,
+ GEN12_KCR_SIP,
+ mask,
+ in_play ? mask : 0,
+ 100);
+
+ return ret;
+}
+
+int intel_pxp_create_arb_session(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret;
+
+ pxp->arb_is_valid = false;
+
+ if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) {
+ drm_err(>->i915->drm, "arb session already in play at creation time\n");
+ return -EEXIST;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
+ if (ret) {
+ drm_err(>->i915->drm, "tee cmd for arb session creation failed\n");
+ return ret;
+ }
+
+ ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true);
+ if (ret) {
+ drm_err(>->i915->drm, "arb session failed to go in play\n");
+ return ret;
+ }
+
+ pxp->arb_is_valid = true;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
new file mode 100644
index 000000000000..316c3bebed9c
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SESSION_H__
+#define __INTEL_PXP_SESSION_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_create_arb_session(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_SESSION_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 33130fb7113b..170dd9fa5bb2 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -8,13 +8,72 @@
#include "drm/i915_component.h"
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
+#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_ARB_CMDID 0x1e
+#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+
+/* PXP TEE message header */
+struct pxp_tee_cmd_header {
+ u32 api_version;
+ u32 command_id;
+ u32 status;
+ /* Length of the message (excluding the header) */
+ u32 buffer_len;
+} __packed;
+
+/* PXP TEE message input to create a arbitrary session */
+struct pxp_tee_create_arb_in {
+ struct pxp_tee_cmd_header header;
+ u32 protection_mode;
+ u32 session_id;
+} __packed;
+
+/* PXP TEE message output to create a arbitrary session */
+struct pxp_tee_create_arb_out {
+ struct pxp_tee_cmd_header header;
+} __packed;
+
static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
{
return &kdev_to_i915(i915_kdev)->gt.pxp;
}
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 msg_out_max_size,
+ u32 *msg_out_rcv_size)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_pxp_component *pxp_component = pxp->pxp_component;
+ int ret;
+
+ ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send PXP TEE message\n");
+ return ret;
+ }
+
+ ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out, msg_out_max_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive PXP TEE message\n");
+ return ret;
+ }
+
+ if (ret > msg_out_max_size) {
+ drm_err(&i915->drm,
+ "Failed to receive PXP TEE message due to unexpected output size\n");
+ return -ENOSPC;
+ }
+
+ if (msg_out_rcv_size)
+ *msg_out_rcv_size = ret;
+
+ return 0;
+}
+
/**
* i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee
* @i915_kdev: pointer to i915 kernel device
@@ -28,6 +87,7 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
pxp->pxp_component = data;
@@ -36,6 +96,13 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
/* the component is required to fully start the PXP HW */
intel_pxp_init_hw(pxp);
+ if (!pxp->arb_is_valid) {
+ drm_err(&i915->drm, "Failed to create arb session during bind\n");
+ intel_pxp_fini_hw(pxp);
+ pxp->pxp_component = NULL;
+ return -EIO;
+ }
+
return 0;
}
@@ -80,3 +147,28 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct pxp_tee_create_arb_in msg_in = {0};
+ struct pxp_tee_create_arb_out msg_out = {0};
+ int ret;
+
+ msg_in.header.api_version = PXP_TEE_APIVER;
+ msg_in.header.command_id = PXP_TEE_ARB_CMDID;
+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
+ msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
+ msg_in.session_id = arb_session_id;
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in, sizeof(msg_in),
+ &msg_out, sizeof(msg_out),
+ NULL);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 23d050a5d3e7..c136053ce340 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,7 @@
int intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id);
+
#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 3e95d21513e8..b142b8170266 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -6,6 +6,9 @@
#ifndef __INTEL_PXP_TYPES_H__
#define __INTEL_PXP_TYPES_H__
+#include <linux/types.h>
+#include <linux/mutex.h>
+
struct intel_context;
struct i915_pxp_component;
@@ -13,6 +16,13 @@ struct intel_pxp {
struct i915_pxp_component *pxp_component;
struct intel_context *ce;
+
+ /*
+ * After a teardown, the arb session can still be in play on the HW
+ * even if the keys are gone, so we can't rely on the HW state of the
+ * session to know if it's valid and need to track the status in SW.
+ */
+ bool arb_is_valid;
};
#endif /* __INTEL_PXP_TYPES_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ddc47bbf48b6..3dcb8fe64ccd 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2377,6 +2377,9 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
#if defined(__cplusplus)
}
#endif
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
@ 2021-04-08 22:01 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-08 22:01 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Huang, Sean Z, Chris Wilson
On Sun, Mar 28, 2021 at 03:56:59PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session will need to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> The session ID is exposed as part of the uapi so it can be used as part
> of userspace commands.
>
> v2: use gt->uncore->rpm (Chris)
> v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
> init_hw function
not sure about "is_valid"... but I don't have better suggestion...
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74 ++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 92 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 10 +++
> include/uapi/drm/i915_drm.h | 3 +
> 9 files changed, 206 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 14795f6a3c86..219095d9b42c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -273,6 +273,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index c1ad0cf2c664..e496fc4ccf0a 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
> @@ -94,6 +95,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> kcr_pxp_enable(pxp_to_gt(pxp));
> +
> + intel_pxp_create_arb_session(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 5427c3b28aa9..8eeb65af78b1 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> return pxp->ce;
> }
>
> +static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +{
> + return pxp->arb_is_valid;
> +}
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> new file mode 100644
> index 000000000000..3331868f354c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "drm/i915_drm.h"
> +#include "i915_drv.h"
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> +#include "intel_pxp_tee.h"
> +#include "intel_pxp_types.h"
> +
> +#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
> +
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
> +
> +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + intel_wakeref_t wakeref;
> + u32 sip = 0;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
> +
> + return sip & BIT(id);
> +}
> +
> +static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + intel_wakeref_t wakeref;
> + u32 mask = BIT(id);
> + int ret;
> +
> + with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> + ret = intel_wait_for_register(gt->uncore,
> + GEN12_KCR_SIP,
> + mask,
> + in_play ? mask : 0,
> + 100);
> +
> + return ret;
> +}
> +
> +int intel_pxp_create_arb_session(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + pxp->arb_is_valid = false;
> +
> + if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) {
> + drm_err(>->i915->drm, "arb session already in play at creation time\n");
> + return -EEXIST;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
> + if (ret) {
> + drm_err(>->i915->drm, "tee cmd for arb session creation failed\n");
> + return ret;
> + }
> +
> + ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true);
> + if (ret) {
> + drm_err(>->i915->drm, "arb session failed to go in play\n");
> + return ret;
> + }
> +
> + pxp->arb_is_valid = true;
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> new file mode 100644
> index 000000000000..316c3bebed9c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_SESSION_H__
> +#define __INTEL_PXP_SESSION_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_pxp;
> +
> +int intel_pxp_create_arb_session(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_SESSION_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 33130fb7113b..170dd9fa5bb2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -8,13 +8,72 @@
> #include "drm/i915_component.h"
> #include "i915_drv.h"
> #include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
>
> +#define PXP_TEE_APIVER 0x40002
> +#define PXP_TEE_ARB_CMDID 0x1e
> +#define PXP_TEE_ARB_PROTECTION_MODE 0x2
> +
> +/* PXP TEE message header */
> +struct pxp_tee_cmd_header {
> + u32 api_version;
> + u32 command_id;
> + u32 status;
> + /* Length of the message (excluding the header) */
> + u32 buffer_len;
> +} __packed;
> +
> +/* PXP TEE message input to create a arbitrary session */
> +struct pxp_tee_create_arb_in {
> + struct pxp_tee_cmd_header header;
> + u32 protection_mode;
> + u32 session_id;
> +} __packed;
> +
> +/* PXP TEE message output to create a arbitrary session */
> +struct pxp_tee_create_arb_out {
> + struct pxp_tee_cmd_header header;
> +} __packed;
> +
wouldn't be helpful (right?) to have this defined in the intel_pxp_tee_interface.h?
> static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> {
> return &kdev_to_i915(i915_kdev)->gt.pxp;
> }
>
> +static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> + void *msg_in, u32 msg_in_size,
> + void *msg_out, u32 msg_out_max_size,
> + u32 *msg_out_rcv_size)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct i915_pxp_component *pxp_component = pxp->pxp_component;
> + int ret;
> +
> + ret = pxp_component->ops->send(pxp_component->tee_dev, msg_in, msg_in_size);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send PXP TEE message\n");
> + return ret;
> + }
> +
> + ret = pxp_component->ops->recv(pxp_component->tee_dev, msg_out, msg_out_max_size);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to receive PXP TEE message\n");
> + return ret;
> + }
> +
> + if (ret > msg_out_max_size) {
> + drm_err(&i915->drm,
> + "Failed to receive PXP TEE message due to unexpected output size\n");
> + return -ENOSPC;
> + }
> +
> + if (msg_out_rcv_size)
> + *msg_out_rcv_size = ret;
> +
> + return 0;
> +}
> +
> /**
> * i915_pxp_tee_component_bind - bind function to pass the function pointers to pxp_tee
> * @i915_kdev: pointer to i915 kernel device
> @@ -28,6 +87,7 @@ static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> struct device *tee_kdev, void *data)
> {
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
>
> pxp->pxp_component = data;
> @@ -36,6 +96,13 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> /* the component is required to fully start the PXP HW */
> intel_pxp_init_hw(pxp);
>
> + if (!pxp->arb_is_valid) {
> + drm_err(&i915->drm, "Failed to create arb session during bind\n");
> + intel_pxp_fini_hw(pxp);
> + pxp->pxp_component = NULL;
> + return -EIO;
> + }
> +
> return 0;
> }
>
> @@ -80,3 +147,28 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct pxp_tee_create_arb_in msg_in = {0};
> + struct pxp_tee_create_arb_out msg_out = {0};
> + int ret;
> +
> + msg_in.header.api_version = PXP_TEE_APIVER;
> + msg_in.header.command_id = PXP_TEE_ARB_CMDID;
> + msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
> + msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
> + msg_in.session_id = arb_session_id;
> +
> + ret = intel_pxp_tee_io_message(pxp,
> + &msg_in, sizeof(msg_in),
> + &msg_out, sizeof(msg_out),
> + NULL);
> +
> + if (ret)
> + drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> index 23d050a5d3e7..c136053ce340 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,7 @@
> int intel_pxp_tee_component_init(struct intel_pxp *pxp);
> void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
>
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
> + int arb_session_id);
> +
> #endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 3e95d21513e8..b142b8170266 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -6,6 +6,9 @@
> #ifndef __INTEL_PXP_TYPES_H__
> #define __INTEL_PXP_TYPES_H__
>
> +#include <linux/types.h>
> +#include <linux/mutex.h>
> +
> struct intel_context;
> struct i915_pxp_component;
>
> @@ -13,6 +16,13 @@ struct intel_pxp {
> struct i915_pxp_component *pxp_component;
>
> struct intel_context *ce;
> +
> + /*
> + * After a teardown, the arb session can still be in play on the HW
> + * even if the keys are gone, so we can't rely on the HW state of the
> + * session to know if it's valid and need to track the status in SW.
> + */
> + bool arb_is_valid;
> };
>
> #endif /* __INTEL_PXP_TYPES_H__ */
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index ddc47bbf48b6..3dcb8fe64ccd 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -2377,6 +2377,9 @@ struct drm_i915_query_perf_config {
> __u8 data[];
> };
>
> +/* ID of the protected content session managed by i915 when PXP is active */
> +#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
> +
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2021-03-28 22:56 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-09 9:16 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
` (14 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang, Chris Wilson
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
v2: emit in the ring, use high prio request (Chris)
v3: better defines, stalling flush, cleaned up and renamed submission
funcs (Chris)
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 140 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29 ++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
7 files changed, 211 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 219095d9b42c..87a6145b4ae8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 14e2ffb6c0e5..a73f46db4910 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -28,10 +28,13 @@
#define INSTR_26_TO_24_MASK 0x7000000
#define INSTR_26_TO_24_SHIFT 24
+#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
+
/*
* Memory interface instructions used by the kernel
*/
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_INSTR(opcode, flags) \
+ (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
#define MI_GLOBAL_GTT (1<<22)
@@ -57,6 +60,7 @@
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
#define MI_SUSPEND_FLUSH_EN (1<<0)
#define MI_SET_APPID MI_INSTR(0x0e, 0)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
#define MI_OVERLAY_CONTINUE (0x0<<21)
#define MI_OVERLAY_ON (0x1<<21)
@@ -144,6 +148,7 @@
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
+#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22)
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB (1<<18)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
@@ -270,6 +275,19 @@
#define MI_MATH_REG_ZF 0x32
#define MI_MATH_REG_CF 0x33
+/*
+ * Media instructions used by the kernel
+ */
+#define MEDIA_INSTR(pipe, op, sub_op, flags) \
+ (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
+ (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
+
+#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
+
+#define CRYPTO_KEY_EXCHANGE MEDIA_INSTR(2, 6, 9, 0)
+
/*
* Commands used only by the command parser
*/
@@ -326,8 +344,6 @@
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
-#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
-
#define COLOR_BLT ((0x2<<29)|(0x40<<22))
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index e496fc4ccf0a..2a5099034946 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -94,9 +94,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
void intel_pxp_init_hw(struct intel_pxp *pxp)
{
+ int ret;
+
kcr_pxp_enable(pxp_to_gt(pxp));
- intel_pxp_create_arb_session(pxp);
+ /* always emit a full termination to clean the state */
+ ret = intel_pxp_terminate_arb_session_and_global(pxp);
+ if (!ret)
+ intel_pxp_create_arb_session(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..c577f1fbee55
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_ring.h"
+
+#include "i915_trace.h"
+
+/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+#define MFX_WAIT_PXP (MFX_WAIT | \
+ MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG)
+
+static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)
+{
+ *cs++ = MFX_WAIT_PXP;
+
+ /* pxp off */
+ *cs++ = MI_FLUSH_DW;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ /* select session */
+ *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
+
+ *cs++ = MFX_WAIT_PXP;
+
+ /* pxp on */
+ *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN |
+ MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
+ *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT;
+ *cs++ = 0;
+
+ *cs++ = MFX_WAIT_PXP;
+
+ return cs;
+}
+
+static u32 *pxp_emit_inline_termination(u32 *cs)
+{
+ /* session inline termination */
+ *cs++ = CRYPTO_KEY_EXCHANGE;
+ *cs++ = 0;
+
+ return cs;
+}
+
+static u32 *pxp_emit_session_termination(u32 *cs, u32 idx)
+{
+ cs = pxp_emit_session_selection(cs, idx);
+ cs = pxp_emit_inline_termination(cs);
+
+ return cs;
+}
+
+static u32 *pxp_emit_wait(u32 *cs)
+{
+ /* wait for cmds to go through */
+ *cs++ = MFX_WAIT_PXP;
+ *cs++ = 0;
+
+ return cs;
+}
+
+/*
+ * if we ever need to terminate more than one session, we can submit multiple
+ * selections and terminations back-to-back with a single wait at the end
+ */
+#define SELECTION_LEN 10
+#define TERMINATION_LEN 2
+#define SESSION_TERMINATION_LEN(x) ((SELECTION_LEN + TERMINATION_LEN) * (x))
+#define WAIT_LEN 2
+
+static void pxp_request_commit(struct i915_request *rq)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
+ struct intel_timeline * const tl = i915_request_timeline(rq);
+
+ lockdep_unpin_lock(&tl->mutex, rq->cookie);
+
+ trace_i915_request_add(rq);
+ __i915_request_commit(rq);
+ __i915_request_queue(rq, &attr);
+
+ mutex_unlock(&tl->mutex);
+}
+
+int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id)
+{
+ struct i915_request *rq;
+ struct intel_context *ce = pxp->ce;
+ u32 *cs;
+ int err;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ cs = intel_ring_begin(rq, SESSION_TERMINATION_LEN(1) + WAIT_LEN);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto out_rq;
+ }
+
+ cs = pxp_emit_session_termination(cs, id);
+ cs = pxp_emit_wait(cs);
+
+ intel_ring_advance(rq, cs);
+
+out_rq:
+ i915_request_get(rq);
+
+ if (unlikely(err))
+ i915_request_set_error_once(rq, err);
+
+ pxp_request_commit(rq);
+
+ if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+
+ i915_request_put(rq);
+
+ return err;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..6d6299543578
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 idx);
+
+#endif /* __INTEL_PXP_CMD_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 3331868f354c..b8e24adeb1f3 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_cmd.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
@@ -15,6 +16,9 @@
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+/* PXP global terminate register for session termination */
+#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
+
static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
{
struct intel_gt *gt = pxp_to_gt(pxp);
@@ -72,3 +76,28 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
return 0;
}
+
+int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ pxp->arb_is_valid = false;
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to submit session termination\n");
+ return ret;
+ }
+
+ ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
+ if (ret) {
+ drm_err(>->i915->drm, "Session state did not clear\n");
+ return ret;
+ }
+
+ intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
index 316c3bebed9c..7354314b1cc4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
@@ -11,5 +11,6 @@
struct intel_pxp;
int intel_pxp_create_arb_session(struct intel_pxp *pxp);
+int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_SESSION_H__ */
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
@ 2021-04-09 9:16 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-09 9:16 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Huang, Sean Z, Chris Wilson
On Sun, Mar 28, 2021 at 03:57:00PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. Additionally, we want to emit a
> teardown operation to make sure we're clean on boot and resume
>
> v2: emit in the ring, use high prio request (Chris)
> v3: better defines, stalling flush, cleaned up and renamed submission
> funcs (Chris)
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 140 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 29 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
> 7 files changed, 211 insertions(+), 4 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 219095d9b42c..87a6145b4ae8 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -273,6 +273,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 14e2ffb6c0e5..a73f46db4910 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -28,10 +28,13 @@
> #define INSTR_26_TO_24_MASK 0x7000000
> #define INSTR_26_TO_24_SHIFT 24
>
> +#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
> +
> /*
> * Memory interface instructions used by the kernel
> */
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_INSTR(opcode, flags) \
> + (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
> /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
> #define MI_GLOBAL_GTT (1<<22)
>
> @@ -57,6 +60,7 @@
> #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
> #define MI_SUSPEND_FLUSH_EN (1<<0)
> #define MI_SET_APPID MI_INSTR(0x0e, 0)
> +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
> #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
> #define MI_OVERLAY_CONTINUE (0x0<<21)
> #define MI_OVERLAY_ON (0x1<<21)
> @@ -144,6 +148,7 @@
> #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
> #define MI_SRM_LRM_GLOBAL_GTT (1<<22)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> +#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22)
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> #define MI_FLUSH_DW_OP_STOREDW (1<<14)
> @@ -270,6 +275,19 @@
> #define MI_MATH_REG_ZF 0x32
> #define MI_MATH_REG_CF 0x33
>
> +/*
> + * Media instructions used by the kernel
> + */
> +#define MEDIA_INSTR(pipe, op, sub_op, flags) \
> + (__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
> + (op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))
> +
> +#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
> +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
> +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
> +
> +#define CRYPTO_KEY_EXCHANGE MEDIA_INSTR(2, 6, 9, 0)
> +
> /*
> * Commands used only by the command parser
> */
> @@ -326,8 +344,6 @@
> #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
> ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
>
> -#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
> -
> #define COLOR_BLT ((0x2<<29)|(0x40<<22))
> #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index e496fc4ccf0a..2a5099034946 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -94,9 +94,14 @@ void intel_pxp_fini(struct intel_pxp *pxp)
>
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> + int ret;
> +
> kcr_pxp_enable(pxp_to_gt(pxp));
>
> - intel_pxp_create_arb_session(pxp);
> + /* always emit a full termination to clean the state */
> + ret = intel_pxp_terminate_arb_session_and_global(pxp);
> + if (!ret)
> + intel_pxp_create_arb_session(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> new file mode 100644
> index 000000000000..c577f1fbee55
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_ring.h"
> +
> +#include "i915_trace.h"
> +
> +/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
> +#define MFX_WAIT_PXP (MFX_WAIT | \
> + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG)
> +
> +static u32 *pxp_emit_session_selection(u32 *cs, u32 idx)
> +{
> + *cs++ = MFX_WAIT_PXP;
> +
> + /* pxp off */
> + *cs++ = MI_FLUSH_DW;
> + *cs++ = 0;
> + *cs++ = 0;
> +
> + /* select session */
> + *cs++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
> +
> + *cs++ = MFX_WAIT_PXP;
> +
> + /* pxp on */
> + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN |
> + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
> + *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT;
> + *cs++ = 0;
> +
> + *cs++ = MFX_WAIT_PXP;
> +
> + return cs;
> +}
> +
> +static u32 *pxp_emit_inline_termination(u32 *cs)
> +{
> + /* session inline termination */
> + *cs++ = CRYPTO_KEY_EXCHANGE;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +static u32 *pxp_emit_session_termination(u32 *cs, u32 idx)
> +{
> + cs = pxp_emit_session_selection(cs, idx);
> + cs = pxp_emit_inline_termination(cs);
> +
> + return cs;
> +}
> +
> +static u32 *pxp_emit_wait(u32 *cs)
> +{
> + /* wait for cmds to go through */
> + *cs++ = MFX_WAIT_PXP;
> + *cs++ = 0;
> +
> + return cs;
> +}
> +
> +/*
> + * if we ever need to terminate more than one session, we can submit multiple
> + * selections and terminations back-to-back with a single wait at the end
> + */
> +#define SELECTION_LEN 10
> +#define TERMINATION_LEN 2
> +#define SESSION_TERMINATION_LEN(x) ((SELECTION_LEN + TERMINATION_LEN) * (x))
> +#define WAIT_LEN 2
I always ask myself if we don't have a better automatic way to count the entries
or why we don't keep the size near its function so it is easier to see...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> +static void pxp_request_commit(struct i915_request *rq)
> +{
> + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX };
> + struct intel_timeline * const tl = i915_request_timeline(rq);
> +
> + lockdep_unpin_lock(&tl->mutex, rq->cookie);
> +
> + trace_i915_request_add(rq);
> + __i915_request_commit(rq);
> + __i915_request_queue(rq, &attr);
> +
> + mutex_unlock(&tl->mutex);
> +}
> +
> +int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 id)
> +{
> + struct i915_request *rq;
> + struct intel_context *ce = pxp->ce;
> + u32 *cs;
> + int err;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return 0;
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq))
> + return PTR_ERR(rq);
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err)
> + goto out_rq;
> + }
> +
> + cs = intel_ring_begin(rq, SESSION_TERMINATION_LEN(1) + WAIT_LEN);
> + if (IS_ERR(cs)) {
> + err = PTR_ERR(cs);
> + goto out_rq;
> + }
> +
> + cs = pxp_emit_session_termination(cs, id);
> + cs = pxp_emit_wait(cs);
> +
> + intel_ring_advance(rq, cs);
> +
> +out_rq:
> + i915_request_get(rq);
> +
> + if (unlikely(err))
> + i915_request_set_error_once(rq, err);
> +
> + pxp_request_commit(rq);
> +
> + if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
> + err = -ETIME;
> +
> + i915_request_put(rq);
> +
> + return err;
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> new file mode 100644
> index 000000000000..6d6299543578
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CMD_H__
> +#define __INTEL_PXP_CMD_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_pxp;
> +
> +int intel_pxp_terminate_session(struct intel_pxp *pxp, u32 idx);
> +
> +#endif /* __INTEL_PXP_CMD_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index 3331868f354c..b8e24adeb1f3 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -7,6 +7,7 @@
> #include "i915_drv.h"
>
> #include "intel_pxp.h"
> +#include "intel_pxp_cmd.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "intel_pxp_types.h"
> @@ -15,6 +16,9 @@
>
> #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
>
> +/* PXP global terminate register for session termination */
> +#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
> +
> static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> {
> struct intel_gt *gt = pxp_to_gt(pxp);
> @@ -72,3 +76,28 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
>
> return 0;
> }
> +
> +int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> + pxp->arb_is_valid = false;
> +
> + /* terminate the hw sessions */
> + ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to submit session termination\n");
> + return ret;
> + }
> +
> + ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
> + if (ret) {
> + drm_err(>->i915->drm, "Session state did not clear\n");
> + return ret;
> + }
> +
> + intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> index 316c3bebed9c..7354314b1cc4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> @@ -11,5 +11,6 @@
> struct intel_pxp;
>
> int intel_pxp_create_arb_session(struct intel_pxp *pxp);
> +int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp);
>
> #endif /* __INTEL_PXP_SESSION_H__ */
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-09 9:38 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
` (13 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang, Chris Wilson
From: "Huang, Sean Z" <sean.z.huang@intel.com>
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
Since the termination and re-creation flow is something we want to
trigger from the driver as well, use a common work function that can be
called both from the irq handler and from the driver set-up flows, which
has the addded benefit of allowing us to skip any extra locks because
the work itself serializes the operations.
v2: use struct completion instead of bool (Chris)
v3: drop locks, clean up functions and improve comments (Chris),
move to common work function.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 73 ++++++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 97 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 ++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 10 ++
11 files changed, 281 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 87a6145b4ae8..9e6e61aca95f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -274,6 +274,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 9fc6c912a4e5..7c4ec8880b1a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -232,6 +236,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbf7a60afe54..1fe42f4a4e4b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7969,6 +7969,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 2a5099034946..948b8153c8c9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include <linux/workqueue.h>
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
@@ -66,6 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ /*
+ * we'll use the completion to check if there is a termination pending,
+ * so we start it as completed and we reinit it when a termination
+ * is triggered.
+ */
+ init_completion(&pxp->termination);
+ complete_all(&pxp->termination);
+
+ INIT_WORK(&pxp->session_work, intel_pxp_session_work);
+
ret = create_vcs_context(pxp);
if (ret)
return;
@@ -87,24 +99,75 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ pxp->arb_is_valid = false;
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
}
-void intel_pxp_init_hw(struct intel_pxp *pxp)
+void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp)
+{
+ pxp->arb_is_valid = false;
+ reinit_completion(&pxp->termination);
+}
+
+static void intel_pxp_queue_termination(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ /*
+ * We want to get the same effect as if we received a termination
+ * interrupt, so just pretend that we did.
+ */
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_mark_termination_in_progress(pxp);
+ pxp->session_events |= PXP_TERMINATION_REQUEST;
+ queue_work(system_unbound_wq, &pxp->session_work);
+ spin_unlock_irq(>->irq_lock);
+}
+
+/*
+ * the arb session is restarted from the irq work when we receive the
+ * termination completion interrupt
+ */
+int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
{
int ret;
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ ret = wait_for_completion_timeout(&pxp->termination,
+ msecs_to_jiffies(100));
+
+ /* the wait returns 0 on failure */
+ if (ret)
+ ret = 0;
+ else
+ return -ETIMEDOUT;
+
+ if (!pxp->arb_is_valid)
+ return -EIO;
+
+ return 0;
+}
+
+void intel_pxp_init_hw(struct intel_pxp *pxp)
+{
kcr_pxp_enable(pxp_to_gt(pxp));
+ intel_pxp_irq_enable(pxp);
- /* always emit a full termination to clean the state */
- ret = intel_pxp_terminate_arb_session_and_global(pxp);
- if (!ret)
- intel_pxp_create_arb_session(pxp);
+ /*
+ * the session could've been attacked while we weren't loaded, so
+ * handle it as if it was and re-create it.
+ */
+ intel_pxp_queue_termination(pxp);
}
void intel_pxp_fini_hw(struct intel_pxp *pxp)
{
kcr_pxp_disable(pxp_to_gt(pxp));
+
+ intel_pxp_irq_disable(pxp);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 8eeb65af78b1..074b3b980957 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -30,6 +30,9 @@ void intel_pxp_fini(struct intel_pxp *pxp);
void intel_pxp_init_hw(struct intel_pxp *pxp);
void intel_pxp_fini_hw(struct intel_pxp *pxp);
+
+void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
+int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
{
@@ -38,6 +41,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_fini(struct intel_pxp *pxp)
{
}
+
+static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
+{
+ return 0;
+}
#endif
#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
new file mode 100644
index 000000000000..196449243515
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include <linux/workqueue.h>
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_session.h"
+#include "gt/intel_gt_irq.h"
+#include "i915_irq.h"
+#include "i915_reg.h"
+
+/**
+ * intel_pxp_irq_handler - Handles PXP interrupts.
+ * @pxp: pointer to pxp struct
+ * @iir: interrupt vector
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp)))
+ return;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!iir))
+ return;
+
+ if (iir & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT |
+ GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) {
+ /* immediately mark PXP as inactive on termination */
+ intel_pxp_mark_termination_in_progress(pxp);
+ pxp->session_events |= PXP_TERMINATION_REQUEST;
+ }
+
+ if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
+ pxp->session_events |= PXP_TERMINATION_COMPLETE;
+
+ if (pxp->session_events)
+ queue_work(system_unbound_wq, &pxp->session_work);
+}
+
+static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ const u32 mask = interrupts << 16;
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, mask);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~mask);
+}
+
+static inline void pxp_irq_reset(struct intel_gt *gt)
+{
+ spin_lock_irq(>->irq_lock);
+ gen11_gt_reset_one_iir(gt, 0, GEN11_KCR);
+ spin_unlock_irq(>->irq_lock);
+}
+
+void intel_pxp_irq_enable(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ if (!pxp->irq_enabled) {
+ WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+ }
+ spin_unlock_irq(>->irq_lock);
+}
+
+void intel_pxp_irq_disable(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ /*
+ * We always need to submit a global termination when we re-enable the
+ * interrupts, so there is no need to make sure that the session state
+ * makes sense at the end of this function. Just make sure this is not
+ * called in a path were the driver consider the session as valid and
+ * doesn't call a termination on restart.
+ */
+ GEM_WARN_ON(intel_pxp_is_active(pxp));
+
+ spin_lock_irq(>->irq_lock);
+
+ pxp->irq_enabled = false;
+ __pxp_set_interrupts(gt, 0);
+
+ spin_unlock_irq(>->irq_lock);
+ intel_synchronize_irq(gt->i915);
+
+ pxp_irq_reset(gt);
+
+ flush_work(&pxp->session_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
new file mode 100644
index 000000000000..8b5793654844
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_IRQ_H__
+#define __INTEL_PXP_IRQ_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+#define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1)
+#define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2)
+#define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3)
+
+#define GEN12_PXP_INTERRUPTS \
+ (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | \
+ GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT | \
+ GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_enable(struct intel_pxp *pxp);
+void intel_pxp_irq_disable(struct intel_pxp *pxp);
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+#else
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_IRQ_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index b8e24adeb1f3..e751122cb24a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -48,7 +48,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla
return ret;
}
-int intel_pxp_create_arb_session(struct intel_pxp *pxp)
+static int pxp_create_arb_session(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
int ret;
@@ -77,12 +77,13 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
return 0;
}
-int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
+static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
{
int ret;
struct intel_gt *gt = pxp_to_gt(pxp);
- pxp->arb_is_valid = false;
+ /* must mark termination in progress calling this function */
+ GEM_WARN_ON(pxp->arb_is_valid);
/* terminate the hw sessions */
ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
@@ -101,3 +102,50 @@ int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
return ret;
}
+
+static void pxp_terminate(struct intel_pxp *pxp)
+{
+ int ret;
+
+ pxp->global_state_attacked = true;
+
+ /*
+ * if we fail to submit the termination there is no point in waiting for
+ * it to complete. PXP will be marked as non-active until the next
+ * termination is issued.
+ */
+ ret = pxp_terminate_arb_session_and_global(pxp);
+ if (ret)
+ complete_all(&pxp->termination);
+}
+
+static void pxp_terminate_complete(struct intel_pxp *pxp)
+{
+ /* Re-create the arb session after teardown handle complete */
+ if (fetch_and_zero(&pxp->global_state_attacked))
+ pxp_create_arb_session(pxp);
+
+ complete_all(&pxp->termination);
+}
+
+void intel_pxp_session_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), session_work);
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->session_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (!events)
+ return;
+
+ if (events & PXP_TERMINATION_REQUEST) {
+ events &= ~PXP_TERMINATION_COMPLETE;
+ pxp_terminate(pxp);
+ }
+
+ if (events & PXP_TERMINATION_COMPLETE)
+ pxp_terminate_complete(pxp);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
index 7354314b1cc4..ba4c9d2b94b7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
@@ -8,9 +8,8 @@
#include <linux/types.h>
-struct intel_pxp;
+struct work_struct;
-int intel_pxp_create_arb_session(struct intel_pxp *pxp);
-int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp);
+void intel_pxp_session_work(struct work_struct *work);
#endif /* __INTEL_PXP_SESSION_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 170dd9fa5bb2..6d82531af11c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -89,21 +89,21 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
{
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+ int ret;
pxp->pxp_component = data;
pxp->pxp_component->tee_dev = tee_kdev;
/* the component is required to fully start the PXP HW */
intel_pxp_init_hw(pxp);
-
- if (!pxp->arb_is_valid) {
+ ret = intel_pxp_wait_for_arb_start(pxp);
+ if (ret) {
drm_err(&i915->drm, "Failed to create arb session during bind\n");
intel_pxp_fini_hw(pxp);
pxp->pxp_component = NULL;
- return -EIO;
}
- return 0;
+ return ret;
}
static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index b142b8170266..6c9265fb8e4b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -6,8 +6,10 @@
#ifndef __INTEL_PXP_TYPES_H__
#define __INTEL_PXP_TYPES_H__
+#include <linux/completion.h>
#include <linux/types.h>
#include <linux/mutex.h>
+#include <linux/workqueue.h>
struct intel_context;
struct i915_pxp_component;
@@ -23,6 +25,14 @@ struct intel_pxp {
* session to know if it's valid and need to track the status in SW.
*/
bool arb_is_valid;
+ bool global_state_attacked;
+ bool irq_enabled;
+ struct completion termination;
+
+ struct work_struct session_work;
+ u32 session_events; /* protected with gt->irq_lock */
+#define PXP_TERMINATION_REQUEST BIT(0)
+#define PXP_TERMINATION_COMPLETE BIT(1)
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
@ 2021-04-09 9:38 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-09 9:38 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Huang, Sean Z, Chris Wilson
On Sun, Mar 28, 2021 at 03:57:01PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
> which point it is safe to re-create the session.
>
> Since the termination and re-creation flow is something we want to
> trigger from the driver as well, use a common work function that can be
> called both from the irq handler and from the driver set-up flows, which
> has the addded benefit of allowing us to skip any extra locks because
> the work itself serializes the operations.
>
> v2: use struct completion instead of bool (Chris)
> v3: drop locks, clean up functions and improve comments (Chris),
> move to common work function.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 73 ++++++++++++++-
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 97 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 ++++++++++-
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 10 ++
> 11 files changed, 281 insertions(+), 15 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 87a6145b4ae8..9e6e61aca95f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -274,6 +274,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> + pxp/intel_pxp_irq.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 9fc6c912a4e5..7c4ec8880b1a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp_irq.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(>->pxp, iir);
> +
> WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> instance, iir);
> }
> @@ -232,6 +236,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
> +
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
> }
>
> void gen11_gt_irq_postinstall(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cbf7a60afe54..1fe42f4a4e4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7969,6 +7969,7 @@ enum {
> /* irq instances for OTHER_CLASS */
> #define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> +#define OTHER_KCR_INSTANCE 4
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 2a5099034946..948b8153c8c9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -2,7 +2,9 @@
> /*
> * Copyright(c) 2020 Intel Corporation.
> */
> +#include <linux/workqueue.h>
> #include "intel_pxp.h"
> +#include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> @@ -66,6 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (!HAS_PXP(gt->i915))
> return;
>
> + /*
> + * we'll use the completion to check if there is a termination pending,
> + * so we start it as completed and we reinit it when a termination
> + * is triggered.
> + */
> + init_completion(&pxp->termination);
> + complete_all(&pxp->termination);
> +
> + INIT_WORK(&pxp->session_work, intel_pxp_session_work);
> +
> ret = create_vcs_context(pxp);
> if (ret)
> return;
> @@ -87,24 +99,75 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + pxp->arb_is_valid = false;
oh! this should be part of the patch introducing this variable, no?!
> +
> intel_pxp_tee_component_fini(pxp);
>
> destroy_vcs_context(pxp);
> }
>
> -void intel_pxp_init_hw(struct intel_pxp *pxp)
> +void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp)
> +{
> + pxp->arb_is_valid = false;
> + reinit_completion(&pxp->termination);
> +}
> +
> +static void intel_pxp_queue_termination(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> + /*
> + * We want to get the same effect as if we received a termination
> + * interrupt, so just pretend that we did.
> + */
> + spin_lock_irq(>->irq_lock);
> + intel_pxp_mark_termination_in_progress(pxp);
> + pxp->session_events |= PXP_TERMINATION_REQUEST;
> + queue_work(system_unbound_wq, &pxp->session_work);
> + spin_unlock_irq(>->irq_lock);
> +}
> +
> +/*
> + * the arb session is restarted from the irq work when we receive the
> + * termination completion interrupt
> + */
> +int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> {
> int ret;
>
> + if (!intel_pxp_is_enabled(pxp))
> + return 0;
> +
> + ret = wait_for_completion_timeout(&pxp->termination,
> + msecs_to_jiffies(100));
> +
> + /* the wait returns 0 on failure */
instead of justifying, why not simply
if (!wait_for_completion_timeout(&pxp->termination,
msecs_to_jiffies(100)))
return -ETIMEDOUT;
?!
> + if (ret)
> + ret = 0;
> + else
> + return -ETIMEDOUT;
> +
> + if (!pxp->arb_is_valid)
> + return -EIO;
> +
> + return 0;
> +}
> +
> +void intel_pxp_init_hw(struct intel_pxp *pxp)
> +{
> kcr_pxp_enable(pxp_to_gt(pxp));
> + intel_pxp_irq_enable(pxp);
>
> - /* always emit a full termination to clean the state */
> - ret = intel_pxp_terminate_arb_session_and_global(pxp);
> - if (!ret)
> - intel_pxp_create_arb_session(pxp);
> + /*
> + * the session could've been attacked while we weren't loaded, so
> + * handle it as if it was and re-create it.
> + */
> + intel_pxp_queue_termination(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> {
> kcr_pxp_disable(pxp_to_gt(pxp));
> +
> + intel_pxp_irq_disable(pxp);
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 8eeb65af78b1..074b3b980957 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -30,6 +30,9 @@ void intel_pxp_fini(struct intel_pxp *pxp);
>
> void intel_pxp_init_hw(struct intel_pxp *pxp);
> void intel_pxp_fini_hw(struct intel_pxp *pxp);
> +
> +void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> +int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> @@ -38,6 +41,11 @@ static inline void intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_fini(struct intel_pxp *pxp)
> {
> }
> +
> +static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> #endif
>
> #endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> new file mode 100644
> index 000000000000..196449243515
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include <linux/workqueue.h>
> +#include "intel_pxp.h"
> +#include "intel_pxp_irq.h"
> +#include "intel_pxp_session.h"
> +#include "gt/intel_gt_irq.h"
> +#include "i915_irq.h"
> +#include "i915_reg.h"
> +
> +/**
> + * intel_pxp_irq_handler - Handles PXP interrupts.
> + * @pxp: pointer to pxp struct
> + * @iir: interrupt vector
> + */
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> + if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp)))
> + return;
> +
> + lockdep_assert_held(>->irq_lock);
> +
> + if (unlikely(!iir))
> + return;
> +
> + if (iir & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT |
> + GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) {
> + /* immediately mark PXP as inactive on termination */
> + intel_pxp_mark_termination_in_progress(pxp);
> + pxp->session_events |= PXP_TERMINATION_REQUEST;
> + }
> +
> + if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
> + pxp->session_events |= PXP_TERMINATION_COMPLETE;
> +
> + if (pxp->session_events)
> + queue_work(system_unbound_wq, &pxp->session_work);
> +}
> +
> +static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)
> +{
> + struct intel_uncore *uncore = gt->uncore;
> + const u32 mask = interrupts << 16;
> +
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, mask);
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~mask);
> +}
> +
> +static inline void pxp_irq_reset(struct intel_gt *gt)
> +{
> + spin_lock_irq(>->irq_lock);
> + gen11_gt_reset_one_iir(gt, 0, GEN11_KCR);
> + spin_unlock_irq(>->irq_lock);
> +}
> +
> +void intel_pxp_irq_enable(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> + spin_lock_irq(>->irq_lock);
> + if (!pxp->irq_enabled) {
> + WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
> + __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
> + pxp->irq_enabled = true;
> + }
> + spin_unlock_irq(>->irq_lock);
> +}
> +
> +void intel_pxp_irq_disable(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> + /*
> + * We always need to submit a global termination when we re-enable the
> + * interrupts, so there is no need to make sure that the session state
> + * makes sense at the end of this function. Just make sure this is not
> + * called in a path were the driver consider the session as valid and
> + * doesn't call a termination on restart.
> + */
> + GEM_WARN_ON(intel_pxp_is_active(pxp));
> +
> + spin_lock_irq(>->irq_lock);
> +
> + pxp->irq_enabled = false;
> + __pxp_set_interrupts(gt, 0);
> +
> + spin_unlock_irq(>->irq_lock);
> + intel_synchronize_irq(gt->i915);
> +
> + pxp_irq_reset(gt);
> +
> + flush_work(&pxp->session_work);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
> new file mode 100644
> index 000000000000..8b5793654844
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_IRQ_H__
> +#define __INTEL_PXP_IRQ_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_pxp;
> +
> +#define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1)
> +#define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2)
> +#define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3)
> +
> +#define GEN12_PXP_INTERRUPTS \
> + (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | \
> + GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT | \
> + GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_irq_enable(struct intel_pxp *pxp);
> +void intel_pxp_irq_disable(struct intel_pxp *pxp);
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
> +#else
> +static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_IRQ_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index b8e24adeb1f3..e751122cb24a 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -48,7 +48,7 @@ static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_pla
> return ret;
> }
>
> -int intel_pxp_create_arb_session(struct intel_pxp *pxp)
> +static int pxp_create_arb_session(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = pxp_to_gt(pxp);
> int ret;
> @@ -77,12 +77,13 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
> return 0;
> }
>
> -int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> +static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> {
> int ret;
> struct intel_gt *gt = pxp_to_gt(pxp);
>
> - pxp->arb_is_valid = false;
> + /* must mark termination in progress calling this function */
> + GEM_WARN_ON(pxp->arb_is_valid);
>
> /* terminate the hw sessions */
> ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> @@ -101,3 +102,50 @@ int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
>
> return ret;
> }
> +
> +static void pxp_terminate(struct intel_pxp *pxp)
> +{
> + int ret;
> +
> + pxp->global_state_attacked = true;
> +
> + /*
> + * if we fail to submit the termination there is no point in waiting for
> + * it to complete. PXP will be marked as non-active until the next
> + * termination is issued.
> + */
> + ret = pxp_terminate_arb_session_and_global(pxp);
> + if (ret)
> + complete_all(&pxp->termination);
> +}
> +
> +static void pxp_terminate_complete(struct intel_pxp *pxp)
> +{
> + /* Re-create the arb session after teardown handle complete */
> + if (fetch_and_zero(&pxp->global_state_attacked))
> + pxp_create_arb_session(pxp);
> +
> + complete_all(&pxp->termination);
> +}
> +
> +void intel_pxp_session_work(struct work_struct *work)
> +{
> + struct intel_pxp *pxp = container_of(work, typeof(*pxp), session_work);
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + u32 events = 0;
> +
> + spin_lock_irq(>->irq_lock);
> + events = fetch_and_zero(&pxp->session_events);
> + spin_unlock_irq(>->irq_lock);
> +
> + if (!events)
> + return;
> +
> + if (events & PXP_TERMINATION_REQUEST) {
> + events &= ~PXP_TERMINATION_COMPLETE;
> + pxp_terminate(pxp);
> + }
> +
> + if (events & PXP_TERMINATION_COMPLETE)
> + pxp_terminate_complete(pxp);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> index 7354314b1cc4..ba4c9d2b94b7 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> @@ -8,9 +8,8 @@
>
> #include <linux/types.h>
>
> -struct intel_pxp;
> +struct work_struct;
>
> -int intel_pxp_create_arb_session(struct intel_pxp *pxp);
> -int intel_pxp_terminate_arb_session_and_global(struct intel_pxp *pxp);
> +void intel_pxp_session_work(struct work_struct *work);
>
> #endif /* __INTEL_PXP_SESSION_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 170dd9fa5bb2..6d82531af11c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -89,21 +89,21 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> {
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> + int ret;
>
> pxp->pxp_component = data;
> pxp->pxp_component->tee_dev = tee_kdev;
>
> /* the component is required to fully start the PXP HW */
> intel_pxp_init_hw(pxp);
> -
> - if (!pxp->arb_is_valid) {
> + ret = intel_pxp_wait_for_arb_start(pxp);
> + if (ret) {
> drm_err(&i915->drm, "Failed to create arb session during bind\n");
> intel_pxp_fini_hw(pxp);
> pxp->pxp_component = NULL;
> - return -EIO;
> }
>
> - return 0;
> + return ret;
> }
>
> static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index b142b8170266..6c9265fb8e4b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -6,8 +6,10 @@
> #ifndef __INTEL_PXP_TYPES_H__
> #define __INTEL_PXP_TYPES_H__
>
> +#include <linux/completion.h>
> #include <linux/types.h>
> #include <linux/mutex.h>
> +#include <linux/workqueue.h>
>
> struct intel_context;
> struct i915_pxp_component;
> @@ -23,6 +25,14 @@ struct intel_pxp {
> * session to know if it's valid and need to track the status in SW.
> */
> bool arb_is_valid;
> + bool global_state_attacked;
could you please describe a bit more about the attacked case?
I missed the attacked = false on this patch, but also looking at
the final result, to me it is strange that we set true on termination
and false only on suspend... So I'm afraid I didn't fully understand this flow.
Thanks,
Rodrigo.
> + bool irq_enabled;
> + struct completion termination;
> +
> + struct work_struct session_work;
> + u32 session_events; /* protected with gt->irq_lock */
> +#define PXP_TERMINATION_REQUEST BIT(0)
> +#define PXP_TERMINATION_COMPLETE BIT(1)
> };
>
> #endif /* __INTEL_PXP_TYPES_H__ */
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-20 14:31 ` Rodrigo Vivi
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
` (12 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang, Chris Wilson
From: "Huang, Sean Z" <sean.z.huang@intel.com>
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should unconditionally terminate the hardware
sessions and cleanup all the software states after the power cycle.
v2: runtime suspend also invalidates the keys
v3: fix return codes, simplify rpm ops (Chris), use the new worker func
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 14 +++++++-
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 11 +++---
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 37 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 ++++++++++++++------
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +++++
8 files changed, 119 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9e6e61aca95f..f6d7e11e0e90 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -275,6 +275,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_irq.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index aef3084e8b16..9ed8c17dda0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -265,6 +266,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -299,6 +302,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
@@ -349,6 +353,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
void intel_gt_runtime_suspend(struct intel_gt *gt)
{
+ intel_pxp_suspend(>->pxp);
intel_uc_runtime_suspend(>->uc);
GT_TRACE(gt, "\n");
@@ -356,11 +361,18 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
int intel_gt_runtime_resume(struct intel_gt *gt)
{
+ int ret;
+
GT_TRACE(gt, "\n");
intel_gt_init_swizzling(gt);
intel_ggtt_restore_fences(gt->ggtt);
- return intel_uc_runtime_resume(>->uc);
+ ret = intel_uc_runtime_resume(>->uc);
+
+ if (!ret)
+ intel_pxp_resume(>->pxp);
+
+ return ret;
}
static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b2018e85afc2..02d5b2b6ee39 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -67,6 +67,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 196449243515..2a58ce1fa788 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -9,6 +9,7 @@
#include "gt/intel_gt_irq.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_runtime_pm.h"
/**
* intel_pxp_irq_handler - Handles PXP interrupts.
@@ -62,11 +63,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
struct intel_gt *gt = pxp_to_gt(pxp);
spin_lock_irq(>->irq_lock);
- if (!pxp->irq_enabled) {
+
+ if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
- __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
- pxp->irq_enabled = true;
- }
+
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+
spin_unlock_irq(>->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..bd2a8d550419
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_pm.h"
+#include "intel_pxp_session.h"
+
+void intel_pxp_suspend(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ pxp->arb_is_valid = false;
+
+ intel_pxp_fini_hw(pxp);
+
+ pxp->global_state_attacked = false;
+}
+
+void intel_pxp_resume(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ /*
+ * The PXP component gets automatically unbound when we go into S3 and
+ * re-bound after we come out, so in that scenario we can defer the
+ * termination and re-creation of the arb session to the bind call.
+ */
+ if (!pxp->pxp_component)
+ return;
+
+ intel_pxp_init_hw(pxp);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..6f488789db6a
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_suspend(struct intel_pxp *pxp);
+void intel_pxp_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_suspend(struct intel_pxp *pxp)
+{
+}
+static inline void intel_pxp_resume(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index e751122cb24a..ef7c891cef14 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -21,29 +21,36 @@
static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
{
- struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore;
intel_wakeref_t wakeref;
u32 sip = 0;
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ /* if we're suspended the session is considered off */
+ with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
+ sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
return sip & BIT(id);
}
static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
{
- struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore;
intel_wakeref_t wakeref;
u32 mask = BIT(id);
int ret;
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- ret = intel_wait_for_register(gt->uncore,
- GEN12_KCR_SIP,
- mask,
- in_play ? mask : 0,
- 100);
+ /* if we're suspended the session is considered off */
+ wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
+ if (!wakeref)
+ return in_play ? -ENODEV : 0;
+
+ ret = intel_wait_for_register(uncore,
+ GEN12_KCR_SIP,
+ mask,
+ in_play ? mask : 0,
+ 100);
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
return ret;
}
@@ -132,6 +139,7 @@ void intel_pxp_session_work(struct work_struct *work)
{
struct intel_pxp *pxp = container_of(work, typeof(*pxp), session_work);
struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
u32 events = 0;
spin_lock_irq(>->irq_lock);
@@ -141,6 +149,14 @@ void intel_pxp_session_work(struct work_struct *work)
if (!events)
return;
+ /*
+ * If we're processing an event while suspending then don't bother,
+ * we're going to re-init everything on resume anyway.
+ */
+ wakeref = intel_runtime_pm_get_if_in_use(gt->uncore->rpm);
+ if (!wakeref)
+ return;
+
if (events & PXP_TERMINATION_REQUEST) {
events &= ~PXP_TERMINATION_COMPLETE;
pxp_terminate(pxp);
@@ -148,4 +164,6 @@ void intel_pxp_session_work(struct work_struct *work)
if (events & PXP_TERMINATION_COMPLETE)
pxp_terminate_complete(pxp);
+
+ intel_runtime_pm_put(gt->uncore->rpm, wakeref);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 6d82531af11c..524a4c83179a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -89,11 +89,17 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
{
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
+ intel_wakeref_t wakeref;
int ret;
pxp->pxp_component = data;
pxp->pxp_component->tee_dev = tee_kdev;
+ /* if we are suspended, the HW will be re-initialized on resume */
+ wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm);
+ if (!wakeref)
+ return 0;
+
/* the component is required to fully start the PXP HW */
intel_pxp_init_hw(pxp);
ret = intel_pxp_wait_for_arb_start(pxp);
@@ -103,6 +109,8 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
pxp->pxp_component = NULL;
}
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
return ret;
}
--
2.29.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
@ 2021-04-20 14:31 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-20 14:31 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Huang, Sean Z, Chris Wilson
On Sun, Mar 28, 2021 at 03:57:02PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> During the power event S3+ sleep/resume, hardware will lose all the
> encryption keys for every hardware session, even though the
> software session state was marked as alive after resume. So to
> handle such case, PXP should unconditionally terminate the hardware
> sessions and cleanup all the software states after the power cycle.
>
> v2: runtime suspend also invalidates the keys
> v3: fix return codes, simplify rpm ops (Chris), use the new worker func
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 14 +++++++-
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 11 +++---
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 37 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 ++++++++++++++------
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +++++
> 8 files changed, 119 insertions(+), 15 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9e6e61aca95f..f6d7e11e0e90 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -275,6 +275,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_irq.o \
> + pxp/intel_pxp_pm.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index aef3084e8b16..9ed8c17dda0d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -19,6 +19,7 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_pm.h"
>
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> @@ -265,6 +266,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> intel_uc_resume(>->uc);
>
> + intel_pxp_resume(>->pxp);
> +
> user_forcewake(gt, false);
>
> out_fw:
> @@ -299,6 +302,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> user_forcewake(gt, true);
> wait_for_suspend(gt);
>
> + intel_pxp_suspend(>->pxp);
> intel_uc_suspend(>->uc);
> }
>
> @@ -349,6 +353,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
>
> void intel_gt_runtime_suspend(struct intel_gt *gt)
> {
> + intel_pxp_suspend(>->pxp);
> intel_uc_runtime_suspend(>->uc);
>
> GT_TRACE(gt, "\n");
> @@ -356,11 +361,18 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
>
> int intel_gt_runtime_resume(struct intel_gt *gt)
> {
> + int ret;
> +
> GT_TRACE(gt, "\n");
> intel_gt_init_swizzling(gt);
> intel_ggtt_restore_fences(gt->ggtt);
>
> - return intel_uc_runtime_resume(>->uc);
> + ret = intel_uc_runtime_resume(>->uc);
> +
> + if (!ret)
> + intel_pxp_resume(>->pxp);
nip: I'd prefer to go like most of places and if (!ret) return ret;
> +
> + return ret;
> }
>
> static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b2018e85afc2..02d5b2b6ee39 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -67,6 +67,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
>
> +#include "pxp/intel_pxp_pm.h"
> +
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> #include "i915_ioc32.h"
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> index 196449243515..2a58ce1fa788 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> @@ -9,6 +9,7 @@
> #include "gt/intel_gt_irq.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_runtime_pm.h"
>
> /**
> * intel_pxp_irq_handler - Handles PXP interrupts.
> @@ -62,11 +63,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
> struct intel_gt *gt = pxp_to_gt(pxp);
>
> spin_lock_irq(>->irq_lock);
> - if (!pxp->irq_enabled) {
> +
> + if (!pxp->irq_enabled)
> WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
> - __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
> - pxp->irq_enabled = true;
> - }
> +
> + __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
> + pxp->irq_enabled = true;
> +
> spin_unlock_irq(>->irq_lock);
> }
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> new file mode 100644
> index 000000000000..bd2a8d550419
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_irq.h"
> +#include "intel_pxp_pm.h"
> +#include "intel_pxp_session.h"
> +
> +void intel_pxp_suspend(struct intel_pxp *pxp)
> +{
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + pxp->arb_is_valid = false;
> +
> + intel_pxp_fini_hw(pxp);
> +
> + pxp->global_state_attacked = false;
> +}
> +
> +void intel_pxp_resume(struct intel_pxp *pxp)
> +{
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + /*
> + * The PXP component gets automatically unbound when we go into S3 and
> + * re-bound after we come out, so in that scenario we can defer the
> + * termination and re-creation of the arb session to the bind call.
> + */
> + if (!pxp->pxp_component)
> + return;
> +
> + intel_pxp_init_hw(pxp);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> new file mode 100644
> index 000000000000..6f488789db6a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_PM_H__
> +#define __INTEL_PXP_PM_H__
> +
> +#include "i915_drv.h"
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_suspend(struct intel_pxp *pxp);
> +void intel_pxp_resume(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_suspend(struct intel_pxp *pxp)
> +{
> +}
> +static inline void intel_pxp_resume(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index e751122cb24a..ef7c891cef14 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -21,29 +21,36 @@
>
> static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> {
> - struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore;
> intel_wakeref_t wakeref;
> u32 sip = 0;
>
> - with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
> + /* if we're suspended the session is considered off */
> + with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref)
> + sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
>
> return sip & BIT(id);
> }
>
> static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
> {
> - struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_uncore *uncore = pxp_to_gt(pxp)->uncore;
> intel_wakeref_t wakeref;
> u32 mask = BIT(id);
> int ret;
>
> - with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - ret = intel_wait_for_register(gt->uncore,
> - GEN12_KCR_SIP,
> - mask,
> - in_play ? mask : 0,
> - 100);
> + /* if we're suspended the session is considered off */
> + wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
> + if (!wakeref)
> + return in_play ? -ENODEV : 0;
> +
> + ret = intel_wait_for_register(uncore,
> + GEN12_KCR_SIP,
> + mask,
> + in_play ? mask : 0,
> + 100);
> +
> + intel_runtime_pm_put(uncore->rpm, wakeref);
>
> return ret;
> }
> @@ -132,6 +139,7 @@ void intel_pxp_session_work(struct work_struct *work)
> {
> struct intel_pxp *pxp = container_of(work, typeof(*pxp), session_work);
> struct intel_gt *gt = pxp_to_gt(pxp);
> + intel_wakeref_t wakeref;
> u32 events = 0;
>
> spin_lock_irq(>->irq_lock);
> @@ -141,6 +149,14 @@ void intel_pxp_session_work(struct work_struct *work)
> if (!events)
> return;
>
> + /*
> + * If we're processing an event while suspending then don't bother,
> + * we're going to re-init everything on resume anyway.
> + */
> + wakeref = intel_runtime_pm_get_if_in_use(gt->uncore->rpm);
> + if (!wakeref)
> + return;
> +
> if (events & PXP_TERMINATION_REQUEST) {
> events &= ~PXP_TERMINATION_COMPLETE;
> pxp_terminate(pxp);
> @@ -148,4 +164,6 @@ void intel_pxp_session_work(struct work_struct *work)
>
> if (events & PXP_TERMINATION_COMPLETE)
> pxp_terminate_complete(pxp);
> +
> + intel_runtime_pm_put(gt->uncore->rpm, wakeref);
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index 6d82531af11c..524a4c83179a 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -89,11 +89,17 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> {
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> + intel_wakeref_t wakeref;
> int ret;
>
> pxp->pxp_component = data;
> pxp->pxp_component->tee_dev = tee_kdev;
>
> + /* if we are suspended, the HW will be re-initialized on resume */
> + wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm);
> + if (!wakeref)
> + return 0;
> +
> /* the component is required to fully start the PXP HW */
> intel_pxp_init_hw(pxp);
> ret = intel_pxp_wait_for_arb_start(pxp);
> @@ -103,6 +109,8 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> pxp->pxp_component = NULL;
> }
>
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> +
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> return ret;
> }
>
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 10/16] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-01 12:06 ` Lionel Landwerlin
` (2 more replies)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
` (11 subsequent siblings)
22 siblings, 3 replies; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
Extra tracking and checks around protected objects, coming in a follow-up
patch, will be enabled only for contexts that opt in. Contexts can only be
marked as using protected content at creation time and they must be both
bannable and not recoverable.
When a PXP teardown occurs, all gem contexts marked this way that
have been used at least once will be marked as invalid and all new
submissions using them will be rejected. All intel contexts within the
invalidated gem contexts will be marked banned.
A new flag has been added to the RESET_STATS ioctl to report the
invalidation to userspace.
v2: split to its own patch and improve doc (Chris), invalidate contexts
on teardown
v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
context flag not mandatory in protected object execbuf to avoid
abuse (Lionel)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++++++++++++++++++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++++++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 ++++++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
include/uapi/drm/i915_drm.h | 26 ++++++++
8 files changed, 172 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fd8ee52e17a4..f3fd302682bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_gem_context.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -1972,6 +1974,40 @@ static int set_priority(struct i915_gem_context *ctx,
return 0;
}
+static int set_protected(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ int ret = 0;
+
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ ret = -ENODEV;
+ else if (ctx->file_priv) /* can't change this after creation! */
+ ret = -EEXIST;
+ else if (args->size)
+ ret = -EINVAL;
+ else if (!args->value)
+ clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ else if (i915_gem_context_is_recoverable(ctx) ||
+ !i915_gem_context_is_bannable(ctx))
+ ret = -EPERM;
+ else
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+
+ return ret;
+}
+
+static int get_protected(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ return -ENODEV;
+
+ args->size = 0;
+ args->value = i915_gem_context_uses_protected_content(ctx);
+
+ return 0;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -2004,6 +2040,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
ret = -EPERM;
else if (args->value)
i915_gem_context_set_bannable(ctx);
+ else if (i915_gem_context_uses_protected_content(ctx))
+ ret = -EPERM; /* can't clear this for protected contexts */
else
i915_gem_context_clear_bannable(ctx);
break;
@@ -2011,10 +2049,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
- else
+ else if (!args->value)
i915_gem_context_clear_recoverable(ctx);
+ else if (i915_gem_context_uses_protected_content(ctx))
+ ret = -EPERM; /* can't set this for protected contexts */
+ else
+ i915_gem_context_set_recoverable(ctx);
break;
case I915_CONTEXT_PARAM_PRIORITY:
@@ -2041,6 +2081,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
ret = set_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = set_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2494,6 +2538,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
ret = get_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = get_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2554,6 +2602,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
args->batch_active = atomic_read(&ctx->guilty_count);
args->batch_pending = atomic_read(&ctx->active_count);
+ /* re-use args->flags for output flags */
+ args->flags = 0;
+ if (i915_gem_context_invalidated(ctx))
+ args->flags |= I915_CONTEXT_INVALIDATED;
+
ret = 0;
out:
rcu_read_unlock();
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..169d3fb49252 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -108,6 +108,24 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
}
+static inline bool
+i915_gem_context_invalidated(const struct i915_gem_context *ctx)
+{
+ return test_bit(CONTEXT_INVALID, &ctx->flags);
+}
+
+static inline void
+i915_gem_context_set_invalid(struct i915_gem_context *ctx)
+{
+ set_bit(CONTEXT_INVALID, &ctx->flags);
+}
+
+static inline bool
+i915_gem_context_uses_protected_content(const struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
/* i915_gem_context.c */
void i915_gem_init__contexts(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 340473aa70de..a0f80475da05 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -134,6 +134,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
@@ -141,6 +142,7 @@ struct i915_gem_context {
unsigned long flags;
#define CONTEXT_CLOSED 0
#define CONTEXT_USER_ENGINES 1
+#define CONTEXT_INVALID 2
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5964e67c7d36..72c2470fcfe6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -21,6 +21,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
@@ -746,6 +748,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
if (unlikely(!ctx))
return -ENOENT;
+ if (i915_gem_context_invalidated(ctx)) {
+ i915_gem_context_put(ctx);
+ return -EACCES;
+ }
+
eb->gem_context = ctx;
if (rcu_access_pointer(ctx->vm))
eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
@@ -2940,6 +2947,17 @@ eb_select_engine(struct i915_execbuffer *eb)
intel_gt_pm_get(ce->engine->gt);
+ if (i915_gem_context_uses_protected_content(eb->gem_context)) {
+ err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
+ if (err)
+ goto err;
+
+ if (i915_gem_context_invalidated(eb->gem_context)) {
+ err = -EACCES;
+ goto err;
+ }
+ }
+
if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
err = intel_context_alloc_state(ce);
if (err)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 948b8153c8c9..cbc5249a1bf9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp_irq.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
+#include "gem/i915_gem_context.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -171,3 +172,50 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
intel_pxp_irq_disable(pxp);
}
+
+void intel_pxp_invalidate(struct intel_pxp *pxp)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_gem_context *ctx, *cn;
+
+ /* ban all contexts marked as protected */
+ spin_lock_irq(&i915->gem.contexts.lock);
+ list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ if (!kref_get_unless_zero(&ctx->ref))
+ continue;
+
+ if (likely(!i915_gem_context_uses_protected_content(ctx)) ||
+ i915_gem_context_invalidated(ctx)) {
+ i915_gem_context_put(ctx);
+ continue;
+ }
+
+ spin_unlock_irq(&i915->gem.contexts.lock);
+
+ /*
+ * Note that by the time we get here the HW keys are already
+ * long gone, so any batch using them that's already on the
+ * engines is very likely a lost cause (and it has probably
+ * already hung the engine). Therefore, we skip attempting to
+ * pull the running context out of the HW and we prioritize
+ * bringing the session back as soon as possible.
+ */
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ /* only invalidate if at least one ce was allocated */
+ if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ intel_context_set_banned(ce);
+ i915_gem_context_set_invalid(ctx);
+ }
+ }
+ i915_gem_context_unlock_engines(ctx);
+
+ spin_lock_irq(&i915->gem.contexts.lock);
+ list_safe_reset_next(ctx, cn, link);
+ i915_gem_context_put(ctx);
+ }
+ spin_unlock_irq(&i915->gem.contexts.lock);
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 074b3b980957..91c1a2056309 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -33,6 +33,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
+void intel_pxp_invalidate(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
{
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index ef7c891cef14..707c908acfcc 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -92,6 +92,9 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
/* must mark termination in progress calling this function */
GEM_WARN_ON(pxp->arb_is_valid);
+ /* invalidate protected objects */
+ intel_pxp_invalidate(pxp);
+
/* terminate the hw sessions */
ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
if (ret) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3dcb8fe64ccd..7a2088eccc9f 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1695,6 +1695,26 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Mark that the context makes use of protected content, which will result
+ * in the context being invalidated when the protected content session is.
+ * This flag can only be set at context creation time and, when set to true,
+ * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
+ * to false. This flag can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false.
+ *
+ * Given the numerous restriction on this flag, there are several unique
+ * failure cases:
+ *
+ * -ENODEV: feature not available
+ * -EEXIST: trying to modify an existing context
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ * -EACCES: submitting an invalidated context for execution
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -1925,6 +1945,12 @@ struct drm_i915_reg_read {
struct drm_i915_reset_stats {
__u32 ctx_id;
__u32 flags;
+ /*
+ * contexts marked as using protected content are invalidated when the
+ * protected content session dies. Submission of invalidated contexts
+ * is rejected with -EACCES.
+ */
+#define I915_CONTEXT_INVALIDATED 0x1
/* All resets since boot/module reload, for all contexts */
__u32 reset_count;
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
@ 2021-04-01 12:06 ` Lionel Landwerlin
2021-04-15 17:20 ` Daniel Vetter
2021-04-20 14:35 ` Rodrigo Vivi
2 siblings, 0 replies; 62+ messages in thread
From: Lionel Landwerlin @ 2021-04-01 12:06 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Chris Wilson
On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
> Extra tracking and checks around protected objects, coming in a follow-up
> patch, will be enabled only for contexts that opt in. Contexts can only be
> marked as using protected content at creation time and they must be both
> bannable and not recoverable.
>
> When a PXP teardown occurs, all gem contexts marked this way that
> have been used at least once will be marked as invalid and all new
> submissions using them will be rejected. All intel contexts within the
> invalidated gem contexts will be marked banned.
> A new flag has been added to the RESET_STATS ioctl to report the
> invalidation to userspace.
>
> v2: split to its own patch and improve doc (Chris), invalidate contexts
> on teardown
>
> v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
> context flag not mandatory in protected object execbuf to avoid
> abuse (Lionel)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
> include/uapi/drm/i915_drm.h | 26 ++++++++
> 8 files changed, 172 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index fd8ee52e17a4..f3fd302682bb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_globals.h"
> #include "i915_trace.h"
> @@ -1972,6 +1974,40 @@ static int set_priority(struct i915_gem_context *ctx,
> return 0;
> }
>
> +static int set_protected(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + int ret = 0;
> +
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + ret = -ENODEV;
> + else if (ctx->file_priv) /* can't change this after creation! */
> + ret = -EEXIST;
> + else if (args->size)
> + ret = -EINVAL;
> + else if (!args->value)
> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + else if (i915_gem_context_is_recoverable(ctx) ||
> + !i915_gem_context_is_bannable(ctx))
> + ret = -EPERM;
> + else
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +
> + return ret;
> +}
> +
> +static int get_protected(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + return -ENODEV;
> +
> + args->size = 0;
> + args->value = i915_gem_context_uses_protected_content(ctx);
> +
> + return 0;
> +}
> +
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> struct i915_gem_context *ctx,
> struct drm_i915_gem_context_param *args)
> @@ -2004,6 +2040,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = -EPERM;
> else if (args->value)
> i915_gem_context_set_bannable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't clear this for protected contexts */
> else
> i915_gem_context_clear_bannable(ctx);
> break;
> @@ -2011,10 +2049,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> - else
> + else if (!args->value)
> i915_gem_context_clear_recoverable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't set this for protected contexts */
> + else
> + i915_gem_context_set_recoverable(ctx);
> break;
>
> case I915_CONTEXT_PARAM_PRIORITY:
> @@ -2041,6 +2081,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = set_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2494,6 +2538,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> ret = get_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = get_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2554,6 +2602,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
> args->batch_active = atomic_read(&ctx->guilty_count);
> args->batch_pending = atomic_read(&ctx->active_count);
>
> + /* re-use args->flags for output flags */
> + args->flags = 0;
> + if (i915_gem_context_invalidated(ctx))
> + args->flags |= I915_CONTEXT_INVALIDATED;
> +
> ret = 0;
> out:
> rcu_read_unlock();
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..169d3fb49252 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -108,6 +108,24 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
> }
>
> +static inline bool
> +i915_gem_context_invalidated(const struct i915_gem_context *ctx)
> +{
> + return test_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline void
> +i915_gem_context_set_invalid(struct i915_gem_context *ctx)
> +{
> + set_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline bool
> +i915_gem_context_uses_protected_content(const struct i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 340473aa70de..a0f80475da05 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,6 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
>
> /**
> * @flags: small set of booleans
> @@ -141,6 +142,7 @@ struct i915_gem_context {
> unsigned long flags;
> #define CONTEXT_CLOSED 0
> #define CONTEXT_USER_ENGINES 1
> +#define CONTEXT_INVALID 2
>
> struct mutex mutex;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5964e67c7d36..72c2470fcfe6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -21,6 +21,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> @@ -746,6 +748,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
> if (unlikely(!ctx))
> return -ENOENT;
>
> + if (i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + return -EACCES;
> + }
> +
> eb->gem_context = ctx;
> if (rcu_access_pointer(ctx->vm))
> eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
> @@ -2940,6 +2947,17 @@ eb_select_engine(struct i915_execbuffer *eb)
>
> intel_gt_pm_get(ce->engine->gt);
>
> + if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> + err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> + if (err)
> + goto err;
> +
> + if (i915_gem_context_invalidated(eb->gem_context)) {
> + err = -EACCES;
> + goto err;
> + }
> + }
> +
> if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> err = intel_context_alloc_state(ce);
> if (err)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 948b8153c8c9..cbc5249a1bf9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -7,6 +7,7 @@
> #include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> +#include "gem/i915_gem_context.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -171,3 +172,50 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
>
> intel_pxp_irq_disable(pxp);
> }
> +
> +void intel_pxp_invalidate(struct intel_pxp *pxp)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct i915_gem_context *ctx, *cn;
> +
> + /* ban all contexts marked as protected */
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + if (!kref_get_unless_zero(&ctx->ref))
> + continue;
> +
> + if (likely(!i915_gem_context_uses_protected_content(ctx)) ||
> + i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + continue;
> + }
> +
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +
> + /*
> + * Note that by the time we get here the HW keys are already
> + * long gone, so any batch using them that's already on the
> + * engines is very likely a lost cause (and it has probably
> + * already hung the engine). Therefore, we skip attempting to
> + * pull the running context out of the HW and we prioritize
> + * bringing the session back as soon as possible.
> + */
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + /* only invalidate if at least one ce was allocated */
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + intel_context_set_banned(ce);
> + i915_gem_context_set_invalid(ctx);
> + }
> + }
> + i915_gem_context_unlock_engines(ctx);
> +
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_safe_reset_next(ctx, cn, link);
> + i915_gem_context_put(ctx);
> + }
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 074b3b980957..91c1a2056309 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -33,6 +33,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index ef7c891cef14..707c908acfcc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -92,6 +92,9 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> /* must mark termination in progress calling this function */
> GEM_WARN_ON(pxp->arb_is_valid);
>
> + /* invalidate protected objects */
> + intel_pxp_invalidate(pxp);
> +
> /* terminate the hw sessions */
> ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> if (ret) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 3dcb8fe64ccd..7a2088eccc9f 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1695,6 +1695,26 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Mark that the context makes use of protected content, which will result
> + * in the context being invalidated when the protected content session is.
> + * This flag can only be set at context creation time and, when set to true,
> + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
> + * to false. This flag can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + * -EACCES: submitting an invalidated context for execution
Should we also add at what point those error code apply?
-Lionel
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1925,6 +1945,12 @@ struct drm_i915_reg_read {
> struct drm_i915_reset_stats {
> __u32 ctx_id;
> __u32 flags;
> + /*
> + * contexts marked as using protected content are invalidated when the
> + * protected content session dies. Submission of invalidated contexts
> + * is rejected with -EACCES.
> + */
> +#define I915_CONTEXT_INVALIDATED 0x1
>
> /* All resets since boot/module reload, for all contexts */
> __u32 reset_count;
_______________________________________________
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
@ 2021-04-15 17:20 ` Daniel Vetter
2021-04-15 17:20 ` Daniel Vetter
2021-04-20 14:35 ` Rodrigo Vivi
2 siblings, 0 replies; 62+ messages in thread
From: Daniel Vetter @ 2021-04-15 17:20 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jason Ekstrand, dri-devel
Cc: Lionel Landwerlin, intel-gfx, Chris Wilson, Rodrigo Vivi
On Mon, Mar 29, 2021 at 12:58 AM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> Extra tracking and checks around protected objects, coming in a follow-up
> patch, will be enabled only for contexts that opt in. Contexts can only be
> marked as using protected content at creation time and they must be both
> bannable and not recoverable.
>
> When a PXP teardown occurs, all gem contexts marked this way that
> have been used at least once will be marked as invalid and all new
> submissions using them will be rejected. All intel contexts within the
> invalidated gem contexts will be marked banned.
> A new flag has been added to the RESET_STATS ioctl to report the
> invalidation to userspace.
>
> v2: split to its own patch and improve doc (Chris), invalidate contexts
> on teardown
>
> v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
> context flag not mandatory in protected object execbuf to avoid
> abuse (Lionel)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Same here, needs to be cc'ed to dri-devel. Also Jason is working on a
big cleanup of the context creation uapi, so needs coordination. Also
ping maintainers for awareness, not sure yet how to get this merged
with the branches we have (I forgot the maintainer ping on patch 12).
-Daniel
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
> include/uapi/drm/i915_drm.h | 26 ++++++++
> 8 files changed, 172 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index fd8ee52e17a4..f3fd302682bb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_globals.h"
> #include "i915_trace.h"
> @@ -1972,6 +1974,40 @@ static int set_priority(struct i915_gem_context *ctx,
> return 0;
> }
>
> +static int set_protected(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + int ret = 0;
> +
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + ret = -ENODEV;
> + else if (ctx->file_priv) /* can't change this after creation! */
> + ret = -EEXIST;
> + else if (args->size)
> + ret = -EINVAL;
> + else if (!args->value)
> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + else if (i915_gem_context_is_recoverable(ctx) ||
> + !i915_gem_context_is_bannable(ctx))
> + ret = -EPERM;
> + else
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +
> + return ret;
> +}
> +
> +static int get_protected(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + return -ENODEV;
> +
> + args->size = 0;
> + args->value = i915_gem_context_uses_protected_content(ctx);
> +
> + return 0;
> +}
> +
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> struct i915_gem_context *ctx,
> struct drm_i915_gem_context_param *args)
> @@ -2004,6 +2040,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = -EPERM;
> else if (args->value)
> i915_gem_context_set_bannable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't clear this for protected contexts */
> else
> i915_gem_context_clear_bannable(ctx);
> break;
> @@ -2011,10 +2049,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> - else
> + else if (!args->value)
> i915_gem_context_clear_recoverable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't set this for protected contexts */
> + else
> + i915_gem_context_set_recoverable(ctx);
> break;
>
> case I915_CONTEXT_PARAM_PRIORITY:
> @@ -2041,6 +2081,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = set_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2494,6 +2538,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> ret = get_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = get_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2554,6 +2602,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
> args->batch_active = atomic_read(&ctx->guilty_count);
> args->batch_pending = atomic_read(&ctx->active_count);
>
> + /* re-use args->flags for output flags */
> + args->flags = 0;
> + if (i915_gem_context_invalidated(ctx))
> + args->flags |= I915_CONTEXT_INVALIDATED;
> +
> ret = 0;
> out:
> rcu_read_unlock();
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..169d3fb49252 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -108,6 +108,24 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
> }
>
> +static inline bool
> +i915_gem_context_invalidated(const struct i915_gem_context *ctx)
> +{
> + return test_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline void
> +i915_gem_context_set_invalid(struct i915_gem_context *ctx)
> +{
> + set_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline bool
> +i915_gem_context_uses_protected_content(const struct i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 340473aa70de..a0f80475da05 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,6 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
>
> /**
> * @flags: small set of booleans
> @@ -141,6 +142,7 @@ struct i915_gem_context {
> unsigned long flags;
> #define CONTEXT_CLOSED 0
> #define CONTEXT_USER_ENGINES 1
> +#define CONTEXT_INVALID 2
>
> struct mutex mutex;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5964e67c7d36..72c2470fcfe6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -21,6 +21,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> @@ -746,6 +748,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
> if (unlikely(!ctx))
> return -ENOENT;
>
> + if (i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + return -EACCES;
> + }
> +
> eb->gem_context = ctx;
> if (rcu_access_pointer(ctx->vm))
> eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
> @@ -2940,6 +2947,17 @@ eb_select_engine(struct i915_execbuffer *eb)
>
> intel_gt_pm_get(ce->engine->gt);
>
> + if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> + err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> + if (err)
> + goto err;
> +
> + if (i915_gem_context_invalidated(eb->gem_context)) {
> + err = -EACCES;
> + goto err;
> + }
> + }
> +
> if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> err = intel_context_alloc_state(ce);
> if (err)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 948b8153c8c9..cbc5249a1bf9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -7,6 +7,7 @@
> #include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> +#include "gem/i915_gem_context.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -171,3 +172,50 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
>
> intel_pxp_irq_disable(pxp);
> }
> +
> +void intel_pxp_invalidate(struct intel_pxp *pxp)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct i915_gem_context *ctx, *cn;
> +
> + /* ban all contexts marked as protected */
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + if (!kref_get_unless_zero(&ctx->ref))
> + continue;
> +
> + if (likely(!i915_gem_context_uses_protected_content(ctx)) ||
> + i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + continue;
> + }
> +
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +
> + /*
> + * Note that by the time we get here the HW keys are already
> + * long gone, so any batch using them that's already on the
> + * engines is very likely a lost cause (and it has probably
> + * already hung the engine). Therefore, we skip attempting to
> + * pull the running context out of the HW and we prioritize
> + * bringing the session back as soon as possible.
> + */
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + /* only invalidate if at least one ce was allocated */
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + intel_context_set_banned(ce);
> + i915_gem_context_set_invalid(ctx);
> + }
> + }
> + i915_gem_context_unlock_engines(ctx);
> +
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_safe_reset_next(ctx, cn, link);
> + i915_gem_context_put(ctx);
> + }
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 074b3b980957..91c1a2056309 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -33,6 +33,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index ef7c891cef14..707c908acfcc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -92,6 +92,9 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> /* must mark termination in progress calling this function */
> GEM_WARN_ON(pxp->arb_is_valid);
>
> + /* invalidate protected objects */
> + intel_pxp_invalidate(pxp);
> +
> /* terminate the hw sessions */
> ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> if (ret) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 3dcb8fe64ccd..7a2088eccc9f 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1695,6 +1695,26 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Mark that the context makes use of protected content, which will result
> + * in the context being invalidated when the protected content session is.
> + * This flag can only be set at context creation time and, when set to true,
> + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
> + * to false. This flag can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + * -EACCES: submitting an invalidated context for execution
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1925,6 +1945,12 @@ struct drm_i915_reg_read {
> struct drm_i915_reset_stats {
> __u32 ctx_id;
> __u32 flags;
> + /*
> + * contexts marked as using protected content are invalidated when the
> + * protected content session dies. Submission of invalidated contexts
> + * is rejected with -EACCES.
> + */
> +#define I915_CONTEXT_INVALIDATED 0x1
>
> /* All resets since boot/module reload, for all contexts */
> __u32 reset_count;
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content
@ 2021-04-15 17:20 ` Daniel Vetter
0 siblings, 0 replies; 62+ messages in thread
From: Daniel Vetter @ 2021-04-15 17:20 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jason Ekstrand, dri-devel
Cc: Lionel Landwerlin, intel-gfx, Chris Wilson
On Mon, Mar 29, 2021 at 12:58 AM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> Extra tracking and checks around protected objects, coming in a follow-up
> patch, will be enabled only for contexts that opt in. Contexts can only be
> marked as using protected content at creation time and they must be both
> bannable and not recoverable.
>
> When a PXP teardown occurs, all gem contexts marked this way that
> have been used at least once will be marked as invalid and all new
> submissions using them will be rejected. All intel contexts within the
> invalidated gem contexts will be marked banned.
> A new flag has been added to the RESET_STATS ioctl to report the
> invalidation to userspace.
>
> v2: split to its own patch and improve doc (Chris), invalidate contexts
> on teardown
>
> v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
> context flag not mandatory in protected object execbuf to avoid
> abuse (Lionel)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Same here, needs to be cc'ed to dri-devel. Also Jason is working on a
big cleanup of the context creation uapi, so needs coordination. Also
ping maintainers for awareness, not sure yet how to get this merged
with the branches we have (I forgot the maintainer ping on patch 12).
-Daniel
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
> include/uapi/drm/i915_drm.h | 26 ++++++++
> 8 files changed, 172 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index fd8ee52e17a4..f3fd302682bb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_globals.h"
> #include "i915_trace.h"
> @@ -1972,6 +1974,40 @@ static int set_priority(struct i915_gem_context *ctx,
> return 0;
> }
>
> +static int set_protected(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + int ret = 0;
> +
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + ret = -ENODEV;
> + else if (ctx->file_priv) /* can't change this after creation! */
> + ret = -EEXIST;
> + else if (args->size)
> + ret = -EINVAL;
> + else if (!args->value)
> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + else if (i915_gem_context_is_recoverable(ctx) ||
> + !i915_gem_context_is_bannable(ctx))
> + ret = -EPERM;
> + else
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +
> + return ret;
> +}
> +
> +static int get_protected(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + return -ENODEV;
> +
> + args->size = 0;
> + args->value = i915_gem_context_uses_protected_content(ctx);
> +
> + return 0;
> +}
> +
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> struct i915_gem_context *ctx,
> struct drm_i915_gem_context_param *args)
> @@ -2004,6 +2040,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = -EPERM;
> else if (args->value)
> i915_gem_context_set_bannable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't clear this for protected contexts */
> else
> i915_gem_context_clear_bannable(ctx);
> break;
> @@ -2011,10 +2049,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> - else
> + else if (!args->value)
> i915_gem_context_clear_recoverable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't set this for protected contexts */
> + else
> + i915_gem_context_set_recoverable(ctx);
> break;
>
> case I915_CONTEXT_PARAM_PRIORITY:
> @@ -2041,6 +2081,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = set_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2494,6 +2538,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> ret = get_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = get_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2554,6 +2602,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
> args->batch_active = atomic_read(&ctx->guilty_count);
> args->batch_pending = atomic_read(&ctx->active_count);
>
> + /* re-use args->flags for output flags */
> + args->flags = 0;
> + if (i915_gem_context_invalidated(ctx))
> + args->flags |= I915_CONTEXT_INVALIDATED;
> +
> ret = 0;
> out:
> rcu_read_unlock();
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..169d3fb49252 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -108,6 +108,24 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
> }
>
> +static inline bool
> +i915_gem_context_invalidated(const struct i915_gem_context *ctx)
> +{
> + return test_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline void
> +i915_gem_context_set_invalid(struct i915_gem_context *ctx)
> +{
> + set_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline bool
> +i915_gem_context_uses_protected_content(const struct i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 340473aa70de..a0f80475da05 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,6 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
>
> /**
> * @flags: small set of booleans
> @@ -141,6 +142,7 @@ struct i915_gem_context {
> unsigned long flags;
> #define CONTEXT_CLOSED 0
> #define CONTEXT_USER_ENGINES 1
> +#define CONTEXT_INVALID 2
>
> struct mutex mutex;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5964e67c7d36..72c2470fcfe6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -21,6 +21,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> @@ -746,6 +748,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
> if (unlikely(!ctx))
> return -ENOENT;
>
> + if (i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + return -EACCES;
> + }
> +
> eb->gem_context = ctx;
> if (rcu_access_pointer(ctx->vm))
> eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
> @@ -2940,6 +2947,17 @@ eb_select_engine(struct i915_execbuffer *eb)
>
> intel_gt_pm_get(ce->engine->gt);
>
> + if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> + err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> + if (err)
> + goto err;
> +
> + if (i915_gem_context_invalidated(eb->gem_context)) {
> + err = -EACCES;
> + goto err;
> + }
> + }
> +
> if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> err = intel_context_alloc_state(ce);
> if (err)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 948b8153c8c9..cbc5249a1bf9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -7,6 +7,7 @@
> #include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> +#include "gem/i915_gem_context.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -171,3 +172,50 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
>
> intel_pxp_irq_disable(pxp);
> }
> +
> +void intel_pxp_invalidate(struct intel_pxp *pxp)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct i915_gem_context *ctx, *cn;
> +
> + /* ban all contexts marked as protected */
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + if (!kref_get_unless_zero(&ctx->ref))
> + continue;
> +
> + if (likely(!i915_gem_context_uses_protected_content(ctx)) ||
> + i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + continue;
> + }
> +
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +
> + /*
> + * Note that by the time we get here the HW keys are already
> + * long gone, so any batch using them that's already on the
> + * engines is very likely a lost cause (and it has probably
> + * already hung the engine). Therefore, we skip attempting to
> + * pull the running context out of the HW and we prioritize
> + * bringing the session back as soon as possible.
> + */
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + /* only invalidate if at least one ce was allocated */
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + intel_context_set_banned(ce);
> + i915_gem_context_set_invalid(ctx);
> + }
> + }
> + i915_gem_context_unlock_engines(ctx);
> +
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_safe_reset_next(ctx, cn, link);
> + i915_gem_context_put(ctx);
> + }
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 074b3b980957..91c1a2056309 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -33,6 +33,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index ef7c891cef14..707c908acfcc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -92,6 +92,9 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> /* must mark termination in progress calling this function */
> GEM_WARN_ON(pxp->arb_is_valid);
>
> + /* invalidate protected objects */
> + intel_pxp_invalidate(pxp);
> +
> /* terminate the hw sessions */
> ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> if (ret) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 3dcb8fe64ccd..7a2088eccc9f 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1695,6 +1695,26 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Mark that the context makes use of protected content, which will result
> + * in the context being invalidated when the protected content session is.
> + * This flag can only be set at context creation time and, when set to true,
> + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
> + * to false. This flag can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + * -EACCES: submitting an invalidated context for execution
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1925,6 +1945,12 @@ struct drm_i915_reg_read {
> struct drm_i915_reset_stats {
> __u32 ctx_id;
> __u32 flags;
> + /*
> + * contexts marked as using protected content are invalidated when the
> + * protected content session dies. Submission of invalidated contexts
> + * is rejected with -EACCES.
> + */
> +#define I915_CONTEXT_INVALIDATED 0x1
>
> /* All resets since boot/module reload, for all contexts */
> __u32 reset_count;
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
2021-04-01 12:06 ` Lionel Landwerlin
2021-04-15 17:20 ` Daniel Vetter
@ 2021-04-20 14:35 ` Rodrigo Vivi
2 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-20 14:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Chris Wilson
On Sun, Mar 28, 2021 at 03:57:03PM -0700, Daniele Ceraolo Spurio wrote:
> Extra tracking and checks around protected objects, coming in a follow-up
> patch, will be enabled only for contexts that opt in. Contexts can only be
> marked as using protected content at creation time and they must be both
> bannable and not recoverable.
>
> When a PXP teardown occurs, all gem contexts marked this way that
> have been used at least once will be marked as invalid and all new
> submissions using them will be rejected. All intel contexts within the
> invalidated gem contexts will be marked banned.
> A new flag has been added to the RESET_STATS ioctl to report the
> invalidation to userspace.
>
> v2: split to its own patch and improve doc (Chris), invalidate contexts
> on teardown
>
> v3: improve doc, use -EACCES for execbuf fail (Chris), make protected
> context flag not mandatory in protected object execbuf to avoid
> abuse (Lionel)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
this patch looks good to me... but let's make sure this gets to the dri-devel
eyes before we add any rv-b here...
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 ++++++++++++++++++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 3 +
> include/uapi/drm/i915_drm.h | 26 ++++++++
> 8 files changed, 172 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index fd8ee52e17a4..f3fd302682bb 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_globals.h"
> #include "i915_trace.h"
> @@ -1972,6 +1974,40 @@ static int set_priority(struct i915_gem_context *ctx,
> return 0;
> }
>
> +static int set_protected(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + int ret = 0;
> +
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + ret = -ENODEV;
> + else if (ctx->file_priv) /* can't change this after creation! */
> + ret = -EEXIST;
> + else if (args->size)
> + ret = -EINVAL;
> + else if (!args->value)
> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + else if (i915_gem_context_is_recoverable(ctx) ||
> + !i915_gem_context_is_bannable(ctx))
> + ret = -EPERM;
> + else
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +
> + return ret;
> +}
> +
> +static int get_protected(struct i915_gem_context *ctx,
> + struct drm_i915_gem_context_param *args)
> +{
> + if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + return -ENODEV;
> +
> + args->size = 0;
> + args->value = i915_gem_context_uses_protected_content(ctx);
> +
> + return 0;
> +}
> +
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> struct i915_gem_context *ctx,
> struct drm_i915_gem_context_param *args)
> @@ -2004,6 +2040,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = -EPERM;
> else if (args->value)
> i915_gem_context_set_bannable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't clear this for protected contexts */
> else
> i915_gem_context_clear_bannable(ctx);
> break;
> @@ -2011,10 +2049,12 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> - else if (args->value)
> - i915_gem_context_set_recoverable(ctx);
> - else
> + else if (!args->value)
> i915_gem_context_clear_recoverable(ctx);
> + else if (i915_gem_context_uses_protected_content(ctx))
> + ret = -EPERM; /* can't set this for protected contexts */
> + else
> + i915_gem_context_set_recoverable(ctx);
> break;
>
> case I915_CONTEXT_PARAM_PRIORITY:
> @@ -2041,6 +2081,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = set_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2494,6 +2538,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> ret = get_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = get_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2554,6 +2602,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
> args->batch_active = atomic_read(&ctx->guilty_count);
> args->batch_pending = atomic_read(&ctx->active_count);
>
> + /* re-use args->flags for output flags */
> + args->flags = 0;
> + if (i915_gem_context_invalidated(ctx))
> + args->flags |= I915_CONTEXT_INVALIDATED;
> +
> ret = 0;
> out:
> rcu_read_unlock();
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..169d3fb49252 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -108,6 +108,24 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
> }
>
> +static inline bool
> +i915_gem_context_invalidated(const struct i915_gem_context *ctx)
> +{
> + return test_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline void
> +i915_gem_context_set_invalid(struct i915_gem_context *ctx)
> +{
> + set_bit(CONTEXT_INVALID, &ctx->flags);
> +}
> +
> +static inline bool
> +i915_gem_context_uses_protected_content(const struct i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 340473aa70de..a0f80475da05 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -134,6 +134,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
>
> /**
> * @flags: small set of booleans
> @@ -141,6 +142,7 @@ struct i915_gem_context {
> unsigned long flags;
> #define CONTEXT_CLOSED 0
> #define CONTEXT_USER_ENGINES 1
> +#define CONTEXT_INVALID 2
>
> struct mutex mutex;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 5964e67c7d36..72c2470fcfe6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -21,6 +21,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> @@ -746,6 +748,11 @@ static int eb_select_context(struct i915_execbuffer *eb)
> if (unlikely(!ctx))
> return -ENOENT;
>
> + if (i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + return -EACCES;
> + }
> +
> eb->gem_context = ctx;
> if (rcu_access_pointer(ctx->vm))
> eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
> @@ -2940,6 +2947,17 @@ eb_select_engine(struct i915_execbuffer *eb)
>
> intel_gt_pm_get(ce->engine->gt);
>
> + if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> + err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> + if (err)
> + goto err;
> +
> + if (i915_gem_context_invalidated(eb->gem_context)) {
> + err = -EACCES;
> + goto err;
> + }
> + }
> +
> if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> err = intel_context_alloc_state(ce);
> if (err)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 948b8153c8c9..cbc5249a1bf9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -7,6 +7,7 @@
> #include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> +#include "gem/i915_gem_context.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -171,3 +172,50 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
>
> intel_pxp_irq_disable(pxp);
> }
> +
> +void intel_pxp_invalidate(struct intel_pxp *pxp)
> +{
> + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct i915_gem_context *ctx, *cn;
> +
> + /* ban all contexts marked as protected */
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + if (!kref_get_unless_zero(&ctx->ref))
> + continue;
> +
> + if (likely(!i915_gem_context_uses_protected_content(ctx)) ||
> + i915_gem_context_invalidated(ctx)) {
> + i915_gem_context_put(ctx);
> + continue;
> + }
> +
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +
> + /*
> + * Note that by the time we get here the HW keys are already
> + * long gone, so any batch using them that's already on the
> + * engines is very likely a lost cause (and it has probably
> + * already hung the engine). Therefore, we skip attempting to
> + * pull the running context out of the HW and we prioritize
> + * bringing the session back as soon as possible.
> + */
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + /* only invalidate if at least one ce was allocated */
> + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
> + intel_context_set_banned(ce);
> + i915_gem_context_set_invalid(ctx);
> + }
> + }
> + i915_gem_context_unlock_engines(ctx);
> +
> + spin_lock_irq(&i915->gem.contexts.lock);
> + list_safe_reset_next(ctx, cn, link);
> + i915_gem_context_put(ctx);
> + }
> + spin_unlock_irq(&i915->gem.contexts.lock);
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 074b3b980957..91c1a2056309 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -33,6 +33,7 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> index ef7c891cef14..707c908acfcc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -92,6 +92,9 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
> /* must mark termination in progress calling this function */
> GEM_WARN_ON(pxp->arb_is_valid);
>
> + /* invalidate protected objects */
> + intel_pxp_invalidate(pxp);
> +
> /* terminate the hw sessions */
> ret = intel_pxp_terminate_session(pxp, ARB_SESSION);
> if (ret) {
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 3dcb8fe64ccd..7a2088eccc9f 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1695,6 +1695,26 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Mark that the context makes use of protected content, which will result
> + * in the context being invalidated when the protected content session is.
> + * This flag can only be set at context creation time and, when set to true,
> + * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
> + * to false. This flag can't be set to true in conjunction with setting the
> + * I915_CONTEXT_PARAM_BANNABLE flag to false.
> + *
> + * Given the numerous restriction on this flag, there are several unique
> + * failure cases:
> + *
> + * -ENODEV: feature not available
> + * -EEXIST: trying to modify an existing context
> + * -EPERM: trying to mark a recoverable or not bannable context as protected
> + * -EACCES: submitting an invalidated context for execution
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1925,6 +1945,12 @@ struct drm_i915_reg_read {
> struct drm_i915_reset_stats {
> __u32 ctx_id;
> __u32 flags;
> + /*
> + * contexts marked as using protected content are invalidated when the
> + * protected content session dies. Submission of invalidated contexts
> + * is rejected with -EACCES.
> + */
> +#define I915_CONTEXT_INVALIDATED 0x1
>
> /* All resets since boot/module reload, for all contexts */
> __u32 reset_count;
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 11/16] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-03-30 9:26 ` Matthew Auld
2021-04-15 17:16 ` Daniel Vetter
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
` (10 subsequent siblings)
22 siblings, 2 replies; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Bommu Krishnaiah, Matthew Auld
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 45d60e3d98e3..3ad3413c459f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -7,6 +7,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_user_extensions.h"
static int
i915_gem_create(struct drm_file *file,
@@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 02d5b2b6ee39..f13e1ca2087b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1707,7 +1707,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 7a2088eccc9f..d5e502269a55 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1720,6 +1742,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull << 32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.29.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
@ 2021-03-30 9:26 ` Matthew Auld
2021-04-15 17:16 ` Daniel Vetter
1 sibling, 0 replies; 62+ messages in thread
From: Matthew Auld @ 2021-03-30 9:26 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Bommu Krishnaiah
On 28/03/2021 23:57, Daniele Ceraolo Spurio wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support PAVP.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 45d60e3d98e3..3ad3413c459f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -7,6 +7,7 @@
> #include "gem/i915_gem_region.h"
>
> #include "i915_drv.h"
> +#include "i915_user_extensions.h"
>
> static int
> i915_gem_create(struct drm_file *file,
> @@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
> &args->size, &args->handle);
> }
>
> +struct create_ext {
> + struct drm_i915_private *i915;
> +};
> +
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct create_ext *ext_data)
> +{
> + if (!(args->param & I915_OBJECT_PARAM)) {
> + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int create_setparam(struct i915_user_extension __user *base, void *data)
> +{
> + struct drm_i915_gem_create_ext_setparam ext;
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + return __create_setparam(&ext.param, data);
> +}
> +
> +static const i915_user_extension_fn create_extensions[] = {
> + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
> +};
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_i915_gem_create *args = data;
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
>
> i915_gem_flush_free_objects(i915);
>
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + &ext_data);
> + if (ret)
> + return ret;
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 02d5b2b6ee39..f13e1ca2087b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1707,7 +1707,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 7a2088eccc9f..d5e502269a55 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
> #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -729,6 +730,27 @@ struct drm_i915_gem_create {
> __u32 pad;
> };
>
> +struct drm_i915_gem_create_ext {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> + (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> + __u64 extensions;
> +
> +};
> +
> struct drm_i915_gem_pread {
> /** Handle for the object being read. */
> __u32 handle;
> @@ -1720,6 +1742,31 @@ struct drm_i915_gem_context_param {
> __u64 value;
> };
>
> +struct drm_i915_gem_object_param {
> + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> + __u32 handle;
> +
> + /* Data pointer size */
> + __u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM (1ull << 32)
> +
> + __u64 param;
> +
> + /* Data value or pointer */
> + __u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> + struct i915_user_extension base;
> + struct drm_i915_gem_object_param param;
> +};
> +
Fwiw there were some minor uAPI changes(like using a separate ioctl)
needed for this, as per the upstream review feedback for the placements
extension. I think the required changes should already be incorporated here:
https://patchwork.freedesktop.org/series/86866/
> /**
> * Context SSEU programming
> *
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
@ 2021-04-15 17:16 ` Daniel Vetter
2021-04-15 17:16 ` Daniel Vetter
1 sibling, 0 replies; 62+ messages in thread
From: Daniel Vetter @ 2021-04-15 17:16 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jason Ekstrand, Lionel Landwerlin, dri-devel
Cc: Bommu Krishnaiah, intel-gfx, Matthew Auld
On Mon, Mar 29, 2021 at 12:58 AM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support PAVP.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
gem changes need to be cc'ed to dri-devel. Also adding Jason on this,
since he just reviewed the gem_create_ext rfc from Matt.
-Daniel
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 45d60e3d98e3..3ad3413c459f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -7,6 +7,7 @@
> #include "gem/i915_gem_region.h"
>
> #include "i915_drv.h"
> +#include "i915_user_extensions.h"
>
> static int
> i915_gem_create(struct drm_file *file,
> @@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
> &args->size, &args->handle);
> }
>
> +struct create_ext {
> + struct drm_i915_private *i915;
> +};
> +
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct create_ext *ext_data)
> +{
> + if (!(args->param & I915_OBJECT_PARAM)) {
> + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int create_setparam(struct i915_user_extension __user *base, void *data)
> +{
> + struct drm_i915_gem_create_ext_setparam ext;
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + return __create_setparam(&ext.param, data);
> +}
> +
> +static const i915_user_extension_fn create_extensions[] = {
> + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
> +};
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_i915_gem_create *args = data;
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
>
> i915_gem_flush_free_objects(i915);
>
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + &ext_data);
> + if (ret)
> + return ret;
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 02d5b2b6ee39..f13e1ca2087b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1707,7 +1707,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 7a2088eccc9f..d5e502269a55 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
> #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -729,6 +730,27 @@ struct drm_i915_gem_create {
> __u32 pad;
> };
>
> +struct drm_i915_gem_create_ext {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> + (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> + __u64 extensions;
> +
> +};
> +
> struct drm_i915_gem_pread {
> /** Handle for the object being read. */
> __u32 handle;
> @@ -1720,6 +1742,31 @@ struct drm_i915_gem_context_param {
> __u64 value;
> };
>
> +struct drm_i915_gem_object_param {
> + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> + __u32 handle;
> +
> + /* Data pointer size */
> + __u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM (1ull << 32)
> +
> + __u64 param;
> +
> + /* Data value or pointer */
> + __u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> + struct i915_user_extension base;
> + struct drm_i915_gem_object_param param;
> +};
> +
> /**
> * Context SSEU programming
> *
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
@ 2021-04-15 17:16 ` Daniel Vetter
0 siblings, 0 replies; 62+ messages in thread
From: Daniel Vetter @ 2021-04-15 17:16 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jason Ekstrand, Lionel Landwerlin, dri-devel
Cc: Bommu Krishnaiah, intel-gfx, Matthew Auld
On Mon, Mar 29, 2021 at 12:58 AM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support PAVP.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
gem changes need to be cc'ed to dri-devel. Also adding Jason on this,
since he just reviewed the gem_create_ext rfc from Matt.
-Daniel
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 45d60e3d98e3..3ad3413c459f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -7,6 +7,7 @@
> #include "gem/i915_gem_region.h"
>
> #include "i915_drv.h"
> +#include "i915_user_extensions.h"
>
> static int
> i915_gem_create(struct drm_file *file,
> @@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
> &args->size, &args->handle);
> }
>
> +struct create_ext {
> + struct drm_i915_private *i915;
> +};
> +
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct create_ext *ext_data)
> +{
> + if (!(args->param & I915_OBJECT_PARAM)) {
> + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int create_setparam(struct i915_user_extension __user *base, void *data)
> +{
> + struct drm_i915_gem_create_ext_setparam ext;
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + return __create_setparam(&ext.param, data);
> +}
> +
> +static const i915_user_extension_fn create_extensions[] = {
> + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
> +};
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_i915_gem_create *args = data;
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
>
> i915_gem_flush_free_objects(i915);
>
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + &ext_data);
> + if (ret)
> + return ret;
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 02d5b2b6ee39..f13e1ca2087b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1707,7 +1707,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 7a2088eccc9f..d5e502269a55 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
> #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -729,6 +730,27 @@ struct drm_i915_gem_create {
> __u32 pad;
> };
>
> +struct drm_i915_gem_create_ext {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> + (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> + __u64 extensions;
> +
> +};
> +
> struct drm_i915_gem_pread {
> /** Handle for the object being read. */
> __u32 handle;
> @@ -1720,6 +1742,31 @@ struct drm_i915_gem_context_param {
> __u64 value;
> };
>
> +struct drm_i915_gem_object_param {
> + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> + __u32 handle;
> +
> + /* Data pointer size */
> + __u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM (1ull << 32)
> +
> + __u64 param;
> +
> + /* Data value or pointer */
> + __u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> + struct i915_user_extension base;
> + struct drm_i915_gem_object_param param;
> +};
> +
> /**
> * Context SSEU programming
> *
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (11 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-01 12:05 ` Lionel Landwerlin
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
` (9 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Chris Wilson, Kondapally Kalyan, Bommu Krishnaiah
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffers. Only contexts
marked as protected are allowed to operate on protected buffers.
We only allow setting the flags at creation time.
All protected objects that have backing storage will be considered
invalid when the session is destroyed and they won't be usable anymore.
This is a rework of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks have not been modified.
v2: split context changes, fix defines and improve documentation (Chris),
add object invalidation logic
v3: fix spinlock definition and usage, only validate objects when
they're first added to a context lut, only remove them once (Chris),
make protected context flag not mandatory in protected object execbuf
to avoid abuse (Lionel)
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 16 ++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++++++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++++++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 41 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
include/uapi/drm/i915_drm.h | 20 +++++++++
9 files changed, 150 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..d02e5938afbe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
if (ret)
return ret;
+ if (user_flags & I915_GEM_OBJECT_PROTECTED)
+ intel_pxp_object_add(obj);
+
*handle_p = handle;
*size_p = size;
return 0;
@@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -104,6 +112,19 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
+ return -ENODEV;
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -148,5 +169,5 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 72c2470fcfe6..2fb6579ad301 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
#include "pxp/intel_pxp.h"
@@ -839,6 +840,21 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
if (unlikely(!obj))
return ERR_PTR(-ENOENT);
+ /*
+ * If the user has opted-in for protected-object tracking, make
+ * sure the object encryption can be used.
+ * We only need to do this when the object is first used with
+ * this context, because the context itself will be banned when
+ * the protected objects become invalid.
+ */
+ if (i915_gem_context_uses_protected_content(eb->gem_context) &&
+ i915_gem_object_is_protected(obj)) {
+ if (!intel_pxp_is_active(&vm->gt->pxp))
+ return ERR_PTR(-ENODEV);
+ if (!i915_gem_object_has_valid_protection(obj))
+ return ERR_PTR(-EIO);
+ }
+
vma = i915_vma_instance(obj, vm, NULL);
if (IS_ERR(vma)) {
i915_gem_object_put(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index ea74cbca95be..80ccefd641e8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -25,6 +25,7 @@
#include <linux/sched/mm.h>
#include "display/intel_frontbuffer.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
@@ -70,6 +71,8 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(&obj->lut_list);
spin_lock_init(&obj->lut_lock);
+ INIT_LIST_HEAD(&obj->pxp_link);
+
spin_lock_init(&obj->mmo.lock);
obj->mmo.offsets = RB_ROOT;
@@ -232,6 +235,9 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
spin_unlock(&obj->vma.lock);
}
+ if (i915_gem_object_has_valid_protection(obj))
+ intel_pxp_object_remove(obj);
+
__i915_gem_object_free_mmaps(obj);
GEM_BUG_ON(!list_empty(&obj->lut_list));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 2ebd79537aea..61b101560352 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -288,6 +288,18 @@ i915_gem_object_never_mmap(const struct drm_i915_gem_object *obj)
return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_MMAP);
}
+static inline bool
+i915_gem_object_is_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_GEM_OBJECT_PROTECTED;
+}
+
+static inline bool
+i915_gem_object_has_valid_protection(const struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_is_protected(obj) && !list_empty(&obj->pxp_link);
+}
+
static inline bool
i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 8e485cb3343c..0d4bd2747375 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -167,6 +167,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_GEM_OBJECT_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
@@ -286,6 +291,14 @@ struct drm_i915_gem_object {
bool dirty:1;
} mm;
+ /*
+ * When the PXP session is invalidated, we need to mark all protected
+ * objects as invalid. To easily do so we add them all to a list. The
+ * presence on the list is used to check if the encryption is valid or
+ * not.
+ */
+ struct list_head pxp_link;
+
/** Record of address bit 17 of each page at last unbind. */
unsigned long *bit_17;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index cbc5249a1bf9..7f9902eac7ec 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -69,6 +69,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ spin_lock_init(&pxp->lock);
+ INIT_LIST_HEAD(&pxp->protected_objects);
+
/*
* we'll use the completion to check if there is a termination pending,
* so we start it as completed and we reinit it when a termination
@@ -173,11 +176,49 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
intel_pxp_irq_disable(pxp);
}
+int intel_pxp_object_add(struct drm_i915_gem_object *obj)
+{
+ struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return -ENODEV;
+
+ if (!list_empty(&obj->pxp_link))
+ return -EEXIST;
+
+ spin_lock_irq(&pxp->lock);
+ list_add(&obj->pxp_link, &pxp->protected_objects);
+ spin_unlock_irq(&pxp->lock);
+
+ return 0;
+}
+
+void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
+{
+ struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ spin_lock_irq(&pxp->lock);
+ list_del_init(&obj->pxp_link);
+ spin_unlock_irq(&pxp->lock);
+}
+
void intel_pxp_invalidate(struct intel_pxp *pxp)
{
struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct drm_i915_gem_object *obj, *tmp;
struct i915_gem_context *ctx, *cn;
+ /* delete objects that have been used with the invalidated session */
+ spin_lock_irq(&pxp->lock);
+ list_for_each_entry_safe(obj, tmp, &pxp->protected_objects, pxp_link) {
+ if (i915_gem_object_has_pages(obj))
+ list_del_init(&obj->pxp_link);
+ }
+ spin_unlock_irq(&pxp->lock);
+
/* ban all contexts marked as protected */
spin_lock_irq(&i915->gem.contexts.lock);
list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 91c1a2056309..194b00149247 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -9,6 +9,8 @@
#include "gt/intel_gt_types.h"
#include "intel_pxp_types.h"
+struct drm_i915_gem_object;
+
static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
{
return container_of(pxp, struct intel_gt, pxp);
@@ -33,6 +35,9 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
+
+int intel_pxp_object_add(struct drm_i915_gem_object *obj);
+void intel_pxp_object_remove(struct drm_i915_gem_object *obj);
void intel_pxp_invalidate(struct intel_pxp *pxp);
#else
static inline void intel_pxp_init(struct intel_pxp *pxp)
@@ -47,6 +52,14 @@ static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
{
return 0;
}
+
+static inline int intel_pxp_object_add(struct drm_i915_gem_object *obj)
+{
+ return 0;
+}
+static inline void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
+{
+}
#endif
#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 6c9265fb8e4b..665704d7793e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -7,8 +7,10 @@
#define __INTEL_PXP_TYPES_H__
#include <linux/completion.h>
+#include <linux/list.h>
#include <linux/types.h>
#include <linux/mutex.h>
+#include <linux/spinlock.h>
#include <linux/workqueue.h>
struct intel_context;
@@ -33,6 +35,9 @@ struct intel_pxp {
u32 session_events; /* protected with gt->irq_lock */
#define PXP_TERMINATION_REQUEST BIT(0)
#define PXP_TERMINATION_COMPLETE BIT(1)
+
+ spinlock_t lock; /* protects the objects list */
+ struct list_head protected_objects;
};
#endif /* __INTEL_PXP_TYPES_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index d5e502269a55..420412c08745 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1756,6 +1756,26 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull << 32)
+/*
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true, buffer contents is expected to be protected by PXP
+ * encryption and requires decryption for scan out and processing. This is
+ * only possible on platforms that have PXP enabled, on all other scenarios
+ * setting this flag will cause the ioctl to fail and return -ENODEV.
+ *
+ * The buffer contents are considered invalid after a PXP session teardown.
+ * It is recommended to use protected buffers only with contexts created
+ * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that will enable
+ * extra checks at submission time on the validity of the objects involved,
+ * which can lead to the following errors:
+ *
+ * -ENODEV: PXP session not currently active
+ * -EIO: buffer has become invalid after a teardown event
+ */
+#define I915_OBJECT_PARAM_PROTECTED_CONTENT 0x0
+/* Must be kept compact -- no holes and well documented */
+
__u64 param;
/* Data value or pointer */
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
@ 2021-04-01 12:05 ` Lionel Landwerlin
2021-04-01 20:45 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 62+ messages in thread
From: Lionel Landwerlin @ 2021-04-01 12:05 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Cc: Huang Sean Z, Chris Wilson, Kondapally Kalyan, Bommu Krishnaiah
On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> This api allow user mode to create Protected buffers. Only contexts
> marked as protected are allowed to operate on protected buffers.
>
> We only allow setting the flags at creation time.
>
> All protected objects that have backing storage will be considered
> invalid when the session is destroyed and they won't be usable anymore.
>
> This is a rework of the original code by Bommu Krishnaiah. I've
> authorship unchanged since significant chunks have not been modified.
>
> v2: split context changes, fix defines and improve documentation (Chris),
> add object invalidation logic
> v3: fix spinlock definition and usage, only validate objects when
> they're first added to a context lut, only remove them once (Chris),
> make protected context flag not mandatory in protected object execbuf
> to avoid abuse (Lionel)
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++--
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 16 ++++++++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++++++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 41 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
> include/uapi/drm/i915_drm.h | 20 +++++++++
> 9 files changed, 150 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 3ad3413c459f..d02e5938afbe 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -5,6 +5,7 @@
>
> #include "gem/i915_gem_ioctls.h"
> #include "gem/i915_gem_region.h"
> +#include "pxp/intel_pxp.h"
>
> #include "i915_drv.h"
> #include "i915_user_extensions.h"
> @@ -13,7 +14,8 @@ static int
> i915_gem_create(struct drm_file *file,
> struct intel_memory_region *mr,
> u64 *size_p,
> - u32 *handle_p)
> + u32 *handle_p,
> + u64 user_flags)
> {
> struct drm_i915_gem_object *obj;
> u32 handle;
> @@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
>
> GEM_BUG_ON(size != obj->base.size);
>
> + obj->user_flags = user_flags;
> +
> ret = drm_gem_handle_create(file, &obj->base, &handle);
> /* drop reference from allocate - handle holds it now */
> i915_gem_object_put(obj);
> if (ret)
> return ret;
>
> + if (user_flags & I915_GEM_OBJECT_PROTECTED)
> + intel_pxp_object_add(obj);
> +
> *handle_p = handle;
> *size_p = size;
> return 0;
> @@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
> return i915_gem_create(file,
> intel_memory_region_by_type(to_i915(dev),
> mem_type),
> - &args->size, &args->handle);
> + &args->size, &args->handle, 0);
> }
>
> struct create_ext {
> struct drm_i915_private *i915;
> + unsigned long user_flags;
> };
>
> static int __create_setparam(struct drm_i915_gem_object_param *args,
> @@ -104,6 +112,19 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
> return -EINVAL;
> }
>
> + switch (lower_32_bits(args->param)) {
> + case I915_OBJECT_PARAM_PROTECTED_CONTENT:
> + if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
> + return -ENODEV;
> + if (args->size) {
> + return -EINVAL;
> + } else if (args->data) {
> + ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
> + return 0;
> + }
> + break;
> + }
> +
> return -EINVAL;
> }
>
> @@ -148,5 +169,5 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> - &args->size, &args->handle);
> + &args->size, &args->handle, ext_data.user_flags);
> }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 72c2470fcfe6..2fb6579ad301 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -20,6 +20,7 @@
> #include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
> +#include "pxp/intel_pxp.h"
>
> #include "pxp/intel_pxp.h"
>
> @@ -839,6 +840,21 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
> if (unlikely(!obj))
> return ERR_PTR(-ENOENT);
>
> + /*
> + * If the user has opted-in for protected-object tracking, make
> + * sure the object encryption can be used.
> + * We only need to do this when the object is first used with
> + * this context, because the context itself will be banned when
> + * the protected objects become invalid.
> + */
> + if (i915_gem_context_uses_protected_content(eb->gem_context) &&
> + i915_gem_object_is_protected(obj)) {
> + if (!intel_pxp_is_active(&vm->gt->pxp))
> + return ERR_PTR(-ENODEV);
> + if (!i915_gem_object_has_valid_protection(obj))
> + return ERR_PTR(-EIO);
> + }
> +
> vma = i915_vma_instance(obj, vm, NULL);
> if (IS_ERR(vma)) {
> i915_gem_object_put(obj);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index ea74cbca95be..80ccefd641e8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -25,6 +25,7 @@
> #include <linux/sched/mm.h>
>
> #include "display/intel_frontbuffer.h"
> +#include "pxp/intel_pxp.h"
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
> @@ -70,6 +71,8 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
> INIT_LIST_HEAD(&obj->lut_list);
> spin_lock_init(&obj->lut_lock);
>
> + INIT_LIST_HEAD(&obj->pxp_link);
> +
> spin_lock_init(&obj->mmo.lock);
> obj->mmo.offsets = RB_ROOT;
>
> @@ -232,6 +235,9 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915,
> spin_unlock(&obj->vma.lock);
> }
>
> + if (i915_gem_object_has_valid_protection(obj))
> + intel_pxp_object_remove(obj);
> +
> __i915_gem_object_free_mmaps(obj);
>
> GEM_BUG_ON(!list_empty(&obj->lut_list));
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 2ebd79537aea..61b101560352 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -288,6 +288,18 @@ i915_gem_object_never_mmap(const struct drm_i915_gem_object *obj)
> return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_MMAP);
> }
>
> +static inline bool
> +i915_gem_object_is_protected(const struct drm_i915_gem_object *obj)
> +{
> + return obj->user_flags & I915_GEM_OBJECT_PROTECTED;
> +}
> +
> +static inline bool
> +i915_gem_object_has_valid_protection(const struct drm_i915_gem_object *obj)
> +{
> + return i915_gem_object_is_protected(obj) && !list_empty(&obj->pxp_link);
> +}
> +
> static inline bool
> i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
> {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 8e485cb3343c..0d4bd2747375 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -167,6 +167,11 @@ struct drm_i915_gem_object {
> } mmo;
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
> + /**
> + * @user_flags: small set of booleans set by the user
> + */
> + unsigned long user_flags;
> +#define I915_GEM_OBJECT_PROTECTED BIT(0)
>
> unsigned long flags;
> #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
> @@ -286,6 +291,14 @@ struct drm_i915_gem_object {
> bool dirty:1;
> } mm;
>
> + /*
> + * When the PXP session is invalidated, we need to mark all protected
> + * objects as invalid. To easily do so we add them all to a list. The
> + * presence on the list is used to check if the encryption is valid or
> + * not.
> + */
> + struct list_head pxp_link;
> +
> /** Record of address bit 17 of each page at last unbind. */
> unsigned long *bit_17;
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index cbc5249a1bf9..7f9902eac7ec 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -69,6 +69,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (!HAS_PXP(gt->i915))
> return;
>
> + spin_lock_init(&pxp->lock);
> + INIT_LIST_HEAD(&pxp->protected_objects);
> +
> /*
> * we'll use the completion to check if there is a termination pending,
> * so we start it as completed and we reinit it when a termination
> @@ -173,11 +176,49 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
> intel_pxp_irq_disable(pxp);
> }
>
> +int intel_pxp_object_add(struct drm_i915_gem_object *obj)
> +{
> + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return -ENODEV;
> +
> + if (!list_empty(&obj->pxp_link))
> + return -EEXIST;
> +
> + spin_lock_irq(&pxp->lock);
> + list_add(&obj->pxp_link, &pxp->protected_objects);
> + spin_unlock_irq(&pxp->lock);
> +
> + return 0;
> +}
> +
> +void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
> +{
> + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + spin_lock_irq(&pxp->lock);
> + list_del_init(&obj->pxp_link);
> + spin_unlock_irq(&pxp->lock);
> +}
> +
> void intel_pxp_invalidate(struct intel_pxp *pxp)
> {
> struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> + struct drm_i915_gem_object *obj, *tmp;
> struct i915_gem_context *ctx, *cn;
>
> + /* delete objects that have been used with the invalidated session */
> + spin_lock_irq(&pxp->lock);
> + list_for_each_entry_safe(obj, tmp, &pxp->protected_objects, pxp_link) {
> + if (i915_gem_object_has_pages(obj))
> + list_del_init(&obj->pxp_link);
> + }
> + spin_unlock_irq(&pxp->lock);
> +
> /* ban all contexts marked as protected */
> spin_lock_irq(&i915->gem.contexts.lock);
> list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 91c1a2056309..194b00149247 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -9,6 +9,8 @@
> #include "gt/intel_gt_types.h"
> #include "intel_pxp_types.h"
>
> +struct drm_i915_gem_object;
> +
> static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> {
> return container_of(pxp, struct intel_gt, pxp);
> @@ -33,6 +35,9 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +
> +int intel_pxp_object_add(struct drm_i915_gem_object *obj);
> +void intel_pxp_object_remove(struct drm_i915_gem_object *obj);
> void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> @@ -47,6 +52,14 @@ static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> {
> return 0;
> }
> +
> +static inline int intel_pxp_object_add(struct drm_i915_gem_object *obj)
> +{
> + return 0;
> +}
> +static inline void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
> +{
> +}
> #endif
>
> #endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> index 6c9265fb8e4b..665704d7793e 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -7,8 +7,10 @@
> #define __INTEL_PXP_TYPES_H__
>
> #include <linux/completion.h>
> +#include <linux/list.h>
> #include <linux/types.h>
> #include <linux/mutex.h>
> +#include <linux/spinlock.h>
> #include <linux/workqueue.h>
>
> struct intel_context;
> @@ -33,6 +35,9 @@ struct intel_pxp {
> u32 session_events; /* protected with gt->irq_lock */
> #define PXP_TERMINATION_REQUEST BIT(0)
> #define PXP_TERMINATION_COMPLETE BIT(1)
> +
> + spinlock_t lock; /* protects the objects list */
> + struct list_head protected_objects;
> };
>
> #endif /* __INTEL_PXP_TYPES_H__ */
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index d5e502269a55..420412c08745 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1756,6 +1756,26 @@ struct drm_i915_gem_object_param {
> */
> #define I915_OBJECT_PARAM (1ull << 32)
>
> +/*
> + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true, buffer contents is expected to be protected by PXP
> + * encryption and requires decryption for scan out and processing. This is
> + * only possible on platforms that have PXP enabled, on all other scenarios
> + * setting this flag will cause the ioctl to fail and return -ENODEV.
> + *
> + * The buffer contents are considered invalid after a PXP session teardown.
> + * It is recommended to use protected buffers only with contexts created
> + * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that will enable
> + * extra checks at submission time on the validity of the objects involved,
> + * which can lead to the following errors:
> + *
> + * -ENODEV: PXP session not currently active
> + * -EIO: buffer has become invalid after a teardown event
I was a bit confused on reading those comments. Maybe we should specify
when they apply.
My understanding is that you can get -ENODEV on object creation, while
-EIO happens at execbuffer time.
Did I get this right?
-Lionel
> + */
> +#define I915_OBJECT_PARAM_PROTECTED_CONTENT 0x0
> +/* Must be kept compact -- no holes and well documented */
> +
> __u64 param;
>
> /* Data value or pointer */
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer
2021-04-01 12:05 ` Lionel Landwerlin
@ 2021-04-01 20:45 ` Daniele Ceraolo Spurio
2021-04-20 14:40 ` Rodrigo Vivi
0 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-04-01 20:45 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: Bommu Krishnaiah, Huang Sean Z, Chris Wilson
On 4/1/2021 5:05 AM, Lionel Landwerlin wrote:
> On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
>> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>
>> This api allow user mode to create Protected buffers. Only contexts
>> marked as protected are allowed to operate on protected buffers.
>>
>> We only allow setting the flags at creation time.
>>
>> All protected objects that have backing storage will be considered
>> invalid when the session is destroyed and they won't be usable anymore.
>>
>> This is a rework of the original code by Bommu Krishnaiah. I've
>> authorship unchanged since significant chunks have not been modified.
>>
>> v2: split context changes, fix defines and improve documentation
>> (Chris),
>> add object invalidation logic
>> v3: fix spinlock definition and usage, only validate objects when
>> they're first added to a context lut, only remove them once
>> (Chris),
>> make protected context flag not mandatory in protected object
>> execbuf
>> to avoid abuse (Lionel)
>>
>> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
>> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
>> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++--
>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 16 ++++++++
>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++++++
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 41 +++++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
>> include/uapi/drm/i915_drm.h | 20 +++++++++
>> 9 files changed, 150 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> index 3ad3413c459f..d02e5938afbe 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> @@ -5,6 +5,7 @@
>> #include "gem/i915_gem_ioctls.h"
>> #include "gem/i915_gem_region.h"
>> +#include "pxp/intel_pxp.h"
>> #include "i915_drv.h"
>> #include "i915_user_extensions.h"
>> @@ -13,7 +14,8 @@ static int
>> i915_gem_create(struct drm_file *file,
>> struct intel_memory_region *mr,
>> u64 *size_p,
>> - u32 *handle_p)
>> + u32 *handle_p,
>> + u64 user_flags)
>> {
>> struct drm_i915_gem_object *obj;
>> u32 handle;
>> @@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
>> GEM_BUG_ON(size != obj->base.size);
>> + obj->user_flags = user_flags;
>> +
>> ret = drm_gem_handle_create(file, &obj->base, &handle);
>> /* drop reference from allocate - handle holds it now */
>> i915_gem_object_put(obj);
>> if (ret)
>> return ret;
>> + if (user_flags & I915_GEM_OBJECT_PROTECTED)
>> + intel_pxp_object_add(obj);
>> +
>> *handle_p = handle;
>> *size_p = size;
>> return 0;
>> @@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
>> return i915_gem_create(file,
>> intel_memory_region_by_type(to_i915(dev),
>> mem_type),
>> - &args->size, &args->handle);
>> + &args->size, &args->handle, 0);
>> }
>> struct create_ext {
>> struct drm_i915_private *i915;
>> + unsigned long user_flags;
>> };
>> static int __create_setparam(struct drm_i915_gem_object_param *args,
>> @@ -104,6 +112,19 @@ static int __create_setparam(struct
>> drm_i915_gem_object_param *args,
>> return -EINVAL;
>> }
>> + switch (lower_32_bits(args->param)) {
>> + case I915_OBJECT_PARAM_PROTECTED_CONTENT:
>> + if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
>> + return -ENODEV;
>> + if (args->size) {
>> + return -EINVAL;
>> + } else if (args->data) {
>> + ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
>> + return 0;
>> + }
>> + break;
>> + }
>> +
>> return -EINVAL;
>> }
>> @@ -148,5 +169,5 @@ i915_gem_create_ioctl(struct drm_device *dev,
>> void *data,
>> return i915_gem_create(file,
>> intel_memory_region_by_type(i915,
>> INTEL_MEMORY_SYSTEM),
>> - &args->size, &args->handle);
>> + &args->size, &args->handle, ext_data.user_flags);
>> }
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> index 72c2470fcfe6..2fb6579ad301 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> @@ -20,6 +20,7 @@
>> #include "gt/intel_gt_buffer_pool.h"
>> #include "gt/intel_gt_pm.h"
>> #include "gt/intel_ring.h"
>> +#include "pxp/intel_pxp.h"
>> #include "pxp/intel_pxp.h"
>> @@ -839,6 +840,21 @@ static struct i915_vma *eb_lookup_vma(struct
>> i915_execbuffer *eb, u32 handle)
>> if (unlikely(!obj))
>> return ERR_PTR(-ENOENT);
>> + /*
>> + * If the user has opted-in for protected-object tracking, make
>> + * sure the object encryption can be used.
>> + * We only need to do this when the object is first used with
>> + * this context, because the context itself will be banned when
>> + * the protected objects become invalid.
>> + */
>> + if (i915_gem_context_uses_protected_content(eb->gem_context) &&
>> + i915_gem_object_is_protected(obj)) {
>> + if (!intel_pxp_is_active(&vm->gt->pxp))
>> + return ERR_PTR(-ENODEV);
>> + if (!i915_gem_object_has_valid_protection(obj))
>> + return ERR_PTR(-EIO);
>> + }
>> +
>> vma = i915_vma_instance(obj, vm, NULL);
>> if (IS_ERR(vma)) {
>> i915_gem_object_put(obj);
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> index ea74cbca95be..80ccefd641e8 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
>> @@ -25,6 +25,7 @@
>> #include <linux/sched/mm.h>
>> #include "display/intel_frontbuffer.h"
>> +#include "pxp/intel_pxp.h"
>> #include "i915_drv.h"
>> #include "i915_gem_clflush.h"
>> #include "i915_gem_context.h"
>> @@ -70,6 +71,8 @@ void i915_gem_object_init(struct
>> drm_i915_gem_object *obj,
>> INIT_LIST_HEAD(&obj->lut_list);
>> spin_lock_init(&obj->lut_lock);
>> + INIT_LIST_HEAD(&obj->pxp_link);
>> +
>> spin_lock_init(&obj->mmo.lock);
>> obj->mmo.offsets = RB_ROOT;
>> @@ -232,6 +235,9 @@ static void __i915_gem_free_objects(struct
>> drm_i915_private *i915,
>> spin_unlock(&obj->vma.lock);
>> }
>> + if (i915_gem_object_has_valid_protection(obj))
>> + intel_pxp_object_remove(obj);
>> +
>> __i915_gem_object_free_mmaps(obj);
>> GEM_BUG_ON(!list_empty(&obj->lut_list));
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> index 2ebd79537aea..61b101560352 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> @@ -288,6 +288,18 @@ i915_gem_object_never_mmap(const struct
>> drm_i915_gem_object *obj)
>> return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_MMAP);
>> }
>> +static inline bool
>> +i915_gem_object_is_protected(const struct drm_i915_gem_object *obj)
>> +{
>> + return obj->user_flags & I915_GEM_OBJECT_PROTECTED;
>> +}
>> +
>> +static inline bool
>> +i915_gem_object_has_valid_protection(const struct
>> drm_i915_gem_object *obj)
>> +{
>> + return i915_gem_object_is_protected(obj) &&
>> !list_empty(&obj->pxp_link);
>> +}
>> +
>> static inline bool
>> i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
>> {
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> index 8e485cb3343c..0d4bd2747375 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> @@ -167,6 +167,11 @@ struct drm_i915_gem_object {
>> } mmo;
>> I915_SELFTEST_DECLARE(struct list_head st_link);
>> + /**
>> + * @user_flags: small set of booleans set by the user
>> + */
>> + unsigned long user_flags;
>> +#define I915_GEM_OBJECT_PROTECTED BIT(0)
>> unsigned long flags;
>> #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
>> @@ -286,6 +291,14 @@ struct drm_i915_gem_object {
>> bool dirty:1;
>> } mm;
>> + /*
>> + * When the PXP session is invalidated, we need to mark all
>> protected
>> + * objects as invalid. To easily do so we add them all to a
>> list. The
>> + * presence on the list is used to check if the encryption is
>> valid or
>> + * not.
>> + */
>> + struct list_head pxp_link;
>> +
>> /** Record of address bit 17 of each page at last unbind. */
>> unsigned long *bit_17;
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> index cbc5249a1bf9..7f9902eac7ec 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> @@ -69,6 +69,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
>> if (!HAS_PXP(gt->i915))
>> return;
>> + spin_lock_init(&pxp->lock);
>> + INIT_LIST_HEAD(&pxp->protected_objects);
>> +
>> /*
>> * we'll use the completion to check if there is a termination
>> pending,
>> * so we start it as completed and we reinit it when a termination
>> @@ -173,11 +176,49 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
>> intel_pxp_irq_disable(pxp);
>> }
>> +int intel_pxp_object_add(struct drm_i915_gem_object *obj)
>> +{
>> + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
>> +
>> + if (!intel_pxp_is_enabled(pxp))
>> + return -ENODEV;
>> +
>> + if (!list_empty(&obj->pxp_link))
>> + return -EEXIST;
>> +
>> + spin_lock_irq(&pxp->lock);
>> + list_add(&obj->pxp_link, &pxp->protected_objects);
>> + spin_unlock_irq(&pxp->lock);
>> +
>> + return 0;
>> +}
>> +
>> +void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
>> +{
>> + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
>> +
>> + if (!intel_pxp_is_enabled(pxp))
>> + return;
>> +
>> + spin_lock_irq(&pxp->lock);
>> + list_del_init(&obj->pxp_link);
>> + spin_unlock_irq(&pxp->lock);
>> +}
>> +
>> void intel_pxp_invalidate(struct intel_pxp *pxp)
>> {
>> struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
>> + struct drm_i915_gem_object *obj, *tmp;
>> struct i915_gem_context *ctx, *cn;
>> + /* delete objects that have been used with the invalidated
>> session */
>> + spin_lock_irq(&pxp->lock);
>> + list_for_each_entry_safe(obj, tmp, &pxp->protected_objects,
>> pxp_link) {
>> + if (i915_gem_object_has_pages(obj))
>> + list_del_init(&obj->pxp_link);
>> + }
>> + spin_unlock_irq(&pxp->lock);
>> +
>> /* ban all contexts marked as protected */
>> spin_lock_irq(&i915->gem.contexts.lock);
>> list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list,
>> link) {
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> index 91c1a2056309..194b00149247 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> @@ -9,6 +9,8 @@
>> #include "gt/intel_gt_types.h"
>> #include "intel_pxp_types.h"
>> +struct drm_i915_gem_object;
>> +
>> static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
>> {
>> return container_of(pxp, struct intel_gt, pxp);
>> @@ -33,6 +35,9 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
>> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
>> int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
>> +
>> +int intel_pxp_object_add(struct drm_i915_gem_object *obj);
>> +void intel_pxp_object_remove(struct drm_i915_gem_object *obj);
>> void intel_pxp_invalidate(struct intel_pxp *pxp);
>> #else
>> static inline void intel_pxp_init(struct intel_pxp *pxp)
>> @@ -47,6 +52,14 @@ static inline int
>> intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
>> {
>> return 0;
>> }
>> +
>> +static inline int intel_pxp_object_add(struct drm_i915_gem_object *obj)
>> +{
>> + return 0;
>> +}
>> +static inline void intel_pxp_object_remove(struct
>> drm_i915_gem_object *obj)
>> +{
>> +}
>> #endif
>> #endif /* __INTEL_PXP_H__ */
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> index 6c9265fb8e4b..665704d7793e 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> @@ -7,8 +7,10 @@
>> #define __INTEL_PXP_TYPES_H__
>> #include <linux/completion.h>
>> +#include <linux/list.h>
>> #include <linux/types.h>
>> #include <linux/mutex.h>
>> +#include <linux/spinlock.h>
>> #include <linux/workqueue.h>
>> struct intel_context;
>> @@ -33,6 +35,9 @@ struct intel_pxp {
>> u32 session_events; /* protected with gt->irq_lock */
>> #define PXP_TERMINATION_REQUEST BIT(0)
>> #define PXP_TERMINATION_COMPLETE BIT(1)
>> +
>> + spinlock_t lock; /* protects the objects list */
>> + struct list_head protected_objects;
>> };
>> #endif /* __INTEL_PXP_TYPES_H__ */
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index d5e502269a55..420412c08745 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -1756,6 +1756,26 @@ struct drm_i915_gem_object_param {
>> */
>> #define I915_OBJECT_PARAM (1ull << 32)
>> +/*
>> + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
>> + *
>> + * If set to true, buffer contents is expected to be protected by PXP
>> + * encryption and requires decryption for scan out and processing.
>> This is
>> + * only possible on platforms that have PXP enabled, on all other
>> scenarios
>> + * setting this flag will cause the ioctl to fail and return -ENODEV.
>> + *
>> + * The buffer contents are considered invalid after a PXP session
>> teardown.
>> + * It is recommended to use protected buffers only with contexts
>> created
>> + * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that will
>> enable
>> + * extra checks at submission time on the validity of the objects
>> involved,
>> + * which can lead to the following errors:
>> + *
>> + * -ENODEV: PXP session not currently active
>> + * -EIO: buffer has become invalid after a teardown event
>
>
> I was a bit confused on reading those comments. Maybe we should
> specify when they apply.
>
> My understanding is that you can get -ENODEV on object creation, while
> -EIO happens at execbuffer time.
>
> Did I get this right?
>
Both of them apply to execbuf. -ENODEV covers the case where the session
has been invalidated (i.e. PXP not considered currently active) but we
are still processing the event, so the object hasn't been marked as
invalid yet.
It is true however that -ENODEV can come from object creation as well if
the platform does not support PXP, so I'll make the distinction clear.
Daniele
>
> -Lionel
>
>
>> + */
>> +#define I915_OBJECT_PARAM_PROTECTED_CONTENT 0x0
>> +/* Must be kept compact -- no holes and well documented */
>> +
>> __u64 param;
>> /* Data value or pointer */
>
>
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer
2021-04-01 20:45 ` Daniele Ceraolo Spurio
@ 2021-04-20 14:40 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-20 14:40 UTC (permalink / raw)
To: Daniele Ceraolo Spurio
Cc: Bommu Krishnaiah, intel-gfx, Huang Sean Z, Chris Wilson
On Thu, Apr 01, 2021 at 01:45:20PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 4/1/2021 5:05 AM, Lionel Landwerlin wrote:
> > On 29/03/2021 01:57, Daniele Ceraolo Spurio wrote:
> > > From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > >
> > > This api allow user mode to create Protected buffers. Only contexts
> > > marked as protected are allowed to operate on protected buffers.
> > >
> > > We only allow setting the flags at creation time.
> > >
> > > All protected objects that have backing storage will be considered
> > > invalid when the session is destroyed and they won't be usable anymore.
> > >
> > > This is a rework of the original code by Bommu Krishnaiah. I've
> > > authorship unchanged since significant chunks have not been modified.
> > >
> > > v2: split context changes, fix defines and improve documentation
> > > (Chris),
> > > add object invalidation logic
> > > v3: fix spinlock definition and usage, only validate objects when
> > > they're first added to a context lut, only remove them once
> > > (Chris),
> > > make protected context flag not mandatory in protected object
> > > execbuf
> > > to avoid abuse (Lionel)
> > >
> > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> > > Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
> > > Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
> > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 ++++++++++--
> > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 16 ++++++++
> > > drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +++
> > > drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 ++++++
> > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 ++++++
> > > drivers/gpu/drm/i915/pxp/intel_pxp.c | 41 +++++++++++++++++++
> > > drivers/gpu/drm/i915/pxp/intel_pxp.h | 13 ++++++
> > > drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 5 +++
> > > include/uapi/drm/i915_drm.h | 20 +++++++++
> > > 9 files changed, 150 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > index 3ad3413c459f..d02e5938afbe 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > > @@ -5,6 +5,7 @@
> > > #include "gem/i915_gem_ioctls.h"
> > > #include "gem/i915_gem_region.h"
> > > +#include "pxp/intel_pxp.h"
> > > #include "i915_drv.h"
> > > #include "i915_user_extensions.h"
> > > @@ -13,7 +14,8 @@ static int
> > > i915_gem_create(struct drm_file *file,
> > > struct intel_memory_region *mr,
> > > u64 *size_p,
> > > - u32 *handle_p)
> > > + u32 *handle_p,
> > > + u64 user_flags)
> > > {
> > > struct drm_i915_gem_object *obj;
> > > u32 handle;
> > > @@ -35,12 +37,17 @@ i915_gem_create(struct drm_file *file,
> > > GEM_BUG_ON(size != obj->base.size);
> > > + obj->user_flags = user_flags;
> > > +
> > > ret = drm_gem_handle_create(file, &obj->base, &handle);
> > > /* drop reference from allocate - handle holds it now */
> > > i915_gem_object_put(obj);
> > > if (ret)
> > > return ret;
> > > + if (user_flags & I915_GEM_OBJECT_PROTECTED)
> > > + intel_pxp_object_add(obj);
> > > +
> > > *handle_p = handle;
> > > *size_p = size;
> > > return 0;
> > > @@ -89,11 +96,12 @@ i915_gem_dumb_create(struct drm_file *file,
> > > return i915_gem_create(file,
> > > intel_memory_region_by_type(to_i915(dev),
> > > mem_type),
> > > - &args->size, &args->handle);
> > > + &args->size, &args->handle, 0);
> > > }
> > > struct create_ext {
> > > struct drm_i915_private *i915;
> > > + unsigned long user_flags;
> > > };
> > > static int __create_setparam(struct drm_i915_gem_object_param *args,
> > > @@ -104,6 +112,19 @@ static int __create_setparam(struct
> > > drm_i915_gem_object_param *args,
> > > return -EINVAL;
> > > }
> > > + switch (lower_32_bits(args->param)) {
> > > + case I915_OBJECT_PARAM_PROTECTED_CONTENT:
> > > + if (!intel_pxp_is_enabled(&ext_data->i915->gt.pxp))
> > > + return -ENODEV;
> > > + if (args->size) {
> > > + return -EINVAL;
> > > + } else if (args->data) {
> > > + ext_data->user_flags |= I915_GEM_OBJECT_PROTECTED;
> > > + return 0;
> > > + }
> > > + break;
> > > + }
> > > +
> > > return -EINVAL;
> > > }
> > > @@ -148,5 +169,5 @@ i915_gem_create_ioctl(struct drm_device *dev,
> > > void *data,
> > > return i915_gem_create(file,
> > > intel_memory_region_by_type(i915,
> > > INTEL_MEMORY_SYSTEM),
> > > - &args->size, &args->handle);
> > > + &args->size, &args->handle, ext_data.user_flags);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > index 72c2470fcfe6..2fb6579ad301 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > @@ -20,6 +20,7 @@
> > > #include "gt/intel_gt_buffer_pool.h"
> > > #include "gt/intel_gt_pm.h"
> > > #include "gt/intel_ring.h"
> > > +#include "pxp/intel_pxp.h"
> > > #include "pxp/intel_pxp.h"
> > > @@ -839,6 +840,21 @@ static struct i915_vma *eb_lookup_vma(struct
> > > i915_execbuffer *eb, u32 handle)
> > > if (unlikely(!obj))
> > > return ERR_PTR(-ENOENT);
> > > + /*
> > > + * If the user has opted-in for protected-object tracking, make
> > > + * sure the object encryption can be used.
> > > + * We only need to do this when the object is first used with
> > > + * this context, because the context itself will be banned when
> > > + * the protected objects become invalid.
> > > + */
> > > + if (i915_gem_context_uses_protected_content(eb->gem_context) &&
> > > + i915_gem_object_is_protected(obj)) {
> > > + if (!intel_pxp_is_active(&vm->gt->pxp))
> > > + return ERR_PTR(-ENODEV);
> > > + if (!i915_gem_object_has_valid_protection(obj))
> > > + return ERR_PTR(-EIO);
> > > + }
> > > +
> > > vma = i915_vma_instance(obj, vm, NULL);
> > > if (IS_ERR(vma)) {
> > > i915_gem_object_put(obj);
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > > index ea74cbca95be..80ccefd641e8 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> > > @@ -25,6 +25,7 @@
> > > #include <linux/sched/mm.h>
> > > #include "display/intel_frontbuffer.h"
> > > +#include "pxp/intel_pxp.h"
> > > #include "i915_drv.h"
> > > #include "i915_gem_clflush.h"
> > > #include "i915_gem_context.h"
> > > @@ -70,6 +71,8 @@ void i915_gem_object_init(struct
> > > drm_i915_gem_object *obj,
> > > INIT_LIST_HEAD(&obj->lut_list);
> > > spin_lock_init(&obj->lut_lock);
> > > + INIT_LIST_HEAD(&obj->pxp_link);
> > > +
> > > spin_lock_init(&obj->mmo.lock);
> > > obj->mmo.offsets = RB_ROOT;
> > > @@ -232,6 +235,9 @@ static void __i915_gem_free_objects(struct
> > > drm_i915_private *i915,
> > > spin_unlock(&obj->vma.lock);
> > > }
> > > + if (i915_gem_object_has_valid_protection(obj))
> > > + intel_pxp_object_remove(obj);
> > > +
> > > __i915_gem_object_free_mmaps(obj);
> > > GEM_BUG_ON(!list_empty(&obj->lut_list));
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > > b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > > index 2ebd79537aea..61b101560352 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > > @@ -288,6 +288,18 @@ i915_gem_object_never_mmap(const struct
> > > drm_i915_gem_object *obj)
> > > return i915_gem_object_type_has(obj, I915_GEM_OBJECT_NO_MMAP);
> > > }
> > > +static inline bool
> > > +i915_gem_object_is_protected(const struct drm_i915_gem_object *obj)
> > > +{
> > > + return obj->user_flags & I915_GEM_OBJECT_PROTECTED;
> > > +}
> > > +
> > > +static inline bool
> > > +i915_gem_object_has_valid_protection(const struct
> > > drm_i915_gem_object *obj)
> > > +{
> > > + return i915_gem_object_is_protected(obj) &&
> > > !list_empty(&obj->pxp_link);
> > > +}
> > > +
> > > static inline bool
> > > i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
> > > {
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > index 8e485cb3343c..0d4bd2747375 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > > @@ -167,6 +167,11 @@ struct drm_i915_gem_object {
> > > } mmo;
> > > I915_SELFTEST_DECLARE(struct list_head st_link);
> > > + /**
> > > + * @user_flags: small set of booleans set by the user
> > > + */
> > > + unsigned long user_flags;
> > > +#define I915_GEM_OBJECT_PROTECTED BIT(0)
> > > unsigned long flags;
> > > #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
> > > @@ -286,6 +291,14 @@ struct drm_i915_gem_object {
> > > bool dirty:1;
> > > } mm;
> > > + /*
> > > + * When the PXP session is invalidated, we need to mark all
> > > protected
> > > + * objects as invalid. To easily do so we add them all to a
> > > list. The
> > > + * presence on the list is used to check if the encryption is
> > > valid or
> > > + * not.
> > > + */
> > > + struct list_head pxp_link;
> > > +
> > > /** Record of address bit 17 of each page at last unbind. */
> > > unsigned long *bit_17;
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > index cbc5249a1bf9..7f9902eac7ec 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > @@ -69,6 +69,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
> > > if (!HAS_PXP(gt->i915))
> > > return;
> > > + spin_lock_init(&pxp->lock);
> > > + INIT_LIST_HEAD(&pxp->protected_objects);
> > > +
> > > /*
> > > * we'll use the completion to check if there is a termination
> > > pending,
> > > * so we start it as completed and we reinit it when a termination
> > > @@ -173,11 +176,49 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp)
> > > intel_pxp_irq_disable(pxp);
> > > }
> > > +int intel_pxp_object_add(struct drm_i915_gem_object *obj)
> > > +{
> > > + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
> > > +
> > > + if (!intel_pxp_is_enabled(pxp))
> > > + return -ENODEV;
> > > +
> > > + if (!list_empty(&obj->pxp_link))
> > > + return -EEXIST;
> > > +
> > > + spin_lock_irq(&pxp->lock);
> > > + list_add(&obj->pxp_link, &pxp->protected_objects);
> > > + spin_unlock_irq(&pxp->lock);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
> > > +{
> > > + struct intel_pxp *pxp = &to_i915(obj->base.dev)->gt.pxp;
> > > +
> > > + if (!intel_pxp_is_enabled(pxp))
> > > + return;
> > > +
> > > + spin_lock_irq(&pxp->lock);
> > > + list_del_init(&obj->pxp_link);
> > > + spin_unlock_irq(&pxp->lock);
> > > +}
> > > +
> > > void intel_pxp_invalidate(struct intel_pxp *pxp)
> > > {
> > > struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> > > + struct drm_i915_gem_object *obj, *tmp;
> > > struct i915_gem_context *ctx, *cn;
> > > + /* delete objects that have been used with the invalidated
> > > session */
> > > + spin_lock_irq(&pxp->lock);
> > > + list_for_each_entry_safe(obj, tmp, &pxp->protected_objects,
> > > pxp_link) {
> > > + if (i915_gem_object_has_pages(obj))
> > > + list_del_init(&obj->pxp_link);
> > > + }
> > > + spin_unlock_irq(&pxp->lock);
> > > +
> > > /* ban all contexts marked as protected */
> > > spin_lock_irq(&i915->gem.contexts.lock);
> > > list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list,
> > > link) {
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > index 91c1a2056309..194b00149247 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > @@ -9,6 +9,8 @@
> > > #include "gt/intel_gt_types.h"
> > > #include "intel_pxp_types.h"
> > > +struct drm_i915_gem_object;
> > > +
> > > static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> > > {
> > > return container_of(pxp, struct intel_gt, pxp);
> > > @@ -33,6 +35,9 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
> > > void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> > > int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> > > +
> > > +int intel_pxp_object_add(struct drm_i915_gem_object *obj);
> > > +void intel_pxp_object_remove(struct drm_i915_gem_object *obj);
> > > void intel_pxp_invalidate(struct intel_pxp *pxp);
> > > #else
> > > static inline void intel_pxp_init(struct intel_pxp *pxp)
> > > @@ -47,6 +52,14 @@ static inline int
> > > intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> > > {
> > > return 0;
> > > }
> > > +
> > > +static inline int intel_pxp_object_add(struct drm_i915_gem_object *obj)
> > > +{
> > > + return 0;
> > > +}
> > > +static inline void intel_pxp_object_remove(struct
> > > drm_i915_gem_object *obj)
> > > +{
> > > +}
> > > #endif
> > > #endif /* __INTEL_PXP_H__ */
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > > index 6c9265fb8e4b..665704d7793e 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > > @@ -7,8 +7,10 @@
> > > #define __INTEL_PXP_TYPES_H__
> > > #include <linux/completion.h>
> > > +#include <linux/list.h>
> > > #include <linux/types.h>
> > > #include <linux/mutex.h>
> > > +#include <linux/spinlock.h>
> > > #include <linux/workqueue.h>
> > > struct intel_context;
> > > @@ -33,6 +35,9 @@ struct intel_pxp {
> > > u32 session_events; /* protected with gt->irq_lock */
> > > #define PXP_TERMINATION_REQUEST BIT(0)
> > > #define PXP_TERMINATION_COMPLETE BIT(1)
> > > +
> > > + spinlock_t lock; /* protects the objects list */
> > > + struct list_head protected_objects;
> > > };
> > > #endif /* __INTEL_PXP_TYPES_H__ */
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index d5e502269a55..420412c08745 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -1756,6 +1756,26 @@ struct drm_i915_gem_object_param {
> > > */
> > > #define I915_OBJECT_PARAM (1ull << 32)
> > > +/*
> > > + * I915_OBJECT_PARAM_PROTECTED_CONTENT:
> > > + *
> > > + * If set to true, buffer contents is expected to be protected by PXP
> > > + * encryption and requires decryption for scan out and processing.
> > > This is
> > > + * only possible on platforms that have PXP enabled, on all other
> > > scenarios
> > > + * setting this flag will cause the ioctl to fail and return -ENODEV.
> > > + *
> > > + * The buffer contents are considered invalid after a PXP session
> > > teardown.
> > > + * It is recommended to use protected buffers only with contexts
> > > created
> > > + * using the I915_CONTEXT_PARAM_PROTECTED_CONTENT flag, as that
> > > will enable
> > > + * extra checks at submission time on the validity of the objects
> > > involved,
> > > + * which can lead to the following errors:
> > > + *
> > > + * -ENODEV: PXP session not currently active
> > > + * -EIO: buffer has become invalid after a teardown event
> >
> >
> > I was a bit confused on reading those comments. Maybe we should specify
> > when they apply.
> >
> > My understanding is that you can get -ENODEV on object creation, while
> > -EIO happens at execbuffer time.
> >
> > Did I get this right?
> >
>
> Both of them apply to execbuf. -ENODEV covers the case where the session has
> been invalidated (i.e. PXP not considered currently active) but we are still
> processing the event, so the object hasn't been marked as invalid yet.
> It is true however that -ENODEV can come from object creation as well if the
> platform does not support PXP, so I'll make the distinction clear.
other than that I believe the patch is good for dri-devel.
It aligns with what we had agreed.
>
> Daniele
>
> >
> > -Lionel
> >
> >
> > > + */
> > > +#define I915_OBJECT_PARAM_PROTECTED_CONTENT 0x0
> > > +/* Must be kept compact -- no holes and well documented */
> > > +
> > > __u64 param;
> > > /* Data value or pointer */
> >
> >
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (12 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-20 14:48 ` Rodrigo Vivi
2021-04-27 10:43 ` Anshuman Gupta
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
` (8 subsequent siblings)
22 siblings, 2 replies; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Gaurav Kumar, Bommu Krishnaiah
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c6d7b6c054b5..b21bfb5be876 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -16,6 +16,7 @@
#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
@@ -971,7 +972,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1051,8 +1052,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
+ i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_plane_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fe42f4a4e4b..a0313d718905 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7234,6 +7234,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.29.2
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^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
@ 2021-04-20 14:48 ` Rodrigo Vivi
2021-04-20 22:00 ` Ville Syrjälä
2021-04-27 10:43 ` Anshuman Gupta
1 sibling, 1 reply; 62+ messages in thread
From: Rodrigo Vivi @ 2021-04-20 14:48 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jani Nikula, Ville Syrjälä,
uma.shankar
Cc: Gaurav Kumar, intel-gfx, Huang Sean Z, Bommu Krishnaiah
On Sun, Mar 28, 2021 at 03:57:06PM -0700, Daniele Ceraolo Spurio wrote:
> From: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PXP session is enabled.
> 2. Buffer object is protected.
>
> v2:
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> v3:
> - intel_pxp_gem_object_status() API changes.
>
> v4: use intel_pxp_is_active (Daniele)
> v5: rebase and use the new protected object status checker (Daniele)
>
> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c6d7b6c054b5..b21bfb5be876 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -16,6 +16,7 @@
> #include "intel_sprite.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "pxp/intel_pxp.h"
>
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> @@ -971,7 +972,7 @@ skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> + u32 keymsk, keymax, plane_surf;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -1051,8 +1052,15 @@ skl_program_plane(struct intel_plane *plane,
> * the control register just before the surface register.
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> +
> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> + i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
> + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> + else
> + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
This part looks right. But what should we do about the async_flip path?
Jani? Ville? Uma? thoughts?
> +
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> if (plane_state->scaler_id >= 0)
> skl_program_plane_scaler(plane, crtc_state, plane_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1fe42f4a4e4b..a0313d718905 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7234,6 +7234,7 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-20 14:48 ` Rodrigo Vivi
@ 2021-04-20 22:00 ` Ville Syrjälä
0 siblings, 0 replies; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-20 22:00 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Jani Nikula, Gaurav Kumar, intel-gfx, Huang Sean Z, Bommu Krishnaiah
On Tue, Apr 20, 2021 at 10:48:08AM -0400, Rodrigo Vivi wrote:
> On Sun, Mar 28, 2021 at 03:57:06PM -0700, Daniele Ceraolo Spurio wrote:
> > From: Anshuman Gupta <anshuman.gupta@intel.com>
> >
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> >
> > v2:
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> >
> > v4: use intel_pxp_is_active (Daniele)
> > v5: rebase and use the new protected object status checker (Daniele)
> >
> > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index c6d7b6c054b5..b21bfb5be876 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -16,6 +16,7 @@
> > #include "intel_sprite.h"
> > #include "skl_scaler.h"
> > #include "skl_universal_plane.h"
> > +#include "pxp/intel_pxp.h"
> >
> > static const u32 skl_plane_formats[] = {
> > DRM_FORMAT_C8,
> > @@ -971,7 +972,7 @@ skl_program_plane(struct intel_plane *plane,
> > u8 alpha = plane_state->hw.alpha >> 8;
> > u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > + u32 keymsk, keymax, plane_surf;
> > u32 plane_ctl = plane_state->ctl;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> > @@ -1051,8 +1052,15 @@ skl_program_plane(struct intel_plane *plane,
> > * the control register just before the surface register.
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > + i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
> > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > + else
> > + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
>
> This part looks right.
The &=~ thing is pointless.
> But what should we do about the async_flip path?
> Jani? Ville? Uma? thoughts?
Presumably it can't be actually changed by an async flip? So
probbly we want to track it in the plane_state and reject async
flips if it has changed.
>
> > +
> > + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >
> > if (plane_state->scaler_id >= 0)
> > skl_program_plane_scaler(plane, crtc_state, plane_state);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1fe42f4a4e4b..a0313d718905 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7234,6 +7234,7 @@ enum {
> > #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> > #define PLANE_SURF(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
> >
> > #define _PLANE_OFFSET_1_B 0x711a4
> > #define _PLANE_OFFSET_2_B 0x712a4
> > --
> > 2.29.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
---------------------------------------------------------------------
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^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
2021-04-20 14:48 ` Rodrigo Vivi
@ 2021-04-27 10:43 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
1 sibling, 1 reply; 62+ messages in thread
From: Anshuman Gupta @ 2021-04-27 10:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Gaurav Kumar, Bommu Krishnaiah
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
v5: rebase and use the new protected object status checker (Daniele)
v6: used plane state for plane_decryption to handle async flip
as suggested by Ville.
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
drivers/gpu/drm/i915/display/intel_display.c | 5 +++
.../drm/i915/display/intel_display_types.h | 3 ++
.../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
.../drm/i915/display/skl_universal_plane.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7bfb26ca0bd0..7057077a2b71 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_framebuffer *fb = new_plane_state->hw.fb;
if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
struct intel_plane *master_plane =
@@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
intel_plane_copy_uapi_to_hw_state(new_plane_state,
new_master_plane_state,
crtc);
+ new_plane_state->plane_decryption =
+ i915_gem_object_has_valid_protection(intel_fb_obj(fb));
new_plane_state->uapi.visible = false;
if (!new_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a10e26380ef3..55ab2d0b92d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
return -EINVAL;
}
+
+ /* plane decryption is allow to change only in synchronous flips */
+ if (old_plane_state->plane_decryption != new_plane_state->plane_decryption)
+ return -EINVAL;
}
return 0;
@@ -12350,6 +12354,7 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
+ intel_plane_read_hw_decryption(plane_state);
intel_set_plane_visible(crtc_state, plane_state, visible);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2e707c4dff5..76b3bb64a36a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -617,6 +617,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Plane pxp decryption state */
+ bool plane_decryption;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 75d3ca3dbb37..74489217e580 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -17,6 +17,7 @@
#include "intel_sprite.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
DRM_FORMAT_C8,
@@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1037,8 +1038,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
+ plane_state->plane_decryption)
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_plane_scaler(plane, crtc_state, plane_state);
@@ -2242,3 +2250,21 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
kfree(intel_fb);
}
+void intel_plane_read_hw_decryption(struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum intel_display_power_domain power_domain;
+ enum plane_id plane_id = plane->id;
+ intel_wakeref_t wakeref;
+
+ power_domain = POWER_DOMAIN_PIPE(plane->pipe);
+ wakeref = intel_display_power_get_if_enabled(i915, power_domain);
+ if (drm_WARN_ON(&i915->drm, !wakeref))
+ return;
+
+ plane_state->plane_decryption =
+ intel_de_read(i915, PLANE_SURF(plane->pipe, plane_id)) & PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_display_power_put(i915, power_domain, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
index 351040b64dc7..2b1d673f8bf5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
@@ -31,5 +31,6 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
+void intel_plane_read_hw_decryption(struct intel_plane_state *plane_state);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 740e97663fec..fbaf9199001d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7240,6 +7240,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-27 10:43 ` Anshuman Gupta
@ 2021-04-27 18:55 ` Ville Syrjälä
2021-04-28 11:25 ` Gupta, Anshuman
2021-04-30 7:01 ` Gupta, Anshuman
0 siblings, 2 replies; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-27 18:55 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: Gaurav Kumar, intel-gfx, Huang Sean Z, Bommu Krishnaiah
On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PXP session is enabled.
> 2. Buffer object is protected.
>
> v2:
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> v3:
> - intel_pxp_gem_object_status() API changes.
>
> v4: use intel_pxp_is_active (Daniele)
>
> v5: rebase and use the new protected object status checker (Daniele)
>
> v6: used plane state for plane_decryption to handle async flip
> as suggested by Ville.
>
> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> .../drm/i915/display/intel_display_types.h | 3 ++
> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
> .../drm/i915/display/skl_universal_plane.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 6 files changed, 42 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 7bfb26ca0bd0..7057077a2b71 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
>
> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> struct intel_plane *master_plane =
> @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state,
> intel_plane_copy_uapi_to_hw_state(new_plane_state,
> new_master_plane_state,
> crtc);
> + new_plane_state->plane_decryption =
> + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
>
> new_plane_state->uapi.visible = false;
> if (!new_crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a10e26380ef3..55ab2d0b92d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
> return -EINVAL;
> }
> +
> + /* plane decryption is allow to change only in synchronous flips */
> + if (old_plane_state->plane_decryption != new_plane_state->plane_decryption)
> + return -EINVAL;
> }
>
> return 0;
> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
>
> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> crtc_state = to_intel_crtc_state(crtc->base.state);
> + intel_plane_read_hw_decryption(plane_state);
We don't have real plane state readout anyway, so seems pointless.
>
> intel_set_plane_visible(crtc_state, plane_state, visible);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2e707c4dff5..76b3bb64a36a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -617,6 +617,9 @@ struct intel_plane_state {
>
> struct intel_fb_view view;
>
> + /* Plane pxp decryption state */
> + bool plane_decryption;
> +
It's all about the plane, so the plane_ prefix is entirely redundant.
Could just call it "decrypt" I guess.
> /* plane control register */
> u32 ctl;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 75d3ca3dbb37..74489217e580 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -17,6 +17,7 @@
> #include "intel_sprite.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "pxp/intel_pxp.h"
>
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> + u32 keymsk, keymax, plane_surf;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -1037,8 +1038,15 @@ skl_program_plane(struct intel_plane *plane,
> * the control register just before the surface register.
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> +
> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
That should all be part of the state computation. And you're missing
this in the .async_flip path totally.
> + plane_state->plane_decryption)
> + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> + else
> + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
This &=~ stuff is still 100% pointless.
So just
if (plane_state->decrypt)
surf_addr |= ...;
should do it. And I'd do it around the top of the function where
we calculate a bunch of the other register values. That keeps
most of the function clean of random ifs. Just after the
aux_dist calculation would seem like the correct spot to me.
> +
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> if (plane_state->scaler_id >= 0)
> skl_program_plane_scaler(plane, crtc_state, plane_state);
> @@ -2242,3 +2250,21 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> kfree(intel_fb);
> }
>
> +void intel_plane_read_hw_decryption(struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> + enum intel_display_power_domain power_domain;
> + enum plane_id plane_id = plane->id;
> + intel_wakeref_t wakeref;
> +
> + power_domain = POWER_DOMAIN_PIPE(plane->pipe);
> + wakeref = intel_display_power_get_if_enabled(i915, power_domain);
> + if (drm_WARN_ON(&i915->drm, !wakeref))
> + return;
> +
> + plane_state->plane_decryption =
> + intel_de_read(i915, PLANE_SURF(plane->pipe, plane_id)) & PLANE_SURF_DECRYPTION_ENABLED;
> +
> + intel_display_power_put(i915, power_domain, wakeref);
> +}
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> index 351040b64dc7..2b1d673f8bf5 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> @@ -31,5 +31,6 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
> bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> enum plane_id plane_id);
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
> +void intel_plane_read_hw_decryption(struct intel_plane_state *plane_state);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 740e97663fec..fbaf9199001d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7240,6 +7240,7 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
Could be just PLANE_SURF_DECRYPT or something along those lines.
>
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> --
> 2.26.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-27 18:55 ` Ville Syrjälä
@ 2021-04-28 11:25 ` Gupta, Anshuman
2021-04-28 12:03 ` Ville Syrjälä
2021-04-30 7:01 ` Gupta, Anshuman
1 sibling, 1 reply; 62+ messages in thread
From: Gupta, Anshuman @ 2021-04-28 11:25 UTC (permalink / raw)
To: Ville Syrjälä, Vivi, Rodrigo, Ceraolo Spurio, Daniele
Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, April 28, 2021 12:25 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
Thanks Ville for review, Below are some doubts with respect to pxp state.
>
> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> >
> > v2:
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> >
> > v4: use intel_pxp_is_active (Daniele)
> >
> > v5: rebase and use the new protected object status checker (Daniele)
> >
> > v6: used plane state for plane_decryption to handle async flip
> > as suggested by Ville.
> >
> > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> > drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> > .../drm/i915/display/intel_display_types.h | 3 ++
> > .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
> > .../drm/i915/display/skl_universal_plane.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 42 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 7bfb26ca0bd0..7057077a2b71 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> intel_atomic_state *state,
> > intel_atomic_get_old_crtc_state(state, crtc);
> > struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> >
> > if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> > struct intel_plane *master_plane =
> > @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
> intel_atomic_state *state,
> > intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > new_master_plane_state,
> > crtc);
> > + new_plane_state->plane_decryption =
> > + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> >
> > new_plane_state->uapi.visible = false;
> > if (!new_crtc_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a10e26380ef3..55ab2d0b92d8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
> > drm_dbg_kms(&i915->drm, "Color range cannot be
> changed in async flip\n");
> > return -EINVAL;
> > }
> > +
> > + /* plane decryption is allow to change only in synchronous flips
> */
> > + if (old_plane_state->plane_decryption != new_plane_state-
> >plane_decryption)
> > + return -EINVAL;
> > }
> >
> > return 0;
> > @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> > drm_i915_private *dev_priv)
> >
> > crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> > + intel_plane_read_hw_decryption(plane_state);
>
> We don't have real plane state readout anyway, so seems pointless.
>
> >
> > intel_set_plane_visible(crtc_state, plane_state, visible);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e2e707c4dff5..76b3bb64a36a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -617,6 +617,9 @@ struct intel_plane_state {
> >
> > struct intel_fb_view view;
> >
> > + /* Plane pxp decryption state */
> > + bool plane_decryption;
> > +
>
> It's all about the plane, so the plane_ prefix is entirely redundant.
> Could just call it "decrypt" I guess.
>
> > /* plane control register */
> > u32 ctl;
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 75d3ca3dbb37..74489217e580 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -17,6 +17,7 @@
> > #include "intel_sprite.h"
> > #include "skl_scaler.h"
> > #include "skl_universal_plane.h"
> > +#include "pxp/intel_pxp.h"
> >
> > static const u32 skl_plane_formats[] = {
> > DRM_FORMAT_C8,
> > @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> > u8 alpha = plane_state->hw.alpha >> 8;
> > u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > + u32 keymsk, keymax, plane_surf;
> > u32 plane_ctl = plane_state->ctl;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
> > skl_program_plane(struct intel_plane *plane,
> > * the control register just before the surface register.
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
>
> That should all be part of the state computation. And you're missing this in the
> .async_flip path totally.
Hi Ville / Rodrigo / Daniele,
Is it possible to check intel_pxp_is_active() in plane atomic check function to compute plane decryption state?
with my best knowledge session can be invalid at any time, Let's say in plane atomic check function pxp session was enabled
but while in atomic commit pxp session can be still disabled.
Please provide your inputs.
Thanks,
Anshuman Gupta.
>
> > + plane_state->plane_decryption)
> > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > + else
> > + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
>
> This &=~ stuff is still 100% pointless.
>
> So just
> if (plane_state->decrypt)
> surf_addr |= ...;
>
> should do it. And I'd do it around the top of the function where we calculate a
> bunch of the other register values. That keeps most of the function clean of
> random ifs. Just after the aux_dist calculation would seem like the correct spot
> to me.
>
> > +
> > + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >
> > if (plane_state->scaler_id >= 0)
> > skl_program_plane_scaler(plane, crtc_state, plane_state); @@
> > -2242,3 +2250,21 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > kfree(intel_fb);
> > }
> >
> > +void intel_plane_read_hw_decryption(struct intel_plane_state
> > +*plane_state) {
> > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > + enum intel_display_power_domain power_domain;
> > + enum plane_id plane_id = plane->id;
> > + intel_wakeref_t wakeref;
> > +
> > + power_domain = POWER_DOMAIN_PIPE(plane->pipe);
> > + wakeref = intel_display_power_get_if_enabled(i915, power_domain);
> > + if (drm_WARN_ON(&i915->drm, !wakeref))
> > + return;
> > +
> > + plane_state->plane_decryption =
> > + intel_de_read(i915, PLANE_SURF(plane->pipe, plane_id)) &
> > +PLANE_SURF_DECRYPTION_ENABLED;
> > +
> > + intel_display_power_put(i915, power_domain, wakeref); }
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > index 351040b64dc7..2b1d673f8bf5 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > @@ -31,5 +31,6 @@ int skl_calc_main_surface_offset(const struct
> > intel_plane_state *plane_state, bool icl_is_nv12_y_plane(struct
> drm_i915_private *dev_priv,
> > enum plane_id plane_id);
> > bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum
> > plane_id plane_id);
> > +void intel_plane_read_hw_decryption(struct intel_plane_state
> > +*plane_state);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 740e97663fec..fbaf9199001d
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7240,6 +7240,7 @@ enum {
> > #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A,
> _PLANE_SURF_3_B)
> > #define PLANE_SURF(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> Could be just PLANE_SURF_DECRYPT or something along those lines.
>
> >
> > #define _PLANE_OFFSET_1_B 0x711a4
> > #define _PLANE_OFFSET_2_B 0x712a4
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-28 11:25 ` Gupta, Anshuman
@ 2021-04-28 12:03 ` Ville Syrjälä
2021-04-28 17:32 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-28 12:03 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Wednesday, April 28, 2021 12:25 AM
> > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> > Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
> > <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> > Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> > Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
> Thanks Ville for review, Below are some doubts with respect to pxp state.
> >
> > On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> > > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > > It requires only to enable plane decryption support when following
> > > condition met.
> > > 1. PXP session is enabled.
> > > 2. Buffer object is protected.
> > >
> > > v2:
> > > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> > >
> > > v3:
> > > - intel_pxp_gem_object_status() API changes.
> > >
> > > v4: use intel_pxp_is_active (Daniele)
> > >
> > > v5: rebase and use the new protected object status checker (Daniele)
> > >
> > > v6: used plane state for plane_decryption to handle async flip
> > > as suggested by Ville.
> > >
> > > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > <daniele.ceraolospurio@intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> > > drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> > > .../drm/i915/display/intel_display_types.h | 3 ++
> > > .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
> > > .../drm/i915/display/skl_universal_plane.h | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 6 files changed, 42 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 7bfb26ca0bd0..7057077a2b71 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> > intel_atomic_state *state,
> > > intel_atomic_get_old_crtc_state(state, crtc);
> > > struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> > >
> > > if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> > > struct intel_plane *master_plane =
> > > @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
> > intel_atomic_state *state,
> > > intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > > new_master_plane_state,
> > > crtc);
> > > + new_plane_state->plane_decryption =
> > > + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> > >
> > > new_plane_state->uapi.visible = false;
> > > if (!new_crtc_state)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index a10e26380ef3..55ab2d0b92d8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> > intel_atomic_state *state)
> > > drm_dbg_kms(&i915->drm, "Color range cannot be
> > changed in async flip\n");
> > > return -EINVAL;
> > > }
> > > +
> > > + /* plane decryption is allow to change only in synchronous flips
> > */
> > > + if (old_plane_state->plane_decryption != new_plane_state-
> > >plane_decryption)
> > > + return -EINVAL;
> > > }
> > >
> > > return 0;
> > > @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> > > drm_i915_private *dev_priv)
> > >
> > > crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > crtc_state = to_intel_crtc_state(crtc->base.state);
> > > + intel_plane_read_hw_decryption(plane_state);
> >
> > We don't have real plane state readout anyway, so seems pointless.
> >
> > >
> > > intel_set_plane_visible(crtc_state, plane_state, visible);
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index e2e707c4dff5..76b3bb64a36a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -617,6 +617,9 @@ struct intel_plane_state {
> > >
> > > struct intel_fb_view view;
> > >
> > > + /* Plane pxp decryption state */
> > > + bool plane_decryption;
> > > +
> >
> > It's all about the plane, so the plane_ prefix is entirely redundant.
> > Could just call it "decrypt" I guess.
> >
> > > /* plane control register */
> > > u32 ctl;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 75d3ca3dbb37..74489217e580 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -17,6 +17,7 @@
> > > #include "intel_sprite.h"
> > > #include "skl_scaler.h"
> > > #include "skl_universal_plane.h"
> > > +#include "pxp/intel_pxp.h"
> > >
> > > static const u32 skl_plane_formats[] = {
> > > DRM_FORMAT_C8,
> > > @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> > > u8 alpha = plane_state->hw.alpha >> 8;
> > > u32 plane_color_ctl = 0, aux_dist = 0;
> > > unsigned long irqflags;
> > > - u32 keymsk, keymax;
> > > + u32 keymsk, keymax, plane_surf;
> > > u32 plane_ctl = plane_state->ctl;
> > >
> > > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
> > > skl_program_plane(struct intel_plane *plane,
> > > * the control register just before the surface register.
> > > */
> > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > > +
> > > + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> >
> > That should all be part of the state computation. And you're missing this in the
> > .async_flip path totally.
> Hi Ville / Rodrigo / Daniele,
> Is it possible to check intel_pxp_is_active() in plane atomic check function to compute plane decryption state?
> with my best knowledge session can be invalid at any time, Let's say in plane atomic check function pxp session was enabled
> but while in atomic commit pxp session can be still disabled.
I can be invalidated any time after the commit anyway. What happens in
that case?
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-28 12:03 ` Ville Syrjälä
@ 2021-04-28 17:32 ` Daniele Ceraolo Spurio
2021-04-28 20:04 ` Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-04-28 17:32 UTC (permalink / raw)
To: Ville Syrjälä, Gupta, Anshuman
Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
> On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
>>
>>> -----Original Message-----
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Sent: Wednesday, April 28, 2021 12:25 AM
>>> To: Gupta, Anshuman <anshuman.gupta@intel.com>
>>> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>>> Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
>>> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
>>> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
>>> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
>> Thanks Ville for review, Below are some doubts with respect to pxp state.
>>> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
>>>> Add support to enable/disable PLANE_SURF Decryption Request bit.
>>>> It requires only to enable plane decryption support when following
>>>> condition met.
>>>> 1. PXP session is enabled.
>>>> 2. Buffer object is protected.
>>>>
>>>> v2:
>>>> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>>>>
>>>> v3:
>>>> - intel_pxp_gem_object_status() API changes.
>>>>
>>>> v4: use intel_pxp_is_active (Daniele)
>>>>
>>>> v5: rebase and use the new protected object status checker (Daniele)
>>>>
>>>> v6: used plane state for plane_decryption to handle async flip
>>>> as suggested by Ville.
>>>>
>>>> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
>>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>>> Signed-off-by: Daniele Ceraolo Spurio
>>>> <daniele.ceraolospurio@intel.com>
>>>> ---
>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
>>>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
>>>> .../drm/i915/display/intel_display_types.h | 3 ++
>>>> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
>>>> .../drm/i915/display/skl_universal_plane.h | 1 +
>>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>>>> 6 files changed, 42 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> index 7bfb26ca0bd0..7057077a2b71 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
>>> intel_atomic_state *state,
>>>> intel_atomic_get_old_crtc_state(state, crtc);
>>>> struct intel_crtc_state *new_crtc_state =
>>>> intel_atomic_get_new_crtc_state(state, crtc);
>>>> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
>>>>
>>>> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
>>>> struct intel_plane *master_plane =
>>>> @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
>>> intel_atomic_state *state,
>>>> intel_plane_copy_uapi_to_hw_state(new_plane_state,
>>>> new_master_plane_state,
>>>> crtc);
>>>> + new_plane_state->plane_decryption =
>>>> + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
>>>>
>>>> new_plane_state->uapi.visible = false;
>>>> if (!new_crtc_state)
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index a10e26380ef3..55ab2d0b92d8 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
>>> intel_atomic_state *state)
>>>> drm_dbg_kms(&i915->drm, "Color range cannot be
>>> changed in async flip\n");
>>>> return -EINVAL;
>>>> }
>>>> +
>>>> + /* plane decryption is allow to change only in synchronous flips
>>> */
>>>> + if (old_plane_state->plane_decryption != new_plane_state-
>>>> plane_decryption)
>>>> + return -EINVAL;
>>>> }
>>>>
>>>> return 0;
>>>> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
>>>> drm_i915_private *dev_priv)
>>>>
>>>> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>>> crtc_state = to_intel_crtc_state(crtc->base.state);
>>>> + intel_plane_read_hw_decryption(plane_state);
>>> We don't have real plane state readout anyway, so seems pointless.
>>>
>>>> intel_set_plane_visible(crtc_state, plane_state, visible);
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index e2e707c4dff5..76b3bb64a36a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -617,6 +617,9 @@ struct intel_plane_state {
>>>>
>>>> struct intel_fb_view view;
>>>>
>>>> + /* Plane pxp decryption state */
>>>> + bool plane_decryption;
>>>> +
>>> It's all about the plane, so the plane_ prefix is entirely redundant.
>>> Could just call it "decrypt" I guess.
>>>
>>>> /* plane control register */
>>>> u32 ctl;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 75d3ca3dbb37..74489217e580 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -17,6 +17,7 @@
>>>> #include "intel_sprite.h"
>>>> #include "skl_scaler.h"
>>>> #include "skl_universal_plane.h"
>>>> +#include "pxp/intel_pxp.h"
>>>>
>>>> static const u32 skl_plane_formats[] = {
>>>> DRM_FORMAT_C8,
>>>> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
>>>> u8 alpha = plane_state->hw.alpha >> 8;
>>>> u32 plane_color_ctl = 0, aux_dist = 0;
>>>> unsigned long irqflags;
>>>> - u32 keymsk, keymax;
>>>> + u32 keymsk, keymax, plane_surf;
>>>> u32 plane_ctl = plane_state->ctl;
>>>>
>>>> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
>>>> skl_program_plane(struct intel_plane *plane,
>>>> * the control register just before the surface register.
>>>> */
>>>> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>>>> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>>>> - intel_plane_ggtt_offset(plane_state) + surf_addr);
>>>> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
>>>> +
>>>> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
>>> That should all be part of the state computation. And you're missing this in the
>>> .async_flip path totally.
>> Hi Ville / Rodrigo / Daniele,
>> Is it possible to check intel_pxp_is_active() in plane atomic check function to compute plane decryption state?
Yes, it should be possible to call that function from anywhere.
>> with my best knowledge session can be invalid at any time, Let's say in plane atomic check function pxp session was enabled
>> but while in atomic commit pxp session can be still disabled.
> I can be invalidated any time after the commit anyway. What happens in
> that case?
If we flip a PXP object after the relevant key has been invalidated we
just get garbage on the screen.
Note that it is understood that this is a race we can't completely close
given that the session invalidation can hit us at any time, the aim here
is just to make the window as small as we can and replace invalid
objects with a black frame where possible.
Daniele
_______________________________________________
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-28 17:32 ` Daniele Ceraolo Spurio
@ 2021-04-28 20:04 ` Ville Syrjälä
2021-04-28 20:39 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-28 20:04 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
> > On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
> >>
> >>> -----Original Message-----
> >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> Sent: Wednesday, April 28, 2021 12:25 AM
> >>> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> >>> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> >>> Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
> >>> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> >>> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> >>> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
> >> Thanks Ville for review, Below are some doubts with respect to pxp state.
> >>> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> >>>> Add support to enable/disable PLANE_SURF Decryption Request bit.
> >>>> It requires only to enable plane decryption support when following
> >>>> condition met.
> >>>> 1. PXP session is enabled.
> >>>> 2. Buffer object is protected.
> >>>>
> >>>> v2:
> >>>> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >>>>
> >>>> v3:
> >>>> - intel_pxp_gem_object_status() API changes.
> >>>>
> >>>> v4: use intel_pxp_is_active (Daniele)
> >>>>
> >>>> v5: rebase and use the new protected object status checker (Daniele)
> >>>>
> >>>> v6: used plane state for plane_decryption to handle async flip
> >>>> as suggested by Ville.
> >>>>
> >>>> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> >>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
> >>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> >>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> >>>> Signed-off-by: Daniele Ceraolo Spurio
> >>>> <daniele.ceraolospurio@intel.com>
> >>>> ---
> >>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> >>>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> >>>> .../drm/i915/display/intel_display_types.h | 3 ++
> >>>> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
> >>>> .../drm/i915/display/skl_universal_plane.h | 1 +
> >>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
> >>>> 6 files changed, 42 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> index 7bfb26ca0bd0..7057077a2b71 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> >>> intel_atomic_state *state,
> >>>> intel_atomic_get_old_crtc_state(state, crtc);
> >>>> struct intel_crtc_state *new_crtc_state =
> >>>> intel_atomic_get_new_crtc_state(state, crtc);
> >>>> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> >>>>
> >>>> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> >>>> struct intel_plane *master_plane =
> >>>> @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
> >>> intel_atomic_state *state,
> >>>> intel_plane_copy_uapi_to_hw_state(new_plane_state,
> >>>> new_master_plane_state,
> >>>> crtc);
> >>>> + new_plane_state->plane_decryption =
> >>>> + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> >>>>
> >>>> new_plane_state->uapi.visible = false;
> >>>> if (!new_crtc_state)
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >>>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>>> index a10e26380ef3..55ab2d0b92d8 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>>> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> >>> intel_atomic_state *state)
> >>>> drm_dbg_kms(&i915->drm, "Color range cannot be
> >>> changed in async flip\n");
> >>>> return -EINVAL;
> >>>> }
> >>>> +
> >>>> + /* plane decryption is allow to change only in synchronous flips
> >>> */
> >>>> + if (old_plane_state->plane_decryption != new_plane_state-
> >>>> plane_decryption)
> >>>> + return -EINVAL;
> >>>> }
> >>>>
> >>>> return 0;
> >>>> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> >>>> drm_i915_private *dev_priv)
> >>>>
> >>>> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> >>>> crtc_state = to_intel_crtc_state(crtc->base.state);
> >>>> + intel_plane_read_hw_decryption(plane_state);
> >>> We don't have real plane state readout anyway, so seems pointless.
> >>>
> >>>> intel_set_plane_visible(crtc_state, plane_state, visible);
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> index e2e707c4dff5..76b3bb64a36a 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>> @@ -617,6 +617,9 @@ struct intel_plane_state {
> >>>>
> >>>> struct intel_fb_view view;
> >>>>
> >>>> + /* Plane pxp decryption state */
> >>>> + bool plane_decryption;
> >>>> +
> >>> It's all about the plane, so the plane_ prefix is entirely redundant.
> >>> Could just call it "decrypt" I guess.
> >>>
> >>>> /* plane control register */
> >>>> u32 ctl;
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> index 75d3ca3dbb37..74489217e580 100644
> >>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>> @@ -17,6 +17,7 @@
> >>>> #include "intel_sprite.h"
> >>>> #include "skl_scaler.h"
> >>>> #include "skl_universal_plane.h"
> >>>> +#include "pxp/intel_pxp.h"
> >>>>
> >>>> static const u32 skl_plane_formats[] = {
> >>>> DRM_FORMAT_C8,
> >>>> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> >>>> u8 alpha = plane_state->hw.alpha >> 8;
> >>>> u32 plane_color_ctl = 0, aux_dist = 0;
> >>>> unsigned long irqflags;
> >>>> - u32 keymsk, keymax;
> >>>> + u32 keymsk, keymax, plane_surf;
> >>>> u32 plane_ctl = plane_state->ctl;
> >>>>
> >>>> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
> >>>> skl_program_plane(struct intel_plane *plane,
> >>>> * the control register just before the surface register.
> >>>> */
> >>>> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> >>>> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> >>>> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> >>>> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> >>>> +
> >>>> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> >>> That should all be part of the state computation. And you're missing this in the
> >>> .async_flip path totally.
> >> Hi Ville / Rodrigo / Daniele,
> >> Is it possible to check intel_pxp_is_active() in plane atomic check function to compute plane decryption state?
>
> Yes, it should be possible to call that function from anywhere.
>
> >> with my best knowledge session can be invalid at any time, Let's say in plane atomic check function pxp session was enabled
> >> but while in atomic commit pxp session can be still disabled.
> > I can be invalidated any time after the commit anyway. What happens in
> > that case?
>
> If we flip a PXP object after the relevant key has been invalidated we
> just get garbage on the screen.
> Note that it is understood that this is a race we can't completely close
> given that the session invalidation can hit us at any time,
It should be possible if the invalidation thingy gave us a warning
ahead of time and then waited for us to actually stop scanout.
> the aim here
> is just to make the window as small as we can and replace invalid
> objects with a black frame where possible.
>
> Daniele
>
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-28 20:04 ` Ville Syrjälä
@ 2021-04-28 20:39 ` Daniele Ceraolo Spurio
2021-04-30 6:56 ` Gupta, Anshuman
0 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-04-28 20:39 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
On 4/28/2021 1:04 PM, Ville Syrjälä wrote:
> On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
>>
>> On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
>>> On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
>>>>> -----Original Message-----
>>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>> Sent: Wednesday, April 28, 2021 12:25 AM
>>>>> To: Gupta, Anshuman <anshuman.gupta@intel.com>
>>>>> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>>>>> Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
>>>>> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
>>>>> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
>>>>> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
>>>> Thanks Ville for review, Below are some doubts with respect to pxp state.
>>>>> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
>>>>>> Add support to enable/disable PLANE_SURF Decryption Request bit.
>>>>>> It requires only to enable plane decryption support when following
>>>>>> condition met.
>>>>>> 1. PXP session is enabled.
>>>>>> 2. Buffer object is protected.
>>>>>>
>>>>>> v2:
>>>>>> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>>>>>>
>>>>>> v3:
>>>>>> - intel_pxp_gem_object_status() API changes.
>>>>>>
>>>>>> v4: use intel_pxp_is_active (Daniele)
>>>>>>
>>>>>> v5: rebase and use the new protected object status checker (Daniele)
>>>>>>
>>>>>> v6: used plane state for plane_decryption to handle async flip
>>>>>> as suggested by Ville.
>>>>>>
>>>>>> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>>>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>>>>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
>>>>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>>>>> Signed-off-by: Daniele Ceraolo Spurio
>>>>>> <daniele.ceraolospurio@intel.com>
>>>>>> ---
>>>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
>>>>>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
>>>>>> .../drm/i915/display/intel_display_types.h | 3 ++
>>>>>> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
>>>>>> .../drm/i915/display/skl_universal_plane.h | 1 +
>>>>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>>>>>> 6 files changed, 42 insertions(+), 3 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> index 7bfb26ca0bd0..7057077a2b71 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>>>>>> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
>>>>> intel_atomic_state *state,
>>>>>> intel_atomic_get_old_crtc_state(state, crtc);
>>>>>> struct intel_crtc_state *new_crtc_state =
>>>>>> intel_atomic_get_new_crtc_state(state, crtc);
>>>>>> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
>>>>>>
>>>>>> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
>>>>>> struct intel_plane *master_plane =
>>>>>> @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
>>>>> intel_atomic_state *state,
>>>>>> intel_plane_copy_uapi_to_hw_state(new_plane_state,
>>>>>> new_master_plane_state,
>>>>>> crtc);
>>>>>> + new_plane_state->plane_decryption =
>>>>>> + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
>>>>>>
>>>>>> new_plane_state->uapi.visible = false;
>>>>>> if (!new_crtc_state)
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> index a10e26380ef3..55ab2d0b92d8 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>>>> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
>>>>> intel_atomic_state *state)
>>>>>> drm_dbg_kms(&i915->drm, "Color range cannot be
>>>>> changed in async flip\n");
>>>>>> return -EINVAL;
>>>>>> }
>>>>>> +
>>>>>> + /* plane decryption is allow to change only in synchronous flips
>>>>> */
>>>>>> + if (old_plane_state->plane_decryption != new_plane_state-
>>>>>> plane_decryption)
>>>>>> + return -EINVAL;
>>>>>> }
>>>>>>
>>>>>> return 0;
>>>>>> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
>>>>>> drm_i915_private *dev_priv)
>>>>>>
>>>>>> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>>>>> crtc_state = to_intel_crtc_state(crtc->base.state);
>>>>>> + intel_plane_read_hw_decryption(plane_state);
>>>>> We don't have real plane state readout anyway, so seems pointless.
>>>>>
>>>>>> intel_set_plane_visible(crtc_state, plane_state, visible);
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>>> index e2e707c4dff5..76b3bb64a36a 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>>>> @@ -617,6 +617,9 @@ struct intel_plane_state {
>>>>>>
>>>>>> struct intel_fb_view view;
>>>>>>
>>>>>> + /* Plane pxp decryption state */
>>>>>> + bool plane_decryption;
>>>>>> +
>>>>> It's all about the plane, so the plane_ prefix is entirely redundant.
>>>>> Could just call it "decrypt" I guess.
>>>>>
>>>>>> /* plane control register */
>>>>>> u32 ctl;
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> index 75d3ca3dbb37..74489217e580 100644
>>>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>>> @@ -17,6 +17,7 @@
>>>>>> #include "intel_sprite.h"
>>>>>> #include "skl_scaler.h"
>>>>>> #include "skl_universal_plane.h"
>>>>>> +#include "pxp/intel_pxp.h"
>>>>>>
>>>>>> static const u32 skl_plane_formats[] = {
>>>>>> DRM_FORMAT_C8,
>>>>>> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
>>>>>> u8 alpha = plane_state->hw.alpha >> 8;
>>>>>> u32 plane_color_ctl = 0, aux_dist = 0;
>>>>>> unsigned long irqflags;
>>>>>> - u32 keymsk, keymax;
>>>>>> + u32 keymsk, keymax, plane_surf;
>>>>>> u32 plane_ctl = plane_state->ctl;
>>>>>>
>>>>>> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
>>>>>> skl_program_plane(struct intel_plane *plane,
>>>>>> * the control register just before the surface register.
>>>>>> */
>>>>>> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>>>>>> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>>>>>> - intel_plane_ggtt_offset(plane_state) + surf_addr);
>>>>>> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
>>>>>> +
>>>>>> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
>>>>> That should all be part of the state computation. And you're missing this in the
>>>>> .async_flip path totally.
>>>> Hi Ville / Rodrigo / Daniele,
>>>> Is it possible to check intel_pxp_is_active() in plane atomic check function to compute plane decryption state?
>> Yes, it should be possible to call that function from anywhere.
>>
>>>> with my best knowledge session can be invalid at any time, Let's say in plane atomic check function pxp session was enabled
>>>> but while in atomic commit pxp session can be still disabled.
>>> I can be invalidated any time after the commit anyway. What happens in
>>> that case?
>> If we flip a PXP object after the relevant key has been invalidated we
>> just get garbage on the screen.
>> Note that it is understood that this is a race we can't completely close
>> given that the session invalidation can hit us at any time,
> It should be possible if the invalidation thingy gave us a warning
> ahead of time and then waited for us to actually stop scanout.
Apart from suspend/resume scenarios, invalidations mainly occur when
there is an event that the HW perceives as something that could
compromise the security, so the keys are revoked immediately. There is a
GuC-controlled timer that can be enabled to have a grace period for the
user to remove the problem before revoking the keys (I was planning to
send that as a follow-up), but AFAIU there is no way to control that
from the CPU.
Daniele
>
>> the aim here
>> is just to make the window as small as we can and replace invalid
>> objects with a black frame where possible.
>>
>> Daniele
>>
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-28 20:39 ` Daniele Ceraolo Spurio
@ 2021-04-30 6:56 ` Gupta, Anshuman
2021-04-30 12:52 ` Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Gupta, Anshuman @ 2021-04-30 6:56 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Ville Syrjälä
Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
> -----Original Message-----
> From: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> Sent: Thursday, April 29, 2021 2:10 AM
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; intel-gfx@lists.freedesktop.org; Bommu, Krishnaiah
> <krishnaiah.bommu@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>
> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
>
>
>
> On 4/28/2021 1:04 PM, Ville Syrjälä wrote:
> > On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
> >>
> >> On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
> >>> On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
> >>>>> -----Original Message-----
> >>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>>> Sent: Wednesday, April 28, 2021 12:25 AM
> >>>>> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> >>>>> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
> >>>>> <rodrigo.vivi@intel.com>; Bommu, Krishnaiah
> >>>>> <krishnaiah.bommu@intel.com>; Huang Sean Z
> >>>>> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> >>>>> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> >>>>> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption
> >>>>> support
> >>>> Thanks Ville for review, Below are some doubts with respect to pxp state.
> >>>>> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> >>>>>> Add support to enable/disable PLANE_SURF Decryption Request bit.
> >>>>>> It requires only to enable plane decryption support when
> >>>>>> following condition met.
> >>>>>> 1. PXP session is enabled.
> >>>>>> 2. Buffer object is protected.
> >>>>>>
> >>>>>> v2:
> >>>>>> - Used gen fb obj user_flags instead gem_object_metadata.
> >>>>>> [Krishna]
> >>>>>>
> >>>>>> v3:
> >>>>>> - intel_pxp_gem_object_status() API changes.
> >>>>>>
> >>>>>> v4: use intel_pxp_is_active (Daniele)
> >>>>>>
> >>>>>> v5: rebase and use the new protected object status checker
> >>>>>> (Daniele)
> >>>>>>
> >>>>>> v6: used plane state for plane_decryption to handle async flip
> >>>>>> as suggested by Ville.
> >>>>>>
> >>>>>> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> >>>>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
> >>>>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> >>>>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> >>>>>> Signed-off-by: Daniele Ceraolo Spurio
> >>>>>> <daniele.ceraolospurio@intel.com>
> >>>>>> ---
> >>>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> >>>>>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> >>>>>> .../drm/i915/display/intel_display_types.h | 3 ++
> >>>>>> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++-
> -
> >>>>>> .../drm/i915/display/skl_universal_plane.h | 1 +
> >>>>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
> >>>>>> 6 files changed, 42 insertions(+), 3 deletions(-)
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>>>> index 7bfb26ca0bd0..7057077a2b71 100644
> >>>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> >>>>>> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> >>>>> intel_atomic_state *state,
> >>>>>> intel_atomic_get_old_crtc_state(state, crtc);
> >>>>>> struct intel_crtc_state *new_crtc_state =
> >>>>>> intel_atomic_get_new_crtc_state(state, crtc);
> >>>>>> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> >>>>>>
> >>>>>> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> >>>>>> struct intel_plane *master_plane = @@ -409,6 +410,8
> @@ int
> >>>>>> intel_plane_atomic_check(struct
> >>>>> intel_atomic_state *state,
> >>>>>> intel_plane_copy_uapi_to_hw_state(new_plane_state,
> >>>>>> new_master_plane_state,
> >>>>>> crtc);
> >>>>>> + new_plane_state->plane_decryption =
> >>>>>> +
> i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> >>>>>>
> >>>>>> new_plane_state->uapi.visible = false;
> >>>>>> if (!new_crtc_state)
> >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>> index a10e26380ef3..55ab2d0b92d8 100644
> >>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>>>>> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> >>>>> intel_atomic_state *state)
> >>>>>> drm_dbg_kms(&i915->drm, "Color range
> cannot be
> >>>>> changed in async flip\n");
> >>>>>> return -EINVAL;
> >>>>>> }
> >>>>>> +
> >>>>>> + /* plane decryption is allow to change only in
> synchronous
> >>>>>> +flips
> >>>>> */
> >>>>>> + if (old_plane_state->plane_decryption !=
> new_plane_state-
> >>>>>> plane_decryption)
> >>>>>> + return -EINVAL;
> >>>>>> }
> >>>>>>
> >>>>>> return 0;
> >>>>>> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> >>>>>> drm_i915_private *dev_priv)
> >>>>>>
> >>>>>> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> >>>>>> crtc_state = to_intel_crtc_state(crtc->base.state);
> >>>>>> + intel_plane_read_hw_decryption(plane_state);
> >>>>> We don't have real plane state readout anyway, so seems pointless.
> >>>>>
> >>>>>> intel_set_plane_visible(crtc_state, plane_state, visible);
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>>>> index e2e707c4dff5..76b3bb64a36a 100644
> >>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>>>>> @@ -617,6 +617,9 @@ struct intel_plane_state {
> >>>>>>
> >>>>>> struct intel_fb_view view;
> >>>>>>
> >>>>>> + /* Plane pxp decryption state */
> >>>>>> + bool plane_decryption;
> >>>>>> +
> >>>>> It's all about the plane, so the plane_ prefix is entirely redundant.
> >>>>> Could just call it "decrypt" I guess.
> >>>>>
> >>>>>> /* plane control register */
> >>>>>> u32 ctl;
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>>>> index 75d3ca3dbb37..74489217e580 100644
> >>>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >>>>>> @@ -17,6 +17,7 @@
> >>>>>> #include "intel_sprite.h"
> >>>>>> #include "skl_scaler.h"
> >>>>>> #include "skl_universal_plane.h"
> >>>>>> +#include "pxp/intel_pxp.h"
> >>>>>>
> >>>>>> static const u32 skl_plane_formats[] = {
> >>>>>> DRM_FORMAT_C8,
> >>>>>> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> >>>>>> u8 alpha = plane_state->hw.alpha >> 8;
> >>>>>> u32 plane_color_ctl = 0, aux_dist = 0;
> >>>>>> unsigned long irqflags;
> >>>>>> - u32 keymsk, keymax;
> >>>>>> + u32 keymsk, keymax, plane_surf;
> >>>>>> u32 plane_ctl = plane_state->ctl;
> >>>>>>
> >>>>>> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8
> >>>>>> +1038,15 @@ skl_program_plane(struct intel_plane *plane,
> >>>>>> * the control register just before the surface register.
> >>>>>> */
> >>>>>> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id),
> plane_ctl);
> >>>>>> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> >>>>>> - intel_plane_ggtt_offset(plane_state) +
> surf_addr);
> >>>>>> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> >>>>>> +
> >>>>>> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> >>>>> That should all be part of the state computation. And you're
> >>>>> missing this in the .async_flip path totally.
> >>>> Hi Ville / Rodrigo / Daniele,
> >>>> Is it possible to check intel_pxp_is_active() in plane atomic check function
> to compute plane decryption state?
> >> Yes, it should be possible to call that function from anywhere.
> >>
> >>>> with my best knowledge session can be invalid at any time, Let's
> >>>> say in plane atomic check function pxp session was enabled but while in
> atomic commit pxp session can be still disabled.
> >>> I can be invalidated any time after the commit anyway. What happens
> >>> in that case?
> >> If we flip a PXP object after the relevant key has been invalidated
> >> we just get garbage on the screen.
> >> Note that it is understood that this is a race we can't completely
> >> close given that the session invalidation can hit us at any time,
> > It should be possible if the invalidation thingy gave us a warning
> > ahead of time and then waited for us to actually stop scanout.
>
> Apart from suspend/resume scenarios, invalidations mainly occur when there is
> an event that the HW perceives as something that could compromise the
> security, so the keys are revoked immediately. There is a GuC-controlled timer
> that can be enabled to have a grace period for the user to remove the problem
> before revoking the keys (I was planning to send that as a follow-up), but AFAIU
> there is no way to control that from the CPU.
>
> Daniele
AFAIU with respect to inputs from Ville and Daniele, I can think of something like below ,
Compute plane state by checking both PXP session is enabled and Buffer object is protected
plane_state->plane_decryption = intel_pxp_is_active() && i915_gem_object_has_valid_protection()
and let's check the whether pxp session is still valid before setting the plane decryption bit.
If (plane_state->plane_decryption = = intel_pxp_is_active )
plane_surf |= PLANE_SURF_DECRYPTION_ENABLED
else
display black pixels
Please provide yours opinion if above approach is correct ?
Thanks,
Anshuman Gupta.
>
> >
> >> the aim here
> >> is just to make the window as small as we can and replace invalid
> >> objects with a black frame where possible.
> >>
> >> Daniele
> >>
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-30 6:56 ` Gupta, Anshuman
@ 2021-04-30 12:52 ` Ville Syrjälä
0 siblings, 0 replies; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-30 12:52 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
On Fri, Apr 30, 2021 at 06:56:10AM +0000, Gupta, Anshuman wrote:
>
>
> > -----Original Message-----
> > From: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> > Sent: Thursday, April 29, 2021 2:10 AM
> > To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Vivi, Rodrigo
> > <rodrigo.vivi@intel.com>; intel-gfx@lists.freedesktop.org; Bommu, Krishnaiah
> > <krishnaiah.bommu@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>
> > Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
> >
> >
> >
> > On 4/28/2021 1:04 PM, Ville Syrjälä wrote:
> > > On Wed, Apr 28, 2021 at 10:32:46AM -0700, Daniele Ceraolo Spurio wrote:
> > >>
> > >> On 4/28/2021 5:03 AM, Ville Syrjälä wrote:
> > >>> On Wed, Apr 28, 2021 at 11:25:23AM +0000, Gupta, Anshuman wrote:
> > >>>>> -----Original Message-----
> > >>>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>>>> Sent: Wednesday, April 28, 2021 12:25 AM
> > >>>>> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > >>>>> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
> > >>>>> <rodrigo.vivi@intel.com>; Bommu, Krishnaiah
> > >>>>> <krishnaiah.bommu@intel.com>; Huang Sean Z
> > >>>>> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> > >>>>> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> > >>>>> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption
> > >>>>> support
> > >>>> Thanks Ville for review, Below are some doubts with respect to pxp state.
> > >>>>> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> > >>>>>> Add support to enable/disable PLANE_SURF Decryption Request bit.
> > >>>>>> It requires only to enable plane decryption support when
> > >>>>>> following condition met.
> > >>>>>> 1. PXP session is enabled.
> > >>>>>> 2. Buffer object is protected.
> > >>>>>>
> > >>>>>> v2:
> > >>>>>> - Used gen fb obj user_flags instead gem_object_metadata.
> > >>>>>> [Krishna]
> > >>>>>>
> > >>>>>> v3:
> > >>>>>> - intel_pxp_gem_object_status() API changes.
> > >>>>>>
> > >>>>>> v4: use intel_pxp_is_active (Daniele)
> > >>>>>>
> > >>>>>> v5: rebase and use the new protected object status checker
> > >>>>>> (Daniele)
> > >>>>>>
> > >>>>>> v6: used plane state for plane_decryption to handle async flip
> > >>>>>> as suggested by Ville.
> > >>>>>>
> > >>>>>> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > >>>>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
> > >>>>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > >>>>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > >>>>>> Signed-off-by: Daniele Ceraolo Spurio
> > >>>>>> <daniele.ceraolospurio@intel.com>
> > >>>>>> ---
> > >>>>>> .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> > >>>>>> drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> > >>>>>> .../drm/i915/display/intel_display_types.h | 3 ++
> > >>>>>> .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++-
> > -
> > >>>>>> .../drm/i915/display/skl_universal_plane.h | 1 +
> > >>>>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
> > >>>>>> 6 files changed, 42 insertions(+), 3 deletions(-)
> > >>>>>>
> > >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >>>>>> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >>>>>> index 7bfb26ca0bd0..7057077a2b71 100644
> > >>>>>> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > >>>>>> @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> > >>>>> intel_atomic_state *state,
> > >>>>>> intel_atomic_get_old_crtc_state(state, crtc);
> > >>>>>> struct intel_crtc_state *new_crtc_state =
> > >>>>>> intel_atomic_get_new_crtc_state(state, crtc);
> > >>>>>> + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> > >>>>>>
> > >>>>>> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> > >>>>>> struct intel_plane *master_plane = @@ -409,6 +410,8
> > @@ int
> > >>>>>> intel_plane_atomic_check(struct
> > >>>>> intel_atomic_state *state,
> > >>>>>> intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > >>>>>> new_master_plane_state,
> > >>>>>> crtc);
> > >>>>>> + new_plane_state->plane_decryption =
> > >>>>>> +
> > i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> > >>>>>>
> > >>>>>> new_plane_state->uapi.visible = false;
> > >>>>>> if (!new_crtc_state)
> > >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>>> b/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>>> index a10e26380ef3..55ab2d0b92d8 100644
> > >>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > >>>>>> @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> > >>>>> intel_atomic_state *state)
> > >>>>>> drm_dbg_kms(&i915->drm, "Color range
> > cannot be
> > >>>>> changed in async flip\n");
> > >>>>>> return -EINVAL;
> > >>>>>> }
> > >>>>>> +
> > >>>>>> + /* plane decryption is allow to change only in
> > synchronous
> > >>>>>> +flips
> > >>>>> */
> > >>>>>> + if (old_plane_state->plane_decryption !=
> > new_plane_state-
> > >>>>>> plane_decryption)
> > >>>>>> + return -EINVAL;
> > >>>>>> }
> > >>>>>>
> > >>>>>> return 0;
> > >>>>>> @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> > >>>>>> drm_i915_private *dev_priv)
> > >>>>>>
> > >>>>>> crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > >>>>>> crtc_state = to_intel_crtc_state(crtc->base.state);
> > >>>>>> + intel_plane_read_hw_decryption(plane_state);
> > >>>>> We don't have real plane state readout anyway, so seems pointless.
> > >>>>>
> > >>>>>> intel_set_plane_visible(crtc_state, plane_state, visible);
> > >>>>>>
> > >>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > >>>>>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> > >>>>>> index e2e707c4dff5..76b3bb64a36a 100644
> > >>>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > >>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > >>>>>> @@ -617,6 +617,9 @@ struct intel_plane_state {
> > >>>>>>
> > >>>>>> struct intel_fb_view view;
> > >>>>>>
> > >>>>>> + /* Plane pxp decryption state */
> > >>>>>> + bool plane_decryption;
> > >>>>>> +
> > >>>>> It's all about the plane, so the plane_ prefix is entirely redundant.
> > >>>>> Could just call it "decrypt" I guess.
> > >>>>>
> > >>>>>> /* plane control register */
> > >>>>>> u32 ctl;
> > >>>>>>
> > >>>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > >>>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > >>>>>> index 75d3ca3dbb37..74489217e580 100644
> > >>>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > >>>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > >>>>>> @@ -17,6 +17,7 @@
> > >>>>>> #include "intel_sprite.h"
> > >>>>>> #include "skl_scaler.h"
> > >>>>>> #include "skl_universal_plane.h"
> > >>>>>> +#include "pxp/intel_pxp.h"
> > >>>>>>
> > >>>>>> static const u32 skl_plane_formats[] = {
> > >>>>>> DRM_FORMAT_C8,
> > >>>>>> @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> > >>>>>> u8 alpha = plane_state->hw.alpha >> 8;
> > >>>>>> u32 plane_color_ctl = 0, aux_dist = 0;
> > >>>>>> unsigned long irqflags;
> > >>>>>> - u32 keymsk, keymax;
> > >>>>>> + u32 keymsk, keymax, plane_surf;
> > >>>>>> u32 plane_ctl = plane_state->ctl;
> > >>>>>>
> > >>>>>> plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8
> > >>>>>> +1038,15 @@ skl_program_plane(struct intel_plane *plane,
> > >>>>>> * the control register just before the surface register.
> > >>>>>> */
> > >>>>>> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id),
> > plane_ctl);
> > >>>>>> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > >>>>>> - intel_plane_ggtt_offset(plane_state) +
> > surf_addr);
> > >>>>>> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > >>>>>> +
> > >>>>>> + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > >>>>> That should all be part of the state computation. And you're
> > >>>>> missing this in the .async_flip path totally.
> > >>>> Hi Ville / Rodrigo / Daniele,
> > >>>> Is it possible to check intel_pxp_is_active() in plane atomic check function
> > to compute plane decryption state?
> > >> Yes, it should be possible to call that function from anywhere.
> > >>
> > >>>> with my best knowledge session can be invalid at any time, Let's
> > >>>> say in plane atomic check function pxp session was enabled but while in
> > atomic commit pxp session can be still disabled.
> > >>> I can be invalidated any time after the commit anyway. What happens
> > >>> in that case?
> > >> If we flip a PXP object after the relevant key has been invalidated
> > >> we just get garbage on the screen.
> > >> Note that it is understood that this is a race we can't completely
> > >> close given that the session invalidation can hit us at any time,
> > > It should be possible if the invalidation thingy gave us a warning
> > > ahead of time and then waited for us to actually stop scanout.
> >
> > Apart from suspend/resume scenarios, invalidations mainly occur when there is
> > an event that the HW perceives as something that could compromise the
> > security, so the keys are revoked immediately. There is a GuC-controlled timer
> > that can be enabled to have a grace period for the user to remove the problem
> > before revoking the keys (I was planning to send that as a follow-up), but AFAIU
> > there is no way to control that from the CPU.
> >
> > Daniele
> AFAIU with respect to inputs from Ville and Daniele, I can think of something like below ,
> Compute plane state by checking both PXP session is enabled and Buffer object is protected
>
> plane_state->plane_decryption = intel_pxp_is_active() && i915_gem_object_has_valid_protection()
>
> and let's check the whether pxp session is still valid before setting the plane decryption bit.
>
> If (plane_state->plane_decryption = = intel_pxp_is_active )
> plane_surf |= PLANE_SURF_DECRYPTION_ENABLED
> else
> display black pixels
>
> Please provide yours opinion if above approach is correct ?
I think we need something like
plane_state->decrypt = bo_is_encrypted();
plane_state->force_black = plane_state->decrypt && pxp_is_bork;
The other problem with this approach is that it still totally depends on
userspace submitting a new flip/update on this specific plane. To make
it a bit more robust we should perhaps track which planes are scanning
out encrypted stuff and force all of them to update if things got
revoked. But we can think about that more later.
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
2021-04-27 18:55 ` Ville Syrjälä
2021-04-28 11:25 ` Gupta, Anshuman
@ 2021-04-30 7:01 ` Gupta, Anshuman
1 sibling, 0 replies; 62+ messages in thread
From: Gupta, Anshuman @ 2021-04-30 7:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Bommu, Krishnaiah, intel-gfx, Gaurav, Kumar
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, April 28, 2021 12:25 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Huang Sean Z
> <sean.z.huang@intel.com>; Gaurav, Kumar <kumar.gaurav@intel.com>;
> Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support
>
> On Tue, Apr 27, 2021 at 04:13:11PM +0530, Anshuman Gupta wrote:
> > Add support to enable/disable PLANE_SURF Decryption Request bit.
> > It requires only to enable plane decryption support when following
> > condition met.
> > 1. PXP session is enabled.
> > 2. Buffer object is protected.
> >
> > v2:
> > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> >
> > v3:
> > - intel_pxp_gem_object_status() API changes.
> >
> > v4: use intel_pxp_is_active (Daniele)
> >
> > v5: rebase and use the new protected object status checker (Daniele)
> >
> > v6: used plane state for plane_decryption to handle async flip
> > as suggested by Ville.
> >
> > Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Huang Sean Z <sean.z.huang@intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
> > drivers/gpu/drm/i915/display/intel_display.c | 5 +++
> > .../drm/i915/display/intel_display_types.h | 3 ++
> > .../drm/i915/display/skl_universal_plane.c | 32 +++++++++++++++++--
> > .../drm/i915/display/skl_universal_plane.h | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 42 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 7bfb26ca0bd0..7057077a2b71 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -394,6 +394,7 @@ int intel_plane_atomic_check(struct
> intel_atomic_state *state,
> > intel_atomic_get_old_crtc_state(state, crtc);
> > struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + const struct drm_framebuffer *fb = new_plane_state->hw.fb;
> >
> > if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> > struct intel_plane *master_plane =
> > @@ -409,6 +410,8 @@ int intel_plane_atomic_check(struct
> intel_atomic_state *state,
> > intel_plane_copy_uapi_to_hw_state(new_plane_state,
> > new_master_plane_state,
> > crtc);
> > + new_plane_state->plane_decryption =
> > + i915_gem_object_has_valid_protection(intel_fb_obj(fb));
> >
> > new_plane_state->uapi.visible = false;
> > if (!new_crtc_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index a10e26380ef3..55ab2d0b92d8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9367,6 +9367,10 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
> > drm_dbg_kms(&i915->drm, "Color range cannot be
> changed in async flip\n");
> > return -EINVAL;
> > }
> > +
> > + /* plane decryption is allow to change only in synchronous flips
> */
> > + if (old_plane_state->plane_decryption != new_plane_state-
> >plane_decryption)
> > + return -EINVAL;
> > }
> >
> > return 0;
> > @@ -12350,6 +12354,7 @@ static void readout_plane_state(struct
> > drm_i915_private *dev_priv)
> >
> > crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> > + intel_plane_read_hw_decryption(plane_state);
>
> We don't have real plane state readout anyway, so seems pointless.
could u please guide me the correct place to read the old plane decrypt
State, some where we do need to populate the plane decrypt state with plane
surface register decrypt bit.
How about plane->get_hw_state ?
Thanks,
Anshuman Gupta.
>
> >
> > intel_set_plane_visible(crtc_state, plane_state, visible);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e2e707c4dff5..76b3bb64a36a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -617,6 +617,9 @@ struct intel_plane_state {
> >
> > struct intel_fb_view view;
> >
> > + /* Plane pxp decryption state */
> > + bool plane_decryption;
> > +
>
> It's all about the plane, so the plane_ prefix is entirely redundant.
> Could just call it "decrypt" I guess.
>
> > /* plane control register */
> > u32 ctl;
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 75d3ca3dbb37..74489217e580 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -17,6 +17,7 @@
> > #include "intel_sprite.h"
> > #include "skl_scaler.h"
> > #include "skl_universal_plane.h"
> > +#include "pxp/intel_pxp.h"
> >
> > static const u32 skl_plane_formats[] = {
> > DRM_FORMAT_C8,
> > @@ -956,7 +957,7 @@ skl_program_plane(struct intel_plane *plane,
> > u8 alpha = plane_state->hw.alpha >> 8;
> > u32 plane_color_ctl = 0, aux_dist = 0;
> > unsigned long irqflags;
> > - u32 keymsk, keymax;
> > + u32 keymsk, keymax, plane_surf;
> > u32 plane_ctl = plane_state->ctl;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1037,8 +1038,15 @@
> > skl_program_plane(struct intel_plane *plane,
> > * the control register just before the surface register.
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > - intel_plane_ggtt_offset(plane_state) + surf_addr);
> > + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > +
> > + if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
>
> That should all be part of the state computation. And you're missing this in the
> .async_flip path totally.
>
> > + plane_state->plane_decryption)
> > + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > + else
> > + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
>
> This &=~ stuff is still 100% pointless.
>
> So just
> if (plane_state->decrypt)
> surf_addr |= ...;
>
> should do it. And I'd do it around the top of the function where we calculate a
> bunch of the other register values. That keeps most of the function clean of
> random ifs. Just after the aux_dist calculation would seem like the correct spot
> to me.
>
> > +
> > + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >
> > if (plane_state->scaler_id >= 0)
> > skl_program_plane_scaler(plane, crtc_state, plane_state); @@
> > -2242,3 +2250,21 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > kfree(intel_fb);
> > }
> >
> > +void intel_plane_read_hw_decryption(struct intel_plane_state
> > +*plane_state) {
> > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> > + enum intel_display_power_domain power_domain;
> > + enum plane_id plane_id = plane->id;
> > + intel_wakeref_t wakeref;
> > +
> > + power_domain = POWER_DOMAIN_PIPE(plane->pipe);
> > + wakeref = intel_display_power_get_if_enabled(i915, power_domain);
> > + if (drm_WARN_ON(&i915->drm, !wakeref))
> > + return;
> > +
> > + plane_state->plane_decryption =
> > + intel_de_read(i915, PLANE_SURF(plane->pipe, plane_id)) &
> > +PLANE_SURF_DECRYPTION_ENABLED;
> > +
> > + intel_display_power_put(i915, power_domain, wakeref); }
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > index 351040b64dc7..2b1d673f8bf5 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> > @@ -31,5 +31,6 @@ int skl_calc_main_surface_offset(const struct
> > intel_plane_state *plane_state, bool icl_is_nv12_y_plane(struct
> drm_i915_private *dev_priv,
> > enum plane_id plane_id);
> > bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum
> > plane_id plane_id);
> > +void intel_plane_read_hw_decryption(struct intel_plane_state
> > +*plane_state);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 740e97663fec..fbaf9199001d
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7240,6 +7240,7 @@ enum {
> > #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A,
> _PLANE_SURF_3_B)
> > #define PLANE_SURF(pipe, plane) \
> > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> > +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> Could be just PLANE_SURF_DECRYPT or something along those lines.
>
> >
> > #define _PLANE_OFFSET_1_B 0x711a4
> > #define _PLANE_OFFSET_2_B 0x712a4
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (13 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-04-27 10:45 ` Anshuman Gupta
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
` (7 subsequent siblings)
22 siblings, 1 reply; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Gaurav Kumar
From: Anshuman Gupta <anshuman.gupta@intel.com>
When protected sufaces has flipped and pxp session is disabled
display black pixels by using plane color CTM correction.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Cc: Shankar Uma <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 40 +++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++++
2 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index b21bfb5be876..e7a55c7233cd 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -949,6 +949,33 @@ skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
return 0;
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1053,13 +1080,22 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
- i915_gem_object_has_valid_protection(intel_fb_obj(fb)))
+ i915_gem_object_has_valid_protection(intel_fb_obj(fb))) {
plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
- else
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else if (i915_gem_object_is_protected(intel_fb_obj(fb))) {
+ intel_load_plane_csc_black(plane);
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else {
plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ }
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
+ plane_color_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0313d718905..35cd81429b97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7113,6 +7113,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
@@ -11185,6 +11186,51 @@ enum skl_power_gate {
_PAL_PREC_MULTI_SEG_DATA_A, \
_PAL_PREC_MULTI_SEG_DATA_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
2.29.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
@ 2021-04-27 10:45 ` Anshuman Gupta
2021-04-27 18:55 ` Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Anshuman Gupta @ 2021-04-27 10:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Gaurav Kumar
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in aysnc flip too.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Cc: Shankar Uma <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 51 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++
2 files changed, 95 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 74489217e580..a666b86df726 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -934,6 +934,33 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
return plane_color_ctl;
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1039,13 +1066,22 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
- plane_state->plane_decryption)
+ plane_state->plane_decryption) {
plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
- else
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else if (plane_state->plane_decryption) {
+ intel_load_plane_csc_black(plane);
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ } else {
plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+ plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
+ }
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
+ plane_color_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
@@ -1066,6 +1102,7 @@ skl_plane_async_flip(struct intel_plane *plane,
enum pipe pipe = plane->pipe;
u32 surf_addr = plane_state->view.color_plane[0].offset;
u32 plane_ctl = plane_state->ctl;
+ u32 plane_color_ctl = 0;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -1075,6 +1112,16 @@ skl_plane_async_flip(struct intel_plane *plane,
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+
+ if (!intel_pxp_is_active(&dev_priv->gt.pxp) &&
+ plane_state->plane_decryption) {
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
+ intel_load_plane_csc_black(plane);
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
+ plane_color_ctl);
+ }
+
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + surf_addr);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbaf9199001d..0a4deca1098b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7119,6 +7119,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
@@ -11191,6 +11192,51 @@ enum skl_power_gate {
_PAL_PREC_MULTI_SEG_DATA_A, \
_PAL_PREC_MULTI_SEG_DATA_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-04-27 10:45 ` Anshuman Gupta
@ 2021-04-27 18:55 ` Ville Syrjälä
2021-04-30 7:12 ` Gupta, Anshuman
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-27 18:55 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: Gaurav Kumar, intel-gfx
On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> When protected sufaces has flipped and pxp session is disabled,
> display black pixels by using plane color CTM correction.
>
> v2:
> - Display black pixels in aysnc flip too.
We can't change any of that with an async flip.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Cc: Shankar Uma <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 51 ++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++
> 2 files changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 74489217e580..a666b86df726 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -934,6 +934,33 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> return plane_color_ctl;
> }
>
> +static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
> + enum pipe pipe = intel_plane->pipe;
> + enum plane_id plane = intel_plane->id;
> + u16 postoff = 0;
> +
> + drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
> + intel_plane->base.name, plane);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
> +}
> +
> static void
> skl_program_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -1039,13 +1066,22 @@ skl_program_plane(struct intel_plane *plane,
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> + plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
>
> if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> - plane_state->plane_decryption)
> + plane_state->plane_decryption) {
> plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> - else
> + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> + } else if (plane_state->plane_decryption) {
> + intel_load_plane_csc_black(plane);
> + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> + } else {
> plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> + }
>
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> + plane_color_ctl);
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> if (plane_state->scaler_id >= 0)
> @@ -1066,6 +1102,7 @@ skl_plane_async_flip(struct intel_plane *plane,
> enum pipe pipe = plane->pipe;
> u32 surf_addr = plane_state->view.color_plane[0].offset;
> u32 plane_ctl = plane_state->ctl;
> + u32 plane_color_ctl = 0;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>
> @@ -1075,6 +1112,16 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +
> + if (!intel_pxp_is_active(&dev_priv->gt.pxp) &&
> + plane_state->plane_decryption) {
> + plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
> + intel_load_plane_csc_black(plane);
> + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> + plane_color_ctl);
> + }
> +
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> intel_plane_ggtt_offset(plane_state) + surf_addr);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbaf9199001d..0a4deca1098b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7119,6 +7119,7 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
> #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> @@ -11191,6 +11192,51 @@ enum skl_power_gate {
> _PAL_PREC_MULTI_SEG_DATA_A, \
> _PAL_PREC_MULTI_SEG_DATA_B)
>
> +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
> +
> +/* Plane CSC Registers */
> +#define _PLANE_CSC_RY_GY_1_A 0x70210
> +#define _PLANE_CSC_RY_GY_2_A 0x70310
> +
> +#define _PLANE_CSC_RY_GY_1_B 0x71210
> +#define _PLANE_CSC_RY_GY_2_B 0x71310
> +
> +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> + _PLANE_CSC_RY_GY_1_B)
> +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> + _PLANE_INPUT_CSC_RY_GY_2_B)
> +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> +
> +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> +
> +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> + _PLANE_CSC_PREOFF_HI_1_B)
> +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> + _PLANE_CSC_PREOFF_HI_2_B)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
> + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
> + _PLANE_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
> + _PLANE_CSC_POSTOFF_HI_2_B)
> +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> --
> 2.26.2
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-04-27 18:55 ` Ville Syrjälä
@ 2021-04-30 7:12 ` Gupta, Anshuman
2021-04-30 12:55 ` Ville Syrjälä
0 siblings, 1 reply; 62+ messages in thread
From: Gupta, Anshuman @ 2021-04-30 7:12 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Gaurav, Kumar, intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Wednesday, April 28, 2021 12:26 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Gaurav, Kumar <kumar.gaurav@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Ceraolo Spurio, Daniele
> <daniele.ceraolospurio@intel.com>
> Subject: Re: [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
>
> On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> > When protected sufaces has flipped and pxp session is disabled,
> > display black pixels by using plane color CTM correction.
> >
> > v2:
> > - Display black pixels in aysnc flip too.
>
> We can't change any of that with an async flip.
I was thinking of an scenario , when application flip the protected surfaces with synchronous flips
and driver has enable the plane decryption, can application issue an intermediate async flip with
protected surfaces afterwards ?
If above is possible, is it possible to display black pixels in case of pxp session invalidation at the time of
Plane commit?
Thanks,
Anshuman
>
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> > Cc: Shankar Uma <uma.shankar@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > ---
> > .../drm/i915/display/skl_universal_plane.c | 51 ++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++
> > 2 files changed, 95 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 74489217e580..a666b86df726 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -934,6 +934,33 @@ static u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
> > return plane_color_ctl;
> > }
> >
> > +static void intel_load_plane_csc_black(struct intel_plane
> > +*intel_plane) {
> > + struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
> > + enum pipe pipe = intel_plane->pipe;
> > + enum plane_id plane = intel_plane->id;
> > + u16 postoff = 0;
> > +
> > + drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
> > + intel_plane->base.name, plane);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
> > +
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0),
> postoff);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1),
> postoff);
> > + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2),
> > +postoff); }
> > +
> > static void
> > skl_program_plane(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state, @@ -1039,13
> +1066,22
> > @@ skl_program_plane(struct intel_plane *plane,
> > */
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> > + plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> > +plane_id));
> >
> > if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > - plane_state->plane_decryption)
> > + plane_state->plane_decryption) {
> > plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> > - else
> > + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> > + } else if (plane_state->plane_decryption) {
> > + intel_load_plane_csc_black(plane);
> > + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> > + } else {
> > plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> > + plane_color_ctl &= ~PLANE_COLOR_PLANE_CSC_ENABLE;
> > + }
> >
> > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> > + plane_color_ctl);
> > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
> >
> > if (plane_state->scaler_id >= 0)
> > @@ -1066,6 +1102,7 @@ skl_plane_async_flip(struct intel_plane *plane,
> > enum pipe pipe = plane->pipe;
> > u32 surf_addr = plane_state->view.color_plane[0].offset;
> > u32 plane_ctl = plane_state->ctl;
> > + u32 plane_color_ctl = 0;
> >
> > plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> >
> > @@ -1075,6 +1112,16 @@ skl_plane_async_flip(struct intel_plane *plane,
> > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> >
> > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> > +
> > + if (!intel_pxp_is_active(&dev_priv->gt.pxp) &&
> > + plane_state->plane_decryption) {
> > + plane_color_ctl = intel_de_read_fw(dev_priv,
> PLANE_COLOR_CTL(pipe, plane_id));
> > + intel_load_plane_csc_black(plane);
> > + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> > + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> plane_id),
> > + plane_color_ctl);
> > + }
> > +
> > intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> > intel_plane_ggtt_offset(plane_state) + surf_addr);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index fbaf9199001d..0a4deca1098b
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7119,6 +7119,7 @@ enum {
> > #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> > #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /*
> Pre-ICL */
> > #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> > +#define PLANE_COLOR_PLANE_CSC_ENABLE (1 <<
> 21) /* ICL+ */
> > #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> > #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> > #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> > @@ -11191,6 +11192,51 @@ enum skl_power_gate {
> > _PAL_PREC_MULTI_SEG_DATA_A, \
> > _PAL_PREC_MULTI_SEG_DATA_B)
> >
> > +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) +
> > +(i) * 4)
> > +
> > +/* Plane CSC Registers */
> > +#define _PLANE_CSC_RY_GY_1_A 0x70210
> > +#define _PLANE_CSC_RY_GY_2_A 0x70310
> > +
> > +#define _PLANE_CSC_RY_GY_1_B 0x71210
> > +#define _PLANE_CSC_RY_GY_2_B 0x71310
> > +
> > +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A,
> \
> > + _PLANE_CSC_RY_GY_1_B)
> > +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe,
> _PLANE_INPUT_CSC_RY_GY_2_A, \
> > + _PLANE_INPUT_CSC_RY_GY_2_B)
> > +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane,
> \
> > +
> _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> > +
> _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> > +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> > +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> > +
> > +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe,
> _PLANE_CSC_PREOFF_HI_1_A, \
> > + _PLANE_CSC_PREOFF_HI_1_B)
> > +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe,
> _PLANE_CSC_PREOFF_HI_2_A, \
> > + _PLANE_CSC_PREOFF_HI_2_B)
> > +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
> _PLANE_CSC_PREOFF_HI_1(pipe) + \
> > + (index) * 4,
> _PLANE_CSC_PREOFF_HI_2(pipe) + \
> > + (index) * 4)
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
> > +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
> > +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
> > +
> > +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_1_A, \
> > + _PLANE_CSC_POSTOFF_HI_1_B)
> > +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_2_A, \
> > + _PLANE_CSC_POSTOFF_HI_2_B)
> > +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane,
> _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> > + (index) * 4,
> _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> > + (index) * 4)
> > +
> > /* pipe CSC & degamma/gamma LUTs on CHV */
> > #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> > #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-04-30 7:12 ` Gupta, Anshuman
@ 2021-04-30 12:55 ` Ville Syrjälä
2021-05-07 18:42 ` Rodrigo Vivi
0 siblings, 1 reply; 62+ messages in thread
From: Ville Syrjälä @ 2021-04-30 12:55 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: Gaurav, Kumar, intel-gfx
On Fri, Apr 30, 2021 at 07:12:53AM +0000, Gupta, Anshuman wrote:
>
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Wednesday, April 28, 2021 12:26 AM
> > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> > Gaurav, Kumar <kumar.gaurav@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Ceraolo Spurio, Daniele
> > <daniele.ceraolospurio@intel.com>
> > Subject: Re: [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
> >
> > On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> > > When protected sufaces has flipped and pxp session is disabled,
> > > display black pixels by using plane color CTM correction.
> > >
> > > v2:
> > > - Display black pixels in aysnc flip too.
> >
> > We can't change any of that with an async flip.
> I was thinking of an scenario , when application flip the protected surfaces with synchronous flips
> and driver has enable the plane decryption, can application issue an intermediate async flip with
> protected surfaces afterwards ?
> If above is possible, is it possible to display black pixels in case of pxp session invalidation at the time of
> Plane commit?
We'll just have to refuse the async flip if the session has
been invalidated.
--
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-04-30 12:55 ` Ville Syrjälä
@ 2021-05-07 18:42 ` Rodrigo Vivi
2021-05-14 13:41 ` Teres Alexis, Alan Previn
0 siblings, 1 reply; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-07 18:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Gaurav, Kumar
On Fri, Apr 30, 2021 at 03:55:28PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 30, 2021 at 07:12:53AM +0000, Gupta, Anshuman wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Wednesday, April 28, 2021 12:26 AM
> > > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> > > Gaurav, Kumar <kumar.gaurav@intel.com>; Shankar, Uma
> > > <uma.shankar@intel.com>; Ceraolo Spurio, Daniele
> > > <daniele.ceraolospurio@intel.com>
> > > Subject: Re: [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
> > >
> > > On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> > > > When protected sufaces has flipped and pxp session is disabled,
> > > > display black pixels by using plane color CTM correction.
> > > >
> > > > v2:
> > > > - Display black pixels in aysnc flip too.
> > >
> > > We can't change any of that with an async flip.
> > I was thinking of an scenario , when application flip the protected surfaces with synchronous flips
> > and driver has enable the plane decryption, can application issue an intermediate async flip with
> > protected surfaces afterwards ?
> > If above is possible, is it possible to display black pixels in case of pxp session invalidation at the time of
> > Plane commit?
>
> We'll just have to refuse the async flip if the session has
> been invalidated.
This seems the simplest way... but the effect would be different right?
We wouldn't get the desired blank screen, but frozen screen?!
Any possibility of a blank screen on this scenario?
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled
2021-05-07 18:42 ` Rodrigo Vivi
@ 2021-05-14 13:41 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 62+ messages in thread
From: Teres Alexis, Alan Previn @ 2021-05-14 13:41 UTC (permalink / raw)
To: ville.syrjala, Vivi, Rodrigo; +Cc: Gaurav, Kumar, intel-gfx
On Fri, 2021-05-07 at 14:42 -0400, Rodrigo Vivi wrote:
> >
> On Fri, Apr 30, 2021 at 03:55:28PM +0300, Ville Syrjälä wrote:
> > On Fri, Apr 30, 2021 at 07:12:53AM +0000, Gupta, Anshuman wrote:
> > >
> > > > -----Original Message-----
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Sent: Wednesday, April 28, 2021 12:26 AM
> > > > To: Gupta, Anshuman <anshuman.gupta@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <
> > > > rodrigo.vivi@intel.com>;
> > > > Gaurav, Kumar <kumar.gaurav@intel.com>; Shankar, Uma
> > > > <uma.shankar@intel.com>; Ceraolo Spurio, Daniele
> > > > <daniele.ceraolospurio@intel.com>
> > > > Subject: Re: [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp
> > > > disabled
> > > >
> > > > On Tue, Apr 27, 2021 at 04:15:04PM +0530, Anshuman Gupta wrote:
> > > > > When protected sufaces has flipped and pxp session is
> > > > > disabled,
> > > > > display black pixels by using plane color CTM correction.
> > > > >
> > > > > v2:
> > > > > - Display black pixels in aysnc flip too.
> > > >
> > > > We can't change any of that with an async flip.
> > > I was thinking of an scenario , when application flip the
> > > protected surfaces with synchronous flips
> > > and driver has enable the plane decryption, can application issue
> > > an intermediate async flip with
> > > protected surfaces afterwards ?
> > > If above is possible, is it possible to display black pixels in
> > > case of pxp session invalidation at the time of
> > > Plane commit?
> >
> > We'll just have to refuse the async flip if the session has
> > been invalidated.
>
> This seems the simplest way... but the effect would be different
> right?
> We wouldn't get the desired blank screen, but frozen screen?!
>
> Any possibility of a blank screen on this scenario?
>
Not sure if this opinion offers an option: I assume when we say "refuse
the async flip", we mean return a failure on but dont change the HW
state... this would mean the user observes a frozen-and-corrupted-
looking screen since all buffers in the app's swapchain would be
encrypted and invalid at once (the typical case) - including the
current frontbuffer. Along the same lines, if the app + compositor was
paused/idle with no async flips coming in momentarily, a pxp session
invalidation event would then cause the same symptom. Perhaps we need a
uevent drm-master can hook onto specifically for the pxp-teardown so
that drm-master would be able to replace the current front buffer so
long as the session hasnt been re-established. Although this might be
big enough to be seperate patch series after this?
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v3 16/16] drm/i915/pxp: enable PXP for integrated Gen12
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (14 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
@ 2021-03-28 22:57 ` Daniele Ceraolo Spurio
2021-03-28 23:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev3) Patchwork
` (6 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-03-28 22:57 UTC (permalink / raw)
To: intel-gfx
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 480553746794..bd83e8cb05e9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -881,6 +881,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
+ .has_pxp = 1, \
.display.has_dsb = 1
static const struct intel_device_info tgl_info = {
@@ -909,6 +910,7 @@ static const struct intel_device_info rkl_info = {
.memory_regions = REGION_SMEM | REGION_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
+ .has_pxp = 0, \
.has_snoop = 1, \
.is_dgfx = 1
--
2.29.2
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev3)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (15 preceding siblings ...)
2021-03-28 22:57 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
@ 2021-03-28 23:34 ` Patchwork
2021-03-28 23:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-03-28 23:34 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP (rev3)
URL : https://patchwork.freedesktop.org/series/86798/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2fffdc9bd6ba drm/i915/pxp: Define PXP component interface
-:31: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 52 lines checked
02633f66149b mei: pxp: export pavp client to me client bus
-:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#33:
new file mode 100644
-:161: WARNING:TRACING_LOGGING: Unnecessary ftrace-like logging - prefer using ftrace
#161: FILE: drivers/misc/mei/pxp/mei_pxp.c:92:
+ dev_dbg(dev, "%s\n", __func__);
-:176: WARNING:TRACING_LOGGING: Unnecessary ftrace-like logging - prefer using ftrace
#176: FILE: drivers/misc/mei/pxp/mei_pxp.c:107:
+ dev_dbg(dev, "%s\n", __func__);
total: 0 errors, 3 warnings, 0 checks, 280 lines checked
c036327c9e13 drm/i915/pxp: define PXP device flag and kconfig
-:42: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:1736:
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#42: FILE: drivers/gpu/drm/i915/i915_drv.h:1736:
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
total: 1 errors, 0 warnings, 1 checks, 34 lines checked
88337c97ac74 drm/i915/pxp: allocate a vcs context for pxp usage
-:191: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#191:
new file mode 100644
-:215: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line
#215: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:20:
+ for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine; engine++);
total: 1 errors, 1 warnings, 0 checks, 252 lines checked
4243fb716dc6 drm/i915/pxp: Implement funcs to create the TEE channel
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#69:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 142 lines checked
f1f5c9b44578 drm/i915/pxp: set KCR reg init
0eb8fb9b5f41 drm/i915/pxp: Create the arbitrary session after boot
-:75: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#75:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 280 lines checked
16a8074ae79e drm/i915/pxp: Implement arb session teardown
-:62: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#62: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:151:
+#define MI_FLUSH_DW_PROTECTED_MEM_EN (1<<22)
^
-:116: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#116:
new file mode 100644
-:138: ERROR:CODE_INDENT: code indent should use tabs where possible
#138: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:18:
+^I MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG)$
total: 1 errors, 1 warnings, 1 checks, 282 lines checked
79b9cb67b7e9 drm/i915/pxp: Implement PXP irq handler
-:220: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#220:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 426 lines checked
22699a366358 drm/i915/pxp: Enable PXP power management
-:132: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#132:
new file mode 100644
-:197: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#197: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:18:
+}
+static inline void intel_pxp_resume(struct intel_pxp *pxp)
total: 0 errors, 1 warnings, 1 checks, 245 lines checked
3e8ecf822ffa drm/i915/pxp: interface for marking contexts as using protected content
37ca85466387 drm/i915/uapi: introduce drm_i915_gem_create_ext
-:106: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#106: FILE: include/uapi/drm/i915_drm.h:395:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
335d8f6de7b8 drm/i915/pxp: User interface for Protected buffer
-:329: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#329: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.h:60:
+}
+static inline void intel_pxp_object_remove(struct drm_i915_gem_object *obj)
total: 0 errors, 0 warnings, 1 checks, 300 lines checked
4a1dd05541f5 drm/i915/pxp: Add plane decryption support
5078af49bd4f drm/i915/pxp: black pixels on pxp disabled
-:110: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#110: FILE: drivers/gpu/drm/i915/i915_reg.h:11202:
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:110: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#110: FILE: drivers/gpu/drm/i915/i915_reg.h:11202:
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
-:111: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/i915_reg.h:11203:
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
-:124: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#124: FILE: drivers/gpu/drm/i915/i915_reg.h:11216:
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
-:124: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#124: FILE: drivers/gpu/drm/i915/i915_reg.h:11216:
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
-:125: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#125: FILE: drivers/gpu/drm/i915/i915_reg.h:11217:
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
-:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#138: FILE: drivers/gpu/drm/i915/i915_reg.h:11230:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
-:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects?
#138: FILE: drivers/gpu/drm/i915/i915_reg.h:11230:
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
-:139: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#139: FILE: drivers/gpu/drm/i915/i915_reg.h:11231:
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
total: 0 errors, 3 warnings, 6 checks, 115 lines checked
d3fff13e5990 drm/i915/pxp: enable PXP for integrated Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Intel PXP (rev3)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (16 preceding siblings ...)
2021-03-28 23:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev3) Patchwork
@ 2021-03-28 23:36 ` Patchwork
2021-03-28 23:39 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (4 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-03-28 23:36 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP (rev3)
URL : https://patchwork.freedesktop.org/series/86798/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Introduce Intel PXP (rev3)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (17 preceding siblings ...)
2021-03-28 23:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-03-28 23:39 ` Patchwork
2021-03-29 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-03-28 23:39 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP (rev3)
URL : https://patchwork.freedesktop.org/series/86798/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser'
./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser'
/home/cidrm/kernel/Documentation/gpu/i915:22: ./drivers/gpu/drm/i915/intel_runtime_pm.c:423: WARNING: Inline strong start-string without end-string.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP (rev3)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (18 preceding siblings ...)
2021-03-28 23:39 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2021-03-29 0:01 ` Patchwork
2021-03-29 1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-03-29 0:01 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4692 bytes --]
== Series Details ==
Series: Introduce Intel PXP (rev3)
URL : https://patchwork.freedesktop.org/series/86798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9909 -> Patchwork_19874
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/index.html
Known issues
------------
Here are the changes found in Patchwork_19874 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@gem_basic@create-close:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/fi-tgl-y/igt@gem_basic@create-close.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-tgl-y/igt@gem_basic@create-close.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: [DMESG-WARN][6] ([i915#402]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][8] ([i915#2782] / [i915#2940]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][10] ([i915#3303]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (46 -> 40)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-skl-guc fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9909 -> Patchwork_19874
CI-20190529: 20190529
CI_DRM_9909: 3a920a8e00db74289e0bb268c587b11852c1f0b2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6047: 3887134e739f480cefe1dc7f13eb54f7bf3ca27f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19874: d3fff13e5990114e6131f5f88458a43c17efaeda @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d3fff13e5990 drm/i915/pxp: enable PXP for integrated Gen12
5078af49bd4f drm/i915/pxp: black pixels on pxp disabled
4a1dd05541f5 drm/i915/pxp: Add plane decryption support
335d8f6de7b8 drm/i915/pxp: User interface for Protected buffer
37ca85466387 drm/i915/uapi: introduce drm_i915_gem_create_ext
3e8ecf822ffa drm/i915/pxp: interface for marking contexts as using protected content
22699a366358 drm/i915/pxp: Enable PXP power management
79b9cb67b7e9 drm/i915/pxp: Implement PXP irq handler
16a8074ae79e drm/i915/pxp: Implement arb session teardown
0eb8fb9b5f41 drm/i915/pxp: Create the arbitrary session after boot
f1f5c9b44578 drm/i915/pxp: set KCR reg init
4243fb716dc6 drm/i915/pxp: Implement funcs to create the TEE channel
88337c97ac74 drm/i915/pxp: allocate a vcs context for pxp usage
c036327c9e13 drm/i915/pxp: define PXP device flag and kconfig
02633f66149b mei: pxp: export pavp client to me client bus
2fffdc9bd6ba drm/i915/pxp: Define PXP component interface
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/index.html
[-- Attachment #1.2: Type: text/html, Size: 5602 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Intel PXP (rev3)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (19 preceding siblings ...)
2021-03-29 0:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-03-29 1:18 ` Patchwork
2021-04-01 12:07 ` [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Lionel Landwerlin
2021-04-27 13:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP (rev5) Patchwork
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-03-29 1:18 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30248 bytes --]
== Series Details ==
Series: Introduce Intel PXP (rev3)
URL : https://patchwork.freedesktop.org/series/86798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9909_full -> Patchwork_19874_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19874_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19874_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19874_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@gem_userptr_blits@vma-merge.html
Known issues
------------
Here are the changes found in Patchwork_19874_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-clear:
- shard-glk: [PASS][2] -> [FAIL][3] ([i915#1888] / [i915#3160])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk8/igt@gem_create@create-clear.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk6/igt@gem_create@create-clear.html
- shard-skl: [PASS][4] -> [FAIL][5] ([i915#3160])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl8/igt@gem_create@create-clear.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl7/igt@gem_create@create-clear.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#198])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-snb6/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@reset-stress:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#2771])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl3/igt@gem_eio@reset-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl6/igt@gem_eio@reset-stress.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][11] -> [TIMEOUT][12] ([i915#2369] / [i915#2481] / [i915#3070])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb3/igt@gem_eio@unwedge-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +67 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_mmap_gtt@big-copy-xy:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#307])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb8/igt@gem_mmap_gtt@big-copy-xy.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb7/igt@gem_mmap_gtt@big-copy-xy.html
* igt@gem_mmap_offset@clear:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#3160])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk6/igt@gem_mmap_offset@clear.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk3/igt@gem_mmap_offset@clear.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][23] ([i915#3002])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: NOTRUN -> [FAIL][24] ([i915#3296])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@gen9_exec_parse@bb-large.html
* igt@i915_suspend@forcewake:
- shard-apl: NOTRUN -> [DMESG-WARN][25] ([i915#180])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#110725] / [fdo#111614])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_big_fb@linear-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110723])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_joiner@invalid-modeset:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#2705])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-c-crc-primary-basic:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111304])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_ccs@pipe-c-crc-primary-basic.html
* igt@kms_chamelium@dp-audio-edid:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +5 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl6/igt@kms_chamelium@dp-audio-edid.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109284] / [fdo#111827]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_color@pipe-a-gamma:
- shard-tglb: [PASS][32] -> [FAIL][33] ([i915#1149])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-tglb7/igt@kms_color@pipe-a-gamma.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-tglb7/igt@kms_color@pipe-a-gamma.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +9 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +15 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][36] ([i915#1319]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
- shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271]) +127 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-random:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109278]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-256x256-random.html
* igt@kms_cursor_legacy@all-pipes-torture-move:
- shard-glk: [PASS][39] -> [DMESG-WARN][40] ([i915#118] / [i915#95]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk1/igt@kms_cursor_legacy@all-pipes-torture-move.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk1/igt@kms_cursor_legacy@all-pipes-torture-move.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109274] / [fdo#109278])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][42] ([i915#2346])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-blt-ytiled:
- shard-glk: [PASS][43] -> [FAIL][44] ([i915#52] / [i915#54])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk3/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-blt-ytiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#52] / [i915#54])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#2672])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#2642])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109280]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: NOTRUN -> [FAIL][52] ([i915#1188])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][56] ([i915#265]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_cursor@pipe-d-viewport-size-128:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271]) +167 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@kms_plane_cursor@pipe-d-viewport-size-128.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2733])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][62] -> [SKIP][63] ([fdo#109441])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][64] -> [DMESG-WARN][65] ([i915#180] / [i915#295])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2437])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-a-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#2530])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@nouveau_crc@pipe-a-source-outp-inactive.html
* igt@perf@polling:
- shard-skl: [PASS][68] -> [FAIL][69] ([i915#1542])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl9/igt@perf@polling.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl3/igt@perf@polling.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][70] ([i915#2369] / [i915#3063]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-tglb8/igt@gem_eio@unwedge-stress.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-tglb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][72] ([i915#2846]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][74] ([i915#2842]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][76] ([i915#2842]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-tglb8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][78] ([i915#2842]) -> [PASS][79] +4 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk2/igt@gem_exec_fair@basic-throttle@rcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-glk: [FAIL][80] ([i915#307]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-glk2/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-glk5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][82] ([i915#1436] / [i915#716]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-skl: [INCOMPLETE][84] ([i915#151]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [DMESG-WARN][86] ([i915#1982]) -> [PASS][87] +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl9/igt@kms_color@pipe-a-ctm-0-5.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl7/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen:
- shard-skl: [FAIL][88] ([i915#54]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [FAIL][92] ([i915#2122]) -> [PASS][93] +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl10/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl7/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- shard-skl: [FAIL][94] ([i915#53]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl9/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][96] ([fdo#108145] / [i915#265]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_cursor@pipe-c-primary-size-64:
- shard-iclb: [INCOMPLETE][98] -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb7/igt@kms_plane_cursor@pipe-c-primary-size-64.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_plane_cursor@pipe-c-primary-size-64.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][100] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb7/igt@kms_psr2_su@page_flip.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][102] ([fdo#109441]) -> [PASS][103] +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][104] ([i915#2681] / [i915#2684]) -> [WARN][105] ([i915#2684])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][106] ([i915#2681] / [i915#2684]) -> [WARN][107] ([i915#1804] / [i915#2684])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: [SKIP][108] ([i915#658]) -> [SKIP][109] ([i915#2920]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][110] ([i915#2920]) -> [SKIP][111] ([i915#658]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][112], [FAIL][113]) ([i915#3002]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#602])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-kbl2/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-kbl2/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl1/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl2/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][119], [FAIL][120], [FAIL][121]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002]) -> ([FAIL][122], [FAIL][123], [FAIL][124]) ([i915#180] / [i915#3002])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-apl6/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-apl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-apl3/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl8/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-apl1/igt@runner@aborted.html
- shard-skl: ([FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#2263] / [i915#3002]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([i915#1814] / [i915#2029] / [i915#2263])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl2/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl6/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl2/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl3/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl9/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9909/shard-skl3/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl2/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/shard-skl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2263]: https://gitlab.freedesktop.org/drm/intel/issues/2263
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2771]: https://gitlab.freedesktop.org/drm/intel/issues/2771
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3160]:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19874/index.html
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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (20 preceding siblings ...)
2021-03-29 1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-04-01 12:07 ` Lionel Landwerlin
2021-04-27 13:06 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP (rev5) Patchwork
22 siblings, 0 replies; 62+ messages in thread
From: Lionel Landwerlin @ 2021-04-01 12:07 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Alan Previn, Gaurav Kumar, Chris Wilson
On 29/03/2021 01:56, Daniele Ceraolo Spurio wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+, that helps to establish the hardware protected session
> and manage the status of the alive software session, as well
> as its life cycle.
>
> Lots of minor changes and fixes, but the main changes in v3 are:
>
> - Using a protected object with a context not appropriately marked does
> no longer result in an execbuf failure. This is to avoid apps
> maliciously sharing protected/invalid objects to other apps and
> causing them to fail.
> - All the termination work now goes through the same worker function,
> which allows i915 to drop the mutex lock entirely.
>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Juston Li <juston.li@intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
I updated the Mesa MR to use this new version :
- Iris: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8092
- Anv: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8064
No issue with this current iteration :
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
> Anshuman Gupta (2):
> drm/i915/pxp: Add plane decryption support
> drm/i915/pxp: black pixels on pxp disabled
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Daniele Ceraolo Spurio (6):
> drm/i915/pxp: Define PXP component interface
> drm/i915/pxp: define PXP device flag and kconfig
> drm/i915/pxp: allocate a vcs context for pxp usage
> drm/i915/pxp: set KCR reg init
> drm/i915/pxp: interface for marking contexts as using protected
> content
> drm/i915/pxp: enable PXP for integrated Gen12
>
> Huang, Sean Z (5):
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Implement arb session teardown
> drm/i915/pxp: Implement PXP irq handler
> drm/i915/pxp: Enable PXP power management
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 11 +
> drivers/gpu/drm/i915/Makefile | 9 +
> .../drm/i915/display/skl_universal_plane.c | 50 +++-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 59 +++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 18 ++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 ++++-
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 34 +++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 +
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 12 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 13 +
> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 32 ++-
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 14 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 48 ++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 262 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 65 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 140 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 +
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 100 +++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 37 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 172 ++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 182 ++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 43 +++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 233 ++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 +++
> include/uapi/drm/i915_drm.h | 96 +++++++
> 45 files changed, 1931 insertions(+), 24 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Introduce Intel PXP (rev5)
2021-03-28 22:56 [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Daniele Ceraolo Spurio
` (21 preceding siblings ...)
2021-04-01 12:07 ` [Intel-gfx] [PATCH v3 00/16] Introduce Intel PXP Lionel Landwerlin
@ 2021-04-27 13:06 ` Patchwork
22 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-04-27 13:06 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP (rev5)
URL : https://patchwork.freedesktop.org/series/86798/
State : failure
== Summary ==
Applying: drm/i915/pxp: Define PXP component interface
Applying: mei: pxp: export pavp client to me client bus
Applying: drm/i915/pxp: define PXP device flag and kconfig
Applying: drm/i915/pxp: allocate a vcs context for pxp usage
Applying: drm/i915/pxp: Implement funcs to create the TEE channel
Applying: drm/i915/pxp: set KCR reg init
Applying: drm/i915/pxp: Create the arbitrary session after boot
Applying: drm/i915/pxp: Implement arb session teardown
Applying: drm/i915/pxp: Implement PXP irq handler
Applying: drm/i915/pxp: Enable PXP power management
Applying: drm/i915/pxp: interface for marking contexts as using protected content
Applying: drm/i915/uapi: introduce drm_i915_gem_create_ext
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_drv.c
M include/uapi/drm/i915_drm.h
Falling back to patching base and 3-way merge...
Auto-merging include/uapi/drm/i915_drm.h
CONFLICT (content): Merge conflict in include/uapi/drm/i915_drm.h
Auto-merging drivers/gpu/drm/i915/i915_drv.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0012 drm/i915/uapi: introduce drm_i915_gem_create_ext
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread