* [PATCH v1 0/4] ARM: prepare and add netgear gs110emx support
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Arnd Bergmann, David S. Miller,
Florian Fainelli, Frank Rowand, Gregory Clement, Jakub Kicinski,
Olof Johansson, Rob Herring, Russell King, Sebastian Hesselbarth,
Vivien Didelot, Vladimir Oltean, soc
Cleanup mvebu_v7_defconfig and then add support for the Netgear
GS110EMX which is an 8 port Gigabit switch with two additional
Multi-Gig ports. An 88E6390X switch sits at its core connecting to two
88X3310P 10G PHYs while the control plane is handled by an 88F6811
Armada 381 SoC.
Marcel Ziswiler (4):
dt-bindings: net: dsa: marvell: fix compatible in example
ARM: mvebu_v7_defconfig: enable mtd physmap
ARM: mvebu_v7_defconfig: rebuild default configuration
ARM: dts: mvebu: add device tree for netgear gs110emx switch
.../devicetree/bindings/net/dsa/marvell.txt | 2 +-
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/armada-381-netgear-gs110emx.dts | 293 ++++++++++++++++++
arch/arm/configs/mvebu_v7_defconfig | 18 +-
4 files changed, 303 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
--
2.26.2
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 6:03 ` Marcel Ziswiler
-1 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, David S. Miller, Florian Fainelli,
Frank Rowand, Jakub Kicinski, Rob Herring, Vivien Didelot,
Vladimir Oltean
While the MV88E6390 switch chip exists, one is supposed to use a
compatible of "marvell,mv88e6190" for it. Fix this in the given example.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
Documentation/devicetree/bindings/net/dsa/marvell.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 30c11fea491bd..2363b412410c3 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -83,7 +83,7 @@ Example:
#interrupt-cells = <2>;
switch0: switch@0 {
- compatible = "marvell,mv88e6390";
+ compatible = "marvell,mv88e6190";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, David S. Miller, Florian Fainelli,
Frank Rowand, Jakub Kicinski, Rob Herring, Vivien Didelot,
Vladimir Oltean
While the MV88E6390 switch chip exists, one is supposed to use a
compatible of "marvell,mv88e6190" for it. Fix this in the given example.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
Documentation/devicetree/bindings/net/dsa/marvell.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt
index 30c11fea491bd..2363b412410c3 100644
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@@ -83,7 +83,7 @@ Example:
#interrupt-cells = <2>;
switch0: switch@0 {
- compatible = "marvell,mv88e6390";
+ compatible = "marvell,mv88e6190";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 12:48 ` Andrew Lunn
-1 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:48 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
David S. Miller, Florian Fainelli, Frank Rowand, Jakub Kicinski,
Rob Herring, Vivien Didelot, Vladimir Oltean
On Tue, Oct 05, 2021 at 08:03:31AM +0200, Marcel Ziswiler wrote:
> While the MV88E6390 switch chip exists, one is supposed to use a
> compatible of "marvell,mv88e6190" for it. Fix this in the given example.
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Fixes: a3c53be55c95 ("net: dsa: mv88e6xxx: Support multiple MDIO busses")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Hi Marcel
Since this is a fix, it should be sent separately, and for net, not
net-next.
Thanks
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
@ 2021-10-05 12:48 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:48 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
David S. Miller, Florian Fainelli, Frank Rowand, Jakub Kicinski,
Rob Herring, Vivien Didelot, Vladimir Oltean
On Tue, Oct 05, 2021 at 08:03:31AM +0200, Marcel Ziswiler wrote:
> While the MV88E6390 switch chip exists, one is supposed to use a
> compatible of "marvell,mv88e6190" for it. Fix this in the given example.
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Fixes: a3c53be55c95 ("net: dsa: mv88e6xxx: Support multiple MDIO busses")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Hi Marcel
Since this is a fix, it should be sent separately, and for net, not
net-next.
Thanks
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
2021-10-05 12:48 ` Andrew Lunn
@ 2021-10-05 12:54 ` Andrew Lunn
-1 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:54 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
David S. Miller, Florian Fainelli, Frank Rowand, Jakub Kicinski,
Rob Herring, Vivien Didelot, Vladimir Oltean
On Tue, Oct 05, 2021 at 02:48:55PM +0200, Andrew Lunn wrote:
> On Tue, Oct 05, 2021 at 08:03:31AM +0200, Marcel Ziswiler wrote:
> > While the MV88E6390 switch chip exists, one is supposed to use a
> > compatible of "marvell,mv88e6190" for it. Fix this in the given example.
> >
> > Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
>
> Fixes: a3c53be55c95 ("net: dsa: mv88e6xxx: Support multiple MDIO busses")
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
> Hi Marcel
>
> Since this is a fix, it should be sent separately, and for net, not
> net-next.
Ah, i need to expand that comment a bit. This patch is effectively to
the networking subsystem, where as the reset are for
mvebu/arm-soc. They have different Maintainers. Please see:
https://www.kernel.org/doc/html/latest/networking/netdev-FAQ.html
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 1/4] dt-bindings: net: dsa: marvell: fix compatible in example
@ 2021-10-05 12:54 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:54 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
David S. Miller, Florian Fainelli, Frank Rowand, Jakub Kicinski,
Rob Herring, Vivien Didelot, Vladimir Oltean
On Tue, Oct 05, 2021 at 02:48:55PM +0200, Andrew Lunn wrote:
> On Tue, Oct 05, 2021 at 08:03:31AM +0200, Marcel Ziswiler wrote:
> > While the MV88E6390 switch chip exists, one is supposed to use a
> > compatible of "marvell,mv88e6190" for it. Fix this in the given example.
> >
> > Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
>
> Fixes: a3c53be55c95 ("net: dsa: mv88e6xxx: Support multiple MDIO busses")
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
> Hi Marcel
>
> Since this is a fix, it should be sent separately, and for net, not
> net-next.
Ah, i need to expand that comment a bit. This patch is effectively to
the networking subsystem, where as the reset are for
mvebu/arm-soc. They have different Maintainers. Please see:
https://www.kernel.org/doc/html/latest/networking/netdev-FAQ.html
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v1 2/4] ARM: mvebu_v7_defconfig: enable mtd physmap
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 6:03 ` Marcel Ziswiler
-1 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Gregory Clement, Russell King,
Sebastian Hesselbarth
Enable CONFIG_MTD_PHYSMAP which is nowadays required for
CONFIG_MTD_PHYSMAP_OF.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/configs/mvebu_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index cddce57fe4b9e..5e9a9474c93fb 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -49,6 +49,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v1 2/4] ARM: mvebu_v7_defconfig: enable mtd physmap
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Gregory Clement, Russell King,
Sebastian Hesselbarth
Enable CONFIG_MTD_PHYSMAP which is nowadays required for
CONFIG_MTD_PHYSMAP_OF.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/configs/mvebu_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index cddce57fe4b9e..5e9a9474c93fb 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -49,6 +49,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v1 2/4] ARM: mvebu_v7_defconfig: enable mtd physmap
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 12:55 ` Andrew Lunn
-1 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:55 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Gregory Clement, Russell King, Sebastian Hesselbarth
On Tue, Oct 05, 2021 at 08:03:32AM +0200, Marcel Ziswiler wrote:
> Enable CONFIG_MTD_PHYSMAP which is nowadays required for
> CONFIG_MTD_PHYSMAP_OF.
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 2/4] ARM: mvebu_v7_defconfig: enable mtd physmap
@ 2021-10-05 12:55 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:55 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Gregory Clement, Russell King, Sebastian Hesselbarth
On Tue, Oct 05, 2021 at 08:03:32AM +0200, Marcel Ziswiler wrote:
> Enable CONFIG_MTD_PHYSMAP which is nowadays required for
> CONFIG_MTD_PHYSMAP_OF.
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v1 3/4] ARM: mvebu_v7_defconfig: rebuild default configuration
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 6:03 ` Marcel Ziswiler
-1 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Gregory Clement, Russell King,
Sebastian Hesselbarth
Run "make mvebu_v7_defconfig; make savedefconfig" to rebuild
mvebu_v7_defconfig
This re-ordered the following configuration options:
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
And dropped the following nowadays obsolete configuration options:
CONFIG_ZBOOT_ROM_TEXT=0x0 (default now anyway since commit 39c3e304567a
("ARM: 8984/1: Kconfig: set default ZBOOT_ROM_TEXT/BSS value to 0x0"))
CONFIG_ZBOOT_ROM_BSS=0x0 (ditto)
CONFIG_MTD_M25P80=y (got integrated into MTD_SPI_NOR)
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/configs/mvebu_v7_defconfig | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 5e9a9474c93fb..7b713c083a2a7 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -5,8 +5,6 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -14,13 +12,8 @@ CONFIG_MACH_ARMADA_38X=y
CONFIG_MACH_ARMADA_39X=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_MACH_DOVE=y
-CONFIG_PCI=y
-CONFIG_PCI_MVEBU=y
CONFIG_SMP=y
CONFIG_HIGHMEM=y
-# CONFIG_COMPACTION is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
@@ -29,6 +22,9 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -40,6 +36,8 @@ CONFIG_BT=y
CONFIG_BT_MRVL=y
CONFIG_BT_MRVL_SDIO=y
CONFIG_CFG80211=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -51,7 +49,6 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_SPI_NOR=y
@@ -147,10 +144,10 @@ CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_PRINTK_TIME=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 3/4] ARM: mvebu_v7_defconfig: rebuild default configuration
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Gregory Clement, Russell King,
Sebastian Hesselbarth
Run "make mvebu_v7_defconfig; make savedefconfig" to rebuild
mvebu_v7_defconfig
This re-ordered the following configuration options:
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
And dropped the following nowadays obsolete configuration options:
CONFIG_ZBOOT_ROM_TEXT=0x0 (default now anyway since commit 39c3e304567a
("ARM: 8984/1: Kconfig: set default ZBOOT_ROM_TEXT/BSS value to 0x0"))
CONFIG_ZBOOT_ROM_BSS=0x0 (ditto)
CONFIG_MTD_M25P80=y (got integrated into MTD_SPI_NOR)
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/configs/mvebu_v7_defconfig | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 5e9a9474c93fb..7b713c083a2a7 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -5,8 +5,6 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -14,13 +12,8 @@ CONFIG_MACH_ARMADA_38X=y
CONFIG_MACH_ARMADA_39X=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_MACH_DOVE=y
-CONFIG_PCI=y
-CONFIG_PCI_MVEBU=y
CONFIG_SMP=y
CONFIG_HIGHMEM=y
-# CONFIG_COMPACTION is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
@@ -29,6 +22,9 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -40,6 +36,8 @@ CONFIG_BT=y
CONFIG_BT_MRVL=y
CONFIG_BT_MRVL_SDIO=y
CONFIG_CFG80211=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
@@ -51,7 +49,6 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_SPI_NOR=y
@@ -147,10 +144,10 @@ CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_PRINTK_TIME=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v1 3/4] ARM: mvebu_v7_defconfig: rebuild default configuration
2021-10-05 6:03 ` Marcel Ziswiler
@ 2021-10-05 12:56 ` Andrew Lunn
-1 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:56 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Gregory Clement, Russell King, Sebastian Hesselbarth
On Tue, Oct 05, 2021 at 08:03:33AM +0200, Marcel Ziswiler wrote:
> Run "make mvebu_v7_defconfig; make savedefconfig" to rebuild
> mvebu_v7_defconfig
>
> This re-ordered the following configuration options:
>
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_PCI=y
> CONFIG_PCI_MVEBU=y
> CONFIG_CRYPTO_DEV_MARVELL_CESA=y
>
> And dropped the following nowadays obsolete configuration options:
>
> CONFIG_ZBOOT_ROM_TEXT=0x0 (default now anyway since commit 39c3e304567a
> ("ARM: 8984/1: Kconfig: set default ZBOOT_ROM_TEXT/BSS value to 0x0"))
> CONFIG_ZBOOT_ROM_BSS=0x0 (ditto)
> CONFIG_MTD_M25P80=y (got integrated into MTD_SPI_NOR)
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 3/4] ARM: mvebu_v7_defconfig: rebuild default configuration
@ 2021-10-05 12:56 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 12:56 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Gregory Clement, Russell King, Sebastian Hesselbarth
On Tue, Oct 05, 2021 at 08:03:33AM +0200, Marcel Ziswiler wrote:
> Run "make mvebu_v7_defconfig; make savedefconfig" to rebuild
> mvebu_v7_defconfig
>
> This re-ordered the following configuration options:
>
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_PCI=y
> CONFIG_PCI_MVEBU=y
> CONFIG_CRYPTO_DEV_MARVELL_CESA=y
>
> And dropped the following nowadays obsolete configuration options:
>
> CONFIG_ZBOOT_ROM_TEXT=0x0 (default now anyway since commit 39c3e304567a
> ("ARM: 8984/1: Kconfig: set default ZBOOT_ROM_TEXT/BSS value to 0x0"))
> CONFIG_ZBOOT_ROM_BSS=0x0 (ditto)
> CONFIG_MTD_M25P80=y (got integrated into MTD_SPI_NOR)
>
> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v1 4/4] ARM: dts: mvebu: add device tree for netgear gs110emx switch
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Arnd Bergmann, Frank Rowand,
Gregory Clement, Olof Johansson, Rob Herring, Russell King,
Sebastian Hesselbarth, soc
Add the device tree for a Netgear GS110EMX switch featuring 8 Gigabit
ports and 2 Multi-Gig ports (100M/1G/2.5G/5G/10G). An 88E6390X switch
sits at its core connecting to two 88X3310P 10G PHYs. The control plane
is handled by an 88F6811 Armada 381 SoC.
The following functionality is tested:
- 8 gigabit Ethernet ports connecting via 88E6390X to the 88F6811
- serial console UART
- 128 MB commercial grade DDR3L SDRAM
- 16 MB serial SPI NOR flash
The two 88X3310P 10G PHYs while detected during boot seem neither to
detect any link nor pass any traffic.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/armada-381-netgear-gs110emx.dts | 293 ++++++++++++++++++
2 files changed, 294 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ffab04866654..e2fcb55c99c6b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1392,6 +1392,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
+ armada-381-netgear-gs110emx.dtb \
armada-382-rd-ac3x-48g4x2xl.dtb \
armada-385-atl-x530.dtb\
armada-385-clearfog-gtr-s4.dtb \
diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
new file mode 100644
index 0000000000000..e37baeb12bd01
--- /dev/null
+++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Netgear GS110EMX";
+ compatible = "netgear,gs110emx", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&front_button_pins>;
+ pinctrl-names = "default";
+
+ factory_default {
+ label = "Factory Default";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3P3V";
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+ };
+ };
+};
+
+ð0 {
+ /* ethernet@70000 */
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy1: switch0phy1@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy2: switch0phy2@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy3: switch0phy3@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy4: switch0phy4@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy5: switch0phy5@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy6: switch0phy6@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy7: switch0phy7@8 {
+ reg = <0x8>;
+ };
+ };
+
+ mdio-external {
+ compatible = "marvell,mv88e6xxx-mdio-external";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@b {
+ reg = <0xb>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ phy2: ethernet-phy@c {
+ reg = <0xc>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ ethernet = <ð0>;
+ label = "cpu";
+ reg = <0>;
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
+ port@1 {
+ label = "lan1";
+ phy-handle = <&switch0phy0>;
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan2";
+ phy-handle = <&switch0phy1>;
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan3";
+ phy-handle = <&switch0phy2>;
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "lan4";
+ phy-handle = <&switch0phy3>;
+ reg = <4>;
+ };
+
+ port@5 {
+ label = "lan5";
+ phy-handle = <&switch0phy4>;
+ reg = <5>;
+ };
+
+ port@6 {
+ label = "lan6";
+ phy-handle = <&switch0phy5>;
+ reg = <6>;
+ };
+
+ port@7 {
+ label = "lan7";
+ phy-handle = <&switch0phy6>;
+ reg = <7>;
+ };
+
+ port@8 {
+ label = "lan8";
+ phy-handle = <&switch0phy7>;
+ reg = <8>;
+ };
+
+ port@9 {
+ /* 88X3310P external phy */
+ label = "lan9";
+ phy-handle = <&phy1>;
+ phy-mode = "xaui";
+ reg = <9>;
+ };
+
+ port@a {
+ /* 88X3310P external phy */
+ label = "lan10";
+ phy-handle = <&phy2>;
+ phy-mode = "xaui";
+ reg = <0xa>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ front_button_pins: front-button-pins {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+//mtdparts=spi0.0:1m(boot),64k(env),64k(rsv),9m(image0),3m(config),-(debug)
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ read-only;
+ reg = <0x00000000 0x00100000>;
+ };
+
+ partition@100000 {
+ label = "env";
+ reg = <0x00100000 0x00010000>;
+ };
+
+ partition@200000 {
+ label = "rsv";
+ reg = <0x00110000 0x00010000>;
+ };
+
+ partition@300000 {
+ label = "image0";
+ reg = <0x00120000 0x00900000>;
+ };
+
+ partition@400000 {
+ label = "config";
+ reg = <0x00a20000 0x00300000>;
+ };
+
+ partition@480000 {
+ label = "debug";
+ reg = <0x00d20000 0x002e0000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v1 4/4] ARM: dts: mvebu: add device tree for netgear gs110emx switch
@ 2021-10-05 6:03 ` Marcel Ziswiler
0 siblings, 0 replies; 20+ messages in thread
From: Marcel Ziswiler @ 2021-10-05 6:03 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, netdev
Cc: Andrew Lunn, Marcel Ziswiler, Arnd Bergmann, Frank Rowand,
Gregory Clement, Olof Johansson, Rob Herring, Russell King,
Sebastian Hesselbarth, soc
Add the device tree for a Netgear GS110EMX switch featuring 8 Gigabit
ports and 2 Multi-Gig ports (100M/1G/2.5G/5G/10G). An 88E6390X switch
sits at its core connecting to two 88X3310P 10G PHYs. The control plane
is handled by an 88F6811 Armada 381 SoC.
The following functionality is tested:
- 8 gigabit Ethernet ports connecting via 88E6390X to the 88F6811
- serial console UART
- 128 MB commercial grade DDR3L SDRAM
- 16 MB serial SPI NOR flash
The two 88X3310P 10G PHYs while detected during boot seem neither to
detect any link nor pass any traffic.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/armada-381-netgear-gs110emx.dts | 293 ++++++++++++++++++
2 files changed, 294 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5ffab04866654..e2fcb55c99c6b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1392,6 +1392,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
+ armada-381-netgear-gs110emx.dtb \
armada-382-rd-ac3x-48g4x2xl.dtb \
armada-385-atl-x530.dtb\
armada-385-clearfog-gtr-s4.dtb \
diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
new file mode 100644
index 0000000000000..e37baeb12bd01
--- /dev/null
+++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Netgear GS110EMX";
+ compatible = "netgear,gs110emx", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&front_button_pins>;
+ pinctrl-names = "default";
+
+ factory_default {
+ label = "Factory Default";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3P3V";
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+ };
+ };
+ };
+};
+
+ð0 {
+ /* ethernet@70000 */
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ switch@0 {
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy1: switch0phy1@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy2: switch0phy2@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy3: switch0phy3@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy4: switch0phy4@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy5: switch0phy5@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy6: switch0phy6@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy7: switch0phy7@8 {
+ reg = <0x8>;
+ };
+ };
+
+ mdio-external {
+ compatible = "marvell,mv88e6xxx-mdio-external";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@b {
+ reg = <0xb>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ phy2: ethernet-phy@c {
+ reg = <0xc>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ ethernet = <ð0>;
+ label = "cpu";
+ reg = <0>;
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
+ port@1 {
+ label = "lan1";
+ phy-handle = <&switch0phy0>;
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan2";
+ phy-handle = <&switch0phy1>;
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan3";
+ phy-handle = <&switch0phy2>;
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "lan4";
+ phy-handle = <&switch0phy3>;
+ reg = <4>;
+ };
+
+ port@5 {
+ label = "lan5";
+ phy-handle = <&switch0phy4>;
+ reg = <5>;
+ };
+
+ port@6 {
+ label = "lan6";
+ phy-handle = <&switch0phy5>;
+ reg = <6>;
+ };
+
+ port@7 {
+ label = "lan7";
+ phy-handle = <&switch0phy6>;
+ reg = <7>;
+ };
+
+ port@8 {
+ label = "lan8";
+ phy-handle = <&switch0phy7>;
+ reg = <8>;
+ };
+
+ port@9 {
+ /* 88X3310P external phy */
+ label = "lan9";
+ phy-handle = <&phy1>;
+ phy-mode = "xaui";
+ reg = <9>;
+ };
+
+ port@a {
+ /* 88X3310P external phy */
+ label = "lan10";
+ phy-handle = <&phy2>;
+ phy-mode = "xaui";
+ reg = <0xa>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ front_button_pins: front-button-pins {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+//mtdparts=spi0.0:1m(boot),64k(env),64k(rsv),9m(image0),3m(config),-(debug)
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot";
+ read-only;
+ reg = <0x00000000 0x00100000>;
+ };
+
+ partition@100000 {
+ label = "env";
+ reg = <0x00100000 0x00010000>;
+ };
+
+ partition@200000 {
+ label = "rsv";
+ reg = <0x00110000 0x00010000>;
+ };
+
+ partition@300000 {
+ label = "image0";
+ reg = <0x00120000 0x00900000>;
+ };
+
+ partition@400000 {
+ label = "config";
+ reg = <0x00a20000 0x00300000>;
+ };
+
+ partition@480000 {
+ label = "debug";
+ reg = <0x00d20000 0x002e0000>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.26.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v1 4/4] ARM: dts: mvebu: add device tree for netgear gs110emx switch
@ 2021-10-05 13:05 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 13:05 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Arnd Bergmann, Frank Rowand, Gregory Clement, Olof Johansson,
Rob Herring, Russell King, Sebastian Hesselbarth, soc
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0phy0: switch0phy0@1 {
> + reg = <0x1>;
> + };
> +
> + port@1 {
> + label = "lan1";
> + phy-handle = <&switch0phy0>;
> + reg = <1>;
> + };
You numbering of the phy labels is a bit confusing here. Both the port
and the PHY use reg=<1>. So i would use the label
switch0phy1: switch0phy1@1
Andrew
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v1 4/4] ARM: dts: mvebu: add device tree for netgear gs110emx switch
@ 2021-10-05 13:05 ` Andrew Lunn
0 siblings, 0 replies; 20+ messages in thread
From: Andrew Lunn @ 2021-10-05 13:05 UTC (permalink / raw)
To: Marcel Ziswiler
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Arnd Bergmann, Frank Rowand, Gregory Clement, Olof Johansson,
Rob Herring, Russell King, Sebastian Hesselbarth, soc
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0phy0: switch0phy0@1 {
> + reg = <0x1>;
> + };
> +
> + port@1 {
> + label = "lan1";
> + phy-handle = <&switch0phy0>;
> + reg = <1>;
> + };
You numbering of the phy labels is a bit confusing here. Both the port
and the PHY use reg=<1>. So i would use the label
switch0phy1: switch0phy1@1
Andrew
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